Implementation method of drive circuit of ultra-low power consumption and high reliability relay

Abstract

The invention provides an implementation method of a drive circuit of an ultra-low-power-consumption high-reliability relay, and relates to the technical field of electric control isolation devices. The relay body, the processor and the input control circuit are arranged into an integrated relay, the integrated relay is connected with external equipment through the input control circuit, the input voltage of the relay is widened, and the application range of the relay is widened. In addition, a relay control signal is processed through a processor, and when the relay needs to act, the relay is controlled to act. After the relay acts, the relay enters the sleep mode, so that the energy consumption of the relay without action is reduced, and the power consumption of the relay is reduced. Therefore, the power consumption of the relay can be reduced, and the application range of the relay is widened. In addition, the relay provided by the invention also has a failure diagnosis function, and adopts dual-port redundant drive, so that the reliability of the relay is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electric control isolation devices, and in particular to a method for realizing a driving circuit of an ultra-low power consumption and high reliability relay. Background Art

[0002] Relay is an automatic switch element with isolation function, widely used in remote control, telemetry, communication, automatic control, mechatronics and automation instrumentation, and is one of the most important control elements. As a bistable relay, magnetic latching relay is widely used for its advantages of low power consumption, small size and large load capacity.

[0003] On the one hand, the application method of relays is to connect the relays directly to the circuit or to connect the relays to the circuit through the driving circuit. During the use of the relays, the relays need to be powered continuously, which consumes a lot of power. On the other hand, the power supply requirement of the relay driving circuit is 5 to 30V, and the application range is relatively narrow. It cannot adapt to the power supply system with a lower voltage of 3V or a higher voltage of more than 30V, so the application range of the relays is limited. Summary of the invention

[0004] The present invention provides a method for realizing a driving circuit of an ultra-low power consumption and high reliability relay, which can reduce the power consumption of the relay and expand the application range of the relay.

[0005] In a first aspect, the present invention provides a method for realizing a driving circuit of an ultra-low power consumption and high reliability relay, wherein the relay comprises a relay body, a processor and an input control circuit, wherein the input control circuit is respectively connected to an external device and an input end of the processor, and an output end of the processor is connected to a driving coil of the relay body; the method comprises: monitoring a relay control signal input by an external device; if a relay control signal is monitored, performing a logic level conversion on the relay control signal to obtain a level signal; the level signal comprises a low level signal and a high level signal; based on the level signal and a pre-stored control mode, determining an output state of the processor; the control mode is used to define a logical relationship between the level signal and the output state of the processor; adjusting the output end of the processor to an output state and maintaining it for a first time length to realize relay action; and adjusting the processor to enter a sleep state.

[0006] In one possible implementation, the output end of the processor includes a first port, a second port, a third port and a fourth port; the first port and the second port are connected to the first end of the drive coil; the third port and the fourth port are connected to the second end of the drive coil; based on the level signal and a pre-stored control mode, the output state of the processor is determined, including: based on the level signal and the control mode, determining the output levels of the first port, the second port, the third port and the fourth port.

[0007] In one possible implementation, the relay control signal input by the external device is an alarm signal; the method also includes: monitoring the alarm signal; if the alarm signal is detected, the processor enters the interrupt program and adjusts the output state to the forced push mode; after the processor is set to the forced push mode for a second period of time, the processor exits the interrupt program and sets the processor to the first mode, which is the processor output mode set by the user; and controls the relay to enter the sleep mode.

[0008] In one possible implementation, the processor also includes a power-off input port; the method also includes: monitoring the input state of the power-off input port; the input state includes power off and normal power; if the input state is power off, the processor enters an interrupt program and adjusts the output state to a forced push mode; after the processor is set to the forced push mode for a third period of time, the processor exits the interrupt program and sets the processor to a second mode, the second mode being a processor output mode set by a user; and controlling the processor to enter a sleep mode.

[0009] In one possible implementation, the processor also includes a timer; the timer is set with a set period, and the method also includes: detecting the timing duration of the timer; if the timing duration reaches the set period, the processor enters an interrupt program and adjusts the output state to an ADC sampling mode; collects the ADC sampling results of the output end of the processor; based on the ADC sampling results, diagnoses the relay to determine whether the relay has failed; if the relay works normally, controls the processor to enter a sleep mode.

[0010] In a possible implementation, adjusting the output state to the ADC sampling mode includes: adjusting the first port to be connected to VCC through a ninth resistor; adjusting the second port to be connected to the first ADC port; adjusting the third port to be connected to the second ADC port; and adjusting the fourth port to be grounded.

[0011] In one possible implementation, the processor also includes a status output port; the status output port is used to indicate whether the relay has failed; after diagnosing the relay based on the ADC sampling result and determining whether the relay has failed, it also includes: determining the output state of the status output port based on whether the relay has failed.

[0012] In a possible implementation, after diagnosing the relay drive based on the ADC sampling result to determine whether the relay drive has failed, the method further includes: if the relay drive has failed, determining the output port that was in a working state and the output port that was in a standby state before the relay drive failed; switching the output port of the relay drive that was in the standby state to a working state, and switching the output port that was in a working state to a standby state; and controlling the relay action based on the output port after switching.

[0013] In a possible implementation, the relay is diagnosed based on the ADC sampling result to determine whether the relay has failed, including: if the ADC sampling result is a first result, determining that the relay has failed; if the ADC sampling result is a second result, determining that the relay is normal.

[0014] In a possible implementation, the method also includes: monitoring the power-on signal of the relay; if a power-on signal is monitored, obtaining a first logical relationship and a second logical relationship input by the user; the first logical relationship is the logical relationship between the input control signal and whether an alarm occurs; the second logical relationship is the logical relationship between the power-off signal and whether a power-off occurs; based on the first logical relationship and the second logical relationship, setting the processor; starting the processor's timer; and controlling the processor to enter sleep mode.

[0015] In one possible implementation, the input control circuit includes a first branch and / or a second branch; the first branch is connected to the first input port of the processor; the second branch is connected to the second input port of the processor; the first branch receives a relay control signal of a first external device; the second branch receives a relay control signal of a second external device; the method also includes: if a relay control signal input by the first external device is monitored, then based on the relay control signal input by the first external device, the action of the drive coil of the first relay body is controlled; if a relay control signal input by the second external device is monitored, then based on the relay control signal input by the second external device, the action of the drive coil of the second relay body is controlled.

[0016] In the second aspect, an embodiment of the present invention provides an intelligent ultra-low power consumption relay, including: a relay body, a processor and an input control circuit; the input end of the input control circuit is connected to an external device, and the output end is connected to an input port of the processor; the output end of the processor is connected to a drive coil of the relay body; the output end of the relay body is connected to a controlled device; when an external device inputs a relay control signal, the intelligent ultra-low power consumption relay is in a working state; when the external device has no input signal, the intelligent ultra-low power consumption relay is in a sleep state.

[0017] In a possible implementation, the output end of the processor includes a first port, a second port, a third port and a fourth port; the first port and the second port are connected to the first end of the drive coil; the third port and the fourth port are connected to the second end of the drive coil.

[0018] In one possible implementation, the input control circuit includes a first branch and / or a second branch; the first branch is connected to the first input port of the processor; the second branch is connected to the second input port of the processor; the first branch receives a relay control signal of a first external device; and the second branch receives a relay control signal of a second external device.

[0019] In one possible implementation, the processor also includes a mode input port, which is connected to a mode setting circuit, or the mode input port is connected to an external setting device; the mode input port receives a mode setting signal, and the mode setting signal is used to limit the logical relationship between the received signal of the signal input port of the processor and the output state of the processor.

[0020] In a possible implementation, the intelligent ultra-low power consumption relay also includes a power supply circuit; the power supply circuit includes a DC power supply, a first diode and a first capacitor; the anode of the first diode is connected to the DC power supply; the cathode of the first diode is connected to the first end of the first capacitor and then connected to VCC; the second end of the first capacitor is grounded.

[0021] In a possible implementation, the capacitance value of the first capacitor is greater than or equal to C;

[0022]

[0023] Wherein, t is the action time of the magnetic latching relay, P is the action power of the magnetic latching relay, U1 is the voltage of the first capacitor before the magnetic latching relay is actuated, and U2 is the voltage of the first capacitor after the magnetic latching relay is actuated.

[0024] In a possible implementation, the intelligent ultra-low power consumption relay also includes a power-off detection circuit; the power-off detection circuit includes a third resistor, a fourth resistor and a second diode; the first end of the third resistor is connected to the DC power supply and VDD; the second end of the third resistor is connected to the first end of the fourth resistor and the anode of the second diode; the second end of the fourth resistor is connected to the power-off detection port of the processor; and the cathode of the second diode is connected to VCC.

[0025] In a possible implementation, the states of the intelligent ultra-low power relay include a working state, a sleeping state, and an interrupt state; in the interrupt state, the output modes of the processor include a strong push mode, a weak pull mode, and an ADC sampling mode.

[0026] In one possible implementation, a timer is provided inside the processor. When the timing duration of the timer reaches a set period, the relay is in a timed interrupt state. Inside the processor, the first port is connected to VCC through a ninth resistor, the second port is connected to the first ADC port, the third port is connected to the second ADC port, and the fourth port is grounded.

[0027] The present invention provides a method for realizing a driving circuit of an ultra-low power consumption and high reliability relay. The present invention sets a relay body, a processor and an input control circuit as an integrated relay, connects with an external device through the input control circuit, widens the input voltage of the relay, and widens the application range of the relay. In addition, the present invention processes the relay control signal through the processor, and controls the relay action when the relay action is required. After the relay is actuated, the relay enters a sleep mode, reduces the energy consumption when the relay is not actuated, and reduces the power consumption of the relay. Therefore, the relay provided by the present invention can reduce the power consumption of the relay and widen the application range of the relay. In addition, the relay provided by the present invention also has a failure diagnosis function, and adopts a dual-port redundant drive to improve the reliability of the relay. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0029] Figure 1 It is a structural schematic diagram of an intelligent ultra-low power consumption relay provided by an embodiment of the present invention;

[0030] Figure 2 is a schematic structural diagram of two input control circuits provided by an embodiment of the present invention;

[0031] Figure 3 is a structural schematic diagram of a mode setting circuit provided by an embodiment of the present invention;

[0032] Figure 4 is a schematic diagram of the internal structure of a processor provided by an embodiment of the present invention;

[0033] Figure 5 is a structural schematic diagram of another intelligent ultra-low power consumption relay provided by an embodiment of the present invention;

[0034] Figure 6 is a schematic diagram of the structure of a state output circuit provided by an embodiment of the present invention;

[0035] Figure 7 It is a flow chart of a method for realizing a driving circuit of an ultra-low power consumption and high reliability relay provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0037] In the description of the present invention, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" and "plurality" refer to two or more. The words "first", "second", etc. do not limit the quantity and execution order, and the words "first", "second", etc. do not limit them to be different.

[0038] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0039] In addition, the terms "including" and "having" and any variations thereof mentioned in the description of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include other steps or modules that are not listed, or may optionally include other steps or modules that are inherent to these processes, methods, products or devices.

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clear, the following will be described through specific embodiments in conjunction with the accompanying drawings of the present invention.

[0041] As described in the background technology, magnetic latching relay driver chips, such as KY8023 of KEYSEMI and LT8023 of Lingchen Technology, are easy to use and have low driving power consumption, but there are also some problems. For example, each relay driving IO requires two logics to cooperate, and multi-channel relays require more IOs, and the control logic is complicated; the driving circuit power supply requires 5 to 30V, which cannot adapt to the 3V lower voltage power supply system; relays are often key control components, and their failure is very important. This type of chip uses non-closed-loop control and cannot obtain the relay failure state; in addition, when using magnetic latching relay control, the previous relay energized state will be maintained when the power is off, and this state may not be suitable for the control logic of the controlled device at this time, etc.

[0042] To solve the above technical problems, Figure 1 As shown, an embodiment of the present invention provides an intelligent ultra-low power consumption relay. The relay includes a relay body 10, a processor 20 and an input control circuit 30.

[0043] In the embodiment of the present application, the input end of the input control circuit 30 is connected to an external device, and the output end is connected to the input port of the processor 20; the output end of the processor 20 is connected to the drive coil of the relay body 10; and the output end of the relay body 10 is connected to the controlled device.

[0044] In the embodiment of the present application, when the external device inputs a relay control signal, the intelligent ultra-low power consumption relay is in a working state; when the external device has no input signal, the intelligent ultra-low power consumption relay is in a dormant state.

[0045] In some embodiments, the relay body 10 in the present invention may be a magnetic latching relay.

[0046] The driving circuit of the intelligent ultra-low power consumption relay provided by the embodiment of the present invention can be applied to a variety of power supply ranges of 2 to 40V DC, and can be well compatible with more power supply systems; only one control IO is needed to realize the action of the magnetic latching relay, which is the same as the conventional relay control method; the magnetic latching relay control adopts closed-loop control, and has a diagnostic function of detecting whether the magnetic latching relay fails, such as open circuit and short circuit of the driving coil; the control logic and power-off reset state of the relay can be flexibly set.

[0047] Optionally, the output end of the processor 20 includes a first port OUT1, a second port OUT2, a third port OUT3 and a fourth port OUT4; the first port OUT1 and the second port OUT2 are connected to the first end of the driving coil; the third port OUT3 and the fourth port OUT4 are connected to the second end of the driving coil.

[0048] Exemplarily, the first port OUT1 , the second port OUT2 , the third port OUT3 , and the fourth port OUT4 may be configured as redundant port drivers.

[0049] For example, the processor 20 can control the relay to operate through the first port OUT1 and the third port OUT3. The second port OUT2 and the fourth port OUT4 are redundant ports, and control the relay to operate when the first port OUT1 and the third port OUT3 fail.

[0050] For another example, the processor 20 can control the relay to operate through the first port OUT1 and the fourth port OUT4. The second port OUT2 and the third port OUT3 are redundant ports, and control the relay to operate when the first port OUT1 and the fourth port OUT4 fail.

[0051] In this way, the embodiment of the present invention can form a port drive redundancy setting through multiple ports to improve the reliability of the relay.

[0052] Optional, such as Figure 2 As shown, the input control circuit 30 includes a first branch and / or a second branch; the first branch is connected to the first input port of the processor 20; the second branch is connected to the second input port of the processor 20; the first branch receives a relay control signal of a first external device; and the second branch receives a relay control signal of a second external device.

[0053] Exemplarily, the first branch includes a first resistor R1, a second resistor R2 and a first switch tube T1. The first end of the first resistor R1 is connected to the first external device, the second end of the first resistor R1 is connected to the gate of the first switch tube T1, the source of the first switch tube T1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to VCC; the drain of the first switch tube T1 is grounded; and the source of the first switch tube T1 is connected to the first input port.

[0054] Exemplarily, the second branch includes a third resistor R3, a fourth resistor R4, and a second switch tube T2. The first end of the third resistor R3 is connected to the gate of the first switch tube T1 and then connected to the second external device, the second end of the third resistor R3 is connected to the drain of the first switch tube T1, the source of the first switch tube T1 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to VCC; the source of the first switch tube T1 is connected to the second input port.

[0055] Optionally, the processor 20 further includes a mode input port SET_IN, and the mode input port SET_IN is connected to the mode setting circuit 60, or the mode input port SET_IN is connected to an external setting device.

[0056] It should be noted that the mode input port SET_IN receives a mode setting signal, and the mode setting signal is used to define a logical relationship between a received signal of the signal input port of the processor and an output state of the processor.

[0057] For example, Figure 3 As shown, the mode setting port is connected to a mode setting circuit, which may include a seventh resistor R7, a first switch S1, an eighth resistor R8 and a second switch S2.

[0058] The first end of the seventh resistor R7 is connected to VCC, the second end of the seventh resistor R7 is connected to the first end of the first switch S1, the second end of the first switch S1 is grounded; the second end of the seventh resistor R7 is connected to the mode setting port.

[0059] A first end of the eighth resistor R8 is connected to VCC, a second end of the eighth resistor R8 is connected to a first end of the second switch S2, a second end of the second switch S2 is grounded; and a second end of the eighth resistor R8 is connected to the mode setting port.

[0060] Exemplarily, the mode input port SET_IN can also be connected to an external setting device such as a host computer through RS485 or RS232 to communicate with the external setting device. After the processor 20 receives the mode setting signal, it sets the logical relationship between the received signal of the signal input port and the output state of the processor 20 based on the mode setting signal.

[0061] Optionally, the intelligent ultra-low power consumption relay further includes a power supply circuit 40 .

[0062] In some embodiments, Figure 1 As shown, the power supply circuit 40 includes a DC power supply, a first diode D1 and a first capacitor C1; the anode of the first diode D1 is connected to the DC power supply; the cathode of the first diode D1 is connected to the first end of the first capacitor C1 and then connected to VCC; the second end of the first capacitor C1 is grounded.

[0063] It should be noted that the first capacitor C1 is an energy storage capacitor. When the magnetic latching relay needs to be activated, the energy stored in the first capacitor C1 can smooth out instantaneous energy consumption fluctuations; when the external power is off, it can ensure that the processor 20 has enough energy to work until the power-off signal is detected and processed.

[0064] Exemplarily, the capacitance value of the first capacitor C1 is greater than or equal to C;

[0065]

[0066] Wherein, t is the action time of the magnetic latching relay, P is the action power of the magnetic latching relay, U1 is the voltage of the first capacitor before the magnetic latching relay is actuated, and U2 is the voltage of the first capacitor after the magnetic latching relay is actuated.

[0067] Exemplarily, the action power of the magnetic latching relay selected in the embodiment of the present invention is approximately P=50mw, and the action time t≤2ms. In order to ensure the stability of the system operating voltage, assuming that the voltage on the first capacitor C1 before and after the relay executes the action is set to U1=3.3V and U2=3V respectively, then, the first capacitor C1≥2*t*P / (U1^2-U2^2)=105uF. In order to ensure a reliable safety margin, the first capacitor C1 can be selected as 330uF / 10V.

[0068] The power supply is a low-power DC-DC conversion power supply, and the logic control circuit is a conversion circuit that converts an external control level into an internal logic level, which can accept a wider power supply and logic control input voltage input to adapt to a wider range of working conditions.

[0069] Optionally, the intelligent ultra-low power consumption relay further includes a power failure detection circuit 50 .

[0070] In some embodiments, Figure 1 As shown, the power-off detection circuit 50 includes a fifth resistor R5, a sixth resistor R6 and a second diode D2; the first end of the fifth resistor R5 is connected to the DC power supply VDD; the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the anode of the second diode D2; the second end of the sixth resistor R6 is connected to the power-off detection port INT0 of the processor 20; and the cathode of the second diode D2 is connected to VCC.

[0071] In the embodiment of the present invention, the power supply supplies power to the processor 20 and related circuits. The processor 20 detects the states of the control input port INT1 and the power-off detection port INT0, and controls the magnetic latching relay to perform corresponding actions after judging the logical relationship preset by the mode input port SET_IN.

[0072] The signal input port INT1 is connected to the input control circuit 30, which is responsible for the conversion between the external input logic and the internal logic level. The magnetic latching relay consumes low power, and the action direction is realized by the voltage polarity at both ends of the driving coil. After the action, the driving coil loses power and continues to maintain the original state.

[0073] Optionally, the states of the intelligent ultra-low power relay include a working state, a sleeping state and an interruption state.

[0074] In the interrupt state, the output modes of the processor 20 include a strong push mode, a weak pull mode and an ADC sampling mode.

[0075] Exemplarily, a timer is provided inside the processor 20, and when the timing duration of the timer reaches a set period, the relay is in a timing interrupt state.

[0076] like Figure 4As shown, the first port inside the processor 20 is connected to VCC through a ninth resistor, the second port is connected to the first ADC port, the third port is connected to the second ADC port, and the fourth port is grounded.

[0077] Processor 20 is a processor with multiple modes such as IO strong drive mode, weak pull mode and ADC multiplexing function. The two sets of multi-function mode drive IOs of processor 20 are directly connected to the drive coil control end of the magnetic latching relay. The different level polarities of the two sets of IOs control the action direction of the magnetic latching relay. Each set of IO can be composed of two IOs or multiple IOs.

[0078] The mode input port SET_IN is the IO level logic control setting mode of the processor 20, and can also be a communication interface. The control logic relationship parameters are set through the mode input port SET_IN to determine the action logic relationship between the magnetic latching relay and the external input signal.

[0079] It should be noted that if Figure 4 As shown, the first contact OUT1 is set to a weak pull-up mode with a resistor, and the pull-up resistor, that is, the ninth resistor, is about 4.7k. The fourth contact OUT4 is a quasi-bidirectional IO low level, so that the pull-up resistor R3 and the coil of the relay are connected in series as the load of the two IOs OUT1 and OUT4. The second contact OUT2 and the third contact OUT3 are set to ADC mode. The voltage division judgment of R3 and the load of the coil can be used to diagnose whether the relay is in a failed state; by changing the combination state of OUT1~OUT4, the performance of the processor IO or the diagnosis of welding quality can also be judged.

[0080] Correspondingly, such as Figure 5 As shown, the output end of the processor 20 can be connected to two relay bodies to control the actions of the two relays. Exemplarily, the processor 20 can include a fifth port OUTB1, a sixth port OUTB2, a seventh port OUTB3 and an eighth port OUTB4.

[0081] The first port OUT1 , the second port OUT2 , the third port OUT3 and the fourth port OUT4 control the first relay body 111 to operate, and the fifth port OUTB1 , the sixth port OUTB2 , the seventh port OUTB3 and the eighth port OUTB4 control the second relay body 112 to operate.

[0082] Optionally, the processor 20 is further provided with a status output port; the status output port is connected to an indicator light to indicate the working status of the relay.

[0083] For example, Figure 6As shown, the state output port of the processor 20 is connected to the first end of the tenth resistor R10, the second end of the tenth resistor R10 is connected to the cathode of the indicator light DL, and the anode of the indicator light DL is connected to VCC. The state output port of the processor 20 is also connected to an external device, such as a host computer, to transmit the state of the relay to the host computer.

[0084] like Figure 7 As shown, the embodiment of the present invention also provides a method for realizing a driving circuit of an ultra-low power consumption and high reliability relay. Figure 1 The intelligent ultra-low power consumption relay shown in the figure comprises a relay body 10, a processor 20 and an input control circuit 30. The input control circuit 30 is connected to an external device and an input end of the processor 20 respectively, and the output end of the processor 20 is connected to a driving coil of the relay body. The method comprises steps S101-S105.

[0085] S101, monitoring the relay control signal input from the external device.

[0086] S102: If a relay control signal is detected, a logic level conversion is performed on the relay control signal to obtain a level signal.

[0087] In the embodiment of the present invention, the level signal includes a low level signal and a high level signal.

[0088] S103: Determine the output state of the processor based on the level signal and the pre-stored control mode.

[0089] In the embodiment of the present invention, the control mode is used to define the logical relationship between the level signal and the output state of the processor.

[0090] Exemplarily, the logical relationship between the level signal and the output state of the processor can be the logical relationship between the rising edge and falling edge of the level signal and the output state of the processor, or can also be expressed as the logical relationship between the rising edge and falling edge of the level signal and the relay action.

[0091] For example, when the level signal rises, the relay is closed; when the level signal falls, the relay is disconnected. Alternatively, when the level signal rises, the relay is disconnected; when the level signal falls, the relay is closed.

[0092] As another example, the logical relationship between the level signal and the output state of the processor may be the logical relationship between the state value of the level signal and the output state of the processor, or may be expressed as the logical relationship between the state value of the level signal and the action of a relay.

[0093] For example, if the level signal is high, the relay is closed; if the level signal is low, the relay is disconnected. Alternatively, if the level signal is high, the relay is disconnected; if the level signal is low, the relay is closed.

[0094] In some embodiments, the output end of the processor includes a first port, a second port, a third port, and a fourth port; the first port and the second port are connected to the first end of the driving coil; the third port and the fourth port are connected to the second end of the driving coil;

[0095] Accordingly, as a possible implementation manner, the embodiment of the present invention may determine the output levels of the first port, the second port, the third port, and the fourth port based on the level signal and the control mode.

[0096] S104, adjusting the output end of the processor to an output state and maintaining the state for a first time length to realize relay action.

[0097] The first duration is a set value and can be adjusted according to the working condition of the relay drive coil.

[0098] S105: Adjust the processor to enter a sleep state.

[0099] In some embodiments, the sleep state is also a non-driving state. Exemplarily, the sleep state can adjust all output ports of the processor to a high level, or all output ports of the processor to a low level, or all output ports of the processor to an IO input state.

[0100] It should be noted that the output port of the processor can be a dual-mode port, which can work in both output state and input state. Adjusting the output port of the processor to the IO input state means that the relay loses drive, the relay is disconnected or maintains the original state.

[0101] In this way, adjusting the processor to enter the sleep state can reduce the energy consumption of the relay when it is not in action, and thus controlling the relay to enter the sleep state can reduce the power consumption of the relay as a whole.

[0102] The present invention provides a method for realizing a driving circuit of an ultra-low power consumption and high reliability relay, wherein a relay body, a processor and an input control circuit are set as an integrated relay, and the relay body is connected to an external device through the input control circuit, so as to widen the input voltage of the relay and widen the application range of the relay. In addition, the present invention processes the relay control signal through the processor, and controls the relay action when the relay action is required. After the relay is actuated, the relay enters a sleep mode, reduces the energy consumption when the relay is not actuated, and reduces the power consumption of the relay. Therefore, the relay provided by the present invention can reduce the power consumption of the relay and widen the application range of the relay.

[0103] Optionally, the processor further includes an alarm input port, wherein the alarm input port is used to receive an alarm signal from a relay.

[0104] In some embodiments, the input control port can be connected to a relay control signal input by an external device, wherein the relay control signal can be an alarm signal of the external device.

[0105] Correspondingly, the method for implementing a driving circuit of an ultra-low power consumption and high reliability relay provided by the embodiment of the present invention further includes steps S201 - S204 .

[0106] S201. Monitor alarm signals.

[0107] S202: If an alarm signal is detected, the processor enters the interrupt program and adjusts the output state to the forced push mode.

[0108] In some embodiments, the forced push mode is that the first port and the second port are both high level, and the third port and the fourth port are both low level; or the first port and the second port are both low level, and the third port and the fourth port are both high level. The processor supplies power to the drive coil through two ports to improve the output current capacity of the processor, that is, to achieve the forced push mode.

[0109] S203: After the processor is set to the forced push mode for the second time period, the processor exits the interrupt program and sets the processor to the first mode.

[0110] The first mode is a processor output mode set by a user.

[0111] S204, control the relay to enter sleep mode.

[0112] When there is an external alarm input, the processor alarm interrupt is triggered, the processor is awakened and enters the alarm interrupt service program. The output end of the processor is in the forced push mode, so that the relay performs the corresponding logical action, and then switches the IO to exit the forced push mode, and keeps the relay in its original state, and then enters the sleep state.

[0113] Optionally, the processor further includes a power-off input port, wherein the power-off input port is used to receive a power-off signal of the relay power supply.

[0114] Correspondingly, the method for implementing a driving circuit of an ultra-low power consumption and high reliability relay provided by the embodiment of the present invention further includes steps S301 - S304 .

[0115] S301, monitoring the input status of the power-off input port.

[0116] In some embodiments, the input status includes power off and power good.

[0117] S302: If the input state is power failure, the processor enters the interrupt program and adjusts the output state to the forced push mode.

[0118] S303: After the processor is set to the forced push mode for a third period of time, the processor exits the interrupt program and sets the processor to the second mode.

[0119] The reset mode is the processor output mode set by the user.

[0120] In some embodiments, the first mode and the second mode may be the same, or the first mode and the second mode may be different. The user may set it according to actual needs.

[0121] S304, controlling the processor to enter a sleep mode.

[0122] When the external power is cut off, the power-off interrupt service program is triggered, so that the output end of the processor is in the forced push mode, causing the magnetic holding relay to perform the required reset action. Due to the continued energy of the power output energy storage device, the interrupt program has enough time to complete the power-off detection and reset the relay action state as set.

[0123] Optionally, the processor also includes a timer; the timer is set with a set period.

[0124] Correspondingly, the method for implementing a driving circuit of an ultra-low power consumption and high reliability relay provided by the embodiment of the present invention further includes steps S401 - S408 .

[0125] S401, detecting the timing duration of the timer.

[0126] S402: If the timing duration reaches the set period, the processor enters the interrupt program and adjusts the output state to the ADC sampling mode.

[0127] Exemplarily, in an embodiment of the present invention, the first port can be adjusted to be connected to VCC through a fifth resistor; the second port can be adjusted to be connected to the first ADC port; the third port can be adjusted to be connected to the second ADC port; and the fourth port can be adjusted to be grounded.

[0128] S403: Acquire ADC sampling results at the output end of the processor.

[0129] S404: Based on the ADC sampling result, diagnose the relay to determine whether the relay is failed.

[0130] As a possible implementation, if the ADC sampling result is the first result, the embodiment of the present invention can determine that the relay is failed. If the ADC sampling result is the second result, it is determined that the relay is normal.

[0131] Exemplarily, the first result is a relay open circuit or a relay short circuit, indicating that the relay fails. Wherein, a relay open circuit means that the second port is VCC and the third port is low level; a relay short circuit means that the second port and the third port are low level.

[0132] Exemplarily, the second result is that the relay is normal, wherein the second port is a voltage-divided value of the fifth resistor and the relay coil, and the third port is grounded.

[0133] In some embodiments, the processor further includes a status output port; the status output port is used to indicate whether the relay fails.

[0134] As a possible implementation manner, the embodiment of the present invention may determine the output state of the state output port based on whether the relay fails after step S404.

[0135] S405: If the relay works normally, the control processor enters the sleep mode.

[0136] S406, if the relay fails, determining the output port in the working state and the output port in the standby state before the relay fails;

[0137] S407, switching the output port of the relay in the standby state to the working state, and switching the output port in the working state to the standby state;

[0138] S408: Based on the switched output port, control the relay action.

[0139] When the timer timing reaches the set period, the timer interrupt service program is triggered to perform the diagnosis of the magnetic latching relay, and the properties of the two groups of drive IO of the processor are switched, so that the first contact of the first group of output ports is in the weak pull mode with resistance, the second contact is in the ADC detection mode, the third contact of the second group of output ports is in the ADC detection mode, and the fourth contact is in the low level mode. By detecting the levels of the two ADC ports, that is, the levels of the second contact and the third contact, it can be determined whether the magnetic latching relay has failed, and the failure changes of the magnetic latching processor drive IO can also be detected, thereby achieving the diagnostic function.

[0140] Optionally, the method for implementing a driving circuit of an ultra-low power consumption and high reliability relay provided by an embodiment of the present invention further includes steps S501 - S505 .

[0141] S501, monitoring the power-on signal of the relay;

[0142] S502: If a power-on signal is detected, obtain a first logical relationship and a second logical relationship input by the user.

[0143] In some embodiments, the first logical relationship is the logical relationship between the input control signal and the action direction of the relay; the second logical relationship is the logical relationship between the input state of the power-off input port and whether a power-off occurs.

[0144] S503, setting the processor based on the first logical relationship and the second logical relationship;

[0145] S504, start the timer of the processor;

[0146] S505: Control the processor to enter sleep mode.

[0147] When powered on, the processor initializes the working parameters and relay reset state according to the logical relationship between the alarm trigger and the normally open and normally closed points of the alarm contact set by the mode input port SET_IN, as well as the state requirements of the relay when power is off or reset, and then sets the relay diagnostic timer interrupt and alarm trigger interrupt mode, and enters a low-power standby sleep state.

[0148] When working normally without alarm triggering, the processor is in sleep mode most of the time, and the power consumption is only a dozen uA. Only when the timer interrupt program works intermittently at specified time intervals will it consume a certain amount of current. However, its instantaneous peak current consumption is also below the mA level, and the duration is short at the ms level, so the overall average current consumption is only twenty to thirty uA. It is completely acceptable to add a relay alarm to most detection systems.

[0149] The driving circuit of the magnetic latching relay provided by the present invention has the advantages of intelligence, low cost, ultra-low power consumption, wide power supply range, few control IOs, etc., and can realize the automatic diagnosis of relay failure function; the control logic and power-off reset state of the relay can be flexibly set.

[0150] Optionally, the input control circuit includes a first branch and / or a second branch; the first branch is connected to the first input port of the processor; the second branch is connected to the second input port of the processor; the first branch receives a relay control signal of a first external device; and the second branch receives a relay control signal of a second external device.

[0151] Correspondingly, the method for implementing the driving circuit of the ultra-low power consumption and high reliability relay provided by the embodiment of the present invention also includes steps A1-A2.

[0152] A1. If a relay control signal input from a first external device is detected, the drive coil of the first relay body is controlled to operate based on the relay control signal input from the first external device.

[0153] A2. If a relay control signal input from a second external device is detected, the drive coil of the second relay body is controlled to operate based on the relay control signal input from the second external device.

[0154] In this way, the embodiment of the present invention can also realize the simultaneous control of two relays or multiple relays, further reducing the power consumption of the relays.

[0155] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A method for realizing a driving circuit of an ultra-low power consumption and high reliability relay, characterized in that: The relay comprises a relay body, a processor and an input control circuit, wherein the input control circuit is connected to an external device and an input end of the processor respectively, and an output end of the processor is connected to a driving coil of the relay body; the method comprises: Monitor the relay control signal input from external devices; If a relay control signal is detected, the relay control signal is converted into a logic level to obtain a level signal; the level signal includes a low level signal and a high level signal; Based on the level signal and a pre-stored control mode, determining an output state of the processor; the control mode is used to define a logical relationship between the level signal and the output state of the processor; Adjusting the output end of the processor to the output state and maintaining the state for a first time length to realize relay action; The processor is adjusted to enter a sleep state.

2. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 1, characterized in that: The output end of the processor includes a first port, a second port, a third port and a fourth port; the first port and the second port are connected to the first end of the drive coil; the third port and the fourth port are connected to the second end of the drive coil; The step of determining the output state of the processor based on the level signal and a pre-stored control mode includes: Based on the level signal and the control mode, output levels of the first port, the second port, the third port, and the fourth port are determined.

3. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 1, characterized in that: The relay control signal input by the external device is an alarm signal; the method further comprises: monitoring the alarm signal; If an alarm signal is detected, the processor enters the interrupt program and adjusts the output state to the forced push mode; After the processor is set to the forced push mode for a second time period, the processor exits the interrupt program and sets the processor to the first mode, where the first mode is a processor output mode set by the user; Control the relay to enter sleep mode.

4. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 1, characterized in that: The processor further includes a power-down input port; and the method further includes: Monitoring the input state of the power-off input port; the input state includes power-off and power-normal; If the input state is power failure, the processor enters the interrupt program and adjusts the output state to the forced push mode; After the processor is set to the forced push mode for a third time period, the processor exits the interrupt program and sets the processor to the second mode, where the second mode is the processor output mode set by the user; The processor is controlled to enter a sleep mode.

5. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 1, characterized in that: The processor further includes a timer; the timer is provided with a set period, and the method further includes: Detect the timing duration of the timer; If the timing duration reaches the set period, the processor enters the interrupt program and adjusts the output state to the ADC sampling mode; Collecting ADC sampling results of the output end of the processor; Based on the ADC sampling result, diagnose the relay to determine whether the relay fails; If the relay works normally, the processor is controlled to enter a sleep mode.

6. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 5, characterized in that: The step of adjusting the output state to an ADC sampling mode comprises: Adjusting the first port to be connected to VCC through a ninth resistor; Adjusting the second port to be connected to the first ADC port; Adjusting the third port to be connected to the second ADC port; The fourth port is adjusted to be grounded.

7. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 5, characterized in that: The processor also includes a status output port; the status output port is used to indicate whether the relay fails; After diagnosing the relay based on the ADC sampling result to determine whether the relay is failed, the method further includes: Based on whether the relay fails, an output state of the state output port is determined.

8. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 5, characterized in that: After diagnosing the relay driver based on the ADC sampling result to determine whether the driver fails, the method further includes: If the relay drive fails, determining the output port in the working state and the output port in the standby state before the relay drive fails; The relay drives the output port in the standby state to switch to the working state, and switches the output port in the working state to the standby state; Based on the switched output port, the relay action is controlled.

9. The method for realizing a driving circuit of an ultra-low power consumption and high reliability relay according to claim 1, characterized in that: The input control circuit includes a first branch and / or a second branch; the first branch is connected to a first input port of the processor; the second branch is connected to a second input port of the processor; The first branch receives a relay control signal of a first external device; The second branch receives a relay control signal of a second external device; The method further comprises: If a relay control signal input from the first external device is detected, the drive coil of the first relay body is controlled to operate based on the relay control signal input from the first external device; If the relay control signal input from the second external device is monitored, the drive coil of the second relay body is controlled to operate based on the relay control signal input from the second external device.

10. An intelligent ultra-low power consumption relay, characterized in that: include: Relay body, processor and input control circuit; The input end of the input control circuit is connected to an external device, and the output end is connected to an input port of the processor; The output end of the processor is connected to the driving coil of the relay body; the output end of the relay body is connected to the controlled device; When the external device inputs a relay control signal, the intelligent ultra-low power consumption relay is in a working state; when the external device has no input signal, the intelligent ultra-low power consumption relay is in a dormant state.

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