Fabrication method of package substrate

Abstract

A manufacturing method of a package substrate includes forming a heterogeneous layer on a substrate body, forming a first circuit layer on the heterogeneous layer, forming a dielectric layer on the heterogeneous layer, embedding the first circuit layer in the dielectric layer, performing a layer-adding circuit, removing the substrate body and the heterogeneous layer to make the depth of the first circuit layer consistent, and forming a second circuit layer on the substrate body. Therefore, a plurality of solder balls can be combined on the first circuit layer.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging process, and in particular to a method for manufacturing a packaging substrate capable of improving reliability. Background Art

[0002] With the rapid development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing in the direction of high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] Figures 1A to 1F It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate 1 .

[0004] like Figure 1A As shown, a carrier 9 is provided, and a spacer layer 91 is provided on the surface of the plate body 90, and a metal layer 92 is formed on the spacer layer 91. Then, a resist layer 10 having an opening area 100 is symmetrically formed on opposite sides of the carrier 9, so that a part of the surface of the carrier 9 is exposed in the opening area 100.

[0005] like Figure 1B As shown, a first circuit layer 11 is formed on the metal layer 92 in the opening area 100. Next, the resist layer 10 is removed.

[0006] like Figure 1C As shown, a dielectric layer 12 is formed on the metal layer 92 of the carrier 9 , and a plurality of blind holes 120 are formed on the dielectric layer 12 .

[0007] like Figure 1D As shown, copper is electroplated on the dielectric layer 12 and in the blind hole 120 to form a second circuit layer 13 on the dielectric layer 12, and a plurality of conductive pillars 14 electrically connecting the first and second circuit layers 11, 13 are formed in the blind hole 120 to form a coreless circuit structure 1a.

[0008] like Figure 1E As shown, the board 90 of the carrier 9 and the circuit structure 1 a are separated by the spacer layer 91 to retain the metal layer 92 on the dielectric layer 12 and the first circuit layer 11 .

[0009] like Figure 1F As shown, the metal layer 92 is removed by etching, and part of the material of the first circuit layer 11 is removed by microetching at the same time, so as to form a plurality of grooves 15 on the dielectric layer 12 .

[0010] In addition, in the subsequent process, such as Figure 1GAs shown, solder balls 16 electrically connected to the first circuit layer 11 may be combined in the groove 15 so that the package substrate 1 is connected to a semiconductor chip (not shown) or an electronic device such as a circuit board (not shown) through the plurality of solder balls 16 .

[0011] However, in the conventional package substrate 1, when the metal layer 92 is etched away, the first circuit layer 11, 11a is also microetched, resulting in inconsistency in the depths D1, D2, D3, D4, D5, and D6 of the plurality of grooves 15, making it difficult to effectively combine all the solder balls 16, and thus the reliability of the package substrate 1 is poor. For example, the depth D2 of some grooves 15 is too shallow, making it difficult for the solder ball 16 to be embedded in the groove 15, causing the solder ball 16 to fall off. Alternatively, the depth D5 of some grooves 15 is too deep, making it difficult for the solder ball 16 to protrude from the groove 15, causing the solder ball 16 to be unable to be soldered to the contact of the external electronic device.

[0012] In addition, since the first circuit layers 11, 11a are also micro-etched when the metal layer 92 is etched away, part of the first circuit layer 11a will be undercut, causing the first circuit layer 11a to be damaged or even disconnected, thereby causing poor signal transmission between the first circuit layer 11a and the solder ball 16.

[0013] In addition, since the first circuit layer 11a has the problem of being damaged by side corrosion, when the line width / line spacing (L / S) of the first circuit layer 11 is designed towards miniaturization, the first circuit layer 11a is more likely to be disconnected, resulting in the interruption of signal transmission between the first circuit layer 11a and the solder ball 16, and thus it is impossible to mass-produce the packaging substrate 1 that requires the miniaturized first circuit layer 11, 11a.

[0014] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0015] An object of the present invention is to provide a method for manufacturing a packaging substrate to solve at least one of the above problems.

[0016] In view of the various defects of the above-mentioned prior art, the present invention provides a packaging substrate, including: a dielectric layer, which has a first surface and a second surface opposite to each other; a first circuit layer, which is embedded in the first surface of the dielectric layer, wherein the first circuit layer is flush with the first surface of the dielectric layer; a second circuit layer, which is formed on the second surface of the dielectric layer; and a plurality of conductive pillars, which are formed in the dielectric layer and electrically connect the first and second circuit layers.

[0017] The present invention also provides a method for manufacturing a packaging substrate, including: providing a board body having a heterogeneous layer thereon; forming a first circuit layer on the heterogeneous layer; forming a dielectric layer on the heterogeneous layer and the first circuit layer, wherein the dielectric layer defines a first surface and a second surface relative to each other so that the dielectric layer is bonded to the heterogeneous layer via its first surface; forming a second circuit layer on the second surface of the dielectric layer, and forming a plurality of conductive columns in the dielectric layer that electrically connect the first circuit layer and the second circuit layer; and separating the board body and etching away the heterogeneous layer to expose the first circuit layer, and making the first circuit layer flush with the first surface of the dielectric layer.

[0018] In the above-mentioned manufacturing method, the material forming the first circuit layer is different from the material forming the heterogeneous layer.

[0019] In the above-mentioned manufacturing method, a spacer layer is first formed on the plate body, and then the heterogeneous layer is formed on the spacer layer. For example, the material forming the spacer layer is different from the material forming the heterogeneous layer. Alternatively, the spacer layer is a copper layer.

[0020] In the aforementioned manufacturing method, the heterogeneous layer is a nickel layer or an aluminum layer.

[0021] In the aforementioned packaging substrate and its manufacturing method, the second circuit layer and the plurality of conductive pillars are formed as one piece.

[0022] As can be seen from the above, the packaging substrate and the manufacturing method thereof of the present invention mainly rely on the configuration of the heterogeneous layer so that the first circuit layer will not be micro-etched when the metal layer is removed. Therefore, when the heterogeneous layer is removed, the thickness of the first circuit layer can be effectively controlled to make the thickness of the first circuit layer consistent. Therefore, compared with the prior art, in the subsequent process of the present invention, the multiple solder balls can be effectively combined on the first circuit layer, thereby avoiding the problem of the solder balls falling off or not being soldered, thereby improving reliability.

[0023] In addition, due to the configuration of the heterogeneous layer, part of the material of the first circuit layer will not be removed when the heterogeneous layer is removed, thereby effectively preventing the first circuit layer from undergoing side corrosion. Therefore, compared to the prior art, the present invention can avoid the problem of damage to the first circuit layer (such as disconnection) to improve the yield of signal transmission between the first circuit layer and the solder ball.

[0024] In addition, when the line width / line spacing (L / S) of the first circuit layer is designed towards miniaturization, the first circuit layer will not be damaged (such as disconnected) due to side corrosion, which can effectively ensure the normal signal transmission between the first circuit layer and the solder ball. Therefore, compared with the prior art, the present invention is conducive to mass production of packaging substrates that need to be equipped with a miniaturized first circuit layer.

[0025] In addition, the manufacturing method of the present invention is applicable to any process of fine circuit specifications, and no matter how thin the carrier is, a groove-free structure can be achieved by coating a thinner heterogeneous layer, which is beneficial to improving the signal transmission speed and packaging yield between the solder ball and the first circuit layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A to 1F It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate.

[0027] Figure 1G for Figure 1F A cross-sectional schematic diagram of the subsequent process.

[0028] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0029] Figure 2A-1 for Figure 2A A cross-sectional schematic diagram of another process.

[0030] The reference numerals are as follows:

[0031] 1,2 Package substrate

[0032] 1a, 2a line structure

[0033] 10,20 barrier layer

[0034] 100,200 opening area

[0035] 11,11a,21First circuit layer

[0036] 12,22 Dielectric layer

[0037] 120 blind holes

[0038] 13,23 Second circuit layer

[0039] 14,24 conductive columns

[0040] 15,25 grooves

[0041] 16 Solder balls

[0042] 22a First surface

[0043] 22b Second surface

[0044] 9 Bearing

[0045] 90 plate body

[0046] 91 Spacer

[0047] 92 Metal Layer

[0048] 93 Heterogeneous Layer

[0049] D Thickness

[0050] D1,D2,D3,D4,D5,D6 depth DETAILED DESCRIPTION

[0051] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0052] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0053] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F It is a cross-sectional schematic diagram of a method for manufacturing a package substrate 2 of the present invention.

[0054] like Figure 2A As shown, a carrier 9 is provided, and a resistance layer 20 having an opening area 200 is symmetrically formed on two opposite sides of the carrier 9 , so that a portion of the surface of the carrier 9 is exposed in the opening area 200 .

[0055] In this embodiment, the carrier 9 is a temporary carrier, which may be a plate having metal layers on opposite sides. The surface of the plate 90 has a spacer layer 91 such as a metal material, and a heterogeneous layer 93 is formed on the spacer layer 91 .

[0056] In addition, the barrier layer 20 is a dry film, and the spacer layer 91 includes a copper metal material, such as a copper layer, and the heterogeneous layer 93 includes a non-copper metal material, such as a nickel layer or an aluminum layer, so the spacer layer 91 and the heterogeneous layer 93 are metal layers of different materials. For example, a plate 90 having a spacer layer 91 may be provided, such as Figure 2A-1The copper foil substrate shown is then used to form the heterogeneous layer 93 on the spacer layer 91 by sputtering, E-less coating or other methods.

[0057] like Figure 2B As shown, a patterning process is performed to form a first wiring layer 21 on the heterogeneous layer 93 .

[0058] In this embodiment, the first circuit layer 21 is made of copper, so that the material forming the first circuit layer 21 is different from the material forming the heterogeneous layer 93. For example, the first circuit layer 21 adopts the specification of redistribution layer (RDL).

[0059] like Figure 2C As shown, the resist layer 20 is removed. Next, a dielectric layer 22 is formed on the heterogeneous layer 93 of the carrier 9, and the dielectric layer 22 defines a first surface 22a and a second surface 22b opposite to each other, so that the dielectric layer 22 is bonded to the heterogeneous layer 93 via the first surface 22a thereof.

[0060] In this embodiment, the dielectric layer 22 is ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0061] like Figure 2D As shown, a second circuit layer 23 is formed on the second surface 22b of the dielectric layer 22, and a plurality of conductive pillars 24 electrically connecting the first circuit layer 21 and the second circuit layer 23 are formed in the dielectric layer 22 to form a coreless circuit structure 2a.

[0062] In this embodiment, the second circuit layer 23 is manufactured by electroplating metal (such as copper) or other methods using a build-up process. For example, a plurality of blind holes are first formed on the second surface 22b of the dielectric layer 22 using a laser, and then copper is electroplated on the dielectric layer 22 and in the blind holes to form the second circuit layer 23 and the conductive pillars 24 as a whole.

[0063] In addition, the second circuit layer 23 is made of copper. For example, the second circuit layer 23 adopts a redistribution layer (RDL) specification.

[0064] It should be understood that by using the build-up method, the number of dielectric layers of the circuit structure 2a can be designed according to requirements to manufacture the required number of second circuit layers 23.

[0065] like Figure 2E As shown, the board 90 of the carrier 9 and the circuit structure 2 a are separated by the spacer layer 91 to retain the heterogeneous layer 93 on the first surface 22 a of the dielectric layer 22 .

[0066] In this embodiment, the spacer layer 91 is removed by etching or other methods. For example, the etchant used to etch the copper material is ferric chloride etchant, hydrochloric acid with oxidant, ammonia water or sulfuric acid with oxidant.

[0067] like Figure 2F As shown, the heterogeneous layer 93 is removed by etching, so that the first circuit layer 21 is embedded in the dielectric layer 22 and exposed on the first surface 22 a of the dielectric layer 22 , and the first circuit layer 21 is flush with the first surface 22 a of the dielectric layer 22 .

[0068] In this embodiment, the etchant used to etch the heterogeneous layer 93 (Ni material) contains free hydrogen, nitrate, phosphate and / or metal ions, so when etching the heterogeneous layer 93, the first circuit layer 21 will not be etched. The selection of the etchant depends on the material used for the heterogeneous layer 93, and is not limited thereto.

[0069] In addition, in the subsequent process, solder balls (not shown) electrically connected to the first circuit layer 21 can be combined on the first circuit layer 21, so that the packaging substrate 2 can be connected to electronic devices such as semiconductor chips, passive components, silicon interposers, circuit boards or other components through the multiple solder balls to form an electronic package.

[0070] Therefore, the manufacturing method of the present invention mainly forms a heterogeneous layer 93 whose material is different from that of the first circuit layer 21, so that the first circuit layer 21 will not be micro-etched when the heterogeneous layer 93 is removed. Therefore, after removing the heterogeneous layer 93, the first circuit layer 21 is flush with the first surface 22a of the dielectric layer 22, and no groove is formed on the first surface 22a of the dielectric layer 22, so as to effectively control the thickness D of the first circuit layer 21 to be consistent, so that the multiple solder balls can be effectively combined on the first circuit layer 21, thereby avoiding the problem of the solder balls falling off or the electronic device not being soldered.

[0071] In addition, since the material forming the first circuit layer 21 is different from the material forming the heterogeneous layer 93, when removing the heterogeneous layer 93, part of the material of the first circuit layer 21 will not be removed, thereby effectively preventing the first circuit layer 21 from being lateral etched, thereby avoiding damage (such as disconnection) and further avoiding the problem of poor signal transmission between the first circuit layer 21 and the solder ball.

[0072] In addition, when the line width / line spacing (L / S) of the first circuit layer 21 is designed towards miniaturization, the first circuit layer 21 will not be damaged (such as disconnected) due to side etching, so as to ensure normal signal transmission between the first circuit layer 21 and the solder ball. Therefore, the manufacturing method of the present invention is conducive to mass production of packaging substrates 2 that need to be equipped with a miniaturized first circuit layer 21 through the design of the heterogeneous layer 93.

[0073] In addition, the manufacturing method of the present invention is applicable to any process of fine circuit specifications, and no matter how thin the board 90 or the copper foil substrate is, a groove-free structure can be achieved by coating a thinner heterogeneous layer 93, which is beneficial to improving the signal transmission speed and packaging yield between the solder ball and the first circuit layer 21.

[0074] The present invention also provides a packaging substrate 2 , comprising: at least one dielectric layer 22 , a first circuit layer 21 , at least one second circuit layer 23 and a plurality of conductive pillars 24 .

[0075] The dielectric layer 22 has a first surface 22 a and a second surface 22 b opposite to each other.

[0076] The first circuit layer 21 is embedded in the first surface 22 a of the dielectric layer 22 , wherein the first circuit layer 21 is flush with the first surface 22 a of the dielectric layer 22 .

[0077] The second circuit layer 23 is formed on the second surface 22 b of the dielectric layer 22 .

[0078] The conductive pillars 24 are formed in the dielectric layer 22 and electrically connect the first and second circuit layers 21 , 23 .

[0079] In one embodiment, the second circuit layer 23 and the plurality of conductive pillars 24 are integrally formed.

[0080] In summary, the packaging substrate and its manufacturing method of the present invention, through the configuration of the heterogeneous layer, can effectively control the thickness of the first circuit layer to be consistent, so that the multiple solder balls can be effectively combined on the first circuit layer, thereby avoiding the problem of the solder balls falling off or not being soldered, so the present invention can improve reliability.

[0081] In addition, due to the configuration of the heterogeneous layer, part of the material of the first circuit layer will not be removed when the heterogeneous layer is removed, thereby effectively preventing the first circuit layer from being eroded. Therefore, the present invention can avoid the problem of damage to the first circuit layer (such as disconnection) to improve the yield of signal transmission between the first circuit layer and the solder ball.

[0082] In addition, when the line width / line spacing (L / S) of the first circuit layer is designed towards miniaturization, the first circuit layer will not be damaged (such as disconnected) due to side corrosion, so as to effectively ensure the normal signal transmission between the first circuit layer and the solder ball. Therefore, the present invention is conducive to the mass production of packaging substrates that need to be equipped with a miniaturized first circuit layer.

[0083] In addition, the manufacturing method of the present invention is applicable to any process of fine circuit specifications, and no matter how thin the carrier is, a groove-free structure can be achieved by coating a thinner heterogeneous layer, which is beneficial to improving the signal transmission speed and packaging yield between the solder ball and the first circuit layer.

[0084] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A method for manufacturing a packaging substrate, comprising: Providing a plate body having a heterogeneous layer thereon; forming a first circuit layer on the heterogeneous layer; Forming a dielectric layer on the heterogeneous layer and the first circuit layer, wherein the dielectric layer is defined with a first surface and a second surface opposite to each other, and the dielectric layer is bonded to the heterogeneous layer via the first surface; Forming a second circuit layer on the second surface of the dielectric layer, and forming a plurality of conductive posts electrically connecting the first circuit layer and the second circuit layer in the dielectric layer; as well as The plate body is separated and the heterogeneous layer is removed by etching to expose the first circuit layer, and the first circuit layer is made flush with the first surface of the dielectric layer.

2. The method for manufacturing a packaging substrate according to claim 1, wherein: The material forming the first circuit layer is different from the material forming the heterogeneous layer.

3. The method for manufacturing a packaging substrate according to claim 1, wherein: A spacing layer is first formed on the plate body, and then the heterogeneous layer is formed on the spacing layer.

4. The method for manufacturing a packaging substrate according to claim 3, wherein: The material forming the spacer layer is different from the material forming the heterogeneous layer.

5. The method for manufacturing a packaging substrate according to claim 3, wherein: The spacer layer is a copper layer.

6. The method for manufacturing a packaging substrate according to claim 1, wherein: The second circuit layer and the plurality of conductive pillars are formed as one piece.

7. The method for manufacturing a packaging substrate according to claim 1, wherein: The heterogeneous layer is a nickel layer or an aluminum layer.

Images