A method and apparatus for fabricating a local isolation oxide layer device structure

Abstract

The application provides a preparation method and device of a local isolation oxide layer device structure, and relates to the technical field of semiconductor manufacturing, and comprises the following steps: comparing the continuous etching workload of phosphoric acid with a preset workload threshold value, determining a target etching reagent for etching the silicon oxynitride layer, calculating the phosphoric acid etching time and the hydrofluoric acid etching time respectively according to the target etching reagent, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the target loss thickness of the pad oxide layer, and completing the etching of the device film layer according to the above-mentioned time. By considering the complex change of the etching rate of the film layer caused by the new and old phosphoric acid in the preparation process of the isolation oxide layer device structure, and combining the target loss thickness of the pad oxide layer film layer in the etching process, the etching time of the film layer by different acids is determined economically and efficiently through the scheme, and the thickness of the pad oxide layer is accurately controlled.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing process, and particularly relates to a preparation method and device of a local isolation oxide layer device structure. BACKGROUND

[0002] LOCOS (LOCal Oxidation of Silicon) is a device isolation technology commonly used in CMOS (Complementary Metal Oxide Semiconductor) silicon process, and silicon selective oxidation is achieved by taking silicon nitride as a mask. Specifically, in the process of local oxidation of silicon, the region to be isolated is opened by photolithography and etching, the isolated region is oxidized by a thermal oxidation process to form an isolation structure, and then the mask layer of silicon nitride is removed by using high-temperature phosphoric acid as an etching agent to obtain a device structure with isolation function.

[0003] In the process of forming a semiconductor device structure by local isolation oxidation, a complex reaction process is involved on the surface of the mask layer of silicon nitride, and a new oxide film layer is formed in the process. The film layer structure of the device from top to bottom is an oxide silicon layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate. In the process of further forming the isolation structure, in order to effectively remove the mask layer and obtain a device structure with local isolation oxidation, the conventional method is to remove the oxide silicon layer by using hydrofluoric acid, remove the silicon oxynitride layer by using hydrofluoric acid or phosphoric acid, and remove the silicon nitride layer by using excessive phosphoric acid. However, the etching rate of the silicon oxynitride film layer varies greatly between new and old phosphoric acid, and excessive etching of the silicon nitride layer by the phosphoric acid etching agent will cause excessive etching of the remaining oxide silicon film layer (i.e. the pad oxide layer) in the active region, so that the thickness of the remaining pad oxide layer cannot meet the requirements, affecting the subsequent process. Therefore, according to the use of phosphoric acid and the etching rate of the silicon oxynitride layer in the current process, it is particularly important to select a suitable target etching agent to etch the silicon oxynitride layer. Selecting a suitable target etching agent to etch the silicon oxynitride layer can ensure that the etching is completed in the shortest time without film layer residue, and also ensure that the thickness of the remaining pad oxide layer meets the requirements. SUMMARY

[0004] Therefore, the purpose of the present application is to provide at least a preparation method and device of a local isolation oxide layer device structure. By considering the influence of new and old phosphoric acid on the etching rate of phosphoric acid, it is determined which etching agent is used to etch the silicon oxynitride layer, and then the etching time of the phosphoric acid and hydrofluoric acid agent is determined. The target limit can improve production efficiency and reduce excessive etching of the pad oxide layer in the etching process, thereby avoiding affecting the subsequent ion implantation process.

[0005] The present application mainly includes the following aspects:

[0006] In a first aspect, the embodiments of the present application provide a preparation method of a local isolation oxide layer device structure, comprising: providing a wafer processed by a thermal oxidation process, the wafer comprising an oxide isolation structure and, from top to bottom, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate; measuring the wafer to determine the thicknesses of the silicon oxide layer, the silicon nitride layer and the silicon oxynitride layer; determining a first etching rate of a hydrofluoric acid reagent on the silicon oxide layer, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, wherein the third etching rate and the fifth etching rate vary with a continuous etching workload of the phosphoric acid, and the continuous etching workload of the phosphoric acid is the cumulative time of etching the wafer from the beginning of a new acid of the phosphoric acid; obtaining a target loss thickness of the pad oxide layer in a continuous etching process; comparing the continuous etching workload of the phosphoric acid with a preset workload threshold, and determining a target etching reagent according to a comparison result, the target etching reagent being a reagent selected to remove the silicon oxynitride layer, and the target etching reagent being the hydrofluoric acid reagent or the phosphoric acid reagent; calculating a phosphoric acid etching time and a hydrofluoric acid etching time according to the target etching reagent, the thicknesses of the silicon oxide layer, the silicon nitride layer and the silicon oxynitride layer, the target loss thickness, the continuous etching workload of the phosphoric acid and the etching rates; and etching the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time using the phosphoric acid reagent and the hydrofluoric acid reagent, wherein the third etching rate is calculated by the following function expression:

[0007] f1(x)=10 -7 x 2 -0.0013x+2.983

[0008] x represents the continuous etching workload of the phosphoric acid, and f1(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous etching workload x of the phosphoric acid;

[0009] The fifth etching rate is calculated by the following function expression:

[0010] f2(x)=9×10 -8 x 2 -0.0007x+1.5945

[0011] f2(x) represents the fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer under the continuous etching workload x of the phosphoric acid.

[0012] In a possible implementation, the target etching agent is determined in the following manner: if the continuous etching workload of phosphoric acid is less than a preset workload threshold, the phosphoric acid agent is taken as the target etching agent; if the continuous etching workload of phosphoric acid is greater than or equal to the preset workload threshold, the hydrofluoric acid agent is taken as the target etching agent, and the preset workload threshold is 1500 min.

[0013] In a possible implementation, the hydrofluoric acid etching time includes the etching time of the hydrofluoric acid agent on the silicon oxide layer, and the phosphoric acid etching time includes the etching time of the phosphoric acid agent on the silicon oxynitride layer, the etching time of the phosphoric acid agent on the silicon nitride layer, and the etching time of the phosphoric acid agent on the pad oxide layer, wherein the phosphoric acid etching time and the hydrofluoric acid etching time are determined in the following manner: if the target etching agent is the phosphoric acid agent, the etching time of the hydrofluoric acid agent on the silicon oxide layer is determined according to the silicon oxide layer thickness, the first etching rate, and the first over-etching coefficient; the etching time of the phosphoric acid agent on the silicon oxynitride layer is determined according to the silicon oxynitride layer thickness and the third etching rate; the etching time of the phosphoric acid agent on the silicon nitride layer is determined according to the silicon nitride layer thickness, the fourth etching rate of the phosphoric acid agent on the silicon nitride layer, and the second over-etching coefficient; and the etching time of the phosphoric acid agent on the pad oxide layer is determined according to the target loss thickness of the pad oxide layer and the fifth etching rate.

[0014] In a possible implementation, the etching time of the hydrofluoric acid agent on the silicon oxide layer is determined by the following formula:

[0015]

[0016] In the formula, T(HF1) represents the etching time of the hydrofluoric acid agent on the silicon oxide layer, X represents the silicon oxide layer thickness, E1 represents the first etching rate, and n1 represents the first over-etching coefficient. a

[0017] In a possible implementation, the etching time of the phosphoric acid agent on the silicon oxynitride layer, the etching time of the phosphoric acid agent on the silicon nitride layer, and the etching time of the phosphoric acid agent on the pad oxide layer are determined by the following formula:

[0018]

[0019] In the formula, T(HPO1) represents the etching time of the phosphoric acid agent on the silicon oxynitride layer, M represents the silicon oxynitride layer thickness, E1 represents the third etching rate of the phosphoric acid agent on the silicon oxynitride layer, T(HPO2) represents the etching time of the phosphoric acid agent on the silicon nitride layer, Y represents the silicon nitride layer thickness, E2 represents the fourth etching rate of the phosphoric acid agent on the silicon nitride layer, and n2 represents the second over-etching coefficient. b ​E2 = f2(x), f2(x) represents a function expression of the etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer varying with the continuous etching work amount of the phosphoric acid, and the fifth etching rate E2 is obtained by bringing the continuous etching work amount of the phosphoric acid into f2(x).

[0020] In a possible implementation, the phosphoric acid etching time further includes a total phosphoric acid etching time of etching the wafer by using the phosphoric acid reagent, wherein the total phosphoric acid etching time T(HPO) is determined by the following formula:

[0021] .

[0022] In a possible implementation, the hydrofluoric acid etching time includes an etching time of etching the silicon oxide layer by using the hydrofluoric acid reagent and an etching time of etching the silicon nitride layer by using the hydrofluoric acid reagent, and the phosphoric acid etching time includes an etching time of etching the silicon nitride layer by using the phosphoric acid reagent and an etching time of etching the pad oxide layer by using the phosphoric acid reagent, wherein the phosphoric acid etching time and the hydrofluoric acid etching time are determined in the following manner: if the target etching reagent is the hydrofluoric acid reagent, the etching time of etching the silicon oxide layer by using the hydrofluoric acid reagent is determined according to the silicon oxide layer thickness, the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, and the first over-etching coefficient; the etching time of etching the silicon oxynitride layer by using the hydrofluoric acid reagent is determined according to the silicon oxynitride layer thickness and the second etching rate; the etching time of etching the silicon nitride layer by using the phosphoric acid reagent is determined according to the silicon nitride layer thickness, the fourth etching rate of the phosphoric acid reagent on the silicon nitride, and the second over-etching coefficient; and the etching time of etching the pad oxide layer by using the phosphoric acid reagent is determined according to the target loss thickness of the pad oxide layer and the fifth etching rate.

[0023] In a possible implementation, the phosphoric acid etching time and the hydrofluoric acid etching time are determined by the following formula:

[0024]

[0025] In the formula, T(HF1) represents the etching time of etching the silicon oxide layer by using the hydrofluoric acid reagent, X represents the silicon oxide layer thickness, E a represents the first etching rate, n1 represents the first over-etching coefficient; T(HF2) represents the etching time of etching the silicon oxynitride layer by using the hydrofluoric acid reagent, M represents the silicon oxynitride layer thickness, Ec represents the second etching rate of the hydrofluoric acid reagent to the silicon oxynitride layer, T(HPO2) represents the etching time of the phosphoric acid reagent to the silicon nitride layer, Y represents the thickness of the silicon nitride layer, E b represents the fourth etching rate of the phosphoric acid reagent to the silicon nitride layer, n2 represents the second over-etching coefficient; T(HPO3) represents the etching time of the phosphoric acid reagent to the pad oxide layer, S represents the target loss thickness of the pad oxide layer, E2 represents the fifth etching rate of the phosphoric acid reagent to the pad oxide layer, wherein E1 = f1(x), f1(x) represents a functional expression of the change of the etching rate of the phosphoric acid reagent to the silicon oxynitride layer with the continuous etching workload of the phosphoric acid, the continuous etching workload of the phosphoric acid is brought into f1(x) to obtain the third etching rate E1 of the phosphoric acid reagent to the silicon oxynitride layer, E2 = f2(x), f2(x) represents a functional expression of the change of the etching rate of the phosphoric acid reagent to the silicon oxide layer and the pad oxide layer with the continuous etching workload of the phosphoric acid, the continuous etching workload of the phosphoric acid is brought into f2(x) to obtain the fifth etching rate E2.

[0026] In a possible implementation, the phosphoric acid etching time further includes total phosphoric acid etching time of etching the wafer using the phosphoric acid reagent, and the hydrofluoric acid etching time further includes total hydrofluoric acid etching time of etching the wafer using the hydrofluoric acid reagent.

[0027] wherein the total phosphoric acid etching time T(HPO) and the total hydrofluoric acid etching time T(HF) are determined by the following formula:

[0028] .

[0029] In a second aspect, the embodiments of the present application further provide a device structure for locally isolating an oxide layer, comprising: a providing module configured to provide a wafer processed by a thermal oxidation process, the wafer comprising an oxide isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom; a measuring module configured to measure the wafer to determine a thickness of the silicon oxide layer, a thickness of the silicon nitride layer and a thickness of the silicon oxynitride layer; an etching rate determining module configured to determine a first etching rate of hydrofluoric acid reagent on the silicon oxide layer, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, respectively, wherein the third etching rate and the fifth etching rate vary with a continuous etching workload of the phosphoric acid, and the continuous etching workload of the phosphoric acid is a cumulative time of etching the wafer from a new acid of the phosphoric acid; an obtaining module configured to obtain a target loss thickness of the pad oxide layer in a continuous etching process; a comparing module configured to compare the continuous etching workload of the phosphoric acid with a preset workload threshold, and determine a target etching reagent according to a comparison result, the target etching reagent being a reagent selected to remove the silicon oxynitride layer, and the target etching reagent being the hydrofluoric acid reagent or the phosphoric acid reagent; a calculating module configured to calculate a phosphoric acid etching time and a hydrofluoric acid etching time according to the target etching reagent, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer, the target loss thickness, the continuous etching workload of the phosphoric acid and the etching rates, respectively; and an etching module configured to use the phosphoric acid reagent and the hydrofluoric acid reagent to etch the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

[0030] The third etching rate is calculated by the following function expression:

[0031] f1(x)=10 -7 x 2 -0.0013x+2.983

[0032] x represents the continuous etching workload of the phosphoric acid, and f1(x) represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer under the continuous etching workload x of the phosphoric acid.

[0033] The fifth etching rate is calculated by the following function expression:

[0034] f2(x)=9×10 -8 x 2 -0.0007x+1.5945

[0035] f2(x) represents the fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer under the continuous etching workload x of the phosphoric acid.

[0036] The embodiment of the present application provides a preparation method and device of a local isolation oxide layer device structure, which comprises the following steps: determining a target etching reagent for etching a nitride oxide layer according to a continuous etching workload of phosphoric acid; calculating a phosphoric acid etching time and a hydrofluoric acid etching time respectively according to the target etching reagent, a silicon oxide layer thickness, a silicon nitride layer thickness, a silicon nitride oxide layer thickness, a target loss thickness, the continuous etching workload of phosphoric acid and an etching rate; and completing etching of the silicon oxide layer, the silicon nitride oxide layer and the silicon nitride layer of a wafer by using the phosphoric acid reagent and the hydrofluoric acid reagent according to the phosphoric acid etching time and the hydrofluoric acid etching time. The present application considers the influence of the complex change of the etching rate of the film layer caused by the new and old acid of phosphoric acid on the wafer etching process in the preparation process of the isolation oxide layer device structure, combines the target loss thickness of the pad oxide layer film layer in the etching process, economically and efficiently determines the optimal etching time of the etching reagent for making the thickness loss of the pad oxide layer in the expected loss range, avoids excessive etching of the pad oxide layer, realizes accurate control of the thickness of the pad oxide layer, and thus reduces the damage of the wafer caused by excessive loss of the pad oxide layer in the subsequent ion implantation process.

[0037] In order to make the above objectives, characteristics and advantages of the present application more apparent and comprehensible, the following will specifically describe a preferred embodiment in combination with the accompanying drawings, and the detailed description is as follows. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without paying creative labor on the basis of these drawings.

[0039] Figure 1 A schematic diagram of a silicon local oxidation process provided by the embodiment of the present application is shown;

[0040] Figure 2 A schematic diagram of a silicon nitride removal process provided by the embodiment of the present application is shown;

[0041] Figure 3 A flow chart of a preparation method of a local isolation oxide layer device structure provided by the embodiment of the present application is shown;

[0042] Figure 4 A schematic diagram of a wafer structure obtained after a thermal oxidation process provided by the embodiment of the present application is shown;

[0043] Figure 5 A trend chart of the etching rate of a phosphoric acid reagent on a silicon nitride oxide with the cumulative use workload of the new acid of phosphoric acid (the cumulative time of etching the wafer from the new acid of phosphoric acid) is shown;

[0044] Figure 6 A trend chart of etching rate of phosphoric acid reagent on silicon oxide with cumulative use of fresh phosphoric acid (from the fresh phosphoric acid, the cumulative time of etching the wafer) is shown;

[0045] Figure 7 A functional module diagram of a preparation device of a local isolation oxide layer device structure provided by an embodiment of the present application is shown.

[0046] Figure 8 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowcharts in the present application show the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowcharts or one or more operations can be removed from the flowcharts under the guidance of the content of the present application.

[0048] In addition, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work belong to the scope of protection of the present application.

[0049] Silicon local oxidation is a commonly used device isolation technology in CMOS silicon process, which realizes selective oxidation of silicon by taking silicon nitride as a mask. Please refer to Figure 1 , Figure 1 A schematic diagram of a silicon local oxidation process provided by an embodiment of the present application is shown. As Figure 1B1, a pad oxide layer 105 and a silicon nitride layer 104 are first grown on a silicon substrate 106, as shown in B2, the region to be isolated is opened by lithography and etching, the region to be isolated is treated by thermal oxidation, an oxide isolation structure 101 is formed, the composition of the oxide isolation structure 101 is silicon oxide, and the silicon nitride layer 104 further has a silicon oxynitride layer 103 and a silicon oxide layer 102 Figure 1 which is not shown in the figure, the silicon oxide layer 102 is then removed by using hydrofluoric acid as an etchant, the silicon oxynitride layer 103 is removed by using hydrofluoric acid or phosphoric acid, and the silicon nitride layer 104 is removed by using high-temperature phosphoric acid as an etchant, so as to obtain a device structure with isolation function, as shown in B4.

[0050] Please refer to Figure 2 , Figure 2 which shows a schematic diagram of a silicon nitride removal process provided by an embodiment of the present application. As shown in Figure 1 and Figure 2 , in the process of forming the oxide isolation structure 101 shown in B2-B3, the silicon nitride layer 104 is affected by the thermal oxidation process, and a silicon oxide layer 102 is formed on the surface of the silicon nitride layer 104. A very thin silicon oxynitride layer 103 is formed between the silicon oxide layer 102 and the silicon nitride layer 104. Hydrofluoric acid is a conventional reagent for etching silicon oxide, and phosphoric acid is a conventional reagent for etching silicon nitride. Both hydrofluoric acid and phosphoric acid can form etching effects on silicon oxynitride.

[0051] As shown in B3-B4 of Figure 1 , the conventional removal method of the silicon nitride layer 104 is to first remove the silicon oxide layer 102 formed on the surface of the silicon nitride layer 104 by using hydrofluoric acid, then rinse the hydrofluoric acid with water, then remove the silicon nitride layer 104 by using phosphoric acid, and finally rinse the phosphoric acid with water.

[0052] In the process of etching the silicon nitride layer 104 by using phosphoric acid, the conventional method is to remove the silicon nitride layer 104 by using excessive phosphoric acid. However, it is found that in the process of etching the silicon nitride layer 104 by using excessive phosphoric acid (excessive etching of 50-100%), the excessive use of the etching reagent will cause etching of the pad oxide layer 105. In the prior art, the thickness loss of the pad oxide layer 105 cannot be mastered, and thus excessive etching of the pad oxide layer 105 often occurs. Since the thickness of the pad oxide layer 105 directly affects the ion implantation process of the semiconductor device, if the thickness of the pad oxide layer 105 does not meet the requirements of the ion implantation process, the electrical properties of the semiconductor device will be further affected.

[0053] Based on this, the embodiment of the present application provides a silicon nitride layer removing method and device based on a local oxidation process. By considering the different etching reagents for removing the silicon nitride layer at the beginning of the process, the overall etching time is reduced, the overall etching efficiency is improved, the excessive etching of the remaining silicon oxide layer is reduced, the impact of the subsequent ion implantation process on the device electrical property is reduced, and the method is specific as follows.

[0054] Please refer to Figure 3 , Figure 3 A flowchart of a preparation method of a local isolation oxide layer device structure provided by the embodiment of the present application is shown. Please refer to Figure 4 , Figure 4 A schematic diagram of a wafer structure obtained after a thermal oxidation process is shown. As shown in Figure 3 and Figure 4 , the method provided by the embodiment of the present application includes the following steps:

[0055] S100, providing a wafer processed by a thermal oxidation process.

[0056] The wafer has an oxidation isolation structure 101 and a silicon oxide layer 102, a silicon oxynitride layer 103, a silicon nitride layer 104, a pad oxide layer 105 and a silicon substrate 106 stacked in sequence from top to bottom.

[0057] S200, measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the thickness of the silicon oxynitride layer.

[0058] The thickness of the silicon oxide layer is the thickness corresponding to the silicon oxide layer 102, and the thickness of the silicon nitride layer is the thickness corresponding to the silicon nitride layer 104.

[0059] S300, determining the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer and the fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, respectively.

[0060] Among them, the third etching rate and the fifth etching rate vary with the continuous etching workload of phosphoric acid, and the continuous etching workload of phosphoric acid is the cumulative time of etching the wafer from the beginning of the new acid of phosphoric acid.

[0061] S400, obtaining a target loss thickness of the pad oxide layer in the continuous etching process.

[0062] The continuous etching workload of phosphoric acid is the current continuous etching workload of the phosphoric acid reagent.

[0063] S500, comparing the continuous etching workload of phosphoric acid with a preset workload threshold, and determining a target etching reagent according to the comparison result.

[0064] The target etching reagent is a reagent selected for removing the silicon oxynitride layer 103, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent.

[0065] The target etching reagent is a reagent selected for removing the silicon oxynitride layer 103, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent.

[0066] S600, according to the target etching reagent, the silicon oxide layer thickness, the silicon nitride layer thickness, the silicon oxynitride layer thickness, the target loss thickness, the phosphoric acid continuous etching workload and the etching rate, the phosphoric acid etching time and the hydrofluoric acid etching time are calculated respectively.

[0067] S700, using the phosphoric acid reagent and the hydrofluoric acid reagent, the etching of the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer on the wafer is completed according to the phosphoric acid etching time and the hydrofluoric acid etching time.

[0068] In the local isolation oxidation technology, the silicon nitride layer 104 on the wafer undergoes the following reactions in the process of thermal oxidation:

[0069] Si3N4(s)+ 3 / 2O2(g) →3SiO(g)+ 2N2(g) ------ A.1

[0070] Si3N4(s)+ 3O2(g) →3SiO2(g)+ 2N2(g) ------ A.2

[0071] Si3N4(s)+ 5O2(g) →3SiO2(g)+ 4NO (g) ------ A.3

[0072] 4Si3N4(s)+ 3O2(g) →6Si2N2O (g)+ 2N2(g) ------ A.4

[0073] From chemical equations A.1~ A.3 and combined, in the process of forming an oxidation isolation structure by thermal oxidation of the silicon nitride layer 104, the surface of the silicon nitride layer 104 is affected by the thermal process of the silicon oxide, and an oxide layer 102 is formed on the surface of the silicon nitride layer 104. It can be known from chemical equation A.4 that under certain temperature conditions (for example, the temperature is controlled between 700℃~1180℃), an interface layer, i.e. a silicon oxynitride layer 103, can be formed between the silicon oxide layer 102 and the silicon nitride layer 104. The silicon oxynitride layer 103 is an interface conversion layer in the oxidation process of silicon nitride. In the prior art, phosphoric acid is repeatedly used, and its effective components change gradually with use. Therefore, the etching rate of the film layer also changes constantly with use.

[0074] In the prior art, in the process of removing the silicon nitride layer 104, the silicon oxide layer 102 is first cleaned using hydrofluoric acid, and then the silicon nitride layer 104 is cleaned using phosphoric acid. The silicon oxynitride layer 103 formed between the silicon nitride layer 104 and the silicon oxide layer 102 can be etched using hydrofluoric acid or phosphoric acid. However, the etching rates of the silicon oxynitride layer 103 using hydrofluoric acid and phosphoric acid are inconsistent, which leads to different etching times.

[0075] In addition, since the composition of the pad oxide layer 105 is silicon oxide, in the process of over-etching the silicon nitride layer 104 using the phosphoric acid reagent, the phosphoric acid will etch the pad oxide layer 105. The thickness of the pad oxide layer 105 directly affects the subsequent ion implantation process. However, due to the over-etching of the phosphoric acid in the prior art, the remaining thickness of the pad oxide layer 105 cannot be controlled, which may not meet the requirements of the subsequent ion implantation process, thereby affecting the electrical properties of the semiconductor device.

[0076] Therefore, in steps S100-S700 of the present application, the etching effect of the phosphoric acid reagent is affected by the age of the phosphoric acid. As the continuous etching workload of the phosphoric acid increases, the etching effect of the phosphoric acid reagent gradually decreases. Based on this, the present application compares the continuous etching workload of the phosphoric acid with a preset workload threshold. Based on the etching effect that can be achieved by the phosphoric acid reagent, the target etching reagent for removing the silicon nitride layer 104 is determined. In combination with the thickness of the silicon oxide layer 102, the thickness of the silicon nitride layer 104, the thickness of the silicon oxynitride layer 103, the target loss thickness , the continuous etching workload of the phosphoric acid, and the etching rate, the etching time of the phosphoric acid and the etching time of the hydrofluoric acid are determined, thereby avoiding over-etching of the thickness of the pad oxide layer 105 and reducing the impact of the subsequent ion implantation process on the electrical properties of the device. The preset workload threshold is 1500 minutes.

[0077] In a preferred embodiment, in step S200, the silicon nitride layer 104, the silicon oxynitride layer 103, and the silicon oxide layer 102 are measured respectively to obtain the thickness X of the silicon oxide layer, the thickness Y of the silicon nitride layer, and the thickness M of the silicon oxynitride layer. The thickness M of the silicon oxynitride layer generally ranges from 8 Å to 16 Å, and M = 13 Å is generally taken, where Å is the length unit Angstrom.

[0078] In step S300, it can be known from the use of the phosphoric acid reagent and the hydrofluoric acid reagent that the first etching rate E a of the hydrofluoric acid reagent on the silicon oxide layer 102, the fourth etching rate E b of the phosphoric acid reagent on the silicon nitride layer 104, and the second etching rate E cGenerally, the second etching rate E c = 1.26 Å / min.

[0079] Specifically, it is also necessary to determine the phosphoric acid continuous etching workload x corresponding to the phosphoric acid new acid reagent. The phosphoric acid continuous etching workload x is the cumulative time of etching wafers from the phosphoric acid new acid. The phosphoric acid continuous etching workload x reflects the degree of new and old phosphoric acid. For example, the phosphoric acid continuous etching workload x = the time required for etching a single wafer × the number of accumulated etched wafer pieces.

[0080] In a preferred embodiment, in step S400, the target loss thickness S corresponding to the pad oxide layer 105 is also determined. The target loss thickness S is determined according to actual requirements.

[0081] In a preferred embodiment, step S500 includes:

[0082] If the phosphoric acid continuous etching workload is less than the preset workload threshold, the phosphoric acid reagent is used as the target etching reagent. If the phosphoric acid continuous etching workload is greater than or equal to the preset workload threshold, the hydrofluoric acid reagent is used as the target etching reagent.

[0083] In an example, the preset workload threshold can be set to 1500 min, and the phosphoric acid continuous etching workload corresponding to the phosphoric acid reagent is fed back by the upper computer in advance.

[0084] In a preferred embodiment, the hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer 102, and the phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon nitride layer 104, the etching time of the phosphoric acid reagent on the pad oxide layer 105, and the etching time of the phosphoric acid reagent on the pad oxide layer 105.

[0085] In a preferred embodiment, step S600 includes:

[0086] If the target etching reagent is the phosphoric acid reagent, the etching time of the hydrofluoric acid reagent on the silicon oxide layer 102 is determined according to the thickness of the silicon oxide layer 102, the first etching rate E a and the first excess etching coefficient n1, the etching time of the phosphoric acid reagent on the silicon nitride layer 104 is determined according to the thickness of the silicon nitride layer 104, the fourth etching rate E b of the phosphoric acid reagent on the silicon nitride layer 104, and the second excess etching coefficient n2, the etching time of the phosphoric acid reagent on the pad oxide layer 105 is determined according to the target loss thickness S corresponding to the pad oxide layer 105 and the fifth etching rate E2.

[0087] Preferably, the first over-etching coefficient n1 and the second over-etching coefficient n2 are generally set to 1.2-2, which can be set according to actual requirements.

[0088] In a specific embodiment, when the target etching reagent is a phosphoric acid reagent, the etching time T(HF1) of the hydrofluoric acid reagent for etching the silicon oxide layer 102 is determined by the following formula:

[0089]

[0090] In another specific embodiment, the etching time T(HPO1) of the phosphoric acid reagent for etching the silicon oxynitride layer 103, the etching time T(HPO2) of the phosphoric acid reagent for etching the silicon nitride layer 104, and the etching time T(HPO3) of the phosphoric acid reagent for etching the pad oxide layer 105 are determined by the following formula:

[0091]

[0092] In an example, E a = 26Å / min, E b = 50 Å / min.

[0093] In the formula, T(HPO1) represents the etching time of the phosphoric acid reagent for etching the silicon oxynitride layer, M represents the thickness of the silicon oxynitride layer, and E1 represents the third etching rate of the phosphoric acid reagent for etching the silicon oxynitride layer.

[0094] T(HPO2) represents the etching time of the phosphoric acid reagent for etching the silicon nitride layer, Y represents the thickness of the silicon nitride layer, E b represents the fourth etching rate, and n2 represents the second over-etching coefficient.

[0095] T(HPO3) represents the etching time of the phosphoric acid reagent for etching the pad oxide layer, S represents the target loss thickness of the pad oxide layer, and E2 represents the fifth etching rate of the phosphoric acid reagent for etching the pad oxide layer.

[0096] E1= f1(x), f1(x) represents a functional expression of the etching rate of the phosphoric acid reagent for etching the silicon oxynitride layer changing with the continuous etching work amount of the phosphoric acid, and the continuous etching work amount x of the phosphoric acid is brought into f1(x) to obtain the third etching rate E1 of the phosphoric acid reagent for etching the silicon oxynitride layer.

[0097] E2= f2(x), f2(x) represents a functional expression of the etching rate of the phosphoric acid reagent for etching the silicon oxide layer and the pad oxide layer changing with the continuous etching work amount of the phosphoric acid, and the continuous etching work amount x of the phosphoric acid is brought into f2(x) to obtain the fifth etching rate E2.

[0098] In a specific embodiment, please refer to Figure 5 , Figure 5A trend chart showing the change of the etching rate of the phosphoric acid reagent on silicon oxide with the cumulative use amount of the fresh phosphoric acid (the cumulative time of etching wafers from the fresh phosphoric acid) is shown. As shown in Figure 5 , the abscissa is the continuous etching amount x of phosphoric acid, the time unit is min (minute), the ordinate represents the etching rate of the phosphoric acid reagent on silicon oxide, the etching rate unit is Å / min (Angstrom / minute), L1 represents the first curve of the third etching rate changing with the continuous etching amount x of phosphoric acid, and the function expression f1(x)=10 - 7 x 2 -0.0013x+2.983 is created from the first curve L1. The third etching rate E1 of the phosphoric acid reagent on the silicon oxide layer 103 at the continuous etching amount x of phosphoric acid can be obtained by bringing the continuous etching amount x of phosphoric acid into f1(x).

[0099] Figure 5 The middle line represents the second etching rate E c of the hydrofluoric acid reagent on silicon oxide, and the second etching rate E c of the hydrofluoric acid reagent on silicon oxide is constant at 1.26 Å / min. It can be known from Figure 5 that when the third etching rate of phosphoric acid on silicon oxide is equal to the second etching rate E c of the hydrofluoric acid reagent on silicon oxide, the corresponding continuous etching amount of phosphoric acid is x a , when the corresponding continuous etching amount of phosphoric acid of the phosphoric acid reagent is less than x a , the etching rate of the phosphoric acid reagent on silicon oxide is greater than that of the hydrofluoric acid reagent on silicon oxide, and when the corresponding continuous etching amount of phosphoric acid of the phosphoric acid reagent is greater than x a , the etching rate of the phosphoric acid reagent on silicon oxide is less than that of the hydrofluoric acid reagent on silicon oxide.

[0100] Please refer to Figure 6 , Figure 6 A trend chart showing the change of the etching rate of the phosphoric acid reagent on silicon oxide with the cumulative use amount of the fresh phosphoric acid (the cumulative time of etching wafers from the fresh phosphoric acid) is shown. As shown in Figure 6 , the abscissa is the continuous etching amount x of phosphoric acid, i.e., the product x of the cumulative number of etched wafers and the required time per wafer unit of phosphoric acid etching from the fresh phosphoric acid, and the ordinate represents the etching rate of the phosphoric acid reagent on silicon oxide, the etching rate unit is Å / min, L2 represents the second curve of the etching rate of the phosphoric acid reagent on silicon oxide changing with the continuous etching amount of phosphoric acid, and the function expression f2(x)=9×10 -8 x 2-0.0007x+1.5945, since the composition of the pad oxide layer is silicon oxide, the phosphoric acid continuous etching workload x is brought into f2(x)=9x10 - 8 x 2 -0.0007x+1.5945, namely the fifth etching rate E2 of the phosphoric acid reagent to the pad oxide layer under the phosphoric acid continuous etching workload x.

[0101] In addition, the phosphoric acid etching time further includes a total phosphoric acid etching time of etching the wafer by using the phosphoric acid reagent, and the total phosphoric acid etching time T(HPO) is:

[0102] .

[0103] In another preferred embodiment, the hydrofluoric acid etching time includes an etching time of etching the silicon oxide layer 102 by using the hydrofluoric acid reagent and an etching time of etching the silicon oxynitride layer 103 by using the hydrofluoric acid reagent, and the phosphoric acid etching time includes an etching time of etching the silicon nitride layer 104 by using the phosphoric acid reagent and an etching time of etching the pad oxide layer 105 by using the phosphoric acid reagent.

[0104] In a preferred embodiment, the step S500 further includes:

[0105] If the target etching reagent is the hydrofluoric acid reagent, the etching time T(HF1) of etching the silicon oxide layer 102 by using the hydrofluoric acid reagent is determined according to the thickness X of the silicon oxide layer 102, the first etching rate E a of the hydrofluoric acid reagent to the silicon oxide layer 102, and the first over-etching coefficient n1.

[0106] The etching time T(HF2) of etching the silicon oxynitride layer 103 by using the hydrofluoric acid reagent is determined according to the thickness M of the silicon oxynitride layer and the second etching rate E c .

[0107] The etching time T(HPO2) of etching the silicon nitride layer 104 by using the phosphoric acid reagent is determined according to the thickness Y of the silicon nitride layer 104, the fourth etching rate E b of the phosphoric acid reagent to the silicon nitride layer, and the second over-etching coefficient n2.

[0108] The etching time T(HPO3) of etching the pad oxide layer 105 by using the phosphoric acid reagent is determined according to the target loss thickness S of the pad oxide layer 105 and the fifth etching rate E2.

[0109] Preferably, the etching time of etching the silicon oxide layer 102 by using the hydrofluoric acid reagent and the etching time of etching the silicon oxynitride layer 103 by using the hydrofluoric acid reagent, and the phosphoric acid etching time include the etching time of etching the silicon nitride layer 104 by using the phosphoric acid reagent and the etching time of etching the pad oxide layer 105 by using the phosphoric acid reagent are determined by the following formula:

[0110]

[0111] In the formula, the fifth etching rate E2 is determined by f2(x) and the continuous etching amount x of phosphoric acid, which is not described herein.

[0112] In addition, the phosphoric acid etching time further includes the total phosphoric acid etching time of etching the wafer by using the phosphoric acid reagent, and the hydrofluoric acid etching time further includes the total hydrofluoric acid etching time of etching the wafer by using the hydrofluoric acid reagent.

[0113] The total phosphoric acid etching time T(HPO) and the total hydrofluoric acid etching time T(HF) are determined by the following formula:

[0114]

[0115] In a specific embodiment, it is assumed that the thickness X of the silicon oxide layer 102 is 80 Å, the thickness Y of the silicon nitride layer 104 is 1000 Å, the first etching rate E1 of the hydrofluoric acid reagent to the silicon oxide layer 102 is 26 Å / min, the fourth etching rate E4 of the phosphoric acid reagent to the silicon nitride layer 104 is 50 Å / min, the first over-etching coefficient n1 is 1.3, the second over-etching coefficient n2 is 1.3, the target loss thickness S of the pad oxide layer 105 is 15±5 Å, the thickness M of the silicon oxynitride layer 103 is 13 Å, and the preset work amount threshold is 1500 min. a b

[0116] When the continuous etching amount x of phosphoric acid is 700 min, the third etching rate E1 of the phosphoric acid reagent to the silicon oxynitride layer 103 is greater than the second etching rate E2 of the hydrofluoric acid reagent to the silicon oxynitride layer 103, i.e., E1>E2, at this time, the silicon oxynitride layer 103 is etched by using the phosphoric acid reagent as the target etching reagent, and the total hydrofluoric acid etching time T(HF) is 3.99 min and the total phosphoric acid etching time T(HPO) is 36.13 min. c

[0117] When the continuous etching amount x of phosphoric acid is 1800 min, the third etching rate E1 of the phosphoric acid reagent to the silicon oxynitride layer 103 is less than the second etching rate E2 of the hydrofluoric acid reagent to the silicon oxynitride layer 103, i.e., E1 c , the silicon oxynitride layer 103 is etched by using the hydrofluoric acid reagent as the target etching reagent, the total hydrofluoric acid etching time T(HF) is 14.30 min, and the total phosphoric acid etching time T(HPO) is 34 min.

[0118] ​​​Based on the same application concept, the embodiment of the present application also provides a wafer etching device corresponding to the wafer etching method provided by the above embodiment. Since the principle of solving problems in the device of the embodiment of the present application is similar to that of the wafer etching method of the above embodiment of the present application, the implementation of the device can be referred to the implementation of the method, and the repeated parts will not be described here.

[0119] Please refer to Figure 7 , Figure 7 A functional module diagram of a preparation device of a local isolation oxide layer device structure provided by the embodiment of the present application is shown. The device comprises:

[0120] The module 800 is provided for providing a wafer processed by a thermal oxidation process, and the wafer is formed with an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom.

[0121] The measurement module 810 is used for measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the thickness of the silicon oxynitride layer.

[0122] The etching rate determination module 820 is used for determining the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer and the fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, respectively. The third etching rate and the fifth etching rate vary with the continuous etching workload of the phosphoric acid, and the continuous etching workload of the phosphoric acid is the cumulative time of etching the wafer from the beginning of the new acid of the phosphoric acid.

[0123] The acquisition module 830 is used for acquiring the target loss thickness of the pad oxide layer in the continuous etching process.

[0124] The comparison module 840 is used for comparing the continuous etching workload of the phosphoric acid with the preset workload threshold, and determining the target etching reagent according to the comparison result. The target etching reagent is the reagent selected for removing the silicon oxynitride layer, and the target etching reagent is the hydrofluoric acid reagent or the phosphoric acid reagent.

[0125] The calculation module 850 is used for calculating the phosphoric acid etching time and the hydrofluoric acid etching time, respectively, according to the target etching reagent, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer, the target loss thickness, the continuous etching workload of the phosphoric acid and the etching rate.

[0126] The etching module 860 is used for using the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

[0127] Based on the same application concept, please refer to Figure 8, Figure 8 A structure schematic diagram of an electronic device provided by an embodiment of the present application is shown. The electronic device 900 comprises a processor 910, a memory 920 and a bus 930. The memory 920 stores machine readable instructions executable by the processor 910. When the electronic device 900 is running, the processor 910 and the memory 920 communicate through the bus 930. The machine readable instructions are executed by the processor 910 to perform the steps of the preparation method of the partial isolation oxide layer device structure provided by any one of the above embodiments.

[0128] Based on the same application concept, the present application further provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to perform the steps of the preparation method of the partial isolation oxide layer device structure provided by any one of the above embodiments.

[0129] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system and device can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here. In the several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented by other ways. The device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interface, device or unit, and can be electrical, mechanical or other forms.

[0130] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the present embodiment.

[0131] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0132] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the parts of the present application that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0133] The above merely describes the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a locally isolated oxide layer device structure, characterized in that, The method includes: Provided a wafer after thermal oxidation process, wherein an oxide isolation structure is formed and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate are stacked from top to bottom; The wafer is measured to determine the thickness of the silicon oxide layer, the silicon nitride layer, and the silicon oxynitride layer; The first etching rate of the silicon oxide layer, the second etching rate of the silicon oxynitride layer, the third etching rate of the silicon oxynitride layer, the fourth etching rate of the silicon nitride layer, and the fifth etching rate of the silicon oxide layer and the pad oxide layer were determined by the phosphoric acid reagent. The third and fifth etching rates varied with the continuous etching workload of the phosphoric acid, which was the cumulative time of etching the wafer from the start of the new phosphoric acid acid. To obtain the target loss thickness of the pad oxide layer during continuous etching; The continuous etching workload of phosphoric acid is compared with a preset workload threshold. Based on the comparison result, a target etching reagent is determined. The target etching reagent is a reagent selected to remove the silicon oxynitride layer. The target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent. The preset workload threshold is 1500 min. Based on the target etching reagent, silicon oxide layer thickness, silicon nitride layer thickness, silicon oxynitride layer thickness, target loss thickness, phosphoric acid continuous etching workload, and etching rate, the phosphoric acid etching time and hydrofluoric acid etching time are calculated respectively. The silicon oxide layer, silicon oxynitride layer, and silicon nitride layer of the wafer are etched using phosphoric acid reagent and hydrofluoric acid reagent, according to the phosphoric acid etching time and the hydrofluoric acid etching time. The third etching rate is calculated using the following functional expression: f1(x) = 10 -7 x 2 -0.0013x + 2.983 x represents the continuous etching workload of phosphoric acid, and f1(x) represents the third etching rate of the silicon oxynitride layer by the phosphoric acid reagent at the continuous etching workload of phosphoric acid x. The fifth etching rate is calculated using the following functional expression: f2(x) = 9x10 -8 x 2 -0.0007x + 1.5945 f2(x) represents the fifth etching rate of the silicon oxide layer and the pad oxide layer by the phosphoric acid reagent under the continuous phosphoric acid etching workload x.

2. The method according to claim 1, characterized in that, The target etching reagent is determined using the following method: If the continuous etching workload of phosphoric acid is less than the preset workload threshold, then the phosphoric acid reagent will be used as the target etching reagent. If the continuous etching workload of phosphoric acid is greater than or equal to the preset workload threshold, then the hydrofluoric acid reagent is used as the target etching reagent.

3. The method according to claim 1, characterized in that, The hydrofluoric acid etching time includes the etching time for the hydrofluoric acid reagent to etch the silicon oxide layer, and the phosphoric acid etching time includes the etching time for the phosphoric acid reagent to etch the silicon oxynitride layer, the etching time for the phosphoric acid reagent to etch the silicon nitride layer, and the etching time for the phosphoric acid reagent to etch the pad oxide layer. The phosphoric acid etching time and the hydrofluoric acid etching time are determined in the following ways: If the target etching reagent is a phosphoric acid reagent, the etching time for the hydrofluoric acid reagent to etch the silicon oxide layer is determined based on the silicon oxide layer thickness, the first etching rate, and the first excess etching coefficient. The etching time of the silicon oxynitride layer by the phosphoric acid reagent is determined based on the thickness of the silicon oxynitride layer and the third etching rate. The etching time for etching the silicon nitride layer with phosphoric acid is determined based on the thickness of the silicon nitride layer, the fourth etching rate of the silicon nitride layer with phosphoric acid, and the second excess etching coefficient. Based on the target loss thickness corresponding to the pad oxide layer and the fifth etching rate, the etching time of the phosphate reagent on the pad oxide layer is determined, wherein the first excess etching coefficient and the second excess etching coefficient are arbitrary values ​​selected from 1.2 to 2 according to actual needs.

4. The method according to claim 3, characterized in that, The etching time for etching the silicon oxide layer with hydrofluoric acid reagent is determined by the following formula: In this formula, T(HF1) represents the etching time of the hydrofluoric acid reagent for etching the silicon oxide layer, X represents the silicon oxide layer thickness, E a represents the first etching rate, and n1 represents the first over-etching coefficient.

5. The method according to claim 3, characterized in that, The etching time of the phosphate reagent on the silicon oxynitride layer, the etching time of the phosphate reagent on the silicon nitride layer, and the etching time of the phosphate reagent on the pad oxide layer are determined by the following formulas: In this formula, T(HPO1) represents the etching time of the silicon oxynitride layer by the phosphoric acid reagent, M represents the thickness of the silicon oxynitride layer, and E1 represents the third etching rate of the silicon oxynitride layer by the phosphoric acid reagent. T(HPO2) represents the etching time of the silicon nitride layer by the phosphoric acid reagent, Y represents the thickness of the silicon nitride layer, and E b This represents the fourth etching rate, and n2 represents the second excess etching coefficient. T(HPO3) represents the etching time of the phosphate reagent on the pad oxide layer, S represents the target loss thickness of the pad oxide layer, and E2 represents the fifth etching rate of the phosphate reagent on the pad oxide layer. Where E1 = f1(x), f1(x) represents the functional expression of the etching rate of the silicon oxynitride layer by phosphoric acid reagent as a function of the continuous etching workload of phosphoric acid. Substituting the continuous etching workload x of phosphoric acid into f1(x), we obtain the third etching rate E1 of the silicon oxynitride layer by phosphoric acid reagent. E2 = f2(x), where f2(x) represents the function expression of the etching rate of the silicon oxide layer and the pad oxide layer by the phosphoric acid reagent as a function of the continuous etching workload of phosphoric acid. Substituting the continuous etching workload of phosphoric acid into f2(x), we obtain the fifth etching rate E2.

6. The method according to claim 5, characterized in that, The phosphoric acid etching time also includes the total phosphoric acid etching time for etching the wafer using the phosphoric acid reagent. The total etching time T(HPO) for phosphoric acid is determined by the following formula: 。 7. The method according to claim 5, characterized in that, The hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer and the etching time of the hydrofluoric acid reagent on the silicon oxynitride layer. The phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon nitride layer and the etching time of the phosphoric acid reagent on the pad oxide layer. The phosphoric acid etching time and hydrofluoric acid etching time were determined using the following methods: If the target etching reagent is hydrofluoric acid, the etching time for the hydrofluoric acid to etch the silicon oxide layer is determined based on the thickness of the silicon oxide layer, the first etching rate of the hydrofluoric acid to the silicon oxide layer, and the first excess etching coefficient. The etching time for etching the silicon oxynitride layer with hydrofluoric acid reagent is determined based on the thickness of the silicon oxynitride layer and the second etching rate. The etching time for etching the silicon nitride layer with phosphoric acid is determined based on the thickness of the silicon nitride layer, the fourth etching rate of the phosphoric acid reagent on the silicon nitride, and the second excess etching coefficient. Based on the target loss thickness corresponding to the pad oxide layer and the fifth etching rate, the etching time of the phosphate reagent on the pad oxide layer is determined, wherein the first excess etching coefficient and the second excess etching coefficient are arbitrary values ​​selected from 1.2 to 2 according to actual needs.

8. The method according to claim 7, characterized in that, The phosphoric acid etching time and hydrofluoric acid etching time are determined using the following formula: In this formula, T(HF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, X represents the thickness of the silicon oxide layer, and E... a n represents the first etching rate, and n1 represents the first excess etching coefficient. T(HF2) represents the etching time of the silicon oxynitride layer by the hydrofluoric acid reagent, M represents the thickness of the silicon oxynitride layer, and E c This indicates the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer; T(HPO2) represents the etching time of the silicon nitride layer by the phosphoric acid reagent, Y represents the thickness of the silicon nitride layer, and E b n1 represents the fourth etching rate of the silicon nitride layer by the phosphoric acid reagent, and n2 represents the second excess etching coefficient. T(HPO3) represents the etching time of the phosphate reagent on the pad oxide layer, S represents the target loss thickness of the pad oxide layer, and E2 represents the fifth etching rate of the phosphate reagent on the pad oxide layer. Where E1 = f1(x), f1(x) represents the functional expression of the etching rate of the silicon oxynitride layer by phosphoric acid reagent as a function of the continuous etching workload of phosphoric acid. Substituting the continuous etching workload of phosphoric acid into f1(x), we obtain the third etching rate E1 of the silicon oxynitride layer by phosphoric acid reagent. E2 = f2(x), where f2(x) represents the function expression of the etching rate of the silicon oxide layer and the pad oxide layer by the phosphoric acid reagent as a function of the continuous etching workload of phosphoric acid. Substituting the continuous etching workload of phosphoric acid into f2(x), we obtain the fifth etching rate E2.

9. The method according to claim 8, characterized in that, The phosphoric acid etching time also includes the total phosphoric acid etching time for etching the wafer using the phosphoric acid reagent, and the hydrofluoric acid etching time also includes the total hydrofluoric acid etching time for etching the wafer using the hydrofluoric acid reagent. The total etching time T(HPO) for phosphoric acid and the total etching time T(HF) for hydrofluoric acid are determined using the following formulas: 。 10. An apparatus for fabricating a locally isolated oxide layer device structure, characterized in that, The device includes: A module is provided for providing a wafer that has undergone a thermal oxidation process, wherein an oxide isolation structure is formed and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate are stacked sequentially from top to bottom; The measurement module is used to measure the wafer and determine the thickness of the silicon oxide layer, the silicon nitride layer, and the silicon oxynitride layer. The etching rate determination module is used to determine the first etching rate of the silicon oxide layer, the second etching rate of the silicon oxynitride layer, the third etching rate of the silicon oxynitride layer, the fourth etching rate of the silicon nitride layer, and the fifth etching rate of the silicon oxide layer and the pad oxide layer by the phosphoric acid reagent. The third and fifth etching rates vary with the continuous etching workload of the phosphoric acid, which is the cumulative time for etching the wafer from the start of the new phosphoric acid acid. The acquisition module is used to acquire the target loss thickness of the pad oxide layer during continuous etching. The comparison module is used to compare the continuous etching workload of phosphoric acid with a preset workload threshold, and determine the target etching reagent based on the comparison result. The target etching reagent is a reagent selected to remove the silicon oxynitride layer. The target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent. The calculation module is used to calculate the phosphoric acid etching time and hydrofluoric acid etching time based on the target etching reagent, silicon oxide layer thickness, silicon nitride layer thickness, silicon oxynitride layer thickness, target loss thickness, phosphoric acid continuous etching workload and etching rate, respectively. An etching module is used to etch the silicon oxide layer, silicon oxynitride layer, and silicon nitride layer of the wafer using phosphoric acid reagent and hydrofluoric acid reagent, according to the phosphoric acid etching time and the hydrofluoric acid etching time. The third etching rate is calculated using the following functional expression: f1(x)=10 -7 x 2 -0.0013x+2.983 x represents the continuous etching workload of phosphoric acid, and f1(x) represents the third etching rate of the silicon oxynitride layer by the phosphoric acid reagent at the continuous etching workload of phosphoric acid x. The fifth etching rate is calculated using the following functional expression: f2(x)=9×10 -8 x 2 -0.0007x+1.5945 f2(x) represents the fifth etching rate of the silicon oxide layer and the pad oxide layer by the phosphoric acid reagent under the continuous phosphoric acid etching workload x.

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