Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate, wherein the substrate comprises a step region and a non-step region; the laminated structure is positioned on the substrate and comprises a first dielectric layer and a conductive layer which are sequentially and alternately laminated from bottom to top; the laminated structure comprises N conductive layers; the upper surface of the ith conductive layer in the step region is flush with the upper surface of the (i + A) th conductive layer in the non-step region; the plurality of groups of interconnection plug structures are respectively positioned in the step region and the non-step region; each group of interconnection plug structure comprises at least one interconnection plug, and each group of interconnection plug structure is positioned in the laminated structure and is in one-to-one correspondence contact with each conductive layer; and the interconnection plug connected with the ith conductive layer in the step region and the interconnection plug connected with the (i + A) th conductive layer in the non-step region are formed by adopting the same preparation process. By adopting the semiconductor structure, the process cost can be saved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, in the current memory structure design and process flow, the storage array used to store data can usually be designed as a multi-layer, and each layer of the storage array usually needs to form an interconnection plug to connect to the peripheral circuit. However, in the traditional technology, the process steps for forming an interconnection plug for each layer of the storage array are relatively cumbersome, and the depth of each interconnection plug is different, resulting in the need to design a separate mask for etching each interconnection plug in the traditional technology, so the process cost of the traditional technology is high. And as the number of memory layers increases, the process cost of preparing an interconnection plug using traditional technology will become higher and higher. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same to address the problem of high process cost in the prior art.

[0004] In order to achieve the above objectives, in a first aspect, the present application provides a semiconductor structure, comprising:

[0005] A substrate, wherein the substrate includes a step region and a non-step region;

[0006] A stacked structure, located on the substrate, comprising a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure comprises N layers of the conductive layer; the upper surface of the i-th conductive layer located in the step area is flush with the upper surface of the i+A-th conductive layer located in the non-step area;

[0007] A plurality of groups of interconnect plug structures are respectively located in the step area and the non-step area; each group of the interconnect plug structures includes at least one interconnect plug, each group of the interconnect plug structures is located in the stacked structure, and is in one-to-one contact with each of the conductive layers; the interconnect plug connected to the i-th conductive layer in the step area and the interconnect plug connected to the i+A-th conductive layer in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N.

[0008] The semiconductor structure comprises: a substrate, a stacked structure and a plurality of interconnection plug structures, wherein the substrate comprises a step region and a non-step region. The stacked structure is located on the substrate, and comprises a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure comprises N conductive layers; the upper surface of the i-th conductive layer located in the step region is flush with the upper surface of the i+A-th conductive layer located in the non-step region. The plurality of interconnection plug structures are located in the step region and the non-step region respectively; each group of the interconnection plug structures comprises at least one interconnection plug, each group of the interconnection plug structures is located in the stacked structure, and is in one-to-one contact with each conductive layer; the interconnection plug connected to the i-th conductive layer in the step region and the interconnection plug connected to the i+A-th conductive layer in the non-step region are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N. In the preparation process of the same group of interconnection plug structures, only one photomask needs to be designed to prepare at least one interconnection plug, and the etching depths of the interconnection plugs in the same group of interconnection plug structures are the same during the etching process, thus reducing process steps and saving process costs.

[0009] In one embodiment, a step region of the substrate is formed with a step structure, and the step structure includes a dielectric layer.

[0010] In one embodiment, the thickness of the step structure is equal to the sum of the thickness of the first dielectric layer in the A layer and the conductive layer in the A layer.

[0011] In one embodiment, in the stacked structure, the thickness of each first dielectric layer is the same, and the thickness of each conductive layer is the same.

[0012] In one embodiment, the stacked structure includes N+1 layers of the first dielectric layer; the stacked structure located above the step area includes NA layers of the conductive layer and N-A+1 layers of the first dielectric layer, and the stacked structure located above the non-step area includes N layers of the conductive layer and N+1 layers of the first dielectric layer.

[0013] In one embodiment, the semiconductor structure further comprises:

[0014] An isolation layer, located on the upper surface of the laminated structure;

[0015] A second dielectric layer is located on the upper surface of the isolation layer; each of the interconnect plugs also penetrates the isolation layer and the second dielectric layer;

[0016] A plurality of metal interconnection lines are located on the upper surface of the second dielectric layer and are in one-to-one contact with the upper surface of each group of the interconnection plug structures;

[0017] An insulating layer covers the upper surface of the second dielectric layer and the exposed surfaces of each of the metal interconnections.

[0018] In one embodiment, each layer of the conductive layer is in an I-shape, and each layer of the conductive layer includes a first extension portion extending along a first direction, and a second extension portion extending along the first direction, the first extension portion and the second extension portion are arranged at intervals along a second direction, and the first direction intersects with the second direction; each layer of the conductive layer also includes a third extension portion extending along the second direction, the third extension portion is located between the first extension portion and the second extension portion, and is integrally connected to the first extension portion and the second extension portion; wherein the first extension portion is located in the step area, the second extension portion is located in the non-step area, and each group of the interconnect plug structures is in contact with the first extension portion and / or the second extension portion;

[0019] The semiconductor structure further comprises:

[0020] A transistor, the transistor comprising a word line, a gate insulating layer and a semiconductor layer, one side of the semiconductor layer is in contact with the outer side of the third extension portion, the gate insulating layer is located on the inner side wall of the semiconductor layer, the inner side of the gate insulating layer is filled with the word line, the first electrode and the second electrode of the transistor are both located in the semiconductor layer and are respectively located on both sides of the word line, and the first electrode of the transistor is connected to the third extension portion;

[0021] The capacitor structure is connected to the second electrode of the transistor.

[0022] In a second aspect, the present application also provides a method for preparing a semiconductor structure, comprising:

[0023] Providing a substrate, wherein the substrate includes a step region and a non-step region;

[0024] A stacked structure is formed on the substrate; the stacked structure comprises a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure comprises N layers of the conductive layer; the upper surface of the i-th conductive layer located in the step area is flush with the upper surface of the i+A-th conductive layer located in the non-step area;

[0025] A plurality of groups of interconnect plug structures are formed in the stacked structure, each group of the interconnect plug structures is located in the step area and the non-step area respectively; each group of the interconnect plug structures includes at least one interconnect plug, each group of the interconnect plug structures is located in the stacked structure, and is in one-to-one contact with each of the conductive layers; the interconnect plug connected to the i-th conductive layer in the step area and the interconnect plug connected to the i+A-th conductive layer in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N.

[0026] The method for preparing the above-mentioned semiconductor structure is by forming a stacked structure on the substrate; the stacked structure includes a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure includes N layers of the conductive layer; a plurality of groups of interconnection plug structures are formed in the stacked structure, each group of the interconnection plug structures is respectively located in the step area and the non-step area; each group of the interconnection plug structures includes at least one interconnection plug, each group of the interconnection plug structures is located in the stacked structure, and is in one-to-one contact with each of the conductive layers; since the upper surface of the i-th conductive layer located in the step area is flush with the upper surface of the i+A-th conductive layer located in the non-step area, the interconnection plug connected to the i-th conductive layer in the step area and the interconnection plug connected to the i+A-th conductive layer in the non-step area can be formed using the same preparation process. Therefore, in the preparation process of the same group of interconnection plug structures, only one mask needs to be designed to prepare at least one interconnection plug, and the etching depth of each interconnection plug in the same group of interconnection plug structures is the same during the etching process, thereby reducing the process steps and saving process costs.

[0027] In one embodiment, the step region of the substrate is formed with a step structure; the providing substrate, the substrate including the step region and the non-step region, comprises:

[0028] Providing an initial substrate; the initial substrate comprises a step region and a non-step region;

[0029] A portion of the initial substrate in the non-step region is removed to form the substrate, and the initial substrate in the step region is retained as the step structure.

[0030] In one embodiment, the step region of the substrate is formed with a step structure, and the step structure includes a dielectric layer; the substrate is provided, and the substrate includes the step region and the non-step region, including:

[0031] Providing an initial substrate; the initial substrate comprises a step region and a non-step region;

[0032] forming the dielectric layer on the initial substrate;

[0033] A portion of the dielectric layer in the non-step region is removed to form the substrate, and the dielectric layer in the step region is retained as the step structure.

[0034] In one embodiment, the thickness of the step structure is equal to the sum of the thickness of the first dielectric layer in the A layer and the conductive layer in the A layer.

[0035] In one embodiment, in the stacked structure, the thickness of each first dielectric layer is the same, and the thickness of each conductive layer is the same.

[0036] In one embodiment, forming a stacked structure on the substrate includes:

[0037] Forming N+1 layers of the first dielectric layer and N layers of the conductive layer in sequence from bottom to top on the substrate;

[0038] Part of the stacked structure located in the step area is removed, so that the stacked structure located above the step area includes NA layers of the conductive layer and N-A+1 layers of the first dielectric layer, and the stacked structure located above the non-step area includes N layers of the conductive layer and N+1 layers of the first dielectric layer.

[0039] In one embodiment, after forming a stacked structure on the substrate and before forming a plurality of interconnect plug structures in the stacked structure, the method for preparing the semiconductor structure further includes:

[0040] forming an isolation layer on the upper surface of the laminated structure;

[0041] A second dielectric layer is formed on the upper surface of the isolation layer; and each of the interconnection plugs also penetrates the isolation layer and the second dielectric layer.

[0042] In one embodiment, after forming a plurality of interconnect plug structures in the stacked structure, the method for preparing the semiconductor structure further includes:

[0043] forming a plurality of metal interconnection lines on the upper surface of the second dielectric layer, wherein each of the metal interconnection lines is in one-to-one contact with the upper surface of each group of the interconnection plug structures;

[0044] An insulating layer is formed on the upper surface of the second dielectric layer and the exposed surfaces of each of the metal interconnections. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0047] Figure 2 A schematic diagram of a 3D structure of a structure obtained in step S10 in a method for preparing a semiconductor structure provided in an embodiment;

[0048] Figure 3 Figure (a) is Figure 2 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Figure 2 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Figure 2 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0049] Figure 4 is a flowchart of step S10 in a method for preparing a semiconductor structure provided in an embodiment;

[0050] Figure 5 A schematic diagram of a 3D structure of a structure obtained in step S101a of a method for preparing a semiconductor structure provided in an embodiment;

[0051] Figure 6 Figure (a) is Figure 5 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Figure 5 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Figure 5 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0052] Figure 7 is a flowchart of step S10 in a method for preparing a semiconductor structure provided in another embodiment;

[0053] Figure 8 A schematic diagram of a 3D structure of a structure obtained in step S102b of a method for preparing a semiconductor structure provided in an embodiment;

[0054] Fig. 9 Figure (a) is Figure 8 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Figure 8 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Figure 8 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0055] Fig.10 A schematic diagram of a 3D structure of a structure obtained in step S20 in a method for preparing a semiconductor structure provided in an embodiment;

[0056] Fig.11 Figure (a) is Fig.10 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.10 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.10 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0057] Fig.12 A schematic cross-sectional view of a structure obtained in step S20 in a method for preparing a semiconductor structure provided in another embodiment;

[0058] Fig.13 is a flowchart of step S20 in a method for preparing a semiconductor structure provided in an embodiment;

[0059] Fig.14 A schematic diagram of a 3D structure of a structure obtained in step S201 in a method for preparing a semiconductor structure provided in an embodiment;

[0060] Fig.15 Figure (a) is Fig.14 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.14 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.14 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0061] Fig.16 A flowchart of the steps of forming an isolation layer and a second dielectric layer in a method for preparing a semiconductor structure provided in an embodiment;

[0062] Fig.17 A schematic diagram of a 3D structure of a structure obtained in step S1602 in a method for preparing a semiconductor structure provided in an embodiment;

[0063] Fig.18 Figure (a) is Fig.17 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.17 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.17 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0064] Fig.19A schematic diagram of a 3D structure of a structure obtained by forming a first group of interconnect plug structures in step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0065] Fig. 20 Figure (a) is Fig.19 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.19 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.19 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0066] Fig.21 A schematic diagram of a 3D structure of a structure obtained by forming a second group of interconnect plug structures in step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0067] Fig. 22 Figure (a) is Fig.21 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.21 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.21 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0068] Fig.23 A schematic diagram of a 3D structure of a structure obtained by forming a third group of interconnect plug structures in step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0069] Fig.24 Figure (a) is Fig.23 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.23 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.23 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0070] Fig.25 A flowchart of steps for forming a plurality of metal interconnects and an insulating layer in a method for preparing a semiconductor structure provided in an embodiment;

[0071] Fig.26 A schematic diagram of a 3D structure of a structure obtained in step S2502 in a method for preparing a semiconductor structure provided in an embodiment;

[0072] Fig. 27 Figure (a) is Fig.26 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.26 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.26 Schematic diagram of the cross-sectional structure of the structure along CC' direction;

[0073] Fig.28 is a schematic diagram of a 3D structure of a semiconductor structure provided in an embodiment;

[0074] Fig.29 for Fig.28 Schematic diagram of the top view of the structure along the DD' direction.

[0075] Explanation of the reference numerals: 10 - substrate, 101 - initial substrate, 102 - step structure, 20 - stacked structure, 201 - first dielectric layer, 202 - conductive layer, 202a - first extension portion, 202b - second extension portion, 202c - third extension portion, 30 - isolation layer, 40 - second dielectric layer, 50 - interconnection plug, 60 - metal interconnection line, 70 - insulating layer, 80 - transistor, 801 - word line, 802 - gate insulating layer, 803 - semiconductor layer, 90 - capacitor structure. DETAILED DESCRIPTION

[0076] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0078] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0079] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0080] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0081] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of preferred embodiments (and intermediate structures) of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0082] See also Figure 1 The present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0083] S10: providing a substrate, wherein the substrate includes a step region and a non-step region;

[0084] S20: forming a stacked structure on the substrate; the stacked structure comprises a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure comprises N conductive layers; the upper surface of the i-th conductive layer located in the step area is flush with the upper surface of the i+A-th conductive layer located in the non-step area;

[0085] S30: forming a plurality of groups of interconnect plug structures in the laminated structure, each group of interconnect plug structures being located in a step area and a non-step area respectively; each group of interconnect plug structures comprises at least one interconnect plug, each group of interconnect plug structures is located in the laminated structure and is in one-to-one contact with each conductive layer; the interconnect plug connected to the i-th conductive layer in the step area and the interconnect plug connected to the i+A-th conductive layer in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N.

[0086] The method for preparing the semiconductor structure is as follows: a stacked structure is formed on a substrate; the stacked structure includes a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure includes N conductive layers; a plurality of interconnection plug structures are formed in the stacked structure, each of which is located in a step area and a non-step area; each of which includes at least one interconnection plug, each of which is located in the stacked structure and is in one-to-one contact with each conductive layer; since the upper surface of the i-th conductive layer located in the step area is flush with the upper surface of the i+A-th conductive layer located in the non-step area, the interconnection plug connected to the i-th conductive layer in the step area and the interconnection plug connected to the i+A-th conductive layer in the non-step area can be formed by the same preparation process. Therefore, in the preparation process of the same group of interconnection plug structures, only one photomask needs to be designed to prepare at least one interconnection plug, and the etching depth of each interconnection plug in the same group of interconnection plug structures is the same during etching, so the process steps can be reduced and the process cost can be saved.

[0087] In order to facilitate a better understanding of the present solution, three directions are given in the drawings of the present application: namely, direction a, direction b and direction c. Direction a can be the vertical direction in the drawings, direction b can be the column direction in the horizontal direction in the drawings, and direction c can be the row direction in the horizontal direction in the drawings. Of course, in other suitable application scenarios, directions a, b and c can also be other suitable directions, and the angles between directions a, b and c can also be other suitable angles, which are not limited in this embodiment. In addition, the height, depth and thickness involved in the following embodiments may refer to the height, depth and thickness along the direction a in the drawings, the first direction involved in the following embodiments may be regarded as direction b, the second direction may be regarded as direction c, and the third direction may be regarded as direction a, and these three directions may be regarded as mutually perpendicular in pairs. Of course, the definition of directions in this application is only for the purpose of facilitating a better understanding of the present solution, and does not constitute any limitation on the present solution.

[0088] In step S10, refer to Figure 1 Step S10 in Figure 2-Figure 3 , providing a substrate 10, the substrate 10 includes a step area and a non-step area.

[0089] in, Figure 2 is a schematic diagram of the 3D structure of the structure obtained in step S10, Figure 3 In the figure, (a) is Figure 2 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Figure 2 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Figure 2 Schematic diagram of the cross-sectional structure of the structure along the CC' direction.

[0090] In one embodiment, Figure 4 As shown, the above step S10 includes:

[0091] S101a: providing an initial substrate 101; the initial substrate 101 includes a step region and a non-step region.

[0092] like Figure 5-Figure 6 As shown, Figure 5 is a schematic diagram of the 3D structure of the structure obtained in step S101a, Figure 6 In the figure, (a) is Figure 5 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Figure 5 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Figure 5 Schematic diagram of the cross-sectional structure of the structure along the CC' direction.

[0093] The material of the initial substrate 101 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as aluminum oxide, quartz or glass substrates, etc., which are not limited in this embodiment. Among them, the step area and the non-step area may be the area where the interconnect plug 50 will be formed in the subsequent preparation process.

[0094] S102 a : removing a portion of the initial substrate 101 in the non-step region to form the substrate 10 , and retaining the initial substrate 101 in the step region as the step structure 102 .

[0095] like Figure 2-Figure 3 As shown, a process combining photolithography and etching can be used to remove part of the initial substrate 101 to form the step structure 102. That is, in this embodiment, the step structure 102 and the substrate 10 can be made of the same material, and the step structure 102 itself can be a part of the initial substrate 101.

[0096] In another embodiment, Figure 7 As shown, the above step S10 includes:

[0097] S101b: providing an initial substrate 101; the initial substrate 101 includes a step region and a non-step region.

[0098] like Figure 5-Figure 6 As shown, the initial substrate 101 obtained in this step may be thinner than the initial substrate 101 obtained in step S101a.

[0099] S102b: forming a dielectric layer on the initial substrate 101 .

[0100] like Figure 8-Figure 9 As shown, Figure 8 is a schematic diagram of the 3D structure of the structure obtained in step S102b, Fig. 9 In the figure, (a) is Figure 8 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Figure 8 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Figure 8 Schematic diagram of the cross-sectional structure of the structure in the CC' direction. A deposition process can be used to form a dielectric layer on the substrate 10, and the deposition process can include an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process. Among them, the material of the dielectric layer can be a combination of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2).

[0101] S103 b : removing part of the dielectric layer in the non-step area to form the substrate 10 , and retaining the dielectric layer in the step area as the step structure 102 .

[0102] like Figure 2-Figure 3 As shown, a process combining photolithography and etching can be used to remove part of the dielectric layer in the non-step area. That is, in this embodiment, the materials of the step structure 102 and the substrate 10 can be different, and the step structure 102 and the substrate 10 are two separate parts.

[0103] Both of these two embodiments can obtain a substrate 10 with a step structure 102 , and the specific method to be selected can be determined according to the actual application scenario and process requirements.

[0104] In step S20, refer to Figure 1 Step S20 in Figure 10-11 , a stacked structure 20 is formed on the substrate 10; the stacked structure 20 includes a first dielectric layer 201 and a conductive layer 202 alternately stacked from bottom to top; the stacked structure 20 includes N conductive layers 202; the upper surface of the i-th conductive layer 202 located in the step area is flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area.

[0105] in, Fig.10 is a schematic diagram of the 3D structure of the structure obtained in step S20, Fig.11 In the figure, (a) is Fig.10 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.10 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.10 Schematic diagram of the cross-sectional structure of the structure along the CC' direction.

[0106] The first dielectric layer 201 and the conductive layer 202 may be alternately formed in sequence by a deposition process to form a Figure 10-11 The stacked structure 20 shown. The material of the first dielectric layer 201 may be a combination of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2). Optionally, when the step structure 102 is a dielectric layer, the material of the first dielectric layer 201 may be the same as the material of the dielectric layer. The material of the conductive layer 202 may include polysilicon, single crystal silicon or a metal material. Further, the metal material may include metals such as copper, gold, titanium, silver, and aluminum, and may also include a multilayer metal composed of the metals of the above materials, and may also include a metal alloy, etc., which is not limited in this embodiment.

[0107] Optionally, the thickness of the first dielectric layer 201 is different from the thickness of the dielectric layer. Further, the thickness of the first dielectric layer 201 is less than the thickness of the dielectric layer.

[0108] like Figure 10-11 As shown, since the step structure 102 only covers the upper surface of the step area, and the non-step area is not covered by the step structure 102, when forming the stacked structure 20, although the conductive layer 202 of each layer and the first dielectric layer 201 of each layer are formed at the same time, due to the existence of the step structure 102, there will be a difference in height between the stacked structure 20 located in the step area and the non-step area.

[0109] Wherein, N is an integer greater than or equal to 2, for example, N can be any integer among 2, 3, 4 or 5, and of course, it can also be other suitable integers. The value of N can be determined according to the number of layers required for the stacked structure 20 in the specific memory design, and this embodiment does not limit this. i is an integer greater than or equal to 1 and less than N, and the value of i is determined according to the value of N. For example, when N is 5, i can be any integer among 1, 2, 3, 4 or 5. The value of i can be determined according to the number of layers required for the stacked structure 20 in the specific memory design, and this embodiment does not limit this. A is an integer greater than or equal to 1 and less than N, for example, when N is 5, A can be any integer among 1, 2, 3, 4 or 5, and the value of i can be determined according to the number of layers required for the stacked structure 20 in the specific memory design, and this embodiment does not limit this. This embodiment does not limit this.

[0110] By utilizing the height misalignment of each conductive layer 202 caused by the step structure 102 and appropriately adjusting the height of the step structure 102, the height of each first dielectric layer 201 and the height of each conductive layer 202, the upper surface of the i-th conductive layer 202 located in the step area can be made flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area.

[0111] For example, taking N as 5 and A as 1, Figure 10-11 As shown, there are 4 conductive layers 202 in the step area and 5 conductive layers 202 in the non-step area. By properly adjusting the height of the step structure 102, the height of each first dielectric layer 201 and the height of each conductive layer 202, it is possible to make: when i=1, the upper surface of the 1st conductive layer 202 in the step area is flush with the upper surface of the 1+1=2nd conductive layer 202 in the non-step area; when i=2, the upper surface of the 2nd conductive layer 202 in the step area is flush with the upper surface of the 2+1=3rd conductive layer 202 in the non-step area; and so on.

[0112] For example, taking N as 6 and A as 2, Fig.12 As shown, Fig.12 is a schematic diagram of a cross-sectional structure of a structure obtained in step S20 in another embodiment, Fig.12 Can be used with Fig.11 Compared with Figure (a) in Fig.12As shown, there are 4 conductive layers 202 in the step area and 6 conductive layers 202 in the non-step area. By properly adjusting the height of the step structure 102, the height of each first dielectric layer 201 and the height of each conductive layer 202, it is possible to make: when i=1, the upper surface of the 1st conductive layer 202 in the step area is flush with the upper surface of the 1st+2=3rd conductive layer 202 in the non-step area; when i=2, the upper surface of the 2nd conductive layer 202 in the step area is flush with the upper surface of the 2nd+2=4th conductive layer 202 in the non-step area; and so on.

[0113] Based on the above embodiments, in one embodiment, the thickness of the step structure 102 is equal to the sum of the thicknesses of the A-layer first dielectric layer 201 and the A-layer conductive layer 202 .

[0114] Among them, the thickness of the step structure 102 can determine to a certain extent whether the upper surfaces of the conductive layer 202 in the step area and the conductive layer 202 in the non-step area can be flush with each other, and the thickness of the step structure 102 can determine to a certain extent which layer of the conductive layer 202 in the step area can be flush with which layer of the conductive layer 202 in the non-step area.

[0115] Based on the above embodiments, in one embodiment, in the stacked structure 20 , the thickness of each first dielectric layer 201 is the same, and the thickness of each conductive layer 202 is the same.

[0116] Each conductive layer 202 may be formed by a deposition process, and the process parameters of the process for forming each conductive layer 202 may be kept consistent (for example, deposition time), so that the thickness of each conductive layer 202 is the same. Each first dielectric layer 201 may also be formed by a deposition process, and the process parameters of the process for forming each first dielectric layer 201 may also be kept consistent (for example, deposition time), so that the thickness of each first dielectric layer 201 is the same.

[0117] For example, taking A as 1, Figure 10-11 As shown, in step S10, the thickness of the step structure 102 is made equal to the sum of the thickness of one second dielectric layer 40 and one conductive layer 202, and the thicknesses of the first dielectric layers 201 are all the same, and the thicknesses of the second dielectric layers 40 are all the same, so that the upper surface of the i-th conductive layer 202 located in the step area can be flush with the upper surface of the i+1-th conductive layer 202 located in the non-step area.

[0118] For example, taking A as 2, Fig.12As shown, in step S10, the thickness of the step structure 102 is made equal to the sum of the thickness of the two second dielectric layers 40 and the two conductive layers 202, and the thickness of each first dielectric layer 201 is the same, and the thickness of the second dielectric layer 40 is the same, so that the upper surface of the i-th conductive layer 202 located in the step area can be flush with the upper surface of the i+2-th conductive layer 202 located in the non-step area.

[0119] In this embodiment, by making the thickness of each conductive layer 202 the same, and making the thickness of each second dielectric layer 40 the same, and when the thickness of the first dielectric layer 201 is the same as the sum of the thickness of the A-layer second dielectric layer 40 and the A-layer conductive layer 202 located above the second preset interconnection area, it can be ensured that the upper surface of the i-th conductive layer 202 located in the step area is flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area.

[0120] Of course, in other suitable embodiments, the thickness of each conductive layer 202 is set to be different, or the thickness of each first dielectric layer 201 is set to be different, or the thickness of the step structure 102 may not be equal to the sum of the thickness of the A-layer first dielectric layer 201 and the A-layer conductive layer 202, so that the upper surface of the i-th conductive layer 202 located in the step area can be flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area. Therefore, in other suitable application scenarios, similar solutions will also fall within the protection scope of this application.

[0121] In one embodiment, Fig.13 As shown, the above step S20 includes:

[0122] S201 : forming N+1 first dielectric layers 201 and N conductive layers 202 in sequence from bottom to top on the substrate 10 .

[0123] like Figure 14-15 As shown, Fig.14 is a schematic diagram of the 3D structure of the structure obtained in step S201, Fig.15 In the figure, (a) is Fig.14 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.14 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.14 A schematic diagram of a cross-sectional structure of the structure in the CC' direction. N+1 first dielectric layers 201 and N conductive layers 202 may be sequentially formed on the substrate 10 by a deposition process, and the number of first dielectric layers 201 may always be one more than the number of conductive layers 202.

[0124] S202: remove part of the stacked structure 20 located in the step area, so that the stacked structure 20 located above the step area includes NA conductive layers 202 and N-A+1 first dielectric layers 201, and the stacked structure 20 located above the non-step area includes N conductive layers 202 and N+1 first dielectric layers 201.

[0125] like Figure 11-Figure 12 As shown, a chemical mechanical polishing (CMP) process can be used to remove part of the stacked structure 20 located in the step area so that the upper surface of the stacked structure 20 is flush with the horizontal direction. After removing part of the stacked structure 20 located in the step area, the stacked structure 20 located above the step area includes NA layers of conductive layer 202 and N-A+1 layers of first dielectric layer 201, and the stacked structure 20 located above the non-step area includes N layers of conductive layer 202 and N+1 layers of first dielectric layer 201.

[0126] For example, taking N=5 and A=1 as an example, Fig.11 As shown, the stacked structure 20 located on the step area includes 5-1=4 conductive layers 202 and 5-1+1=5 first dielectric layers 201, and the stacked structure 20 located on the non-step area includes 5 conductive layers 202 and 5+1=6 first dielectric layers 201.

[0127] For example, taking N=6 and A=2 as an example, Fig.12 As shown, the stacked structure 20 located on the step area includes 6-2=4 conductive layers 202 and 6-2+1=5 first dielectric layers 201, and the stacked structure 20 located on the non-step area includes 6 conductive layers 202 and 6+1=7 first dielectric layers 201.

[0128] Optionally, after forming the Nth conductive layer 202 and before forming the N+1th first dielectric layer 201, the Nth first dielectric layer 201 in the step area is used as an etching stop layer, and a CMP process is used to remove the Nth conductive layer 202 in the step area; then the N+1th first dielectric layer 201 is formed; and then the CMP process is continued to be used to remove the N+1th first dielectric layer 201 in the step area, so as to finally make the upper surface of the stacked structure 20 flush with the horizontal direction.

[0129] Optionally, after forming the Nth and N+1th first dielectric layers 201 , the CMP process may be used to directly remove the excess stacked structure 20 protruding upward in the step area at one time, so that the upper surface of the stacked structure 20 is flush with the horizontal direction.

[0130] In one embodiment, Fig.16As shown, after step S20 and before step S30, the method for preparing the semiconductor structure further includes:

[0131] S1601 : forming an isolation layer 30 on the upper surface of the stacked structure 20 .

[0132] like Figure 17-Figure 18 As shown, the material of the isolation layer 30 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride.

[0133] S1602 : forming a second dielectric layer 40 on the upper surface of the isolation layer 30 .

[0134] like Figure 17-Figure 18 As shown, Fig.17 is a schematic diagram of the 3D structure of the structure obtained in step S1602, Fig.18 In the figure, (a) is Fig.17 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.17 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.17 The cross-sectional structure diagram of the structure in FIG. 4 along the CC' direction. The material of the second dielectric layer 40 may be a combination of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2).

[0135] In step S30, refer to Figure 1 Step S30 in Figure 19-Figure 24 , multiple groups of interconnect plug structures are formed in the stacked structure 20, each group of interconnect plug structures is located in the step area and the non-step area respectively; each group of interconnect plug structures includes at least one interconnect plug 50, each group of interconnect plug structures is located in the stacked structure 20, and is in one-to-one contact with each conductive layer 202. The interconnect plug 50 connected to the i-th conductive layer 202 in the step area and the interconnect plug 50 connected to the i+A-th conductive layer 202 in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N.

[0136] The preparation process of each group of interconnection plugs 50 may include: firstly forming a plurality of grooves in the stacked structure 20 by combining photolithography and etching, and then filling the interconnection plugs 50 in each groove to form a plurality of groups of interconnection plug structures.

[0137] Since the upper surface of the i-th conductive layer 202 located in the step area is flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area, when a groove is formed in the stacked structure 20, the interconnection plugs 50 corresponding to the conductive layers 202 of the same height but different layers can be prepared using the same preparation process, so the interconnection plugs 50 prepared using the same preparation process can be regarded as the same group of interconnection plug structures. In the preparation process of the same group of interconnection plug structures, only one mask needs to be designed, and etching can be performed based on the same mask to form at least one interconnection plug 50. In addition, the depths of the interconnection plugs 50 included in the same group of interconnection plug structures are the same during the etching process, so there is no need to deliberately adjust the corresponding etching parameters. This can reduce the process steps and save process costs.

[0138] By way of example, taking N as 5 and A as 1 as an example, the process of forming multiple groups of interconnect plug structures in the stacked structure 20 is described:

[0139] First, if Figure 17-Figure 18 As shown, the stacked structure 20 includes five conductive layers 202 , wherein the step region includes four conductive layers 202 , and the non-step region includes five conductive layers 202 .

[0140] Afterwards, if Figure 19-20 As shown, Fig.19 is a schematic 3D structural diagram of a structure obtained by forming a first set of interconnect plug structures in the stacked structure 20 by using the first photolithography and etching steps in step S30, Fig. 20 In the figure, (a) is Fig.19 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.19 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.19 The first group of interconnection plug structures includes an interconnection plug 50, and the interconnection plug 50 is in contact with the first conductive layer 202 located in the non-step region.

[0141] Afterwards, if Figure 21-22 As shown, Fig.21 is a schematic 3D structural diagram of a structure obtained by forming a second set of interconnect plug structures in the stacked structure 20 by a second photolithography and etching step in step S30, Fig. 22 In the figure, (a) is Fig.21 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.21 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.21Schematic diagram of the cross-sectional structure of the structure in the CC' direction. The second group of interconnection plug structures includes two interconnection plugs 50, the depths of the two interconnection plugs 50 are the same, and one of the interconnection plugs 50 is in contact with the second conductive layer 202 located in the step area, and the other interconnection plug 50 is in contact with the 2+1=3rd conductive layer 202 located in the non-step area. This is precisely the use of the feature that the upper surface of the second conductive layer 202 located in the step area is flush with the upper surface of the third conductive layer 202 located in the non-step area, so that two different patterns of interconnection plugs 50 can be designed on the same mask, and the stacked structure 20 of the same depth can be removed through the same etching process to form a groove for accommodating the two interconnection plugs 50. Therefore, the two interconnection plugs 50 included in the second group of interconnection plug structures are formed by the same preparation process.

[0142] Finally, if Figure 23-Figure 24 As shown, Fig.23 is a schematic 3D structural diagram of a structure obtained by forming a third set of interconnect plug structures in the stacked structure 20 by the third photolithography and etching steps in step S30, Fig.24 In the figure, (a) is Fig.23 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.23 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.23 Schematic diagram of the cross-sectional structure of the structure in the CC' direction. The third group of interconnection plug structures is formed in the stacked structure 20 by the third photolithography and etching steps. The third group of interconnection plug structures includes two interconnection plugs 50. The depths of the two interconnection plugs 50 are the same, and one of the interconnection plugs 50 is in contact with the 4th conductive layer 202 located in the step area, and the other interconnection plug 50 is in contact with the 4th+1=5th conductive layer 202 located in the non-step area. This is precisely the use of the feature that the upper surface of the 4th conductive layer 202 located in the step area is flush with the upper surface of the 5th conductive layer 202 located in the non-step area. Two different patterns of interconnection plugs 50 can be designed on the same photomask, and the stacked structure 20 of the same depth is removed by the same etching process to form a groove for accommodating the two interconnection plugs 50. Therefore, the two interconnection plugs 50 included in the third group of interconnection plug structures are also formed by the same preparation process.

[0143] In summary, when N is 5 and A is 1, the related art requires 5 preparation processes and 5 photomasks to form 5 interconnection plugs 50 that meet the process requirements. In this embodiment, only 3 preparation processes and 3 photomasks are needed to form 5 interconnection plugs 50 that meet the process requirements, thereby reducing the process steps and saving process costs.

[0144] In addition, it can be observed that for some conductive layers 202 in the stacked structure 20, the heights of the conductive layers 202 adjacent to the upper and lower conductive layers 202 can be considered to be the same. Figure 17-Figure 18 For the second conductive layer 202 in the stacked structure 20, the second conductive layer 202 in the step area is flush with the upper surface of the third conductive layer 202 in the non-step area, and the second conductive layer 202 in the non-step area is flush with the upper surface of the first conductive layer 202 in the step area. One conductive layer 202 can be connected through only one interconnection plug 50, which can bring great flexibility to our design. For example, still taking N as 5 and A as 1 as an example, when a first group of interconnect plug structures is formed in the stacked structure 20 in the first photolithography and etching steps, the first group of interconnect plug structures may include two interconnect plugs 50, one of which is connected to the first conductive layer 202 located in the step area, and the other is connected to the second conductive layer 202 located in the non-step area; when a second group of interconnect plug structures is formed in the stacked structure 20 in the second photolithography and etching steps, the second group of interconnect plug structures may include two interconnect plugs 50, one of which is connected to the third conductive layer 202 located in the step area, and the other is connected to the fourth conductive layer 202 located in the non-step area; when a third group of interconnect plug structures is formed in the stacked structure 20 in the third photolithography and etching steps, the third group of interconnect plug structures may include one interconnect plug 50, and the interconnect plug 50 is connected to the fifth conductive layer 202 located in the non-step area. In this way, the effect of forming five interconnect plugs 50 that meet the process requirements can be achieved through three preparation processes and three photomasks, thereby reducing the process steps and saving process costs. It can be seen that when designing a device, the design of each group of interconnect plug structures is flexible and can be determined according to specific process requirements, and this embodiment does not limit this.

[0145] Optionally, the interconnect plug 50 may include a conductive barrier layer and a metal filling layer, the conductive barrier layer may be located at the bottom and sidewalls of the trench, and the metal filling layer may fill the interior of the trench. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filling layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes.

[0146] In one embodiment, Fig.25 As shown, after step S30, the method for preparing the semiconductor structure further includes:

[0147] S2501 : forming a plurality of metal interconnection lines 60 on the upper surface of the second dielectric layer 40 , wherein each metal interconnection line 60 is in one-to-one contact with the upper surface of each group of interconnection plug structures.

[0148] like Figure 26-Figure 27 As shown, the material of the metal interconnection line 60 may include metals such as copper, gold, titanium, silver, aluminum, etc., or may include multilayer metals composed of the above-mentioned metals, or may include metal alloys, etc., which are not limited in this embodiment.

[0149] S2502 : forming an insulating layer 70 on the upper surface of the second dielectric layer 40 and the exposed surfaces of each metal interconnection line 60 .

[0150] like Figure 26-Figure 27 As shown, Fig.26 is a schematic 3D structural diagram of a structure obtained by forming a second set of interconnect plug structures in the stacked structure 20 by using the second photolithography and etching steps in step S2502, Fig. 27 In the figure, (a) is Fig.26 The schematic diagram of the cross-sectional structure of the structure along the AA' direction, (b) is Fig.26 Schematic diagram of the cross-sectional structure of the structure along the BB' direction, (c) Fig.26 The insulating layer 70 may be formed by a deposition process.

[0151] The present application also provides a semiconductor structure, such as Figure 23-Figure 24 As shown, the semiconductor structure includes: a substrate 10, a stacked structure 20 and a plurality of interconnect plug structures, wherein the substrate 10 includes a step region and a non-step region. The stacked structure 20 is located on the substrate 10, and includes a first dielectric layer 201 and a conductive layer 202 alternately stacked from bottom to top; the stacked structure 20 includes N conductive layers 202; the upper surface of the i-th conductive layer 202 located in the step region is flush with the upper surface of the i+A-th conductive layer 202 located in the non-step region. A plurality of groups of interconnect plug structures are respectively located in the step area and the non-step area; each group of interconnect plug structures includes at least one interconnect plug 50, each group of interconnect plug structures is located in the stacked structure 20, and is in one-to-one contact with each conductive layer 202; the interconnect plug 50 connected to the i-th conductive layer 202 in the step area and the interconnect plug 50 connected to the i+A-th conductive layer 202 in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N.

[0152] The material of the initial substrate 101 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-side polished silicon wafers (DSP), or ceramic substrates such as aluminum oxide, quartz or glass substrates, etc., which are not limited in this embodiment. The step area and the non-step area may be areas where the interconnect plug 50 will be formed in the subsequent preparation process.

[0153] The material of the first dielectric layer 201 may be a combination of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2). Optionally, when the step structure 102 is a dielectric layer, the material of the first dielectric layer 201 may be the same as the material of the dielectric layer. The material of the conductive layer 202 may include polysilicon, single crystal silicon or a metal material. Further, the metal material may include metals such as copper, gold, titanium, silver, and aluminum, or may include a multilayer metal composed of the metals of the above materials, or may include a metal alloy, etc. This embodiment is not limited here.

[0154] Optionally, the thickness of the first dielectric layer 201 is different from the thickness of the dielectric layer. Further, the thickness of the first dielectric layer 201 is less than the thickness of the dielectric layer.

[0155] Wherein, N is an integer greater than or equal to 2, for example, N can be any integer among 2, 3, 4 or 5, and of course, it can also be other suitable integers. The value of N can be determined according to the number of layers required for the stacked structure 20 in the specific memory design, and this embodiment does not limit this. i is an integer greater than or equal to 1 and less than N, and the value of i is determined according to the value of N. For example, when N is 5, i can be any integer among 1, 2, 3, 4 or 5. The value of i can be determined according to the number of layers required for the stacked structure 20 in the specific memory design, and this embodiment does not limit this. A is an integer greater than or equal to 1 and less than N, for example, when N is 5, A can be any integer among 1, 2, 3, 4 or 5, and the value of i can be determined according to the number of layers required for the stacked structure 20 in the specific memory design, and this embodiment does not limit this. This embodiment does not limit this.

[0156] By utilizing the height misalignment of each conductive layer 202 caused by the step structure 102 and appropriately adjusting the height of the step structure 102, the height of each first dielectric layer 201 and the height of each conductive layer 202, the upper surface of the i-th conductive layer 202 located in the step area can be made flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area.

[0157] For example, taking N as 5 and A as 1, Figure 10-11 As shown, there are 4 conductive layers 202 in the step area and 5 conductive layers 202 in the non-step area. By properly adjusting the height of the step structure 102, the height of each first dielectric layer 201 and the height of each conductive layer 202, it is possible to make: when i=1, the upper surface of the 1st conductive layer 202 in the step area is flush with the upper surface of the 1+1=2nd conductive layer 202 in the non-step area; when i=2, the upper surface of the 2nd conductive layer 202 in the step area is flush with the upper surface of the 2+1=3rd conductive layer 202 in the non-step area; and so on.

[0158] For example, taking N as 6 and A as 2, Fig.12 As shown, Fig.12 is a schematic diagram of a cross-sectional structure of a structure obtained in step S20 in another embodiment, Fig.12 Can be used with Fig.11 Compared with Figure (a) in Fig.12 As shown, there are 4 conductive layers 202 in the step area and 6 conductive layers 202 in the non-step area. By properly adjusting the height of the step structure 102, the height of each first dielectric layer 201 and the height of each conductive layer 202, it is possible to make: when i=1, the upper surface of the 1st conductive layer 202 in the step area is flush with the upper surface of the 1st+2=3rd conductive layer 202 in the non-step area; when i=2, the upper surface of the 2nd conductive layer 202 in the step area is flush with the upper surface of the 2nd+2=4th conductive layer 202 in the non-step area; and so on.

[0159] Since the upper surface of the i-th conductive layer 202 located in the step area is flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area, when a groove is formed in the stacked structure 20, the interconnection plugs 50 corresponding to the conductive layers 202 of the same height but different layers can be prepared using the same preparation process, so the interconnection plugs 50 prepared using the same preparation process can be regarded as the same group of interconnection plug structures. In the preparation process of the same group of interconnection plug structures, only one mask needs to be designed, and etching can be performed based on the same mask to form at least one interconnection plug 50. In addition, the depths of the interconnection plugs 50 included in the same group of interconnection plug structures are the same during the etching process, so there is no need to deliberately adjust the corresponding etching parameters. This can reduce the process steps and save process costs.

[0160] The semiconductor structure comprises: a substrate 10, a stacked structure 20 and a plurality of interconnect plug structures, wherein the substrate 10 comprises a step region and a non-step region. The stacked structure 20 is located on the substrate 10 and comprises a first dielectric layer 201 and a conductive layer 202 alternately stacked from bottom to top; the stacked structure 20 comprises N conductive layers 202; the upper surface of the i-th conductive layer 202 located in the step region is flush with the upper surface of the i+A-th conductive layer 202 located in the non-step region. Multiple groups of interconnect plug structures are located in the step area and the non-step area respectively; each group of interconnect plug structures includes at least one interconnect plug 50, each group of interconnect plug structures is located in the stacked structure 20, and is in one-to-one contact with each conductive layer 202; the interconnect plug 50 connected to the i-th conductive layer 202 in the step area and the interconnect plug 50 connected to the i+A-th conductive layer 202 in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N. Since in the preparation process of the same group of interconnect plug structures, only one photomask needs to be designed to prepare at least one interconnect plug 50, and the etching depth of each interconnect plug 50 in the same group of interconnect plug structures is the same during the etching process, the process steps can be reduced and the process cost can be saved.

[0161] Optionally, the interconnect plug 50 may include a conductive barrier layer and a metal filling layer, the conductive barrier layer may be located at the bottom and sidewalls of the trench, and the metal filling layer may fill the interior of the trench. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filling layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and may be formed by CVD, PVD, ALD, electroplating, or other suitable processes.

[0162] In one embodiment, Figure 2-Figure 3 As shown, a step structure 102 is formed in the step region of the substrate 10 , and the step structure 102 includes a dielectric layer.

[0163] The material of the dielectric layer may be a combination of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2). In this embodiment, the materials of the step structure 102 and the substrate 10 may be different, and the step structure 102 and the substrate 10 are two separate parts.

[0164] In another embodiment, the step structure 102 and the substrate 10 may be made of the same material, and the step structure 102 itself may be a part of the initial substrate 101 .

[0165] In one embodiment, the thickness of the stepped structure 102 is equal to the sum of the thicknesses of the A-layer first dielectric layer 201 and the A-layer conductive layer 202 .

[0166] Among them, the thickness of the step structure 102 can determine to a certain extent whether the upper surfaces of the conductive layer 202 in the step area and the conductive layer 202 in the non-step area can be flush with each other, and the thickness of the step structure 102 can determine to a certain extent which layer of the conductive layer 202 in the step area can be flush with which layer of the conductive layer 202 in the non-step area.

[0167] Based on the above embodiments, in one embodiment, in the stacked structure 20 , the thickness of each first dielectric layer 201 is the same, and the thickness of each conductive layer 202 is the same.

[0168] For example, taking A as 1, Figure 10-11As shown, in step S10, the thickness of the step structure 102 is made equal to the sum of the thickness of one second dielectric layer 40 and one conductive layer 202, and the thicknesses of the first dielectric layers 201 are all the same, and the thicknesses of the second dielectric layers 40 are all the same, so that the upper surface of the i-th conductive layer 202 located in the step area can be flush with the upper surface of the i+1-th conductive layer 202 located in the non-step area.

[0169] For example, taking A as 2, Fig.12 As shown, in step S10, the thickness of the step structure 102 is made equal to the sum of the thickness of the two second dielectric layers 40 and the two conductive layers 202, and the thickness of each first dielectric layer 201 is the same, and the thickness of the second dielectric layer 40 is the same, so that the upper surface of the i-th conductive layer 202 located in the step area can be flush with the upper surface of the i+2-th conductive layer 202 located in the non-step area.

[0170] In this embodiment, by making the thickness of each conductive layer 202 the same, and making the thickness of each second dielectric layer 40 the same, and when the thickness of the first dielectric layer 201 is the same as the sum of the thickness of the A-layer second dielectric layer 40 and the A-layer conductive layer 202 located above the second preset interconnection area, it can be ensured that the upper surface of the i-th conductive layer 202 located in the step area is flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area.

[0171] Of course, in other suitable embodiments, the thickness of each conductive layer 202 is set to be different, or the thickness of each first dielectric layer 201 is set to be different, or the thickness of the step structure 102 may not be equal to the sum of the thickness of the A-layer first dielectric layer 201 and the A-layer conductive layer 202, so that the upper surface of the i-th conductive layer 202 located in the step area can be flush with the upper surface of the i+A-th conductive layer 202 located in the non-step area. Therefore, in other suitable application scenarios, similar solutions will also fall within the protection scope of this application.

[0172] In one embodiment, the stacked structure 20 includes N+1 first dielectric layers 201; the stacked structure 20 located on the step area includes NA conductive layers 202 and N-A+1 first dielectric layers 201, and the stacked structure 20 located on the non-step area includes N conductive layers 202 and N+1 first dielectric layers 201.

[0173] For example, taking N=5 and A=1 as an example, Fig.11 As shown, the stacked structure 20 located on the step area includes 5-1=4 conductive layers 202 and 5-1+1=5 first dielectric layers 201, and the stacked structure 20 located on the non-step area includes 5 conductive layers 202 and 5+1=6 first dielectric layers 201.

[0174] For example, taking N=6 and A=2 as an example, Fig.12 As shown, the stacked structure 20 located on the step area includes 6-2=4 conductive layers 202 and 6-2+1=5 first dielectric layers 201, and the stacked structure 20 located on the non-step area includes 6 conductive layers 202 and 6+1=7 first dielectric layers 201.

[0175] In one embodiment, Figure 23-Figure 24 As shown, the semiconductor structure further includes: an isolation layer 30, a second dielectric layer 40, a plurality of metal interconnection lines 60 and an insulating layer 70. The isolation layer 30 is located on the upper surface of the stacked structure 20. The second dielectric layer 40 is located on the upper surface of the isolation layer 30; each interconnection plug 50 also penetrates the isolation layer 30 and the second dielectric layer 40. A plurality of metal interconnection lines 60 are located on the upper surface of the second dielectric layer 40, and are in one-to-one contact with the upper surface of each group of interconnection plug structures. The insulating layer 70 covers the upper surface of the second dielectric layer 40 and the exposed surface of each metal interconnection line 60.

[0176] The material of the isolation layer 30 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide and silicon oxycarbon nitride. The material of the second dielectric layer 40 may be a combination of one or more of titanium nitride (TiN), silicon nitride (SiN), and silicon dioxide (SiO2). The material of the metal interconnection line 60 may include metals such as copper, gold, titanium, silver, and aluminum, or may include a multilayer metal composed of the above-mentioned metals, or may include a metal alloy, etc., which is not limited in this embodiment.

[0177] In one embodiment, Figure 28-29As shown, each conductive layer 202 is in an I-shape, and each conductive layer 202 includes a first extension portion 202a extending along a first direction, and a second extension portion 202b extending along the first direction. The first extension portion 202a and the second extension portion 202b are arranged at intervals along the second direction, and the first direction intersects the second direction; each conductive layer 202 also includes a third extension portion 202c extending along the second direction, and the third extension portion 202c is located between the first extension portion 202a and the second extension portion 202b, and is integrally connected to the first extension portion 202a and the second extension portion 202b; wherein the first extension portion 202a is located in a step area, and the second extension portion 202b is located in a non-step area, and each group of interconnection plug structures is in contact with the first extension portion 202a and / or the second extension portion 202b. The semiconductor structure also includes a transistor 80 and a capacitor structure 90. The transistor 80 includes a word line 801, a gate insulating layer 802 and a semiconductor layer 803. One side of the semiconductor layer 803 is in contact with the outer side of the third extension portion 202c. The gate insulating layer 802 is located on the inner side wall of the semiconductor layer 803. The inner side of the gate insulating layer 802 is filled with the word line 801. The first electrode and the second electrode of the transistor 80 are both located in the semiconductor layer 803 and are respectively located on both sides of the word line 801. The first electrode of the transistor 80 is connected to the third extension portion 202c, and the capacitor structure 90 is connected to the second electrode of the transistor 80.

[0178] in, Fig.28 A 3D schematic diagram of the semiconductor structure provided in this embodiment, Fig.29 Can be regarded as Fig.28 The schematic diagram of the top view of the structure along the DD' direction. Figure 28-Figure 29 As shown, the first direction may be direction b, the second direction may be direction c, and the third direction may be direction a. Of course, in other suitable application scenarios, the first direction, the second direction, and the third direction may also be defined by other directions, and this embodiment is not limited here.

[0179] The material of the word line 801 may include any suitable material known in the art, such as polysilicon, or other suitable metal materials, etc., which are not limited in this embodiment. Furthermore, the conductivity type of polysilicon may be P-type or N-type, which are not limited in this embodiment. The material of the gate insulating layer 802 may include a high dielectric (High-K) material. The material of the semiconductor layer 803 may include an oxide material, such as Indium Gallium Zinc Oxide (IGZO), Indium Oxide-Zinc Oxide (IZO), and Indium Tin Oxide (ITO).

[0180] Optionally, the transistor 80 may include a Channel-All-Around (CAA) transistor, and the third extension portion 202c may serve as a bit line.

[0181] Among them, the semiconductor structure may include a plurality of transistors 80 and a plurality of capacitor structures 90, each transistor 80 may be arranged at intervals along the third direction to form a plurality of transistor strings arranged at intervals along the first direction and the second direction, and each transistor shares the same word line 801. In other words, a plurality of transistors 80 arranged at intervals along the third direction may be provided in a transistor string. Each capacitor structure 90 is connected to the second pole of each transistor 80 in a one-to-one correspondence. The first pole of the transistor 80 may be a source, and the second pole may be a drain, or the first pole of the transistor 80 may be a drain, and the second pole may be a source. Among them, each transistor 80 may also be arranged at intervals along the first direction, and / or, the second direction.

[0182] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0183] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate includes a step region and a non-step region; A stacked structure, located on the substrate, comprising a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure comprises N layers of the conductive layer; the upper surface of the i-th conductive layer located in the step area is flush with the upper surface of the i+A-th conductive layer located in the non-step area; A plurality of groups of interconnect plug structures are respectively located in the step area and the non-step area; each group of the interconnect plug structures includes at least one interconnect plug, each group of the interconnect plug structures is located in the stacked structure, and is in one-to-one contact with each of the conductive layers; the interconnect plug connected to the i-th conductive layer in the step area and the interconnect plug connected to the i+A-th conductive layer in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N.

2. The semiconductor structure according to claim 1, characterized in that: The step region of the substrate forms a step structure, and the step structure includes a dielectric layer.

3. The semiconductor structure according to claim 2, characterized in that: The thickness of the step structure is equal to the sum of the thickness of the first dielectric layer in layer A and the thickness of the conductive layer in layer A.

4. The semiconductor structure according to claim 2, characterized in that: In the stacked structure, the thickness of each first dielectric layer is the same, and the thickness of each conductive layer is the same.

5. The semiconductor structure according to claim 1, characterized in that: The stacked structure includes N+1 layers of the first dielectric layer; the stacked structure located above the step area includes NA layers of the conductive layer and N-A+1 layers of the first dielectric layer, and the stacked structure located above the non-step area includes N layers of the conductive layer and N+1 layers of the first dielectric layer.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: An isolation layer, located on the upper surface of the laminated structure; A second dielectric layer is located on the upper surface of the isolation layer; each of the interconnect plugs also penetrates the isolation layer and the second dielectric layer; A plurality of metal interconnection lines are located on the upper surface of the second dielectric layer and are in one-to-one contact with the upper surface of each group of the interconnection plug structures; An insulating layer covers the upper surface of the second dielectric layer and the exposed surfaces of each of the metal interconnections.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: Each layer of the conductive layer is in an I-shape, and each layer of the conductive layer includes a first extension portion extending along a first direction, and a second extension portion extending along the first direction, the first extension portion and the second extension portion are arranged at intervals along the second direction, and the first direction intersects with the second direction; each layer of the conductive layer also includes a third extension portion extending along the second direction, the third extension portion is located between the first extension portion and the second extension portion, and is integrally connected to the first extension portion and the second extension portion; wherein the first extension portion is located in the step area, the second extension portion is located in the non-step area, and each group of the interconnection plug structures is in contact with the first extension portion and / or the second extension portion; The semiconductor structure further comprises: A transistor, the transistor comprising a word line, a gate insulating layer and a semiconductor layer, one side of the semiconductor layer is in contact with the outer side of the third extension portion, the gate insulating layer is located on the inner side wall of the semiconductor layer, the inner side of the gate insulating layer is filled with the word line, the first electrode and the second electrode of the transistor are both located in the semiconductor layer and are respectively located on both sides of the word line, and the first electrode of the transistor is connected to the third extension portion; The capacitor structure is connected to the second electrode of the transistor.

8. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate includes a step region and a non-step region; A stacked structure is formed on the substrate; the stacked structure comprises a first dielectric layer and a conductive layer alternately stacked from bottom to top; the stacked structure comprises N layers of the conductive layer; the upper surface of the i-th conductive layer located in the step area is flush with the upper surface of the i+A-th conductive layer located in the non-step area; A plurality of groups of interconnect plug structures are formed in the stacked structure, each group of the interconnect plug structures is located in the step area and the non-step area respectively; each group of the interconnect plug structures includes at least one interconnect plug, each group of the interconnect plug structures is located in the stacked structure, and is in one-to-one contact with each of the conductive layers; the interconnect plug connected to the i-th conductive layer in the step area and the interconnect plug connected to the i+A-th conductive layer in the non-step area are formed by the same preparation process; wherein N is an integer greater than or equal to 2, i is an integer greater than or equal to 1 and less than N, A is an integer greater than or equal to 1 and less than N, and i+A is less than or equal to N.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The step region of the substrate is formed with a step structure; the substrate is provided, the substrate including the step region and the non-step region, including: Providing an initial substrate; the initial substrate comprises a step region and a non-step region; A portion of the initial substrate in the non-step region is removed to form the substrate, and the initial substrate in the step region is retained as the step structure.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that: The step region of the substrate is formed with a step structure, and the step structure includes a dielectric layer; the substrate is provided, and the substrate includes the step region and the non-step region, including: Providing an initial substrate; the initial substrate comprises a step region and a non-step region; forming the dielectric layer on the initial substrate; A portion of the dielectric layer in the non-step region is removed to form the substrate, and the dielectric layer in the step region is retained as the step structure.

11. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: The thickness of the step structure is equal to the sum of the thickness of the first dielectric layer in layer A and the thickness of the conductive layer in layer A.

12. The method for preparing a semiconductor structure according to claim 9 or 10, characterized in that: In the stacked structure, the thickness of each first dielectric layer is the same, and the thickness of each conductive layer is the same.

13. The method for preparing a semiconductor structure according to claim 8, characterized in that: The forming of a stacked structure on the substrate comprises: Forming N+1 layers of the first dielectric layer and N layers of the conductive layer in sequence from bottom to top on the substrate; Part of the stacked structure located in the step area is removed, so that the stacked structure located above the step area includes NA layers of the conductive layer and N-A+1 layers of the first dielectric layer, and the stacked structure located above the non-step area includes N layers of the conductive layer and N+1 layers of the first dielectric layer.

14. The method for preparing a semiconductor structure according to claim 8, characterized in that: After forming a stacked structure on the substrate and before forming a plurality of interconnect plug structures in the stacked structure, the method for preparing the semiconductor structure further includes: forming an isolation layer on the upper surface of the laminated structure; A second dielectric layer is formed on the upper surface of the isolation layer; and each of the interconnection plugs also penetrates the isolation layer and the second dielectric layer.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: After forming a plurality of interconnect plug structures in the stacked structure, the method for preparing the semiconductor structure further includes: forming a plurality of metal interconnection lines on the upper surface of the second dielectric layer, wherein each of the metal interconnection lines is in one-to-one contact with the upper surface of each group of the interconnection plug structures; An insulating layer is formed on the upper surface of the second dielectric layer and the exposed surfaces of each of the metal interconnections.

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