Packaging structure and electronic equipment

Abstract

The invention provides a packaging structure and electronic equipment, and the structure comprises a plurality of chips which are laminated and are arranged in an insulating manner; the packaging piece is used for packaging the plurality of chips, and a plurality of via holes are formed in the packaging piece; and a plurality of conductive patterns, the plurality of conductive patterns are respectively filled in the plurality of via holes, and each chip is connected with at least one conductive pattern. According to the invention, the chips are arranged in a laminated manner, and the packaging height is increased and the packaging area of the integrated circuit is reduced by adopting a plastic packaging material through hole process with lower cost, so that the utilization rate of the number of the packaged chips is increased.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip packaging technology, and in particular to a packaging structure and an electronic device. Background Art

[0002] With the development of multifunctionality, intelligence and miniaturization of terminal electronic products, the requirements for packaging technology have also increased significantly. The traditional through silicon via (TSV) process is used to achieve vertical electrical interconnection of silicon vias by filling with conductive materials such as copper, tungsten and polysilicon. However, the packaging cost is high, the process is complicated, and the packaging volume is also large, which is not conducive to the development of miniaturization of electronic products. Summary of the invention

[0003] The embodiments of the present invention provide a packaging structure and an electronic device to solve the problems of high cost and large packaging volume in the prior art.

[0004] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides a packaging structure, including:

[0006] A plurality of chips, wherein the plurality of chips are stacked and insulated;

[0007] A package, used to package the multiple chips, wherein the package is provided with multiple vias;

[0008] A plurality of conductive patterns are respectively filled in the plurality of via holes, wherein each of the chips is connected to at least one of the conductive patterns.

[0009] Optionally, also include:

[0010] The transfer layer is arranged on one side of the package where the via hole is opened, and is used for transferring the conductive pattern to the driving substrate.

[0011] Optionally, the transfer layer includes: a passivation layer, and a redistribution layer and a pad disposed on the passivation layer, and the redistribution layer is connected to the conductive pattern.

[0012] Optionally, also include:

[0013] A solder ball is disposed on a side of the transfer layer away from the package and is transferred to the pad.

[0014] Optionally, among the multiple chips, sizes of the chips gradually decrease in a direction close to a side of the package where the via hole is opened.

[0015] Optionally, among two adjacent chips, the orthographic projection of the chip on the package that is closer to the side of the package where the via hole is opened is within the orthographic projection area on the package of the chip on the side that is farther from the package where the via hole is opened.

[0016] Optionally, among two adjacent chips, a part of the orthographic projection of the chip on the package that is farther away from the side of the package where the via is opened is not located within the orthographic projection area of ​​the chip on the package that is closer to the side of the package where the via is opened.

[0017] Optionally, an insulating layer is provided between adjacent chips.

[0018] Optionally, the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is arranged on the side of the chip in the direction of the via hole on the side close to the package, and the second insulating layer is arranged between the first insulating layer and the chip in the direction of the via hole on the side away from the package.

[0019] In a second aspect, an embodiment of the present invention provides an electronic device, using the packaging structure described in any one of the first aspects.

[0020] In the present invention, by arranging the chips in layers and adopting a lower-cost plastic packaging material through-hole process, the package height is increased and the integrated circuit package area is reduced, the utilization rate of the number of packaged chips is increased, and the problems of high packaging cost, complex process and large packaging volume in the prior art are solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0022] Figure 1 is a structural schematic diagram of a packaging structure provided by an embodiment of the present invention;

[0023] Figure 2 It is a structural schematic diagram of another packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Please refer to Figure 1 , an embodiment of the present invention provides a packaging structure, including:

[0026] A plurality of chips 1, wherein the plurality of chips 1 are stacked and insulated;

[0027] In the embodiment of the present invention, a plurality of chips 1 are stacked and insulated, for example Figure 1 The first chip and the second chip in the device, wherein the multiple chips can be silicon-based chips; the packaging area of ​​the integrated circuit is reduced by the stacked arrangement, which is conducive to the miniaturization of electronic equipment.

[0028] In the embodiment of the present invention, optionally, an insulating layer is arranged between adjacent chips 1; the insulating layer 6 includes a first insulating layer 61 and a second insulating layer 62, the first insulating layer 61 is arranged on the side of the first chip close to the second chip, and the second insulating layer 62 is arranged on the side of the second chip close to the first chip; a third insulating layer is also arranged on the side of the second chip away from the first chip; the material of the first insulating layer 61 may include but is not limited to insulating glue, the material of the second insulating layer 62 may include but is not limited to polyimide, and the material of the third insulating layer may include but is not limited to polyimide; by setting the insulating material to space the chips, circuit abnormalities caused by series connection or other forms between the stacked chips can be prevented, and the function of sealing and buffering protection can be played.

[0029] A package 2, used to package a plurality of chips 1, and a plurality of vias 21 are provided on the package 2;

[0030] In the embodiment of the present invention, the material of the package 2 can be but is not limited to epoxy molding compound (EMC), and can be formed by the epoxy molding compound molding process, that is, the epoxy plastic is extruded into the mold cavity by transfer molding and the multiple chips 1 therein are embedded, and after cross-linking and curing in the mold cavity, it is formed into a package 2 with a certain structural shape and covering the multiple chips 1; by opening a plurality of vias 21 at one end of the package 2 to expose the first surfaces of the multiple chips 1 so as to connect to the conductive pattern through the first surface of the chip 1 for conduction, the cost of using the molding compound through-hole process (TMV) is lower and the manufacturing process is simpler, thereby saving costs.

[0031] A plurality of conductive patterns 3 are respectively filled in the plurality of via holes 21 , wherein each chip 1 is connected to at least one conductive pattern 3 .

[0032] In the embodiment of the present invention, multiple conductive patterns 3 are respectively filled in the insulating material where the multiple vias are located. The material of the conductive patterns 3 may include but is not limited to conductive metals such as copper and tungsten. The multiple chips 1 are connected to the driving substrate of the integrated circuit through the conductive patterns 3.

[0033] In the embodiment of the present invention, by arranging the chips in layers and adopting a lower-cost plastic packaging material through-hole process, the package height is increased and the integrated circuit package area is reduced, thereby increasing the utilization rate of the number of packaged chips, thereby solving the problems of high packaging cost, complex process, and large packaging volume in the prior art.

[0034] In the embodiment of the present invention, optionally, the packaging structure further includes:

[0035] The transfer layer 4 is disposed on one side of the package 2 where the via hole 21 is opened, and is used to transfer the conductive pattern 3 to the driving substrate.

[0036] In an embodiment of the present invention, the transfer layer 4 includes: a passivation layer 41 and a redistribution layer 42 and a pad 43 arranged on the passivation layer 41. The redistribution layer 42 is connected to the conductive pattern 3 and is used to transfer the conductive pattern 3 to the driving substrate. The material of the passivation layer 41 can be but is not limited to being set to polyimide.

[0037] In the embodiment of the present invention, optionally, the following further comprises:

[0038] The solder ball 5 is disposed on a side of the transfer layer away from the package 2 and is transferred to the solder pad 43 .

[0039] In the embodiment of the present invention, in addition to the purpose of conducting electricity, the solder ball packaging helps to achieve good thermal management. Since tin has good thermal conductivity, it can effectively conduct heat, help dissipate heat and keep the temperature of electronic components within an acceptable range, and provide mechanical support for the electronic components and play a buffering role. At the same time, the solder ball packaging can achieve a compact layout of components and space saving, so that electronic equipment can use space more efficiently and achieve a smaller, lighter, and more highly integrated design.

[0040] In the embodiment of the present invention, optionally, among the multiple chips, the size of the chip gradually decreases in the direction close to the side of the package where the via hole is opened.

[0041] Please refer to Figure 1In the embodiment of the present invention, among two adjacent chips, the orthographic projection of the chip on the side close to the package 2 where the via hole 21 is opened is within the orthographic projection area of ​​the chip on the side away from the package 2 where the via hole 21 is opened, that is, the orthographic projection area of ​​the first chip on the package 2 is larger than the orthographic projection area of ​​the second chip on the package 2. The packaging area of ​​the integrated circuit is reduced by stacking and covering, which is conducive to the miniaturization of electronic equipment.

[0042] Please refer to Figure 2 In an embodiment of the present invention, optionally, among two adjacent chips, a portion of the orthographic projection of the chip on the side away from the package where the via is opened is not located within the orthographic projection area of ​​the chip on the side close to the package where the via is opened, that is, a portion of the orthographic projection area of ​​the first chip on the package 2 is not located within the orthographic projection area of ​​the second chip on the package 2. By stacking and staggered arrangement, the packaging area of ​​the integrated circuit is reduced, which is conducive to the miniaturization of electronic devices.

[0043] An embodiment of the present invention provides an electronic device, applying any packaging structure as described in the first aspect.

[0044] In the embodiment of the present invention, the packaging structure is used to package the chip used in the integrated circuit, and can be specifically applied to electronic devices such as storage devices, automotive electronics, and navigation devices. By arranging the chips in layers and adopting a lower-cost plastic packaging material through-hole process, the packaging height is increased and the integrated circuit packaging area is reduced, thereby increasing the utilization rate of the number of packaged chips, which is conducive to the development of miniaturization of terminal electronic devices.

[0045] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0046] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0047] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A packaging structure, characterized in that: include: A plurality of chips, wherein the plurality of chips are stacked and insulated; A package, used to package the multiple chips, wherein the package is provided with multiple vias; A plurality of conductive patterns are respectively filled in the plurality of via holes, wherein each of the chips is connected to at least one of the conductive patterns.

2. The packaging structure according to claim 1, characterized in that: Also includes: The transfer layer is arranged on one side of the package where the via hole is opened, and is used for transferring the conductive pattern to the driving substrate.

3. The packaging structure according to claim 2, characterized in that: The transfer layer includes: a passivation layer, and a redistribution layer and a pad arranged on the passivation layer, and the redistribution layer is connected to the conductive pattern.

4. The packaging structure according to claim 3, characterized in that: Also includes: A solder ball is disposed on a side of the transfer layer away from the package and is transferred to the pad.

5. The packaging structure according to claim 1, characterized in that: Among the plurality of chips, sizes of the chips gradually decrease in a direction close to a side of the package where the via hole is opened.

6. The packaging structure according to claim 5, characterized in that: Of the two adjacent chips, the orthographic projection of the chip close to the side of the package where the via hole is opened on the package is within the orthographic projection area of ​​the chip away from the side of the package where the via hole is opened on the package.

7. The packaging structure according to claim 1, characterized in that: Of the two adjacent chips, a portion of the orthographic projection of the chip on the package that is farther away from the side of the package where the via hole is opened is not located within the orthographic projection area of ​​the chip on the package that is closer to the side of the package where the via hole is opened.

8. The packaging structure according to claim 1, characterized in that: An insulating layer is disposed between adjacent chips.

9. The packaging structure according to claim 8, characterized in that: The insulating layer includes a first insulating layer and a second insulating layer. The first insulating layer is arranged on a side of the chip in the direction of a via hole on a side close to the package, and the second insulating layer is arranged between the first insulating layer and the chip in the direction of a via hole on a side away from the package.

10. An electronic device, characterized in that: Application of the packaging structure as described in any one of claims 1 to 9.

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