Carrier synchronization method and device, inverter and storage medium

Abstract

The invention discloses a carrier synchronization method and device, an inverter and a storage medium, and relates to the technical field of carrier control, and the method comprises the steps: transmitting a host competition signal to a carrier bus in a system when a slave inverter in an inverter parallel system cannot acquire a carrier signal transmitted by a master inverter in the system and reaches a first preset duration, and then transmitting the host competition signal to the carrier bus in the system; all slave inverters in the system respond to the host competition signal to send a first identification number to the bus, and monitor a bus identification number transmitted in the bus at the same time, when a certain slave inverter finds that the first identification number sent by the slave inverter is matched with the bus identification number, it is confirmed that host competition succeeds, and the slave inverters send the first identification number to the bus. The main inverter sends carrier signals to the bus, the other slave inverters acquire the carrier signals to perform carrier synchronization, and the slave inverters establish a master-slave structure of the system through competition of the host, so that the carrier synchronization function of the system is established or recovered, the carrier synchronization stability of the system is improved, and the circulating current of the system can be efficiently inhibited.

Description

Technical Field

[0001] The present invention relates to the field of carrier control technology, and in particular to a carrier synchronization method, device, inverter and storage medium. Background Art

[0002] At present, the circulating current suppression for the inverter parallel system is all based on the carrier synchronization method. In the method of obtaining the carrier signal based on the enhanced acquisition module (ECAP) for carrier synchronization, the inverter parallel system needs to be set as a master-slave control structure, and the carrier synchronization can only be performed by manually issuing master-slave instructions. In this way, once there is an abnormality in the host in the inverter parallel system, the entire inverter parallel system will shut down because it cannot obtain the carrier signal sent by the host based on ECAP, making it difficult to suppress the system circulating current by stably performing carrier synchronization. Summary of the invention

[0003] The purpose of the present invention is to solve at least one of the technical problems existing in the prior art, and to provide a carrier synchronization method, device, inverter and storage medium, which can improve the stability of the inverter parallel system in obtaining carrier signals based on ECAP for carrier synchronization, thereby efficiently suppressing the system circulation.

[0004] In a first aspect, an embodiment of the present invention provides a carrier synchronization method, which is applied to any slave inverter in an inverter parallel system, wherein the slave inverter obtains a carrier signal sent by a master inverter in the inverter parallel system for carrier synchronization; any inverter in the inverter parallel system is respectively connected to a carrier bus in the inverter parallel system;

[0005] The method comprises:

[0006] When a first duration in which a carrier signal is not obtained reaches a first preset duration, sending a host competition signal to the carrier bus;

[0007] In response to the host contention signal, sending a first identification number to the carrier bus and monitoring a bus identification number in the carrier bus;

[0008] When the first identification number matches the bus identification number, the master inverter in the inverter parallel system sends a carrier signal to the carrier bus, so that other slave inverters in the inverter parallel system can obtain the carrier signal for carrier synchronization.

[0009] The carrier synchronization method provided in accordance with an embodiment of the present invention has at least the following beneficial effects: when a slave inverter in an inverter parallel system (hereinafter referred to as the "system") cannot obtain the carrier signal sent by the master inverter (for example, the master inverter has an abnormality and does not send the carrier signal), and when the first duration of the slave inverter not obtaining the carrier signal reaches a first preset duration, the slave inverter enters the host competition mode and sends a host competition signal to the carrier bus in the system. Thereafter, the slave inverter starts to send a first identification number to the carrier bus in response to the host competition signal, and simultaneously monitors the bus identification number transmitted in the carrier bus. When the first identification number matches the bus identification number, the slave inverter confirms that it has successfully competed for the host, thereby sending a carrier signal to the carrier bus as the master inverter in the system, and the remaining slave inverters can normally obtain the carrier signal for carrier synchronization. In this way, even if the main inverter in the system has an abnormality that causes the system carrier synchronization function to crash, the slave inverter in the system can still establish a new master-slave structure of the system by competing with the host after detecting that ECAP has timed out and has not obtained the carrier signal, thereby restoring the system carrier synchronization function, improving the stability of the system based on ECAP to obtain the carrier signal for carrier synchronization, and can effectively suppress the system circulation.

[0010] In addition, even if the system is not assigned to a master-slave machine at the beginning, and each inverter in the system is set as a slave inverter by default, then after the system is powered on and put into operation, each slave inverter can automatically establish the system's carrier synchronization function through competition to suppress the system's circulating current. This does not rely on manual issuance of master-slave machine assignment instructions and human intervention to restore the carrier synchronization function. This improves the efficiency of the system in suppressing circulating current through carrier synchronization while also improving the level of intelligence.

[0011] According to the carrier synchronization method provided by some embodiments of the present invention, any inverter in the inverter parallel system includes a bus logic circuit, and any inverter is connected to the carrier bus through its own bus logic circuit;

[0012] The sending of a first identification number to the carrier bus and monitoring a bus identification number in the carrier bus comprises:

[0013] A first identification number is sent to the carrier bus based on the bus logic circuit, and a level signal in the carrier bus is obtained as a bus identification number in the carrier bus.

[0014] According to the carrier synchronization method provided by some embodiments of the present invention, when the bus logic circuits of all inverters in the inverter parallel system send a high level to the carrier bus, the level signal in the carrier bus is high, and when the bus logic circuit of any inverter among all the inverters sends a low level to the carrier bus, the level signal in the carrier bus is low;

[0015] The method further comprises:

[0016] When the level logic corresponding to the first identification number is the same as the level logic of the level signal in the carrier bus, it is confirmed that the first identification number matches the bus identification number.

[0017] According to some embodiments of the present invention, the carrier synchronization method further includes:

[0018] When the first identification number does not match the bus identification number, obtaining a carrier signal as a slave inverter in the inverter parallel system;

[0019] When the carrier signal is acquired and the second duration that is not synchronized with the acquired carrier signal reaches a second preset duration, the pulse width modulation period is gradually adjusted according to the preset period offset value;

[0020] Among them, the preset cycle offset value is any one in the preset offset range, and the second duration includes: the time consumed for carrier synchronization adjustment by adjusting the pulse width modulation period according to the initial cycle offset value; the initial cycle offset value is less than the maximum value of the preset offset range and greater than the minimum value of the preset offset range.

[0021] According to the carrier synchronization method provided by some embodiments of the present invention, the step of gradually adjusting the pulse width modulation period according to the preset period offset value to perform carrier synchronization adjustment includes at least one of the following:

[0022] Increasing the pulse width modulation period according to a preset step length until the offset of the pulse modulation period increase is equal to a preset period offset value;

[0023] The pulse width modulation period is reduced according to a preset step length until the offset amount of the pulse modulation period reduction is equal to the preset period offset value.

[0024] According to some embodiments of the present invention, the carrier synchronization method further includes:

[0025] Counting the count deviation value of the acquired carrier signal; wherein the count deviation value is: the deviation value between the count of the synchronization signal sent to the carrier bus and the count of the carrier signal;

[0026] When the integral of the count deviation value is greater than or equal to a preset integral threshold, confirming that it is not synchronized with the acquired carrier signal, and recording a duration during which the integral of the count deviation value is greater than or equal to the preset integral threshold as the second duration;

[0027] When the integral of the count deviation value is less than the preset integral threshold, and the duration for which the integral of the count deviation value is less than the preset integral threshold reaches a third preset time length, synchronization with the acquired carrier signal is confirmed.

[0028] According to some embodiments of the present invention, the carrier synchronization method further includes:

[0029] When the first identification number does not match the bus identification number, obtaining a carrier signal as a slave inverter in the inverter parallel system;

[0030] When the carrier signal is acquired, and in synchronization with the acquired carrier signal, a circulating current monitoring result of the inverter current of the inverter parallel system is acquired; wherein the circulating current monitoring result is obtained based on multi-sampling monitoring of the inverter current;

[0031] A static compensation operation of carrier synchronization is performed according to the circulation monitoring result; wherein the static compensation operation includes: according to the circulation direction of the inverter current indicated by the circulation monitoring result, the static compensation error is gradually swung within a preset phase compensation range to compensate for the phase deviation in the circulation direction.

[0032] In a second aspect, an embodiment of the present invention provides another carrier synchronization method, which is also applied to any slave inverter in an inverter parallel system, wherein the slave inverter obtains a carrier signal sent by a master inverter in the inverter parallel system for carrier synchronization; any inverter in the inverter parallel system is respectively connected to a carrier bus in the inverter parallel system;

[0033] The method comprises any of the following:

[0034] When a carrier signal is acquired and a second duration that is not synchronized with the acquired carrier signal reaches a second preset duration, the pulse width modulation period is gradually adjusted according to a preset period offset value; wherein the preset period offset value is any one of a preset offset range; the second duration includes: the time spent on adjusting the pulse width modulation period for carrier synchronization adjustment according to an initial period offset value; the initial period offset value is less than a maximum value of the preset offset range and greater than a minimum value of the preset offset range;

[0035] When a carrier signal is acquired and synchronized with the acquired carrier signal, a carrier-synchronized static compensation operation is performed according to the circulating current monitoring result of the inverter current of the inverter parallel system; wherein the circulating current monitoring result is obtained based on multi-sampling monitoring of the inverter current; the static compensation operation includes: according to the circulating current direction of the inverter current indicated by the circulating current monitoring result, the static compensation error is gradually swung within a preset phase compensation range to compensate for the phase offset in the circulating current direction.

[0036] The carrier synchronization method provided according to an embodiment of the present invention has at least the following beneficial effects: by adopting a variable pulse modulation period swing range from the inverter in the system, the carrier synchronization failure caused by the large system clock difference can be effectively avoided, thereby further improving the stability of the system carrier synchronization function.

[0037] In addition, based on the synchronization of the local synchronization signal and the carrier signal of the slave inverter in the system, the static compensation error is gradually swung within a preset phase compensation range according to the circulation direction of the circulating current generated by the inverter current indicated by the circulating current monitoring result, thereby compensating for the phase deviation in the circulating current direction indicated by the circulating current monitoring result according to the static compensation error after the swing.

[0038] In a third aspect, an embodiment of the present invention provides another carrier synchronization method, which is still applied to any slave inverter in the inverter parallel system, wherein the slave inverter obtains the carrier signal sent by the master inverter in the inverter parallel system for carrier synchronization; any inverter in the inverter parallel system is respectively connected to a carrier bus in the inverter parallel system;

[0039] The method comprises:

[0040] The carrier signal is obtained based on the simultaneous acquisition of the rising edge mark and the falling edge mark; wherein the main inverter in the inverter parallel system uses a preset first duty cycle to send the carrier signal at a non-zero-crossing point of the power grid cycle, and uses a preset second duty cycle to send the carrier signal at a zero-crossing point of the power grid cycle, and the preset second duty cycle is smaller than the preset first duty cycle;

[0041] When the carrier signal is obtained, the zero-crossing point of the power grid cycle is determined according to the duty cycle of the obtained carrier signal.

[0042] The carrier synchronization method provided by the embodiment of the present invention has at least the following beneficial effects: the main inverter in the system uses a larger duty cycle to send the carrier synchronization signal when it is not crossing the zero point in the power grid cycle, and uses a smaller duty cycle to send the carrier synchronization at the zero-crossing moment, the inverter captures the rising edge and the falling edge of the carrier signal at the same time to perform carrier synchronization, and the zero-crossing point of the main inverter is determined by calculating the duty cycle of the carrier signal in the current cycle. In this way, on the basis of realizing carrier synchronization in the system, the function of power frequency synchronization can be realized by sharing the carrier bus, saving system costs.

[0043] In a fourth aspect, an embodiment of the present invention provides a carrier synchronization device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the carrier synchronization method as described in the embodiment of the first aspect above.

[0044] The carrier synchronization device provided according to the embodiment of the present invention has at least the following beneficial effects: when the first duration of the slave inverter where the carrier synchronization device is located not obtaining the carrier signal reaches the first preset duration, the carrier synchronization device causes the slave inverter to enter the competition host mode and send a host competition signal to the system, and then causes the slave inverter to send a first identification number to the system in response to the host competition signal, and simultaneously monitors the bus identification number issued by the system bus, and when the first identification number matches the bus identification number, confirms that the slave inverter successfully competes for the host, so that the slave inverter sends the carrier signal as the master inverter in the system, and the remaining slave inverters can normally obtain the carrier signal for carrier synchronization. In this way, even if the master inverter in the system is abnormal and causes the system carrier synchronization function to shut down, the slave inverters in the system can still establish a new master-slave structure of the system by competing with the host, thereby restoring the system carrier synchronization function, improving the stability of the system for carrier synchronization, and being able to efficiently suppress the system circulation.

[0045] In a fifth aspect, an embodiment of the present invention provides an inverter, comprising the carrier synchronization device as described in the embodiment of the second aspect above.

[0046] The inverter provided according to the embodiment of the present invention has at least the following beneficial effects: the inverter can utilize the carrier synchronization device to make the slave inverter enter the competition host mode and send the host competition signal to the system when the first duration of the slave inverter not obtaining the carrier signal reaches the first preset duration, and then make the slave inverter send the first identification number to the system in response to the host competition signal, and simultaneously monitor the bus identification number issued by the system bus, and when the first identification number matches the bus identification number, confirm that the slave inverter successfully competes for the host, so that the slave inverter sends the carrier signal as the master inverter in the system, and the remaining slave inverters can normally obtain the carrier signal for carrier synchronization. In this way, even if the master inverter in the system is abnormal and causes the system carrier synchronization function to shut down, the slave inverters in the system can still establish a new master-slave structure of the system by competing with the host, thereby restoring the system carrier synchronization function, improving the stability of the system for carrier synchronization, and being able to efficiently suppress the system circulation.

[0047] In a sixth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the carrier synchronization method as described in the embodiment of the first aspect above.

[0048] The computer-readable storage medium provided according to the embodiment of the present invention has at least the following beneficial effects: when the first duration of the slave inverter in the system not obtaining the carrier signal reaches the first preset duration, the slave inverter is made to enter the competition host mode to send a host competition signal to the system, and then the slave inverter is made to send a first identification number to the system in response to the host competition signal, and simultaneously monitor the bus identification number issued by the system bus, and when the first identification number matches the bus identification number, it is confirmed that the slave inverter successfully competes for the host, so that the slave inverter sends the carrier signal as the master inverter in the system, and the remaining slave inverters can normally obtain the carrier signal for carrier synchronization. In this way, even if the master inverter in the system is abnormal and causes the system carrier synchronization function to crash, the slave inverters in the system can still establish a new master-slave structure of the system by competing with the host, thereby restoring the system carrier synchronization function, improving the stability of the system for carrier synchronization, and being able to efficiently suppress the system circulation.

[0049] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0051] The present invention is further described below in conjunction with the accompanying drawings and embodiments;

[0052] Figure 1 is a structural schematic diagram of an inverter parallel system provided by an embodiment of the present invention;

[0053] Figure 2 is a flow chart of a carrier synchronization method provided by an embodiment of the present invention;

[0054] Figure 3 is a flow chart of a carrier synchronization method according to a specific embodiment of the present invention;

[0055] Figure 4 It is a flow chart of determining synchronization status involved in a carrier synchronization method provided by an embodiment of the present invention;

[0056] Figure 5 It is a flow chart of static compensation involved in a carrier synchronization method provided by an embodiment of the present invention;

[0057] Figure 6is a flow chart of another carrier synchronization method provided by an embodiment of the present invention;

[0058] Figure 7 is a flow chart of another carrier synchronization method provided by an embodiment of the present invention;

[0059] Figure 8 It is a structural diagram of a carrier synchronization device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0060] This section will describe in detail the specific embodiments of the present invention. The preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the accompanying drawings is to supplement the description of the text part of the specification with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of the present invention, but it cannot be understood as a limitation on the scope of protection of the present invention.

[0061] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, "above", "below", "within", etc. are understood to include the number itself, "any one" means one or more, "at least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. If there is a description of the first and the second, it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0062] It should be noted that the terms such as setting, parallel connection, and connection in the embodiments of the present invention should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the embodiments of the present invention in combination with the specific content of the technical solution. For example, the term "connection" can be a mechanical connection, an electrical connection, or mutual communication; it can be directly connected or indirectly connected through an intermediate medium.

[0063] It should be noted that the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0064] It is understandable that the circulating current suppression methods commonly used in the field of inverter parallel connection are all based on carrier synchronization. Among them, carrier synchronization based on ECAP to obtain carrier signals is one of the commonly used carrier synchronization implementation methods. ECAP obtains carrier signals for carrier synchronization in a balanced form in terms of cost, synchronization effect and anti-interference, but its own logic is relatively complex and requires a master-slave structure. At the same time, the effect of carrier synchronization is also affected by the delay of the synchronization signal. Usually, the signal delay problem can only be alleviated by fixed compensation to ensure the synchronization effect.

[0065] In the method of obtaining carrier signals based on ECAP for carrier synchronization, since the inverter parallel system needs to be set as a master-slave control structure and relies on manual issuance of master-slave instructions to perform carrier synchronization, once there is an abnormality in the host in the inverter parallel system, the entire inverter parallel system will crash because it cannot obtain the carrier signal sent by the host based on ECAP, making it difficult to suppress the system circulation by stable carrier synchronization.

[0066] In response to the problems in the related art, the embodiments of the present invention provide a carrier synchronization method, device, inverter and storage medium, which can improve the stability of the inverter parallel system in obtaining carrier signals based on ECAP for carrier synchronization, thereby efficiently suppressing the system circulation.

[0067] First, refer to Figure 1 and Figure 2 , an embodiment of the present invention provides a carrier synchronization method, which is applied to any slave inverter in an inverter parallel system.

[0068] like Figure 1 As shown, any inverter in the system is connected to the carrier bus respectively. Specifically, any inverter in the system includes a digital signal processing chip DSP and a bus logic circuit, the DSP chip is connected to the bus logic circuit, and the bus logic circuit is further connected to the carrier bus. The main inverter in the system sends a digital carrier signal to the bus logic circuit through the connection between the DSP chip and the bus logic circuit, and the digital carrier signal is converted into a level carrier signal by the bus logic circuit and transmitted to the carrier bus. The slave inverter in the system obtains the level carrier signal on the carrier bus through its own bus logic circuit, and through the connection between its own DSP chip and the bus logic circuit, captures (for example, based on the enhanced capture module ECAP to perform signal capture) to the digital carrier signal obtained by converting the level carrier signal to the bus logic circuit, and after analyzing and processing the digital carrier signal based on the DSP chip, it still sends a digital synchronization signal to the bus logic circuit through the connection between its own DSP chip and the bus logic circuit, and the digital synchronization signal is converted into a level carrier signal by the bus logic circuit and transmitted to the carrier bus. In this way, the system can complete the carrier synchronization function. In addition, the inverter in the system also connects the bus state detection port to the carrier bus, so that the level signal transmitted on the carrier bus can be obtained.

[0069] like Figure 2 As shown, Figure 2 1 is a flow chart of a carrier synchronization method provided by an embodiment of the present invention. The carrier synchronization method includes but is not limited to the following steps S100 to S300:

[0070] Step S100: When a first duration during which a carrier signal is not obtained reaches a first preset duration, a host competition signal is sent to the carrier bus.

[0071] In this step, any slave inverter in the system acquires a carrier signal based on ECAP after the system is powered on. When the slave inverter detects that the carrier signal is not acquired based on ECAP, it starts to record the first duration of not acquiring the carrier signal based on ECAP. For example, the slave inverter can confirm that the carrier signal is not acquired based on ECAP when the falling edge mark of ECAP is not detected, and record the duration of not detecting the falling edge mark of ECAP as the first duration. Further, when the first duration increases to be greater than or equal to the first preset duration, the slave inverter confirms that there is no master inverter sending a carrier signal in the system at present or the master inverter in the system has not sent a carrier signal for an abnormally long time. In this way, the slave inverter enters the competition host mode to send a host competition signal to the carrier bus in the system.

[0072] In some embodiments, the first preset duration may be a pre-set time threshold, such as 100, 500, 1000 milliseconds or more. If the first duration recorded by the slave inverter for not obtaining a carrier signal based on ECAP reaches 1000 milliseconds, that is, the system has not designated the master inverter to send a carrier signal for carrier synchronization from power-on to greater than or equal to 1000 milliseconds, or the system fails to send a carrier signal due to an abnormality in the main inverter during power-on and causes the system carrier synchronization function to shut down for greater than or equal to 1000 milliseconds, then it can be considered that the system needs to re-establish carrier synchronization. In this way, when the first duration recorded by the slave inverter reaches 1000 milliseconds, the slave inverter enters the competition host mode to send a host competition signal to the carrier bus in the system.

[0073] It should be noted that the host competition signal can be a unified signal for all inverters or all slave inverters in the system, which pre-negotiates the working mode of acquiring the carrier signal for carrier synchronization and switches to the competing host working mode. Specifically, the host competition signal can be a 50% pulse width lasting 5 milliseconds, a 75% pulse width lasting 100 milliseconds and / or a 90% pulse width lasting 3 milliseconds. It is understandable that all inverters or all slave inverters in the system can of course pre-negotiate other level signals not listed here as host competition signals, so that after acquiring the host competition signal in the system, the working mode of acquiring the carrier signal for carrier synchronization will be switched to the competing host working mode.

[0074] In step S200 , in response to the host contention signal, a first identification number is sent to the carrier bus and a bus identification number in the carrier bus is monitored.

[0075] It should be noted that the first identification number may be a unique identification number of each slave inverter. For example, the first identification number may be a unique product serial number SN of each slave inverter.

[0076] In addition, when all inverters or all slave inverters in the system pre-negotiate a unified host competition signal, in addition to negotiating the specific content of the host competition signal, they can also synchronously negotiate the timing of responding to the host synchronization signal. For example, 50 milliseconds after obtaining the last signal mark of the host competition signal, respond to the host competition signal to enter the competition host mode, thereby sending the first identification number in the system.

[0077] In this step, the slave inverter that sends the host competition signal and other slave inverters in the system respond to the host competition signal, thereby sending the first identification code to the carrier bus in the system respectively. In addition, while sending the first identification code, the slave inverter also reads back the bus identification code from the bus status detection port on the carrier bus.

[0078] In some embodiments, a slave inverter that sends a host competition signal in the system can read / acquire the host competition signal sent by itself through a bus status detection port, and then respond to the host competition signal according to a pre-negotiated timing.

[0079] In some embodiments, the slave inverter that sends the host competition signal in the system can also actively respond to the host competition signal after sending the host competition signal, so that there is no need to read / acquire the host competition signal through the bus status detection port. In order to ensure the consistency of the timing of the slave inverter and other slave inverters in the system responding to the host competition signal, combined with the delay of signal transmission and chip processing, all inverters or all slave inverters in the system can pre-negotiate the timing of the slave inverter that sends the host competition signal to respond to the host competition signal, which is a millisecond from the last signal mark of the host competition signal, and the timing of other slave inverters that obtain the host competition signal to respond to the host competition signal is b milliseconds from the last signal mark of the host competition signal, and a is greater than b. Among them, the specific difference between a and b can be determined in combination with the transmission performance of the signal in the system bus and the performance of the slave inverter chip processing the signal, and is not specifically limited here.

[0080] Step S300, when the first identification number matches the bus identification number, the master inverter in the inverter parallel system sends a carrier signal to the carrier bus, so that other slave inverters in the inverter parallel system can obtain the carrier signal for carrier synchronization.

[0081] In this step, after any slave inverter in the system sends the first identification number in the system and reads back the bus identification number in the system, it compares each bit of the first identification number with each bit of the bus identification number one by one. Therefore, when a slave inverter finds that its own first identification number corresponds to the bus identification number one by one, it confirms that its own first identification number matches the bus identification number, and then confirms that it has successfully competed for the host, and immediately and automatically acts as the master inverter in the system to send a carrier signal to the carrier bus in the system. In addition to this, other slave inverters, when the comparison finds that their own first identification number does not match the bus identification number, automatically exit the competition host mode and enter the operation mode of obtaining the carrier signal to obtain the carrier signal transmitted on the carrier bus in the system based on ECAP for carrier synchronization.

[0082] It should be noted that the bus identification number in the system is the same as only one of the first identification numbers sent by all slave inverters. In some embodiments, when all slave inverters send their own SNs to the carrier bus, the carrier bus in the system can automatically and randomly select the SN of a slave inverter for output, or select the SN of a slave inverter with the best performance for output according to the performance differences of the slave inverters, and the output SN is the bus identification number.

[0083] According to the carrier synchronization method provided by an embodiment of the present invention, when the slave inverter of the system is unable to obtain the first duration of the carrier signal sent by the master inverter and reaches a first preset duration, it enters the host competition mode and sends a host competition signal to the carrier bus in the system. After that, all the slave inverters in the system start to send their own first identification numbers in the system in response to the host competition signal, and simultaneously monitor the bus identification number sent by the system bus. When a slave inverter in the system detects that its first identification number matches the bus identification number, it confirms that it has successfully competed for the host, and thus sends a carrier signal to the carrier bus in the system as the master inverter in the system, and the remaining slave inverters perform carrier synchronization based on the acquisition of the carrier signal.

[0084] In this way, even if the main inverter in the system has an abnormality that causes the system carrier synchronization function to crash, the slave inverter in the system can still establish a new master-slave structure of the system by competing with the host after detecting that ECAP has timed out and has not obtained the carrier signal, thereby restoring the system's carrier synchronization function, improving the stability of the system's carrier synchronization based on ECAP to obtain the carrier signal, and can effectively suppress the system circulation.

[0085] In addition, even if the system is not assigned to a master-slave machine at the beginning, and each inverter in the system is set as a slave inverter by default, then after the system is put into operation, each slave inverter can automatically establish the system's carrier synchronization function through competition to suppress the system's circulating current, thereby not relying on manual issuance of master-slave machine assignment instructions and human intervention to restore the carrier synchronization function. This not only improves the efficiency of the system in suppressing circulating current through carrier synchronization, but also improves the degree of intelligence.

[0086] In some embodiments, the above Figure 2 In the embodiment, the step S200 of “sending a first identification number to the carrier bus and monitoring a bus identification number in the carrier bus” includes but is not limited to the following steps:

[0087] Step S210: sending a first identification number to the carrier bus based on the bus logic circuit, and acquiring a level signal in the carrier bus as a bus identification number in the carrier bus.

[0088] In this step, any slave inverter in the system can send its own first identification number to the bus logic circuit through the input / output interface (I / O port) between its own DSP chip and the bus logic circuit for obtaining carrier signals and outputting pulse width modulation PWM signals. The first identification number is converted into a level signal by the bus logic circuit and transmitted to the carrier bus in the system. Afterwards, the slave inverter reads back the level signal transmitted on the carrier bus through the bus state detection port connected to the carrier bus through its own DSP chip, and uses the level signal as the bus identification number transmitted on the carrier bus during the competition for the host.

[0089] It should be noted that the carrier bus in the system can be designed to be based on a single-threaded method, and only transmits the level signal corresponding to the first identification number sent by the bus logic circuit of a certain slave inverter. For example, when the first identification number SN of a certain slave inverter sent to the bus logic circuit through the DSP chip is "0101001", the bus logic circuit converts the first identification number SN "0101001", thereby correspondingly outputting a level signal with a level logic sequence of "low high low high low low high" to the carrier bus. The carrier bus also transmits a level signal with a level logic sequence of "low high low high low low high" based on the selection of outputting the first identification number SN of the slave inverter. This level signal is the bus identification number in the carrier bus in the system.

[0090] In some embodiments, when the bus logic circuits of all inverters in the system send a high level to the carrier bus, the level signal in the carrier bus is high, and when the bus logic circuit of any inverter among all inverters sends a low level to the carrier bus, the level signal in the carrier bus is low. By pre-designing the carrier signal transmitted by the bus logic circuit of any inverter in the system, a high level is a recessive level and a low level is a dominant level. In this way, when the level signals output by the control bus logic circuits of all inverter members on the system bus are simultaneously high, the level signal output by the carrier bus is high, and if the level signal output by one of the control bus logic circuits of all inverters is pulled low, the level signal output by the carrier bus will be low. Under this design, Figure 2 After sending the first identification number to the carrier bus and monitoring the bus identification number in the carrier bus in step S200, the carrier synchronization method provided by the embodiment of the present invention further includes the following steps:

[0091] Step S400: When the level logic corresponding to the first identification number is the same as the level logic of the level signal in the carrier bus, it is confirmed that the first identification number matches the bus identification number.

[0092] In this step, when any slave inverter in the system compares its own first identification number with the bus identification number (the level signal transmitted in the carrier bus) transmitted by the carrier bus in the system that is read back, it can compare the level logic corresponding to its own first identification number with the level logic of the level signal, thereby confirming that its own first identification number matches the bus identification number when the two level logics are consistent.

[0093] In the embodiment of the present invention, the carrier signal transmitted on the system carrier bus is designed to be high as a recessive level and low as a dominant level, so that when the level signals sent to the carrier bus by all the slave inverter member controls in the system are simultaneously high, the level signal output by the carrier bus is high, and as long as one of the slave inverters sends a low level signal to the carrier bus, the level signal output by the bus is low. Based on this, each inverter in the system is designed to be a slave when powered on, waiting to receive the carrier signal, and the level signal output on the carrier bus is high by default. When there is no host in the system, each slave inverter will detect the carrier signal ECAP to obtain the falling edge mark timeout, and then switch to the competition host mode to send a competition host signal to the carrier bus, and then start sending its own first identification number SN to the carrier bus after a short delay, and at the same time start the detection judgment mode (in the process of sending the identification number of uniform length, the logic of the level corresponding to the current bit of SN is consistent with the level logic corresponding to the bus identification signal read from the carrier bus after sending). If it is judged to be a logic conflict, the slave inverter will actively exit the competition host mode and switch to obtaining the carrier signal based on ECAP for carrier synchronization. If the slave inverter judges that the level logic of the bus identification signal completely matches the level logic of its own first identification code, it confirms that it has successfully competed for the system host, and then switches to the master inverter to send a carrier signal to the bus for other slave inverters that have not successfully competed for the host to obtain the carrier signal for carrier synchronization. In this way, the system no longer needs to rely on manual operation to allocate the inverter between master and slave machines, but can automatically perform master-slave allocation. Even if the system's carrier synchronization function fails due to an abnormality in the master inverter, the slave inverter can still re-establish the slave structure through host competition and continue to run the carrier synchronization function after detecting a timeout in acquiring the carrier signal, without having to wait for instructions for passive recovery or human intervention.

[0094] According to the carrier synchronization method of the embodiment of the present invention, in one embodiment of the present invention, as Figure 3 As shown in the figure, the process of the inverter automatically competing for the host in the system includes:

[0095] Step S301: When the system is powered on, all inverters are preset as slave inverters.

[0096] Step S302: any slave inverter in the system detects whether the falling edge flag obtained by ECAP has timed out.

[0097] If yes, execute step S303.

[0098] Step S303, the slave inverter enters the host competition mode and sends a competition protocol, wherein the competition protocol sent by the slave inverter in the carrier bus of the system is a host competition signal.

[0099] If the falling edge flag obtained from the inverter ECAP in the system has not timed out, step S304 is executed.

[0100] Step S304, determining whether a contention protocol is received, wherein the contention protocol is a host contention signal sent by other slave inverters in the system when the ECAP obtains the falling edge mark timeout.

[0101] If yes, then execute step S305. If no, then return to execute step S302.

[0102] Step S305, the slave inverter sending the contention protocol or the inverter receiving the contention protocol in the system sends the current bit of its own unique identification number after a fixed delay. The fixed delay time of the slave inverter can be pre-negotiated 50 milliseconds.

[0103] Step S306: the system determines whether the unique identification number currently sent by the inverter is the same as the bus identification number.

[0104] If yes, execute step S307.

[0105] Step S307, determining whether the unique identification number has been sent.

[0106] If yes, execute step S308.

[0107] Step S308: Switch to the master inverter, thereby sending a carrier signal in the system for other slave inverters to obtain the carrier signal based on the ECAP for carrier synchronization.

[0108] In addition, if the slave inverter determines that its own unique identification number is different from the bus identification number when executing step S306, it returns to execute step S302.

[0109] In addition, if the slave inverter determines that its unique identification number has not been sent yet when executing step S307, it executes step S309, and the number of bits of its unique identification number to be sent by the slave inverter is increased by 1. After that, the slave inverter returns to execute step S305.

[0110] In one embodiment, the carrier synchronization method provided by the embodiment of the present invention further includes but is not limited to the following steps:

[0111] Step S500: when the first identification number does not match the bus identification number, obtaining a carrier signal as a slave inverter in the inverter parallel system.

[0112] In this step, the slave inverter in the system finds that its own first identification number does not match the bus identification number during comparison, and confirms that other slave inverters in the system have successfully competed for the host, thereby automatically exiting the host competition mode and continuing to serve as a slave inverter in the system to enter the operation mode of acquiring the carrier signal, and begins to acquire the carrier signal transmitted on the carrier bus in the system based on ECAP for carrier synchronization.

[0113] Step S600: When a carrier signal is acquired and a second duration that is not synchronized with the acquired carrier signal reaches a second preset duration, the pulse width modulation period is gradually adjusted according to a preset period offset value.

[0114] In this step, if any slave inverter in the system can capture the carrier signal sent by the master inverter in the system based on ECAP but cannot synchronize with the captured carrier signal, the slave inverter records the second duration during which it cannot synchronize with the captured carrier signal, and then when the second duration reaches a second preset duration (such as 100, 500, 1000 milliseconds or more), the slave inverter confirms the need to increase the final range limit of the pulse width modulation period for leading or lagging adjustment, thereby gradually adjusting the pulse width modulation period based on the preset period offset value to perform carrier synchronization adjustment.

[0115] It is understandable that the inability of the slave inverter to synchronize with the carrier signal means that the oscillation wave synchronization signal generated locally by the slave inverter cannot be synchronized with the captured carrier signal in frequency and / or phase due to some reasons. For example, the carrier synchronization fails due to a large gap in the system clock. The slave inverter adjusts the pulse width modulation period for carrier synchronization adjustment as follows: use a preset period offset value as the pulse width modulation period value swing offset for lead adjustment or lag adjustment, wherein the maximum offset of the slave inverter swing does not exceed the extreme value of the preset offset range. For example, in the case where the preset offset range is (-5 to 5), the slave inverter can use any one of (-5 to 5) as the preset period offset value, and then let the pulse width modulation period value swing the offset of the preset period offset value for lead adjustment or lag adjustment.

[0116] In some embodiments, the second duration includes: adjusting the time spent on carrier synchronization adjustment of the pulse width modulation period according to an initial period offset value; the initial period offset value is less than the maximum value of the preset offset range and greater than the minimum value of the preset offset range.

[0117] It should be noted that the slave inverter adjusts the pulse width modulation period according to the initial period offset value to perform carrier synchronization adjustment as follows: the slave inverter pulse width modulation period swings the initial period offset value ±1 in a fixed direction to perform advance or lag adjustment. When the slave inverter detects that it cannot complete synchronization with the captured carrier signal, it starts to record the second duration of the inability to complete carrier synchronization. After that, the slave inverter first makes the pulse width modulation period swing ±1 in a fixed direction according to the initial period offset value ±1 to perform advance or lag adjustment, and the time consumed by this process is also counted in the second duration. If the slave inverter still cannot complete synchronization with the captured carrier signal after making the pulse width modulation period swing ±1 in a fixed direction for advance or lag adjustment, then when the second duration is greater than or equal to the second preset time, the slave inverter further adjusts the pulse width modulation period step by step according to the preset period offset value to perform carrier synchronization adjustment. In addition, if the inverter makes the pulse width modulation period swing in a fixed direction of ±1 to perform lead or lag adjustment, and is able to complete synchronization with the carrier signal, the second duration will not continue to increase, thereby not triggering further operations of gradually adjusting the pulse width modulation period according to the preset period offset value to perform carrier synchronization adjustment.

[0118] It can be understood that, because the slave inverter makes the pulse width modulation period swing in a fixed direction by ±1 to perform lead or lag adjustment, and cannot complete synchronization with the captured carrier signal, the pulse width modulation period is further adjusted step by step according to the preset period offset value to perform carrier synchronization adjustment. Therefore, the maximum value of the preset period offset value needs to be greater than the initial period offset value, so that the slave inverter can perform carrier synchronization adjustment by making the pulse width modulation period swing by a larger offset. That is, the absolute value of the extreme value of the preset offset range to which the preset period offset value belongs is greater than the initial period offset value. For example, when the initial period offset value is (-1 or 1), the preset offset range can be (-5 to 5).

[0119] In some embodiments, in the above step S500, "gradually adjusting the pulse width modulation period according to the preset period offset value to perform carrier synchronization adjustment" may include at least one of the following methods:

[0120] Mode 1: increasing the pulse width modulation period according to a preset step length until the offset of the pulse modulation period increase is equal to a preset period offset value.

[0121] It should be noted that the preset step size can be 0 to 2 or -2 to 0. The carrier lag adjustment performed by the slave inverter can be that the slave inverter reduces the frequency of the local synchronization signal used for carrier synchronization by increasing the pulse width modulation period, thereby lagging the local synchronization signal at the current moment relative to the local synchronization signal at the previous moment, in the expectation that the current local synchronization signal can be synchronized with the carrier signal.

[0122] When the slave inverter detects that the second duration is greater than or equal to the preset second duration, the pulse width modulation cycle swing offset is 0-2, thereby increasing the pulse width modulation cycle to reduce the frequency of the output local synchronization signal to perform carrier lag adjustment. After that, the slave inverter makes the pulse width modulation cycle swing offset 0-2 each time until the offset amount increased by the pulse modulation cycle is equal to the preset cycle offset value (such as the maximum value 5 in the preset offset range of -5 to 5). After that, if the slave inverter still cannot synchronize the local synchronization signal with the captured carrier signal, the slave inverter stops increasing the pulse width modulation cycle.

[0123] Mode 2: reducing the pulse width modulation period according to a preset step length until the offset of the pulse modulation period reduction is equal to a preset period offset value.

[0124] It should be noted that the carrier advance adjustment performed from the inverter can increase the frequency of the local synchronization signal used for carrier synchronization by reducing the pulse width modulation period of the inverter, thereby making the local synchronization signal at the current moment relatively advanced compared to the local synchronization signal at the previous moment, in the expectation that the current local oscillation signal can be synchronized with the carrier signal.

[0125] When the slave inverter detects that the second duration is greater than or equal to the preset second duration, the pulse width modulation cycle swing offset is -2 to 0, thereby reducing the pulse width modulation cycle to increase the frequency of the output local synchronization signal to perform carrier advance adjustment. After that, the slave inverter makes the pulse width modulation cycle swing offset from -2 to 0 each time until the offset amount of the pulse modulation cycle reduction is equal to the preset cycle offset value (such as the minimum value -5 in the preset offset range -5 to 5). After that, if the slave inverter still cannot synchronize the local synchronization signal with the captured carrier signal, the slave inverter stops reducing the pulse width modulation cycle.

[0126] In some embodiments, when the slave inverter makes the pulse modulation cycle swing offset to 0-2 or -2-0 to increase the final range limit for carrier overtime or hysteresis adjustment, when the offset of the pulse modulation cycle swing is equal to the preset cycle offset value, but the second duration of synchronization between the slave inverter and the captured carrier signal is still greater than or equal to the second preset duration, the slave inverter confirms that it is no longer possible to complete carrier synchronization by making the pulse modulation cycle swing offset to 0-2 or -2-0, thereby outputting a preset error signal. Among them, the slave inverter can re-count the second duration after each time the pulse modulation cycle swing is offset to 0-2 or -2-0 for carrier synchronization adjustment (overtime or hysteresis adjustment), and when the second duration is greater than or equal to the second preset duration, continue to make the pulse modulation cycle swing offset to 0-2 or -2-0 for carrier synchronization adjustment, and repeat until the offset of the pulse modulation cycle swing is equal to the preset cycle offset value. In addition, the error signal can be pre-negotiated and unified by all inverters or all slave inverters in the system, and is used to identify a pulse modulation signal that the slave inverter itself cannot complete synchronization with the carrier signal sent by the master inverter.

[0127] According to the carrier synchronization method provided by the embodiment of the present invention, in the process of capturing the carrier signal for carrier synchronization after the slave inverter fails to compete with the host, if the carrier signal can always be captured based on ECAP within a period of time (a second preset time length), but synchronization with the captured carrier signal cannot be completed, the carrier synchronization adjustment is performed by making the pulse modulation period swing offset to 0 to 2 or -2 to 0, and the indication swing pulse modulation period is then deduced to the final range limit (the extreme value of the preset offset range, such as 5 or -5). If synchronization with the captured carrier signal still cannot be completed, the slave inverter reports an error. In this way, by adopting a variable pulse modulation period swing range, the failure of carrier synchronization caused by the large gap in the system clock can be effectively avoided, thereby further improving the stability of the system for carrier synchronization based on ECAP capture of carrier signals.

[0128] In some embodiments, Figure 4 As shown, Figure 4 The present invention provides a flowchart of a carrier synchronization method for determining synchronization conditions. In the carrier synchronization method, determining whether synchronization is completed with a captured carrier signal from an inverter includes but is not limited to the following steps S700 to S900:

[0129] Step S700, counting the count deviation value of the acquired carrier signal; wherein the count deviation value is: the deviation value between the count of the synchronization signal sent to the carrier bus and the count of the carrier signal.

[0130] When it is necessary to explain, the count deviation value may be an ECAP count deviation value. The ECAP count deviation value is the deviation value between the ECAP count when any slave inverter in the system captures the carrier signal based on the ECAP and the ECAP count of the local synchronization signal during the process of carrier synchronization based on the ECAP capture of the carrier signal. It should be understood that if there is an initial phase or frequency deviation between the local synchronization signal and the carrier signal captured based on the ECAP, a deviation in the ECAP count will occur.

[0131] In this step, during the process of carrier synchronization based on ECAP capturing the carrier signal for any slave inverter in the system, if there is a deviation between the count of the local synchronization signal and the count of the carrier signal, the slave inverter uniformly uses the same direction to perform carrier synchronization across carrier cycles, and obtains the count deviation value of the ECAP count between the local synchronization signal and the captured carrier signal during the process.

[0132] It should be understood that when the local oscillation signal from the inverter is at a large degree of deviation from the initial phase of the carrier signal captured based on ECAP, it will be difficult for the system to complete carrier synchronization within one carrier cycle. In some embodiments, the inverter can use the same direction to perform carrier synchronization across carrier cycles in a stage where the ECAP count deviation value is large (for example, the ECAP count deviation value is greater than or equal to A), and then obtain the ECAP count deviation value between the local synchronization signal and the captured carrier signal in this process. Among them, the ECAP count deviation value "A" can be pre-negotiated by all inverters in the system, and is used to identify the ECAP count deviation value corresponding to the situation where the system is difficult to complete carrier synchronization within one carrier cycle.

[0133] Step S800, when the integral of the count deviation value is greater than or equal to a preset integral threshold, confirm that it is not synchronized with the captured carrier signal, and record the duration for which the integral of the count deviation value is greater than or equal to the preset integral threshold as the second duration.

[0134] In this step, after obtaining the count deviation value, the slave inverter counts the integral of the count deviation value (such as the integral or continuous summation of the ECAP count deviation value over time), and then compares the integral of the count deviation value counted with the preset integral threshold (f). If the comparison finds that the integral of the count deviation value is greater than or equal to the preset integral threshold, the slave inverter confirms that it has not yet completed synchronization with the captured carrier signal, and starts recording the duration of the integral of the count deviation value being greater than or equal to the preset integral threshold during the carrier synchronization process of the current captured carrier signal, and then uses the duration as the second duration of not synchronizing with the captured carrier signal. Therefore, when the second duration is greater than or equal to the second preset duration, the slave inverter gradually adjusts the pulse width modulation period according to the preset period offset value to perform carrier synchronization adjustment.

[0135] It should be noted that the preset integral threshold (f) can be an integral value pre-negotiated by all inverters in the system for identifying that the local synchronization signal of the slave inverter in the system has not been synchronized with the captured carrier signal within a period of time. It should be understood that based on different design requirements of actual applications, in different feasible embodiments, the specific size of "f" can certainly be different, and the carrier synchronization signal method proposed in the present invention does not limit the specific size of the preset integral threshold "f".

[0136] When the integral of the count deviation value is less than the preset integral threshold, and the duration for which the integral of the count deviation value is less than the preset integral threshold reaches a third preset time length, synchronization with the acquired carrier signal is confirmed.

[0137] Step S900: When the integral of the count deviation value is less than the preset integral threshold, and the duration during which the integral of the count deviation value is less than the preset integral threshold reaches a third preset time length, it is confirmed that the signal is synchronized with the acquired carrier signal.

[0138] In this step, when the slave inverter compares the integral of the counted counting deviation value with the preset integral threshold (f), if the integral of the counting deviation value is less than the preset integral threshold (f), and the slave inverter finds that the duration for which the integral of the counting deviation value is always less than the preset integral threshold (f) is greater than or equal to a third preset time length (such as 100, 500, 1000 milliseconds or more), the slave inverter confirms that the local synchronization signal and the captured carrier signal are synchronized within the current period of time (the third preset time length).

[0139] According to the carrier synchronization method provided by the embodiment of the present invention, the slave inverters in the system use the same direction for cross-cycle synchronization in the stage where the ECAP count deviation value is large, and the integral of the ECAP count deviation value during the carrier synchronization process is counted, and based on whether the integral in a longer time period is always less than a certain value (preset integral threshold f), it is judged whether the local synchronization signal is successfully synchronized with the carrier signal during the current carrier synchronization process. In this way, by judging whether the carrier synchronization is successful or not in the integral dimension, a faster synchronization speed and a more accurate synchronization state judgment can be achieved.

[0140] In some embodiments, Figure 5 As shown, Figure 5 This is a flow chart of static compensation involved in a carrier synchronization method provided by an embodiment of the present invention. In the carrier synchronization method, the carrier synchronization static compensation operation performed from the inverter includes but is not limited to the following steps S001 to S003:

[0141] Step S001: when the first identification number does not match the bus identification number, obtaining a carrier signal as a slave inverter in the inverter parallel system.

[0142] In this step, after the slave inverter in the system finds that its first identification number does not match the bus identification number, thereby exiting the competition host mode, it continues to act as a slave inverter in the system to obtain the carrier signal transmitted on the carrier bus in the system based on ECAP for carrier synchronization.

[0143] Step S002, when the carrier signal is obtained, and in synchronization with the obtained carrier signal, a circulating current monitoring result of the inverter current of the inverter parallel system is obtained; wherein the circulating current monitoring result is obtained based on multi-sampling monitoring of the inverter current.

[0144] It should be noted that the multi-sampling monitoring of the inverter current can use oversampling technology for any slave inverter in the system. Based on the switching frequency of the pulse width modulation, multiple sampling methods are performed on the system inverter current to determine whether the inverter current generates a circulating current phenomenon, and when it is confirmed that the system inverter current has a circulating current, the circulating current direction is determined by combining at least two adjacent samplings. In some embodiments, the slave inverter can sample the system inverter current at more than 4 evenly distributed points within a pulse width modulation cycle.

[0145] In this step, any slave inverter in the system, based on the carrier signal sent by the master inverter in the system captured by ECAP and being able to synchronize with the captured carrier signal, obtains the circulating current monitoring result obtained by sampling the inverter current of the inverter parallel system multiple times through the multi-sampling technology. Among them, the circulating current monitoring result is at least used to characterize whether the inverter current of the system has a circulating current phenomenon and the direction of the circulating current generated by the inverter current.

[0146] Step S003, performing a static compensation operation of carrier synchronization according to the circulation monitoring result; wherein the static compensation operation includes: according to the circulation direction of the inverter current indicated by the circulation monitoring result, gradually swinging the static compensation error within a preset phase compensation range to compensate for the phase offset in the circulation direction.

[0147] In this step, when the slave inverter obtains the circulating current monitoring result, and the circulating current monitoring result indicates that the inverter current of the system has generated a circulating current phenomenon, and the circulating current monitoring result indicates the circulating current direction, the slave inverter performs a static compensation operation for the carrier synchronization between the local synchronization signal and the acquired carrier signal based on the circulating current monitoring result. That is, on the basis of the synchronization of the local synchronization signal and the carrier signal, the slave inverter further swings the static compensation error gradually within the preset phase compensation range according to the circulating current direction of the circulating current generated by the inverter current indicated by the circulating current monitoring result, so as to compensate the phase offset of the system inverter current in the circulating current direction indicated by the circulating current monitoring result according to the swinging static compensation error.

[0148] According to the carrier synchronization method provided by the embodiment of the present invention, the slave inverter in the system monitors the circulating current in the system inverter current by using oversampling technology, and then swings the original static compensation error within a certain range when the circulating current is monitored. In this way, by adopting the method of analyzing and statistically analyzing the circulating current, the fixed compensation can be controlled to operate in the best state, thereby avoiding the problem of phase offset of the synchronization signal and the carrier signal having a fixed error even if the synchronization is successful due to the attenuation of the synchronization signal voltage and the lag in the processing of the slave inverter DSP chip, thereby improving the accuracy of the system carrier synchronization.

[0149] Second, as Figure 6 As shown, Figure 6 is a flowchart of another carrier synchronization method provided by an embodiment of the present invention. In the carrier synchronization method, the system architecture is the same as the above Figure 1 The system architecture shown is consistent, and the slave inverter in the system can capture the carrier signal sent by the master inverter in the system based on ECAP. At this time, any slave inverter in the system performs carrier synchronization including but not limited to the following steps S004 or S005:

[0150] Step S004, when a carrier signal is acquired and a second duration that is not synchronized with the acquired carrier signal reaches a second preset duration, the pulse width modulation period is gradually adjusted according to a preset period offset value; wherein the preset period offset value is any one in a preset offset range; the second duration includes: adjusting the pulse width modulation period according to an initial period offset value for the time spent on carrier synchronization adjustment; the initial period offset value is less than a maximum value of the preset offset range and greater than a minimum value of the preset offset range.

[0151] In this step, if any slave inverter in the system can capture the carrier signal sent by the master inverter in the system based on ECAP since the system is powered on, but the slave inverter cannot synchronize with the captured carrier signal, then the slave inverter records the second duration during which it cannot synchronize with the captured carrier signal, and then when the second duration reaches the second preset duration, performs the same operation as the slave inverter that failed to compete for the master in the above case, that is, confirms that it is necessary to increase the final range limit of the pulse width modulation period to perform carrier synchronization (lead or lag adjustment) at this time, and thereby gradually adjusts the pulse width modulation period based on the preset period offset value to perform carrier synchronization adjustment.

[0152] According to the carrier synchronization method provided by the embodiment of the present invention, in the system, when the slave inverter can normally capture the carrier signal of the master inverter for carrier synchronization at the beginning, if the slave inverter can always capture the carrier signal based on ECAP within a period of time (the second preset time length), but cannot complete synchronization with the captured carrier signal, the slave inverter adjusts the carrier synchronization by making the pulse modulation period swing offset 0 to 2 or -2 to 0, and so on to indicate the swing pulse modulation period to the final range limit. In this way, the slave inverter can effectively avoid the carrier synchronization failure caused by the large system clock gap by adopting a variable pulse modulation period swing range, thereby further improving the stability of the system carrier synchronization function.

[0153] Step S005, when the carrier signal is obtained and synchronized with the obtained carrier signal, a carrier-synchronized static compensation operation is performed according to the circulating current monitoring result of the inverter current of the inverter parallel system; wherein the circulating current monitoring result is obtained based on multi-sampling monitoring of the inverter current; the static compensation operation includes: according to the circulating direction of the inverter current indicated by the circulating current monitoring result, the static compensation error is gradually swung within a preset phase compensation range to compensate for the phase offset in the circulating direction.

[0154] In this step, any slave inverter in the system can capture the carrier signal sent by the master inverter in the system when the system is powered on, and can synchronize with the carrier signal. In order to avoid the problem of phase offset that may have a fixed error due to the attenuation of the local synchronization signal voltage and the lag in the processing of its own DSP chip, the slave inverter further samples the inverter current of the inverter parallel system multiple times through multi-sampling technology to obtain the circulating current monitoring result. Then, when the inverter current of the system characterized by the circulating current monitoring result generates a circulating current phenomenon and the circulating current monitoring result indicates the circulating current direction, the slave inverter performs a static compensation operation based on the circulating current monitoring result. That is, on the basis of the synchronization of the local synchronization signal and the carrier signal, the slave inverter gradually swings the static compensation error within the preset phase compensation range according to the circulating current direction of the inverter current indicated by the circulating current monitoring result, so as to compensate the phase offset in the circulating current direction indicated by the circulating current monitoring result according to the swinging static compensation error.

[0155] According to the carrier synchronization method provided by the embodiment of the present invention, the slave inverter in the system monitors the circulating current in the system inverter current by using the oversampling technology, and then swings the original static compensation error within a certain range when the circulating current is detected. In this way, the accuracy of the system carrier synchronization can be further improved.

[0156] Thirdly, Figure 7 As shown, Figure 7 is a flowchart of another carrier synchronization method provided by an embodiment of the present invention. In the carrier synchronization method, the system architecture is similar to the above Figure 1 The system architecture shown is consistent, and the slave inverter in the system can capture the carrier signal sent by the master inverter in the system based on ECAP. However, the master inverter in the system uses a preset first duty cycle to send a carrier signal at a non-zero-crossing moment of the grid cycle, and uses a preset second duty cycle to send a carrier signal at a zero-crossing moment of the grid cycle. Among them, the preset second duty cycle is less than the preset first duty cycle. For example, the preset first duty cycle is 80%, and the preset second duty cycle is 20%. At this time, any slave inverter in the system performs carrier synchronization including but not limited to the following steps S006 to S007:

[0157] Step S006, acquiring a carrier signal based on simultaneously acquiring a rising edge flag and a falling edge flag.

[0158] In this step, the master inverter in the system uses a preset first duty cycle (80%) to send a carrier signal at a non-zero-crossing point in the grid cycle, and uses a preset second duty cycle (20%) to send a carrier signal at a zero-crossing point in the grid cycle. The slave inverters in the system uniformly obtain the rising edge flag and the falling edge flag based on ECAP to obtain the carrier signal sent by the master inverter to the system carrier bus.

[0159] In some embodiments, the system can pre-negotiate that from the start of power-on operation until the end of power-off operation, the master inverter uses an 80% duty cycle to send the carrier signal at non-zero-crossing points in the grid cycle, and uses a 20% duty cycle to send the carrier signal at the zero-crossing point of the grid cycle, and the slave inverter always obtains the carrier signal by simultaneously obtaining the rising edge mark and the falling edge mark based on the ECAP.

[0160] Step S007: when the carrier signal is acquired, the zero-crossing point of the power grid cycle is determined according to the duty cycle of the acquired carrier signal.

[0161] In this step, after any slave inverter in the system obtains the carrier signal sent by the master inverter based on the simultaneous acquisition of the rising edge mark and the falling edge mark, it determines the zero-crossing point of the power grid cycle adopted by the master inverter of the system by calculating the duty cycle of the carrier signal obtained in the current cycle. Furthermore, the system can determine whether the synchronization of the system inverter current power frequency is also completed while the carrier synchronization is currently being performed in the power grid cycle based on the zero-crossing point.

[0162] According to the carrier synchronization method provided by the embodiment of the present invention, considering that the system does not have a high-power relay designed between the AC coupling (AC Coupling) end and the load for unified load shutdown in many application scenarios, the system needs to perform current power frequency synchronization while completing the carrier synchronization function. At this time, in order to avoid the cost of introducing a power frequency synchronization bus separately in the system, the main inverter in the system uses a fixed larger duty cycle (preset first duty cycle) to send the carrier synchronization signal when it is not a zero-crossing point in the power grid cycle, and uses a smaller duty cycle (preset second duty cycle) to send the carrier synchronization at the zero-crossing moment. At this time, although the system only needs to use the falling edge for judgment when performing carrier synchronization itself, the slave inverter still captures the carrier signal based on the ECAP to capture the rising edge and the falling edge for carrier synchronization, so that the zero-crossing point of the main inverter can be judged by calculating the duty cycle of the carrier signal in the current cycle, and then on the basis of realizing carrier synchronization in the system, the same signal line (carrier bus) can be shared to realize the power frequency synchronization function at the same time, effectively saving system costs.

[0163] Fourthly, refer to Figure 8 , Figure 8It is a structural diagram of a carrier synchronization device 1000 provided in an embodiment of the present invention, wherein the carrier synchronization device 1000 includes: a memory 1010, a processor 1020, and a computer program stored in the memory 1010 and executable on the processor 1020, and when the processor 1020 executes the computer program, it implements the carrier synchronization method in the above embodiment.

[0164] The memory 1010 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs and non-transitory computer executable programs, such as the carrier synchronization method in the above embodiment of the present invention. The processor 1020 implements the carrier synchronization method in the above embodiment of the present invention by running the non-transitory software programs and instructions stored in the memory 1010.

[0165] The memory 1010 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data required to execute the carrier synchronization method in the above embodiment, etc. In addition, the memory 1010 may include a high-speed random access memory 1010, and may also include a non-transitory memory 1010, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. It should be noted that the memory 1010 may optionally include a memory 1010 remotely arranged relative to the processor 1020, and these remote memories 1010 may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0166] The non-transient software program and instructions required to implement the carrier synchronization method in the above embodiment are stored in the memory. When executed by one or more processors, the carrier synchronization method in the above embodiment is executed, for example, steps S100 to S900, step S210, steps S001 to S007, and the like in the above embodiment are executed. Figure 3 Method steps S301 to S309, as well as method 1 and method 2.

[0167] In a fifth aspect, the present invention provides an inverter, the inverter comprising the carrier synchronization device as in the fourth aspect. The inverter can use the carrier synchronization device to execute the carrier synchronization method in the above embodiment.

[0168] In a sixth aspect, the present invention further provides a computer-readable storage medium, which stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the carrier synchronization method in the above-mentioned first aspect embodiment, for example, to execute the carrier synchronization method in the above embodiment.

[0169] It will be appreciated by those skilled in the art that all or some of the steps and systems in the method disclosed above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium or a non-transitory medium and a communication medium or a temporary medium. As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk DVD or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0170] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in the technical field without departing from the purpose of the present invention.

Claims

1. A carrier synchronization method, characterized in that: Applied to any slave inverter in the inverter parallel system, the slave inverter obtains the carrier signal sent by the master inverter in the inverter parallel system to perform carrier synchronization; any inverter in the inverter parallel system is respectively connected to the carrier bus in the inverter parallel system; The method comprises: When a first duration in which a carrier signal is not obtained reaches a first preset duration, sending a host competition signal to the carrier bus; In response to the host contention signal, sending a first identification number to the carrier bus and monitoring a bus identification number in the carrier bus; When the first identification number matches the bus identification number, the master inverter in the inverter parallel system sends a carrier signal to the carrier bus, so that other slave inverters in the inverter parallel system can obtain the carrier signal for carrier synchronization.

2. The method according to claim 1, characterized in that Any inverter in the inverter parallel system includes a bus logic circuit, and any inverter is connected to the carrier bus through the respective bus logic circuit; The sending of a first identification number to the carrier bus and monitoring a bus identification number in the carrier bus comprises: A first identification number is sent to the carrier bus based on the bus logic circuit, and a level signal in the carrier bus is obtained as a bus identification number in the carrier bus.

3. The method according to claim 2, characterized in that When the bus logic circuits of all the inverters in the inverter parallel system send a high level to the carrier bus, the level signal in the carrier bus is high; when the bus logic circuit of any inverter among all the inverters sends a low level to the carrier bus, the level signal in the carrier bus is low; The method further comprises: When the level logic corresponding to the first identification number is the same as the level logic of the level signal in the carrier bus, it is confirmed that the first identification number matches the bus identification number.

4. The method according to claim 1, characterized in that: The method further comprises: When the first identification number does not match the bus identification number, obtaining a carrier signal as a slave inverter in the inverter parallel system; When the carrier signal is acquired and the second duration that is not synchronized with the acquired carrier signal reaches a second preset duration, the pulse width modulation period is gradually adjusted according to the preset period offset value; Among them, the preset cycle offset value is any one in the preset offset range, and the second duration includes: the time consumed for carrier synchronization adjustment by adjusting the pulse width modulation period according to the initial cycle offset value; the initial cycle offset value is less than the maximum value of the preset offset range and greater than the minimum value of the preset offset range.

5. The method according to claim 4, characterized in that The step of gradually adjusting the pulse width modulation period according to the preset period offset value to perform carrier synchronization adjustment includes at least one of the following: Increasing the pulse width modulation period according to a preset step length until the offset of the pulse modulation period increase is equal to a preset period offset value; The pulse width modulation period is reduced according to a preset step length until the offset amount of the pulse modulation period reduction is equal to the preset period offset value.

6. The method according to claim 4, characterized in that The method further comprises: Counting the count deviation value of the acquired carrier signal; wherein the count deviation value is: the deviation value between the count of the synchronization signal sent to the carrier bus and the count of the carrier signal; When the integral of the count deviation value is greater than or equal to a preset integral threshold, confirming that it is not synchronized with the acquired carrier signal, and recording a duration during which the integral of the count deviation value is greater than or equal to the preset integral threshold as the second duration; When the integral of the count deviation value is less than the preset integral threshold, and the duration for which the integral of the count deviation value is less than the preset integral threshold reaches a third preset time length, synchronization with the acquired carrier signal is confirmed.

7. The method according to claim 1, characterized in that The method further comprises: When the first identification number does not match the bus identification number, obtaining a carrier signal as a slave inverter in the inverter parallel system; When the carrier signal is acquired, and in synchronization with the acquired carrier signal, a circulating current monitoring result of the inverter current of the inverter parallel system is acquired; wherein the circulating current monitoring result is obtained based on multi-sampling monitoring of the inverter current; A static compensation operation of carrier synchronization is performed according to the circulation monitoring result; wherein the static compensation operation includes: according to the circulation direction of the inverter current indicated by the circulation monitoring result, the static compensation error is gradually swung within a preset phase compensation range to compensate for the phase deviation in the circulation direction.

8. A carrier synchronization method, characterized in that: Applied to any slave inverter in the inverter parallel system, the slave inverter obtains the carrier signal sent by the master inverter in the inverter parallel system to perform carrier synchronization; any inverter in the inverter parallel system is respectively connected to the carrier bus in the inverter parallel system; The method comprises any of the following: When a carrier signal is acquired and a second duration that is not synchronized with the acquired carrier signal reaches a second preset duration, the pulse width modulation period is gradually adjusted according to a preset period offset value; wherein the preset period offset value is any one of a preset offset range; the second duration includes: the time spent on adjusting the pulse width modulation period for carrier synchronization adjustment according to an initial period offset value; the initial period offset value is less than a maximum value of the preset offset range and greater than a minimum value of the preset offset range; When a carrier signal is acquired and synchronized with the acquired carrier signal, a carrier-synchronized static compensation operation is performed according to the circulating current monitoring result of the inverter current of the inverter parallel system; wherein the circulating current monitoring result is obtained based on multi-sampling monitoring of the inverter current; the static compensation operation includes: according to the circulating current direction of the inverter current indicated by the circulating current monitoring result, the static compensation error is gradually swung within a preset phase compensation range to compensate for the phase offset in the circulating current direction.

9. A carrier synchronization method, characterized in that: Applied to any slave inverter in the inverter parallel system, the slave inverter obtains the carrier signal sent by the master inverter in the inverter parallel system to perform carrier synchronization; any inverter in the inverter parallel system is respectively connected to the carrier bus in the inverter parallel system; The method comprises: The carrier signal is obtained based on the simultaneous acquisition of the rising edge mark and the falling edge mark; wherein the main inverter in the inverter parallel system uses a preset first duty cycle to send the carrier signal at a non-zero-crossing point of the power grid cycle, and uses a preset second duty cycle to send the carrier signal at a zero-crossing point of the power grid cycle, and the preset second duty cycle is smaller than the preset first duty cycle; When the carrier signal is obtained, the zero-crossing point of the power grid cycle is determined according to the duty cycle of the obtained carrier signal.

10. A carrier synchronization device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the carrier synchronization method according to any one of claims 1 to 9.

11. An inverter, characterized in that: Includes the carrier synchronization device as described in claim 10.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the carrier synchronization method according to any one of claims 1 to 9.

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