Radio frequency front end module

Abstract

The application relates to the radio frequency technical field, in particular to a radio frequency front end module which comprises a substrate and a power amplifier, the power amplifier comprises a power amplification chip and an output circuit arranged on the substrate respectively; the power amplification chip is integrated with a power amplification circuit and a detection circuit; a first setting area of the power amplification circuit and a second setting area of the detection circuit are respectively located on two sides of the power amplification chip along a first direction; by simultaneously integrating the power amplification circuit and the detection circuit in the power amplification chip, the overall size of the radio frequency front end module is reduced; by arranging the power amplification circuit and the detection circuit on the two sides of the power amplification chip along the first direction respectively, the power amplification circuit and the detection circuit are far away from each other on the power amplification chip, signal interference between the two is avoided, the performance of the power amplification circuit and the accuracy of the detection circuit are not affected, and the stability of the power amplifier during work is improved.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a radio frequency front-end module. Background Technology

[0002] Currently, radio frequency (RF) front-end modules are widely used in wireless communication, the Internet of Things (IoT), smart homes, and other fields. Among them, the power amplifier, as the core unit of the RF front-end module, has a significant impact on the signal output performance of the RF front-end module.

[0003] The power amplifier first amplifies a pair of differential RF signals using a power amplification circuit. Then, the output signals from the power amplification circuit are combined to output a single amplified RF signal. Finally, a detection circuit detects the power of the output amplified RF signal to determine the accuracy of the power amplification process. In related technologies, improper configuration of the power amplification and detection circuits can lead to signal interference, affecting both the performance of the power amplification circuit and the accuracy of the detection circuit, thus hindering the stability of the RF front-end module. Summary of the Invention

[0004] In view of the above problems, this application provides a radio frequency front-end module to solve the above-mentioned technical problems that are not conducive to improving the stability of the radio frequency front-end module.

[0005] This application provides a radio frequency front-end module, including:

[0006] substrate;

[0007] A power amplifier, the power amplifier including a power amplifier chip and an output circuit respectively disposed on the substrate;

[0008] The power amplifier chip integrates a power amplifier circuit and a detector circuit.

[0009] The power amplifier circuit amplifies the radio frequency signal and outputs it to the output circuit; the output circuit processes the power amplified signal output by the power amplifier circuit to output a power amplified radio frequency signal, and couples the power amplified radio frequency signal to the detector circuit.

[0010] The power amplifier circuit is located in a first setting area of ​​the power amplifier chip, and the detector circuit is located in a second setting area of ​​the power amplifier chip. The first setting area and the second setting area are spaced apart. The first setting area is close to a first side of the power amplifier chip along a first direction, and the second setting area is close to a second side of the power amplifier chip along the first direction.

[0011] The radio frequency front-end module provided in this application includes a substrate; a power amplifier, the power amplifier including a power amplifier chip and an output circuit respectively disposed on the substrate; the power amplifier chip integrates a power amplification circuit and a detection circuit; the output circuit is used to process the power amplification signal output by the power amplification circuit to output a power amplified radio frequency signal, and couple the power amplified radio frequency signal to the detection circuit; the power amplification circuit is located in a first setting area of ​​the power amplification chip near a first side of the power amplification chip along a first direction, and the detection circuit is located in a second setting area of ​​the power amplification chip near a second side of the power amplification chip along the first direction; by integrating the power amplification circuit and the detection circuit into the power amplification chip, the overall size of the radio frequency front-end module is reduced; by distributing the power amplification circuit and the detection circuit on opposite sides of the power amplification chip along the first direction, the power amplification circuit and the detection circuit are kept far apart on the power amplification chip, avoiding signal interference between them, avoiding affecting the performance of the power amplification circuit and the accuracy of the detection circuit, and improving the stability of the power amplifier during operation.

[0012] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0013] Figure 1 A schematic diagram of the structure of a radio frequency front-end module provided in an embodiment of this application is shown.

[0014] Figure 2 It shows Figure 1 The diagram shows a circuit diagram of the power amplifier and detector circuit in the RF front-end module.

[0015] Figure 3 It shows Figure 1 The diagram shows a power amplifier circuit and an output circuit in the RF front-end module.

[0016] Figure 4 It shows Figure 1 Another circuit diagram of the power amplifier circuit and output circuit in the RF front-end module shown.

[0017] Figure 5 It shows Figure 1 The diagram shows a circuit diagram of the output circuit in the RF front-end module.

[0018] Figure 6 It shows Figure 1 Another circuit diagram of the output circuit in the RF front-end module shown.

[0019] Figure 7 It shows Figure 1The diagram shows another structural schematic of the RF front-end module.

[0020] Figure 8 It shows Figure 1 The diagram shows another structural schematic of the RF front-end module.

[0021] Figure 9 It shows Figure 1 Another circuit diagram of the output circuit in the RF front-end module shown.

[0022] Figure 10 It shows Figure 1 The diagram shows the interaction between the power amplifier chip and the substrate in the RF front-end module.

[0023] Figure 11 It shows Figure 1 The diagram shows another structural schematic of the RF front-end module.

[0024] Figure 12 It shows Figure 1 Another circuit diagram of the output circuit in the RF front-end module shown.

[0025] Figure 13 It shows Figure 1 The diagram shows another structural schematic of the RF front-end module.

[0026] Figure 14 It shows Figure 1 The circuit diagram shown is of the power amplifier circuit and the switching chip in the RF front-end module.

[0027] Figure 15 It shows Figure 1 Another circuit diagram of the power amplifier circuit and output circuit in the RF front-end module shown.

[0028] Figure 16 It shows Figure 1 The diagram shows another structural schematic of the RF front-end module.

[0029] Figure 17 It shows Figure 1 Another circuit diagram of the power amplifier circuit, the first balun, and the second balun in the RF front-end module shown. Detailed Implementation

[0030] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0031] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0033] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0034] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0035] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0036] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0037] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0038] It should be noted that the transistor mentioned in this application specification can be a bipolar junction transistor (BJT), or simply a bipolar transistor, BJT transistor, or triode. The transistor mentioned in this application specification can also be a metal oxide semiconductor field-effect transistor (MOSFET), or simply a MOS transistor, MOSFET, or FET transistor.

[0039] Specifically, a BJT transistor can be a PNP type BJT transistor or an NPN type BJT transistor. A PNP type BJT transistor can correspond to a P-type MOS transistor. The first terminal of a BJT transistor can be the emitter or collector, the second terminal of a BJT transistor can be the collector or emitter, and the control terminal of a BJT transistor can be the base.

[0040] Specifically, the MOS transistor can be a P-type MOS transistor or an N-type MOS transistor. The first terminal of the MOS transistor can be the source or the drain, the second terminal of the MOS transistor can be the drain or the source, and the control terminal of the MOS transistor can be the gate.

[0041] One embodiment of this application provides a radio frequency front-end module 100. Please refer to [link to relevant documentation]. Figures 1 to 2 As shown, the radio frequency front-end module 100 includes a substrate 10 and a power amplifier 20. The power amplifier 20 includes a power amplifier chip 21 and an output circuit 22, which are respectively disposed on the substrate 10.

[0042] The power amplifier chip 21 integrates a power amplifier circuit 21a and a detector circuit 21b.

[0043] The power amplifier circuit 21a amplifies the radio frequency signal and outputs it to the output circuit 22. The output circuit 22 processes the power amplified signal output by the power amplifier circuit 21a to output a power amplified radio frequency signal, and couples the power amplified radio frequency signal to the detector circuit 21b. The detector circuit 21b is used to detect the power of the power amplified radio frequency signal.

[0044] The power amplifier circuit can be composed of at least one type of amplifier circuit, such as a single-ended amplifier circuit, a differential amplifier circuit, a Dougherty power amplifier circuit, or a balanced power amplifier circuit. This embodiment does not specifically limit the type and structure of the power amplifier circuit.

[0045] The power amplifier circuit 21a is located in the first setting area A21a of the power amplifier chip 21, and the detector circuit 21b is located in the second setting area A21b of the power amplifier chip 21. The first setting area A21a and the second setting area A21b are arranged at intervals. The first setting area A21a is close to the first side of the power amplifier chip 21 along the first direction, and the second setting area A21b is close to the second side of the power amplifier chip 21 along the first direction.

[0046] In this context, the first side and the second side of the power amplifier chip are opposite sides of the power amplifier chip along the first direction. For example, the first side of the power amplifier chip is the upper side of the power amplifier chip, and the second side of the power amplifier chip is the lower side of the power amplifier chip; or, the first side of the power amplifier chip is the left side of the power amplifier chip, and the second side of the power amplifier chip is the right side of the power amplifier chip.

[0047] In this embodiment, by integrating the power amplifier circuit and the detector circuit into the power amplifier chip, the overall size of the RF front-end module is reduced. By placing the power amplifier circuit and the detector circuit on opposite sides of the power amplifier chip along the first direction, the power amplifier circuit and the detector circuit are kept far apart on the power amplifier chip, avoiding signal interference between the two and preventing any impact on the performance of the power amplifier circuit and the accuracy of the detector circuit, which is beneficial to improving the stability of the power amplifier during operation.

[0048] As one implementation method, please refer to Figure 3 As shown, the power amplifier circuit 21a includes at least two power amplifier units 210 connected in sequence. Each power amplifier unit 210 includes a power amplifier transistor Q0. The control terminal of the power amplifier transistor Q0 is connected to the input terminal 210a of the power amplifier unit 210. The first terminal of the power amplifier transistor Q0 is connected to the output terminal 210b of the power amplifier unit 210, and the second terminal of the power amplifier transistor Q0 is grounded.

[0049] In this embodiment, each power amplifier transistor and the detector circuit are located on both sides of the power amplifier chip along the first direction, achieving spatial isolation between the power amplifier transistor and the detector circuit. This avoids signal interference between the power amplifier transistor and the detector circuit, prevents it from affecting the performance of the power amplifier circuit and the accuracy of the detector circuit, and helps to improve the stability of the power amplifier during operation.

[0050] In some implementations, please refer to Figure 4As shown, the power amplifier circuit 21a includes a first power amplifier branch 211 and a second power amplifier branch 212. The first power amplifier branch 211 and the second power amplifier branch 212 respectively perform power amplification processing on a pair of differential radio frequency signals. The first power amplifier branch 211 and the second power amplifier branch 212 respectively include at least two stages of the power amplifier unit 210 connected in sequence.

[0051] As one possible implementation method, please refer to [link / reference]. Figure 1 As shown, the output circuit 22 is located on the first side of the power amplifier chip 21 along the first direction.

[0052] In this embodiment, the output circuit is positioned close to the power amplifier circuit, which facilitates the connection between the output circuit and the power amplifier circuit, avoids excessive losses caused by excessively long traces between the output circuit and the power amplifier circuit, and ensures that the traces do not overlap with other traces and that there is little interference between the traces and other traces, which helps to improve the stability of the power amplifier during operation.

[0053] As one implementation method, please refer to Figure 5 As shown, the output circuit 22 includes a signal combining unit 220 and a signal coupling unit 227. The signal combining unit 220 is connected to the power amplifier circuit 21a, and the signal coupling unit 227 is coupled to the signal combining unit 220.

[0054] Among them, the signal combining unit 220 is used to combine the power amplified signal output by the power amplification circuit 21a to output a power amplified radio frequency signal, and the signal coupling unit 227 is used to couple the power amplified radio frequency signal on the signal combining unit 220 to the detector circuit 21b.

[0055] In this embodiment, the power amplifier first uses a power amplification circuit to amplify a pair of differential radio frequency signals, and then uses a signal combining unit to combine the two signals output by the power amplification circuit to output a single power amplified radio frequency signal. Through the coupling relationship between the signal coupling unit and the signal combining unit, the power amplified radio frequency signal is coupled to the detection circuit. The signal combining unit and the detection circuit do not need to be directly connected, which avoids mutual interference between the signal combining unit and the detection circuit and helps to improve the stability of the power amplifier during operation.

[0056] In some implementations, please refer to Figure 6 As shown, the signal coupling unit 227 includes a first coupling line 2271 and a second coupling line 2272 that are coupled to each other. The first coupling line 2271 is connected to the signal combining unit 220, the first end of the second coupling line 2272 is connected to the detector circuit 21b, and the second end of the second coupling line 2272 is grounded.

[0057] The first end of the second coupling line 2272 is connected to the coupling output terminal 2270 of the signal coupling unit 227, and the coupling output terminal 2270 is connected to the detection circuit 21b.

[0058] In this embodiment, the power amplified radio frequency signal in the signal combining unit is coupled to the second coupling line through the coupling between the first coupling line and the second coupling line. The power amplified radio frequency signal is output to the detection circuit through the connection between the second coupling line and the detection circuit. The signal combining unit and the detection circuit do not need to be directly connected, which avoids mutual interference between the signal combining unit and the detection circuit and helps to improve the stability of the power amplifier during operation.

[0059] In some implementations, please refer to [the relevant documentation]. Figure 6 As shown, the signal coupling unit 227 also includes a first resistor R6, which is connected in series between the second end of the second coupling line 2272 and the ground end.

[0060] In this embodiment, the second end of the second coupling line 2272 is grounded through the first resistor R6 to limit the current of the power amplified RF signal coupled to the detector circuit, and can also participate in impedance matching.

[0061] In some implementations, please refer to [the relevant documentation]. Figure 6 As shown, the signal coupling unit 227 also includes a second resistor R5. One end of the second resistor R5 is connected to the first end of the second coupling line 2272, and the second end of the second resistor R5 is connected to the detector circuit 21b.

[0062] In this embodiment, the first end of the second coupling line 2272 is connected to the detector circuit 21b through the second resistor R5 to limit the current of the power amplified RF signal coupled to the detector circuit, and can also participate in impedance matching.

[0063] As one implementation method, please refer to Figure 7 As shown, the RF front-end module 100 also includes a first input bonding wire 2273 and a second input bonding wire 2100.

[0064] The first input bonding wire 2273 is used to transmit the power amplified radio frequency signal to the detector circuit 21b. One end of the first input bonding wire 2273 is connected to the first metal pad on the substrate 10 to connect to the output circuit 22 through the first metal pad, and the other end is connected to the signal input terminal of the detector circuit 21b. Specifically, one end of the first input bonding wire 2273 is connected to the coupling output terminal 2270 of the signal coupling unit 227 through the first metal pad, that is, the first input bonding wire 2273 is connected to the first end of the second coupling wire 2272.

[0065] The second input bonding wire 2100 is used to transmit the radio frequency signal to the power amplifier circuit 21a. The first end of the second input bonding wire 2100 is connected to the switch chip on the substrate 10, and the second end is connected to the signal input terminal of the power amplifier chip 21.

[0066] Among them, the virtual straight line corresponding to the first input binding line 2273 in the extension direction intersects with the virtual straight line corresponding to the second input binding line 2100 in the extension direction.

[0067] In this embodiment, the virtual straight line where the first input binding line of the detector circuit is located is not parallel to the virtual straight line where the second input binding line of the power amplifier chip is located, so as to avoid interference between the power amplified radio frequency signal on the first input binding line and the radio frequency signal on the second input binding line.

[0068] In some implementations, the virtual straight line corresponding to the first input binding line 2273 in the extension direction is perpendicular to the virtual straight line corresponding to the second input binding line 2100 in the extension direction.

[0069] In some implementations, please refer to [the relevant documentation]. Figure 7 As shown, the RF front-end module 100 also includes a first output bonding wire 2274, which is used to output the detection result of the detector circuit 21b. One end of the first output bonding wire 2274 is connected to the second metal pad on the substrate 10, and the other end is connected to the signal output terminal of the detector circuit 21b. The virtual straight line corresponding to the first output bonding wire 2274 in the extension direction intersects with the virtual straight line corresponding to the second input bonding wire 2100 in the extension direction. Specifically, one end of the first output bonding wire 2274 is connected to the processing module through the second metal pad on the substrate 10. For example, the processing module receives the detection result sent by the detector circuit 21b and can calculate the power amplification accuracy of the power amplifier circuit 21a based on the detection result.

[0070] In this embodiment, the virtual straight line where the first output binding line of the detector circuit is located is not parallel to the virtual straight line where the second input binding line of the power amplifier chip is located, so as to avoid interference between the detection result signal on the first output binding line and the radio frequency signal on the second input binding line.

[0071] In some implementations, please refer to [the relevant documentation]. Figure 7 As shown, the RF front-end module 100 also includes at least one signal output binding wire 2200 disposed between the power amplifier chip 21 and the output circuit 22. The signal output binding wire 2200 is disposed close to the first side of the power amplifier chip 21 along the first direction L1, and the first input binding wire 2273 and the first output binding wire 2274 are disposed close to the second side of the power amplifier chip 21 along the first direction L1, respectively.

[0072] In this embodiment, the first input tie wire and the first output tie wire of the detector circuit, as well as the signal output tie wire of the power amplifier chip, are kept far apart from each other to avoid mutual interference between the input signal of the detector circuit and the output signal of the power amplifier chip, and between the output signal of the detector circuit and the output signal of the power amplifier chip.

[0073] For example, the first input bonding wire 2273 and the first output bonding wire 2274 may be located on the same side of the power amplifier chip 21 along the second direction L2.

[0074] For example, the second input binding wire 2100 may be located on the second side of the power amplifier chip 21 along the first direction L1.

[0075] As one implementation method, please refer to Figure 8 As shown, the power amplifier chip 21 also integrates at least one bias circuit, which provides a bias signal to the power amplifier transistor Q0 of the power amplifier circuit 21a. The bias circuit is located in the third setting region A21c of the power amplifier chip 21, which is located between the first setting region A21a and the second setting region A21b.

[0076] In some embodiments, the distance between the center of the third setting area A21c and the center of the first setting area A21a is a first distance y1, and the distance between the center of the third setting area A21c and the center of the second setting area A21b is a second distance y2, wherein the second distance y2 is less than the first distance y1.

[0077] In this embodiment, the bias circuit is positioned close to the detector circuit and far from the power amplifier circuit to avoid signal interference between the bias circuit and the power amplifier circuit, thus avoiding affecting the performance of the power amplifier circuit and improving the stability of the power amplifier during operation.

[0078] As one implementation method, please refer to Figure 9 As shown, the signal combining unit 220 includes a first balun 221, a second balun 222, a signal output terminal 223, and a combining module 224. The first balun 221 and the second balun 222 are respectively connected to the power amplifier circuit 21a. The power amplifier circuit 21a can amplify a pair of differential radio frequency signals, output the amplified signal formed by one of the differential radio frequency signals to the first balun 221, and output the amplified signal formed by the other differential radio frequency signal to the second balun 222.

[0079] The combiner module 224 is used to combine the first power amplified signal output from the first balun 221 and the second power amplified signal output from the second balun 222 to output a power amplified radio frequency signal.

[0080] The combining module 224 includes a first inductor unit 2241, a second inductor unit 2242, and a combining output unit 2243. The first inductor unit 2241 is connected to the first balun 221, the second inductor unit 2242 is connected to the second balun 222, the first end of the combining output unit 2243 is connected to the output end of the first inductor unit 2241 and the output end of the second inductor unit 2242, and the second end of the combining output unit 2243 is connected to the signal output end 223 of the output circuit 22. The first power amplified signal output from the first balun 221 is processed by the first inductor unit 2241 and output to the first terminal of the combiner output unit 2243. The second power amplified signal output from the second balun 222 is processed by the second inductor unit 2242 and output to the first terminal of the combiner output unit 2243. The output terminals of the first inductor unit 2241 and the second inductor unit 2242 form a combiner node 2240. The first power amplified signal from the first inductor unit 2241 and the second power amplified signal from the second inductor unit 2242 are combined at the combiner node 2240 to form a power amplified radio frequency signal. This power amplified radio frequency signal is output from the second terminal of the combiner output unit 2243 after passing through the combiner output unit 2243.

[0081] The signal coupling unit 227 may include a first coupling line 2271 and a second coupling line 2272 that are coupled to each other.

[0082] The first end of the first coupling line 2271 is connected to the output terminals of the first inductor unit 2241 and the second inductor unit 2242, respectively, and the second end of the first coupling line 2271 is connected to the first end of the combining output unit 2243. The first coupling line 2271 is connected between the combining node 2240 and the combining output unit 2243. The power amplified RF signal formed by combining at the combining node 2240 is input to the combining output unit 2243 after passing through the first coupling line 2271.

[0083] The first end of the second coupling line 2272 is connected to the detector circuit, and the second end of the second coupling line 2272 is grounded. The second coupling line 2272 couples the power amplified radio frequency signal on the first coupling line 2271, and the power amplified radio frequency signal coupled to the second coupling line 2272 is output from its first end.

[0084] In this embodiment, by setting a combiner module in the output circuit, the power amplifier first uses the first balun and the second balun to convert the power amplified signals formed by a pair of differential radio frequency signals respectively, and then uses the combiner module to combine the two power amplified signals output by the first balun and the second balun to output a power amplified radio frequency signal, which helps to improve the stability of the power amplifier during operation.

[0085] In some implementations, please refer to Figure 10 , Figure 11 and Figure 7 As shown, the power amplifier chip 21 is located in the mounting area A1 on the substrate 10. The mounting area A1 of the power amplifier chip 21 has a first central axis S1. Figure 11 In the top-down view shown, the first central axis S1 is also the central axis of the power amplifier chip 21.

[0086] The first balun 221 and the second balun 222 are located on opposite sides of the first central axis S1. In this embodiment, since the first balun and the second balun are respectively located on opposite sides of the central axis of the power amplifier chip, overlap between the first trace of the power amplifier circuit and the first balun, and between the power amplifier circuit and the second balun, can be avoided. At the same time, the interference between the first trace and the second trace is reduced, which is beneficial to improving the stability of the power amplifier during operation, and thus improving the stability of the RF front-end module.

[0087] For example, the first balun 221 and the second balun 222 can be implemented by metal traces wound on the substrate 10, the first balun 221 and the second balun 222 can also be implemented by surface mount baluns, or the first balun 221 and the second balun 222 can be implemented by balun chips. This embodiment does not limit the implementation.

[0088] In this embodiment, the first inductor unit 2241 and the second inductor unit 2242 are located on both sides of the first central axis S1 of the setting area A1 of the power amplifier chip 21. By placing the first inductor unit and the second inductor unit in the combining module on both sides of the central axis of the power amplifier chip, the overlap of the third trace between the first balun and the first inductor unit, and the fourth trace between the second balun and the second inductor unit, is avoided. At the same time, the interference between the third trace and the fourth trace is reduced, which is beneficial to improving the stability of the power amplifier during operation.

[0089] For example, the first inductor unit 2241 may include at least one inductor, for example, it may include one inductor or at least two inductors connected in sequence; the second inductor unit 2242 may include at least one inductor, for example, it may include one inductor or at least two inductors connected in sequence; the combined output unit 2243 may include at least one inductor, for example, it may include one inductor or at least two inductors connected in sequence.

[0090] In some implementations, please refer to [the relevant documentation]. Figure 11 and Figure 7As shown, the first balun 221 and the second balun 222 are arranged symmetrically with respect to the first central axis S1 of the power amplifier chip 21. Specifically, when the first balun 221 and the second balun 222 are respectively surface mount baluns, balun chips, or metal traces, the mounting area of ​​the first balun 221 on the substrate 10 and the mounting area of ​​the second balun 222 on the substrate 10 are arranged symmetrically with respect to the first central axis S1.

[0091] In this embodiment, the first balun and the second balun are arranged symmetrically with respect to the first central axis, which can improve the symmetry of the first trace between the power amplifier circuit and the first balun and the second trace between the power amplifier circuit and the second balun, further reduce the interference between the first trace and the second trace, and improve the stability of the RF front-end module.

[0092] In some embodiments, when the first balun 221 and the second balun 222 are respectively made of metal traces, the metal trace pattern of the first balun 221 and the metal trace pattern of the second balun 222 are arranged symmetrically with respect to the first central axis S1.

[0093] In this embodiment, the metal trace patterns of the first balun and the second balun are arranged symmetrically with respect to the first central axis. The positions of the same type of input or output terminals of the first balun and the second balun are symmetrical with respect to the first central axis. This can improve the symmetry of the first trace between the power amplifier circuit and the first balun, as well as the second trace between the power amplifier circuit and the second balun, further reducing the interference between the first trace and the second trace, and improving the stability of the RF front-end module.

[0094] In some implementations, please refer to [the relevant documentation]. Figure 11 and Figure 7 As shown, the first inductor unit 2241 and the second inductor unit 2242 are arranged symmetrically with respect to the first central axis S1 of the power amplifier chip 21.

[0095] In this embodiment, the first inductor unit and the second inductor unit in the combining module are symmetrically arranged on both sides of the central axis of the power amplifier chip. This can improve the symmetry of the third trace between the first balun and the first inductor unit, as well as the fourth trace between the second balun and the second inductor unit, further reducing the interference between the third trace and the fourth trace, which is beneficial to improving the stability of the power amplifier during operation.

[0096] In some implementations, please refer to [the relevant documentation]. Figure 7 and Figure 12As shown, the first inductor unit 2241 includes a first inductor L11 and a second inductor L12. The first inductor L11 is connected to the output terminal of the first balun 221, and the first inductor L11 and the second inductor L12 are connected together. The extension direction of the first inductor L11 is not parallel to the extension direction of the second inductor L12. The second inductor unit 2242 includes a third inductor L21 and a fourth inductor L22. The third inductor L21 is connected to the output terminal of the second balun 222, and the third inductor L21 and the fourth inductor L22 are connected together. The extension direction of the third inductor L21 is not parallel to the extension direction of the fourth inductor L22.

[0097] In this embodiment, the first inductor unit and the second inductor unit are each formed by two non-parallel inductors, which helps to reduce the installation area of ​​the inductors to avoid overlapping of the traces, and at the same time can reduce the coupling between the two inductors.

[0098] In some implementations, the extension direction of the first inductor L11 intersects the extension direction of the second inductor L12, and the extension direction of the third inductor L21 intersects the extension direction of the fourth inductor L22.

[0099] In some embodiments, the intersection angle between the extension directions of the first inductor L11 and the extension directions of the second inductor L12 is at least one of [45°, 60°], [60°, 90°], [90°, 120°], and [120°, 150°]. The intersection angle between the extension directions of the third inductor L21 and the extension directions of the fourth inductor L22 is at least one of [45°, 60°], [60°, 90°], [90°, 120°], and [120°, 150°].

[0100] In some implementations, the first inductor L11 and the second inductor L12 are perpendicular, and the third inductor L21 and the fourth inductor L22 are perpendicular.

[0101] In this embodiment, the first inductor unit and the second inductor unit are each formed by two mutually perpendicular inductors, which helps to reduce the installation area of ​​the inductors to avoid overlapping of the wiring, and at the same time can further reduce the coupling between the two inductors.

[0102] In some embodiments, the first inductor L11 extends in a direction parallel to the first central axis S1, the second inductor L12 extends in a direction perpendicular to the first central axis S1, the third inductor L21 extends in a direction parallel to the first central axis S1, and the fourth inductor L22 extends in a direction perpendicular to the first central axis S1.

[0103] In some embodiments, the first inductor L11, the second inductor L12, the third inductor L21, and the fourth inductor L22 are respectively wound on the substrate 10. Specifically, the substrate may include multiple metal layers, and the inductors may be wound in at least one metal layer. By forming inductors through wiring on the metal layers of the substrate, the inductance of each inductor can be flexibly controlled, and a higher Q value can be achieved, thereby further reducing insertion loss.

[0104] In some embodiments, the first inductor L11, the second inductor L12, the third inductor L21, and the fourth inductor L22 are surface-mount inductors disposed on the surface of the substrate 10. Specifically, by using surface-mount inductors, the fabrication process of each inductor is simplified, and circuit debugging is easier.

[0105] In some implementations, please refer to Figure 11 As shown, the setting area A3 of the combining module 224, the setting area A2 of the first balun 221 and the second balun 222, and the setting area A1 of the power amplifier chip 21 are arranged sequentially along the first direction L1.

[0106] In this embodiment, by arranging the areas for the combining module, the two baluns, and the power amplifier chip sequentially, overlap between the fifth trace of the combining module and the two baluns and the sixth trace of the two baluns and the power amplifier chip is avoided. At the same time, the interference between the fifth and sixth traces is reduced, which helps to improve the stability of the power amplifier during operation.

[0107] As one implementation method, please refer to Figure 7 and Figure 12 As shown, the output circuit 22 also includes an isolation resistor unit 225. The first end of the isolation resistor unit 225 is connected to the output terminal of the first balun 221, and the second end of the isolation resistor unit 225 is connected to the output terminal of the second balun 222. The isolation resistor unit 225 is located on the first central axis S1. For example, the isolation resistor unit 225 may include an isolation resistor R4.

[0108] By setting the isolation resistor unit 225, the output terminals of the first balun 221 and the second balun 222 are isolated, which can improve the balance between the first balun 221 and the second balun 222, thereby improving the stability of the power amplifier during operation.

[0109] By placing the isolation resistor unit 225 on the first central axis S1, the symmetry of the wiring between the first balun 221 and the isolation resistor unit 225, as well as the wiring between the second balun 222 and the isolation resistor unit 225, can be improved, thereby further enhancing the stability of the power amplifier during operation.

[0110] In some implementations, please refer to [the relevant documentation]. Figure 7As shown, the isolation resistor unit 225 is located on the first central axis S1.

[0111] As one implementation method, please refer to Figure 7 and Figure 12 As shown, the output circuit 22 also includes a combining matching capacitor 226. The first end of the combining matching capacitor 226 is connected to the output end of the first inductor unit 2241, the output end of the second inductor unit 2242, and the first end of the combining output unit 2243. The second end of the combining matching capacitor 226 is grounded. The combining matching capacitor 226 is located on the first central axis S1.

[0112] Among them, the combining matching capacitor 226 can participate in impedance matching. Specifically, the combining matching capacitor 226 can be used to increase the output impedance of the first inductor unit 2241 and the output impedance of the second inductor unit 2242.

[0113] By placing the matching capacitor 226 on the first central axis S1, the symmetry of the wiring between the first inductor unit 2241 and the matching capacitor 226, as well as the wiring between the second inductor unit 2242 and the matching capacitor 226, can be improved, thereby further enhancing the stability of the power amplifier during operation.

[0114] In some implementations, please refer to Figure 7 As shown, the first end of the combining matching capacitor 226 is connected to the second inductor L12 and the fourth inductor L22 respectively, and the combining matching capacitor 226 is disposed in the gap region between the second inductor L12 and the fourth inductor L22.

[0115] Since the second inductor L12 and the fourth inductor L22 are symmetrically arranged with respect to the first central axis S1, and the second inductor L12 and the fourth inductor L22 are perpendicular to the first central axis S1 respectively, the combination matching capacitor 226 is located in the gap area between the two, which can shorten the distance between the first inductor unit 2241 and the combination matching capacitor 226 and the second inductor unit 2242 and the combination matching capacitor 226, and can also improve the integration density.

[0116] In some implementations, please refer to Figure 7 and Figure 13 As shown, the first inductor unit 2241, the matching capacitor 226, the second inductor unit 2242, the second balun 222 away from the power amplifier chip 21 and the first balun 221 away from the power amplifier chip 21 are arranged in sequence to form a first rectangular area A4, and the isolation resistor unit 225 is located in the first rectangular area A4.

[0117] By placing the isolation resistor unit 225 within the first rectangular area A4, the integration density can be improved.

[0118] In one implementation, the combining output unit 2243 may include at least two combining inductors connected in sequence, the extending direction of the combining inductors being perpendicular to the first central axis S1, and the combining output unit 2243 outputs the power amplified RF signal after filtering. For example, in... Figure 7 and Figure 12 As shown, the combining output unit 2243 may include a first combining inductor L31 and a second combining inductor L32. The first end of the first combining inductor L31 is connected to the output end of the first inductor unit 2241 and the output end of the second inductor unit 2242, respectively. The second end of the first combining inductor L31 is connected to the first end of the second combining inductor L32, and the second end of the second combining inductor L32 is connected to the signal output terminal 223.

[0119] In this embodiment, at least two sequentially connected combining inductors are respectively set perpendicular to the first central axis, which can increase the inductance of the signal processing unit, making it suitable for application scenarios that require a large inductance. Furthermore, arranging at least two combining inductors sequentially along the connection direction can reduce the trace area occupied by the combining output unit, which is beneficial to increasing the trace area and further avoiding trace overlap, thereby improving stability.

[0120] In some embodiments, the combining inductor is a surface-mount inductor disposed on the surface of the substrate 10. Specifically, using at least two surface-mount inductors connected in series simplifies the fabrication process of each inductor and facilitates circuit debugging. Furthermore, since the inductance value of the combining inductor is relatively large, forming a planar inductor using the metal layer of the substrate would require a large area, while using SMD components can effectively save area.

[0121] In some implementations, in Figure 7 As shown, the signal coupling unit 227 is located on the side of the combining matching capacitor 226 away from the first balun 221 and the second balun 222.

[0122] In this embodiment, the signal coupling unit is kept far away from the two baluns to avoid signal interference.

[0123] As one implementation method, in Figure 12 As shown, the output circuit 22 may further include a first combining harmonic suppression unit 2281 and a second combining harmonic suppression unit 2282. One end of the first combining harmonic suppression unit 2281 is connected to the output terminal of the first balun 221, and the other end of the first combining harmonic suppression unit 2281 is grounded. One end of the second combining harmonic suppression unit 2282 is connected to the output terminal of the second balun 222, and the other end of the second combining harmonic suppression unit 2282 is grounded.

[0124] For example, in Figure 7 and Figure 12As shown, the first combining harmonic suppression unit 2281 includes a first combining inductor L13 and a first combining capacitor C12 connected in series. The first combining inductor L13 is connected to the output terminal of the first balun 221, and the first combining capacitor C12 is grounded. By configuring the inductance value of the first combining inductor L13 and the capacitance value of the first combining capacitor C12, the first combining harmonic suppression unit 2281 can be made to have a impedance close to zero for specific harmonics, thereby short-circuiting specific harmonics and suppressing them to filter the first power amplified signal output by the first balun 221.

[0125] The second harmonic suppression unit 2282 includes a second combining inductor L23 and a second combining capacitor C22 connected in series. The second combining inductor L23 is connected to the output terminal of the second balun 222, and the second combining capacitor C22 is grounded. By configuring the inductance value of the second combining inductor L23 and the capacitance value of the second combining capacitor C22, the second harmonic suppression unit 2282 can be made to have a impedance close to zero for specific harmonics, thereby short-circuiting specific harmonics and suppressing them to filter the first power amplified signal output from the second balun 222.

[0126] In one implementation, power amplifier 20 is used to amplify the power of radio frequency signals across multiple frequency bands. Please refer to... Figure 7 , Figure 13 and Figure 14 As shown, the RF front-end module 100 also includes a switch chip 30 disposed on the substrate 10. The switch chip 30 includes a plurality of switch units 31. Each switch unit 31 is used to select and input RF signals of at least one frequency band to the power amplifier chip 21. The power amplifier circuit 21a integrated in the power amplifier chip 21 performs power amplification processing on the RF signals of the frequency band.

[0127] In this embodiment, each switching unit 31 corresponds to at least one frequency band of radio frequency signal. When a radio frequency signal of a specific frequency band is output, the switching unit 31 corresponding to that specific frequency band is turned on, and the other switching units 31 are turned off. In this way, it is possible to be compatible with the output of radio frequency signals of different frequency bands.

[0128] In some implementations, please refer to [the relevant documentation]. Figure 7 and Figure 13 As shown, the first balun 221 and the second balun 222 are located on the first side of the power amplifier chip 21 along the first direction L1, and the switch chip 30 is located on the second side of the power amplifier chip 21 along the first direction L1.

[0129] In this embodiment, the first balun and the second balun used to process the output signal of the power amplifier chip are located on the first side of the first direction, and the traces of the output terminal of the power amplifier chip are also located on the first side of the first direction; the switch chip used to select the input signal of the power amplifier chip is located on the second side of the first direction, and the traces of the input terminal of the power amplifier chip are also located on the second side of the first direction. The traces of the input terminal and the traces of the output terminal of the power amplifier chip are far apart from each other, so they will not overlap or interfere with each other, which is beneficial to further improve the stability of the RF front-end module.

[0130] In some implementations, please refer to [the relevant documentation]. Figure 7 and Figure 13 As shown, the RF front-end module 100 of this embodiment also includes a control chip 40, which is disposed on the substrate and electrically connected to the power amplifier chip 21. Exemplarily, the control chip 40 can be used to output control signals. These control signals can be a first control signal used to control the switching units in the switching chip 30 to be turned on or off; or a second control signal used to turn on the output switch of the bias signal in the power amplifier chip 21. Exemplarily, the control chip 40 can be a CMOS (Complementary Metal-Oxide-Semiconductor) chip.

[0131] The control chip 40 is located on the second side of the power amplifier chip 21 along the first direction L1.

[0132] In this embodiment, the traces between the power amplifier chip and the control chip are far apart from the traces between the power amplifier chip and the first and second baluns, so they do not overlap or interfere with each other, which helps to further improve the stability of the RF front-end module.

[0133] In some implementations, please refer to [the relevant documentation]. Figure 7 and Figure 13 As shown, the first direction L1 is parallel to the first central axis S1 of the power amplifier chip 21; the control chip 40 and the switch chip 30 are arranged side by side along the second direction L2, which is perpendicular to the first direction L1.

[0134] In this embodiment, the first direction and the second direction correspond to the length / width direction and the width / length direction of the power amplifier chip, respectively, making it easier to arrange the wiring between the power amplifier chip and the first balun, the second balun, the control chip and the switch chip in a regular manner.

[0135] As one implementation method, please refer to Figure 15As shown, the power amplifier circuit 21a includes a first power amplifier branch 211 and a second power amplifier branch 212. The first power amplifier branch 211 includes a first output terminal 211a and a second output terminal 211b, and the second power amplifier branch 212 includes a third output terminal 212a and a fourth output terminal 212b. The first balun 221 includes a first primary side 2210 and a first secondary side 2211 coupled together. The two ends of the first primary side 2210 are respectively connected to the first output terminal 211a and the second output terminal 212b of the first power amplifier branch 211. Terminal 211b, one end of the first secondary side 2211 is connected to the signal output terminal 223 of the output circuit 22, and the other end of the first secondary side 2211 is grounded; the second balun 222 includes a coupled second primary side 2220 and a second secondary side 2222, the two ends of the second primary side 2220 are respectively connected to the third output terminal 212a and the fourth output terminal 212b of the corresponding second power amplifier branch 212, one end of the second secondary side 2222 is connected to the signal output terminal 223 of the output circuit 22, and the other end of the second secondary side 2222 is grounded.

[0136] In this embodiment, the first power amplification branch 211 and the second power amplification branch 212 respectively perform power amplification processing on a pair of differential radio frequency signals. The first power amplification branch 211 outputs the first pair of differential power amplified signals formed by one of the differential radio frequency signals to the first balun 221 through the first output terminal 211a and the second output terminal 211b, respectively. The second power amplification branch 212 outputs the second pair of differential power amplified signals formed by the other differential radio frequency signal to the second balun 222 through the third output terminal 212a and the fourth output terminal 212b, respectively. The first balun 221 and the second balun 222 adopt a differential-to-single-ended architecture. The first balun 221 converts the first pair of differential power amplified signals output by the first power amplification branch 211 into a first power amplified signal. The second balun 222 converts the second pair of differential power amplified signals output by the second power amplification branch 212 into a second power amplified signal. The first power amplified signal and the second power amplified signal are combined and output in the combiner module 224.

[0137] In some implementations, please refer to Figure 7 , Figure 12 and Figure 15 As shown, the output circuit 22 also includes a first capacitor C1 and a second capacitor C2 disposed on the substrate 10. The first capacitor C1 is connected to the first balun 221, and the second capacitor C2 is connected to the second balun 222. The first capacitor C1 is disposed in the magnetic core region of the first balun 221, and the first end of the first capacitor C1 is connected to the midpoint 221a of the first primary side 2210, and the second end of the first capacitor C1 is grounded. The second capacitor C2 is disposed in the magnetic core region of the second balun 222, and the first end of the second capacitor C2 is connected to the midpoint 222a of the second primary side 2220, and the second end of the second capacitor C2 is grounded.

[0138] The first primary edge 2210 may include a first coil segment L1a and a second coil segment L1b connected in series, and the midpoint 221a of the first primary edge 2210 is the connection point of the first coil segment L1a and the second coil segment L1b; the second primary edge 2220 may include a third coil segment L2a and a fourth coil segment L2b connected in series, and the midpoint 222a of the second primary edge 2220 is the connection point of the third coil segment L2a and the fourth coil segment L2b.

[0139] In this embodiment, the first capacitor is positioned between the midpoint of the first primary side and the ground terminal. The first pair of differential power amplified signals output by the first power amplification branch are differential-mode signals. The midpoint of the first primary side is equivalent to a short circuit for differential-mode signals and an open circuit for common-mode signals. The first capacitor, connected in parallel to ground at the midpoint of the first primary side, provides a path to ground the common-mode signals, thereby improving the common-mode signal rejection level. Similarly, the second capacitor is positioned between the midpoint of the second primary side and the ground terminal. The second pair of differential power amplified signals output by the second power amplification branch are differential-mode signals. The midpoint of the second primary side is equivalent to a short circuit for differential-mode signals and an open circuit for common-mode signals. The second capacitor, connected in parallel to ground at the midpoint of the second primary side, provides a path to ground the common-mode signals, thereby improving the common-mode signal rejection level. Therefore, the placement of the first and second capacitors is beneficial for improving the balance of the power amplifier.

[0140] In some implementations, please refer to Figure 16 As shown, the first secondary side 2211 surrounds the magnetic core region, and the first primary side 2210 surrounds the first secondary side 2211. The first primary side 2210 includes a first coil body 22101 and two first connecting portions 22102. The first coil body 22101 is a single-turn structure with a first opening, located on the side of the first primary side 2210 closer to the power amplifier chip 21. The two first connecting portions 22102 are respectively connected to the two ends of the first coil body 22101. The first secondary side 2211 includes a second coil body 22111 and two second connecting portions 22112. The second coil body 22111 is a single-turn structure with a second opening, located on the side of the first primary side 2210 away from the power amplifier chip 21. The two second connecting portions 22112 are respectively connected to the two ends of the second coil body 22111.

[0141] Correspondingly, the second secondary side 2222 is disposed outside the magnetic core region, and the second primary side 2220 is disposed outside the second secondary side 2222. The second primary side 2220 includes a third coil body 22201 and two third connecting parts 22202. The third coil body 22201 is a single-turn structure with a third opening. The third opening is located on the side of the second primary side 2220 closer to the power amplifier chip 21. The two third connecting parts 22202 are respectively connected to the two ends of the third coil body 22201. The second secondary side 2222 includes a fourth coil body 22221 and two fourth connecting parts 22222. The fourth coil body 22221 is a single-turn structure with a fourth opening. The fourth opening is close to the side of the second primary side 2220 away from the power amplifier chip 21. The two fourth connecting parts 22222 are respectively connected to the two ends of the fourth coil body 22221.

[0142] In this embodiment, the two first connection portions of the first primary side are respectively connected to the first output terminal and the second output terminal of the first power amplifier branch. The two first connection portions of the first primary side are positioned close to the power amplifier chip, which helps to shorten the trace distance between the first balun and the power amplifier chip. Similarly, the two third connection portions of the second primary side are respectively connected to the third output terminal and the fourth output terminal of the second power amplifier branch. The two third connection portions of the second primary side are positioned close to the power amplifier chip, which helps to shorten the trace distance between the second balun and the power amplifier chip. Simultaneously, the two second connection portions of the first secondary side are respectively used to connect to the signal output terminal and ground of the output circuit. The two second connection portions of the first secondary side are positioned far from the power amplifier chip, which helps to shorten the trace distance between the first balun and the signal output terminal. Likewise, the two fourth connection portions of the second secondary side are respectively used to connect to the signal output terminal and ground of the output circuit. The two fourth connection portions of the second secondary side are positioned far from the power amplifier chip, which helps to shorten the trace distance between the second balun and the signal output terminal.

[0143] In some embodiments, the first capacitor C1 and the second capacitor C2 are surface-mount capacitors disposed on the surface of the substrate 10. In this embodiment, by using surface-mount capacitors, the capacitor manufacturing process is simplified, and circuit debugging is easier.

[0144] In some implementations, please refer to Figure 15 As shown, the power amplifier circuit 21 further includes a first harmonic suppression unit 2294, a second harmonic suppression unit 2295, a third harmonic suppression unit 2296, and a fourth harmonic suppression unit 2297. The first harmonic suppression unit 2294 is connected in series between the first output terminal 211a and the ground terminal. The second harmonic suppression unit 2295 is connected in series between the second output terminal 211b and the ground terminal. The third harmonic suppression unit 2296 is connected in series between the third output terminal 212a and the ground terminal. The fourth harmonic suppression unit 2297 is connected in series between the fourth output terminal 212b and the ground terminal.

[0145] For example, the first harmonic suppression unit 2294 includes a first matching capacitor C41 and a first matching inductor L41 connected in series, the first matching capacitor C41 is grounded, and the first matching inductor L41 is connected to the first output terminal 211a; the second harmonic suppression unit 2295 includes a second matching capacitor C42 and a second matching inductor L42 connected in series, the second matching capacitor C42 is grounded, and the second matching inductor L42 is connected to the second output terminal 211b; the third harmonic suppression unit 2296 includes a third matching capacitor C43 and a third matching inductor L43 connected in series, the third matching capacitor C43 is grounded, and the third matching inductor L43 is connected to the third output terminal 212a; the fourth harmonic suppression unit 2297 includes a fourth matching capacitor C44 and a fourth matching inductor L44 connected in series, the fourth matching capacitor C44 is grounded, and the fourth matching inductor L44 is connected to the fourth output terminal 212b.

[0146] As one possible implementation method, please refer to [link / reference]. Figure 13 As shown, the setting area A1 of the power amplifier chip 21 is divided into a first chip area A11 and a second chip area A12 by a first central axis S1. The first balun 221 is symmetrically arranged with respect to the second central axis S11 of the first chip area A11, and the second balun 222 is symmetrically arranged with respect to the third central axis S12 of the second chip area A12. The first central axis S1, the second central axis S11, and the third central axis S12 are parallel to each other.

[0147] In this embodiment, when the first balun 221 and the second balun 222 are respectively surface mount baluns, balun chips, or metal traces, the area where the first balun 221 is disposed on the substrate 10 is symmetrically arranged with respect to the second central axis S11 of the first chip area A11, and the area where the second balun 222 is disposed on the substrate 10 is symmetrically arranged with respect to the third central axis S12 of the second chip area A12. This can further improve the symmetry of the first trace between the power amplifier circuit and the first balun and the second trace between the power amplifier circuit and the second balun, further reduce the interference between the first trace and the second trace, and improve the stability of the RF front-end module.

[0148] In some embodiments, when the first balun 221 and the second balun 222 respectively use metal traces, the metal trace pattern of the first balun 221 is symmetrically arranged with respect to the second central axis S11 of the first chip region A11, and the metal trace pattern of the second balun 222 is symmetrically arranged with respect to the third central axis S12 of the second chip region A12.

[0149] In this embodiment, the metal trace patterns of the first balun and the second balun are axially symmetrical patterns, which can further improve the symmetry of the first trace between the power amplifier circuit and the first balun and the second trace between the power amplifier circuit and the second balun, further reduce the interference between the first trace and the second trace, and improve the stability of the RF front-end module.

[0150] In some implementations, please refer to Figure 17 As shown, the first power amplifier branch 211 further includes a first power amplifier module 2111, a third balun 2112, and a second power amplifier module 2113 connected in sequence; the second power amplifier module 2113 is a differential power amplifier module, and its two output terminals are the first output terminal 211a and the second output terminal 211b of the first power amplifier branch 211, respectively. The second power amplifier branch 212 further includes a third power amplifier module 2121, a fourth balun 2122, and a fourth power amplifier module 2123 connected in sequence; the fourth power amplifier module 2123 is a differential power amplifier module, and its two output terminals are the third output terminal 212a and the fourth output terminal 212b of the second power amplifier branch 212, respectively.

[0151] In this embodiment, the last stage of the first power amplification branch and the second power amplification branch adopts a differential amplification structure to ensure high output power.

[0152] In some implementations, please refer to Figure 17 As shown, the third balun 2112 includes a third primary side 211c and a third secondary side 211d that are coupled to each other. One end of the third primary side 211c is connected to the output terminal of the first power amplifier module 2111, and the other end of the third primary side 211c is grounded. The two ends of the third secondary side 211d are respectively connected to the two input terminals of the second power amplifier module 2113.

[0153] Among them, the third balun 2112 adopts a single-ended to differential architecture, which can convert one radio frequency signal output from the output terminal of the first power amplifier module 2111 into a pair of differential signals. The pair of differential signals is amplified by the second power amplifier module 2113 to form the first pair of differential power amplified signals.

[0154] Accordingly, the fourth balun 2122 includes a fourth primary side 212c and a fourth secondary side 212d coupled to each other. One end of the fourth primary side 212c is connected to the output terminal of the third power amplifier module 2121, and the other end of the fourth primary side 212c is grounded. The two ends of the fourth secondary side 212d are respectively connected to the two input terminals of the fourth power amplifier module 2123.

[0155] Among them, the fourth balun 2122 adopts a single-ended to differential architecture, which can convert one radio frequency signal output from the output terminal of the third power amplifier module 2121 into a pair of differential signals. The pair of differential signals is amplified by the fourth power amplifier module 2123 to form a second pair of differential power amplified signals.

[0156] In some embodiments, the power amplifier circuit 21a further includes a third capacitor C3 and a fourth capacitor C4. The third capacitor C3 is connected to the third balun 2112, the first end of the third capacitor C3 is connected to the midpoint of the third secondary side 211d, and the second end of the third capacitor C3 is grounded. The fourth capacitor C4 is connected to the fourth balun 2122, the first end of the fourth capacitor C4 is connected to the midpoint of the fourth secondary side 212d, and the second end of the fourth capacitor C4 is grounded.

[0157] The third secondary side 211d may include a fifth coil segment and a sixth coil segment connected in series, and the midpoint of the third secondary side 211d is the connection point of the fifth coil segment and the sixth coil segment; the fourth secondary side 212d may include a seventh coil segment and an eighth coil segment connected in series, and the midpoint of the fourth secondary side 212d is the connection point of the seventh coil segment and the eighth coil segment.

[0158] In this embodiment, the third capacitor is positioned between the midpoint of the third secondary side and the ground terminal. The midpoint of the third secondary side acts as a short circuit for differential-mode signals and an open circuit for common-mode signals. The third capacitor, connected in parallel to ground at the midpoint of the third secondary side, provides a path for grounding the common-mode signal, thus improving the common-mode signal rejection level. Similarly, the fourth capacitor is positioned between the midpoint of the fourth secondary side and the ground terminal. The midpoint of the fourth secondary side acts as a short circuit for differential-mode signals and an open circuit for common-mode signals. The fourth capacitor, connected in parallel to ground at the midpoint of the fourth secondary side, provides a path for grounding the common-mode signal, further improving the common-mode signal rejection level. Therefore, the placement of the third and fourth capacitors helps improve the balance of the power amplifier.

[0159] In some embodiments, the third capacitor C3 and the fourth capacitor C4 are surface-mount capacitors disposed on the surface of the substrate 10. In this embodiment, by using surface-mount capacitors, the capacitor manufacturing process is simplified, and circuit debugging is easier.

[0160] In some embodiments, the first power amplifier module 2111 includes a first power amplifier unit 2101 and a second power amplifier unit 2102. The input terminal of the first power amplifier unit 2101 is connected to the input terminal of the power amplifier 20. The first power amplifier unit 2101 and the second power amplifier unit 2102 are single-ended power amplifier units, and the output terminal of the second power amplifier unit 2102 is the output terminal of the first power amplifier module 2111.

[0161] The third power amplifier module 2121 includes a third power amplifier unit 2103 and a fourth power amplifier unit 2104. The input terminal of the third power amplifier unit 2103 is connected to the input terminal of the power amplifier 20. The third power amplifier unit 2103 and the fourth power amplifier unit 2104 are both single-ended power amplifier units. The output terminal of the fourth power amplifier unit 2104 is the output terminal of the third power amplifier module 2121.

[0162] In this embodiment, the first power amplifier module and the third power amplifier module each have a two-stage power amplifier structure, which is beneficial to improving the output power.

[0163] For example, please refer to Figure 17 As shown, the first power amplifier unit 2101 may include a first transistor Q1, the second power amplifier unit 2102 may include a second transistor Q2, the third power amplifier unit 2103 may include a third transistor Q3, and the fourth power amplifier unit 2104 may include a fourth transistor Q4. The second power amplifier module 2113 may include a fifth transistor Q5 and a sixth transistor Q6, wherein the control terminal of the fifth transistor Q5 is connected to the first terminal of the third secondary side 211d, and the control terminal of the sixth transistor Q6 is connected to the second terminal of the third secondary side 211d. The fourth power amplifier module 2123 may include a seventh transistor Q7 and an eighth transistor Q8, wherein the control terminal of the seventh transistor Q7 is connected to the first terminal of the fourth secondary side 212d, and the control terminal of the eighth transistor Q8 is connected to the second terminal of the fourth secondary side 212d.

[0164] In some implementations, please refer to Figure 17 As shown, the RF front-end module 100 also includes a first power supply terminal 11 and a second power supply terminal 12 disposed on the substrate 10. The first power amplification unit 2101 and the second power amplification unit 2102 are respectively connected to the first power supply terminal 11. The second power amplification module 2113 is connected to the second power supply terminal 12 through the first balun 221. The third power amplification unit 2103 and the fourth power amplification unit 2104 are respectively connected to the first power supply terminal 11. The fourth power amplification module 2123 is connected to the second power supply terminal 12 through the second balun 222.

[0165] In this embodiment, the first two power amplification structures in the first power amplification branch and the second power amplification branch are connected to the same power supply terminal, and the last power amplification structure in the first power amplification branch and the second power amplification branch is connected to another power supply terminal through a corresponding balun, so as to avoid overlapping of traces and mutual interference of traces and improve the stability of the RF front-end module.

[0166] In some implementations, please refer to Figure 17As shown, the output terminal 210b of the first power amplifier unit 2101 and the output terminal 210b of the second power amplifier unit 2102 are respectively connected to the first power supply terminal 11, the output terminal 210c of the third power amplifier unit 2103 and the output terminal 210d of the fourth power amplifier unit 2104 are respectively connected to the first power supply terminal 11, the second power supply terminal 12 is connected to the midpoint 221a of the first primary side 2210, and the second power supply terminal 12 is also connected to the midpoint 222a of the second primary side 2220.

[0167] In this embodiment, the first, second, third, and fourth power amplification units are each connected to the first power supply terminal through their respective output terminals, thus multiplexing the output terminals as power supply terminals and achieving signal port multiplexing, simplifying the circuit structure. Simultaneously, the first and second baluns are each connected to the second power supply terminal through the midpoint of their respective primary sides, multiplexing the connection terminals with the first or second capacitor as power supply terminals, achieving signal port multiplexing and simplifying the circuit structure.

[0168] In some implementations, please refer to Figure 17 As shown, the power amplifier circuit 21a also includes a choke unit 213. The first end of one choke unit 213 is connected to the output terminal (power supply terminal) 210a of the first power amplifier unit 2101. The second end of the choke unit 213 and the output terminal (power supply terminal) 210b of the second power amplifier unit 2102 are respectively connected to the first power supply terminal 11. The first end of another choke unit 213 is connected to the output terminal (power supply terminal) 210c of the third power amplifier unit 2103. The second end of the choke unit 213 and the output terminal (power supply terminal) 210d of the fourth power amplifier unit 2104 are respectively connected to the first power supply terminal 11.

[0169] The choke unit 213 is used to prevent the radio frequency signals at the first power amplifier unit 2101 and the third power amplifier unit 2103 from leaking to the first power supply terminal 11, thereby ensuring the normal operation of the power amplifier 20. In addition, the choke unit 213 can also prevent the AC component of the first supply voltage VCC1 output from the first power supply terminal 11, which is an interference signal, from entering the first power amplifier unit 2101 and the third power amplifier unit 2103.

[0170] In some implementations, please refer to Figure 17 As shown, the power amplifier circuit 21a further includes a stabilizing unit 214, which is connected in parallel with the choke unit 213. The first end of the stabilizing unit 214 is connected to the first end of the choke unit 213, and the second end of the stabilizing unit 214 is connected to the second end of the choke unit 213. For example, the choke unit 213 may include an inductor.

[0171] One stabilizing unit 214 is used to suppress a portion of the out-of-band low-frequency signals in the radio frequency signals coupled to the first power amplifier unit 2101 by the second power amplifier unit 2102 and the subsequent unit, and the other stabilizing unit 214 is used to suppress a portion of the out-of-band low-frequency signals in the radio frequency signals coupled to the third power amplifier unit 2103 by the fourth power amplifier unit 2104 and the subsequent unit, thereby reducing the out-of-band low-frequency gain of the aforementioned radio frequency signals and improving the stability of the power amplifier 20 during operation. For example, the stabilizing unit 214 may include at least one resistor.

[0172] In some implementations, please refer to Figure 17 As shown, the power amplifier circuit 21a may further include a signal input terminal 20a, a first DC blocking capacitor 215, and a second DC blocking capacitor 216. One of the first DC blocking capacitors 215 is connected between the signal input terminal 20a and the control terminal of the first transistor Q1, preventing the DC bias signal applied to the control terminal of the first transistor Q1 from flowing to the signal input terminal 20a, thus ensuring the smooth operation of the first transistor Q1. The other first DC blocking capacitor 215 is connected between the signal input terminal 20a and the control terminal of the third transistor Q3, preventing the DC bias signal applied to the control terminal of the third transistor Q3 from flowing to the signal input terminal 20a, thus ensuring the smooth operation of the third transistor Q3. One of the second DC blocking capacitors 216 is connected between the first terminal of the first transistor Q1 and the control terminal of the second transistor Q2. It is used to prevent the DC bias signal applied at the control terminal of the second transistor Q2 from flowing to the first transistor Q1, so as to ensure that the second transistor Q2 can work smoothly. The other second DC blocking capacitor 216 is connected between the first terminal of the third transistor Q3 and the control terminal of the fourth transistor Q4. It is used to prevent the DC bias signal applied at the control terminal of the fourth transistor Q4 from flowing to the third transistor Q3, so as to ensure that the fourth transistor Q4 can work smoothly.

[0173] In some implementations, please refer to Figure 17 As shown, the power amplifier circuit 21a may also include a first isolation unit 2171 and a second isolation unit 2172.

[0174] In the first power amplifier branch 211, the first end of the first isolation unit 2171 is connected to the second end of the choke unit 213, and the second end of the first isolation unit 2171 is connected to the first power supply terminal 11. The first end of the second isolation unit 2172 is connected to the output terminal of the second power amplifier unit 2102, and the second end of the second isolation unit 2172 is connected to the first power supply terminal 11. The first isolation unit 2171 and the second isolation unit 2172 are used to isolate the radio frequency signal between the first power amplifier unit 2101 and the second power amplifier unit 2102 to improve the operating stability of the power amplifier 20.

[0175] In the second power amplifier branch 212, the first end of the first isolation unit 2171 is connected to the second end of the choke unit 213, and the second end of the first isolation unit 2171 is connected to the first power supply terminal 11. The first end of the second isolation unit 2172 is connected to the output terminal of the fourth power amplifier unit 2104, and the second end of the second isolation unit 2172 is connected to the first power supply terminal 11. The first isolation unit 2171 and the second isolation unit 2172 are used to isolate the radio frequency signals between the third power amplifier unit 2103 and the fourth power amplifier unit 2104 to improve the operating stability of the power amplifier 20.

[0176] In some implementations, please refer to Figure 17 As shown, the power amplifier circuit 21a may also include a first decoupling unit 2181 and a second decoupling unit 2182.

[0177] In the first power amplifier branch 211, one end of the first decoupling unit 2181 is connected to the first end of the first isolation unit 2171, and the other end is grounded. One end of the second decoupling unit 2182 is connected to the first end of the second isolation unit 2172, and the other end is grounded. By setting the first decoupling unit 2181 and the second decoupling unit 2182, most of the output signals coupled to the first power amplifier unit 2101 can be filtered out. The signals that are not filtered out will reach the branch where the choke unit 213 and the stabilizing unit 214 are located, and then the choke unit 213 and the stabilizing unit 214 will suppress the above signals to avoid the power amplifier 20 from oscillating, thereby improving the operating stability of the power amplifier 20.

[0178] In the second power amplifier branch 212, one end of the first decoupling unit 2181 is connected to the first end of the first isolation unit 2171, and the other end is grounded. One end of the second decoupling unit 2182 is connected to the first end of the second isolation unit 2172, and the other end is grounded. By setting the first decoupling unit 2181 and the second decoupling unit 2182, most of the output signals coupled to the third power amplifier unit 2103 can be filtered out. The unfiltered signals will reach the branch where the choke unit 213 and the stabilizing unit 214 are located, and then the choke unit 213 and the stabilizing unit 214 will suppress the above signals to avoid the power amplifier 20 from oscillating, thereby improving the operating stability of the power amplifier 20.

[0179] In some implementations, please refer to Figure 17 As shown, the power amplifier circuit 21a may also include a third DC blocking capacitor 2191 and a fourth DC blocking capacitor 2192.

[0180] In the first power amplifier branch 211, one end of the third secondary side 211d is connected to the control terminal of the fifth transistor Q5 via a third DC blocking capacitor 2191. The third DC blocking capacitor 2191 prevents the DC bias signal applied to the control terminal of the fifth transistor Q5 from flowing to the third secondary side 211d, thus ensuring the smooth operation of the fifth transistor Q5. The other end of the third secondary side 211d is connected to the control terminal of the sixth transistor Q6 via a fourth DC blocking capacitor 2192. The fourth DC blocking capacitor 2192 prevents the DC bias signal applied to the control terminal of the sixth transistor Q6 from flowing to the third secondary side 211d, thus ensuring the smooth operation of the sixth transistor Q6. Furthermore, the third DC blocking capacitor 2191 and the fourth DC blocking capacitor 2192, together with the third balun 2112, can participate in impedance matching to improve the transmission efficiency of the radio frequency signal.

[0181] In the second power amplifier branch 212, one end of the fourth secondary side 212d is connected to the control terminal of the seventh transistor Q7 via the third DC blocking capacitor 2191. The third DC blocking capacitor 2191 prevents the DC bias signal applied to the control terminal of the seventh transistor Q7 from flowing to the fourth secondary side 212d, thus ensuring the smooth operation of the seventh transistor Q7. The other end of the fourth secondary side 212d is connected to the control terminal of the eighth transistor Q8 via the fourth DC blocking capacitor 2192. The fourth DC blocking capacitor 2192 prevents the DC bias signal applied to the control terminal of the eighth transistor Q8 from flowing to the fourth secondary side 212d, thus ensuring the smooth operation of the eighth transistor Q8. In addition, the third DC blocking capacitor 2191 and the fourth DC blocking capacitor 2192, together with the fourth balun 2122, can participate in impedance matching to improve the transmission efficiency of the radio frequency signal.

[0182] In some implementations, please refer to Figure 17 As shown, the power amplifier circuit 21a may also include a fifth DC blocking capacitor 2193.

[0183] In the first power amplification branch 211, one end of the fifth DC blocking capacitor 2193 is connected to the second end of the third primary side 211c, and the other end is grounded. Since the first supply voltage VCC1 output from the first power supply terminal 11 flows through the third primary side 211c to the first end of the second transistor Q2 to supply power to the second transistor Q2, in order to prevent the first supply voltage VCC1 from short-circuiting to ground at the second end of the third primary side 211c, the fifth DC blocking capacitor 2193 is set between the second end of the third primary side 211c and the ground terminal to block DC and ensure the smooth operation of the second transistor Q2.

[0184] In the second power amplifier branch 212, one end of the fifth DC blocking capacitor 2193 is connected to the second terminal of the fourth primary side 212c, and the other end is grounded. Since the first supply voltage VCC1 output from the first power supply terminal 11 flows through the fourth primary side 212c to the first terminal of the fourth transistor Q4 to supply power to the fourth transistor Q4, in order to prevent the first supply voltage VCC1 from short-circuiting to ground at the second terminal of the fourth primary side 212c, the fifth DC blocking capacitor 2193 is set between the second terminal of the fourth primary side 212c and the ground terminal to block DC and ensure the smooth operation of the fourth transistor Q4.

[0185] The above description is merely an embodiment of this application. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of this application, but these improvements all fall within the protection scope of this application.

Claims

1. A radio frequency front-end module, characterized in that, include: substrate; A power amplifier, the power amplifier including a power amplifier chip and an output circuit respectively disposed on the substrate; The power amplifier chip integrates a power amplifier circuit and a detector circuit. The power amplifier circuit amplifies the radio frequency signal and outputs it to the output circuit; the output circuit processes the power amplified signal output by the power amplifier circuit to output a power amplified radio frequency signal, and couples the power amplified radio frequency signal to the detector circuit. The power amplifier circuit is located in a first setting area of ​​the power amplifier chip, and the detector circuit is located in a second setting area of ​​the power amplifier chip. The first setting area and the second setting area are spaced apart. The first setting area is close to a first side of the power amplifier chip along a first direction, and the second setting area is close to a second side of the power amplifier chip along a first direction. The output circuit is located on the first side of the power amplifier chip along the first direction.

2. The radio frequency front-end module according to claim 1, characterized in that, The power amplifier circuit includes at least two power amplifier units connected in sequence. Each power amplifier unit includes a power amplifier transistor. The control terminal of the power amplifier transistor is connected to the input terminal of the power amplifier unit. The first terminal of the power amplifier transistor is connected to the output terminal of the power amplifier unit, and the second terminal of the power amplifier transistor is grounded.

3. The radio frequency front-end module according to claim 2, characterized in that, The power amplifier circuit includes a first power amplifier branch and a second power amplifier branch. The first power amplifier branch and the second power amplifier branch respectively perform power amplification processing on a pair of differential radio frequency signals. The first power amplifier branch and the second power amplifier branch each include at least two stages of the power amplifier unit connected in sequence.

4. The radio frequency front-end module according to claim 1, characterized in that, The output circuit includes a signal combining unit and a signal coupling unit coupled to the signal combining unit. The signal combining unit is used to combine the power amplified signal output by the power amplification circuit to output the power amplified radio frequency signal. The signal coupling unit is used to couple the power amplified radio frequency signal on the signal combining unit to the detection circuit.

5. The radio frequency front-end module according to claim 4, characterized in that, The signal coupling unit includes a first coupling line and a second coupling line that are coupled to each other. The first coupling line is connected to the signal combining unit, the first end of the second coupling line is connected to the detector circuit, and the second end of the second coupling line is grounded.

6. The radio frequency front-end module according to claim 5, characterized in that, The signal coupling unit further includes a first resistor, which is connected in series between the second end of the second coupling line and the ground terminal.

7. The radio frequency front-end module according to claim 5, characterized in that, The signal coupling unit further includes a second resistor, one end of which is connected to the first end of the second coupling line, and the second end of which is connected to the detection circuit.

8. The radio frequency front-end module according to claim 1, characterized in that, The RF front-end module further includes a first input bonding wire and a second input bonding wire. The first input bonding wire is used to transmit the power amplified RF signal to the detection circuit. One end of the first input bonding wire is connected to a first metal pad on the substrate to connect to the output circuit through the first metal pad, and the other end is connected to the signal input terminal of the detection circuit. The second input bonding wire is used to transmit the RF signal to the power amplification circuit. The first end of the second input bonding wire is connected to a switching chip on the substrate, and the second end is connected to the signal input terminal of the power amplification chip. The virtual straight line corresponding to the first input bonding wire in the extension direction intersects the virtual straight line corresponding to the second input bonding wire in the extension direction.

9. The radio frequency front-end module according to claim 8, characterized in that, The virtual straight line corresponding to the first input binding line in the extension direction is perpendicular to the virtual straight line corresponding to the second input binding line in the extension direction.

10. The radio frequency front-end module according to claim 8, characterized in that, The RF front-end module further includes a first output bonding wire, which is used to output the detection result of the detection circuit. One end of the first output bonding wire is connected to a second metal pad on the substrate, and the other end is connected to the signal output terminal of the detection circuit. The virtual straight line corresponding to the first output bonding wire in the extension direction intersects with the virtual straight line corresponding to the second input bonding wire in the extension direction.

11. The radio frequency front-end module according to claim 10, characterized in that, The radio frequency front-end module further includes at least one signal output bonding wire disposed between the power amplifier chip and the output circuit. The signal output bonding wire is disposed close to a first side of the power amplifier chip along a first direction. The first input bonding wire and the first output bonding wire are respectively disposed close to a second side of the power amplifier chip along a first direction. The signal output bonding wire is disposed away from the first input bonding wire and the first output bonding wire.

12. The radio frequency front-end module according to claim 1, characterized in that, The power amplifier chip integrates at least one bias circuit, which is located in a third setting area of ​​the power amplifier chip, between the first setting area and the second setting area.

13. The radio frequency front-end module according to claim 12, characterized in that, The distance between the center of the third setting area and the center of the first setting area is the first distance, and the distance between the center of the third setting area and the center of the second setting area is the second distance, wherein the second distance is less than the first distance.

14. The radio frequency front-end module according to claim 4, characterized in that, The signal coupling unit includes a first coupling line, which is connected to the signal combining unit; The signal combining unit includes a first balun, a second balun, and a combining module. The first balun and the second balun are respectively connected to the power amplifier circuit. The power amplifier circuit amplifies a pair of differential radio frequency signals and outputs them to the first balun and the second balun. The combining module is used to combine the two power amplified signals output from the first balun and the second balun to output a power amplified radio frequency signal. The combining module includes a first inductor unit connected to the output terminal of the first balun, a second inductor unit connected to the output terminal of the second balun, and a combining output unit. The first end of the combining output unit is connected to the output terminals of the first inductor unit and the second inductor unit, respectively, and the second end of the combining output unit is connected to the signal output terminal of the output circuit. The first end of the first coupling line is connected to the output terminals of the first inductor unit and the second inductor unit, respectively, and the second end of the first coupling line is connected to the first end of the combining output unit.

15. The radio frequency front-end module according to claim 14, characterized in that, The first balun and the second balun are respectively located on both sides of the first central axis of the setting area of ​​the power amplifier chip, and the first inductor unit and the second inductor unit are respectively located on both sides of the first central axis of the setting area of ​​the power amplifier chip.

16. The radio frequency front-end module according to claim 15, characterized in that, The first balun and the second balun are arranged symmetrically with respect to the first central axis of the power amplifier chip, and the first inductor unit and the second inductor unit are arranged symmetrically with respect to the first central axis of the power amplifier chip.

17. The radio frequency front-end module according to claim 15, characterized in that, The first inductor unit includes a first inductor connected to the output terminal of the first balun and a second inductor connected to the first inductor, wherein the extension direction of the first inductor is not parallel to the extension direction of the second inductor; the second inductor unit includes a third inductor connected to the output terminal of the second balun and a fourth inductor connected to the third inductor, wherein the extension direction of the third inductor is not parallel to the extension direction of the fourth inductor.

18. The radio frequency front-end module according to claim 17, characterized in that, The first inductor is perpendicular to the second inductor, and the third inductor is perpendicular to the fourth inductor.

19. The radio frequency front-end module according to claim 18, characterized in that, The first inductor extends parallel to the first central axis, the second inductor extends perpendicular to the first central axis, the third inductor extends parallel to the first central axis, and the fourth inductor extends perpendicular to the first central axis.

20. The radio frequency front-end module according to claim 17, characterized in that, The first inductor, the second inductor, the third inductor, and the fourth inductor are respectively wound on the substrate, or the first inductor, the second inductor, the third inductor, and the fourth inductor are respectively surface mount inductors disposed on the surface of the substrate.

21. The radio frequency front-end module according to claim 14, characterized in that, The output circuit further includes an isolation resistor unit, one end of which is connected to the output terminal of the first balun, and the other end of which is connected to the output terminal of the second balun.

22. The radio frequency front-end module according to claim 21, characterized in that, The isolation resistor unit is located on the first central axis of the setting area of ​​the power amplifier chip.

23. The radio frequency front-end module according to claim 14, characterized in that, The output circuit further includes a combining matching capacitor. The first end of the combining matching capacitor is connected to the output end of the first inductor unit, the output end of the second inductor unit, and the first end of the combining output unit. The second end of the combining matching capacitor is grounded. The combining matching capacitor is located on the first central axis of the setting area of ​​the power amplifier chip.

24. The radio frequency front-end module according to claim 23, characterized in that, The first inductor unit includes a first inductor connected to the output terminal of the first balun and a second inductor connected to the first inductor. The extension direction of the first inductor is parallel to the first central axis, and the extension direction of the second inductor is perpendicular to the first central axis. The second inductor unit includes a third inductor connected to the output terminal of the second balun and a fourth inductor connected to the third inductor. The extension direction of the third inductor is parallel to the first central axis, and the extension direction of the fourth inductor is perpendicular to the first central axis. The first terminal of the combining matching capacitor is connected to the second inductor and the fourth inductor, respectively, and the combining matching capacitor is disposed in the gap region between the second inductor and the fourth inductor.

25. The radio frequency front-end module according to claim 24, characterized in that, The first inductor unit, the combined matching capacitor, the second inductor unit, the side of the second balun away from the power amplifier chip, and the side of the first balun away from the power amplifier chip are sequentially arranged to form a first rectangular area; The output circuit further includes an isolation resistor unit, the two ends of which are respectively connected to the output terminals of the first balun and the second balun. The isolation resistor unit is located on the first central axis and within the first rectangular area.

26. The radio frequency front-end module according to claim 25, characterized in that, The combined output unit includes at least two combined inductors connected in sequence, and the extension direction of the combined inductors is perpendicular to the first central axis.

27. The radio frequency front-end module according to claim 26, characterized in that, The combining inductor is a surface mount inductor disposed on the surface of the substrate.

28. The radio frequency front-end module according to claim 23, characterized in that, The signal coupling unit is located on the side of the combining matching capacitor away from the first balun and the second balun.

29. The radio frequency front-end module according to claim 14, characterized in that, The power amplifier is used to amplify the power of radio frequency signals in multiple frequency bands. The radio frequency front-end module also includes a switching chip disposed on the substrate. The switching chip integrates multiple switching units, and each switching unit is used to select and input the radio frequency signal of at least one frequency band to the power amplifier chip. The first balun and the second balun are located on the first side of the power amplifier chip along the first direction, and the switching chip is located on the second side of the power amplifier chip along the first direction.

30. The radio frequency front-end module according to claim 29, characterized in that, The radio frequency front-end module also includes: A control chip is disposed on the substrate, and the control chip is electrically connected to the power amplifier chip; The control chip is located on the second side of the power amplifier chip along the first direction.

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