A relaxation oscillator, undervoltage protection circuit and high-voltage integrated circuit

Abstract

The present invention relates to the field of undervoltage protection technology, and in particular to a relaxation oscillator, an undervoltage protection circuit, and a high-voltage integrated circuit. When an RS trigger RS3 of the relaxation oscillator is triggered, a first charge-discharge circuit sequentially enters a first pre-charge region, a first transition charge region, a first effective charge region, and a first discharge region, and a second charge-discharge circuit correspondingly enters a second effective charge region, a second discharge region, a second pre-charge region, and a second transition charge region, and so on. The relaxation oscillator is used to generate a clock signal when an undervoltage protection circuit detects an undervoltage fault, and then the undervoltage protection circuit is integrated into a high-voltage integrated circuit. Thus, a high-tuning linearity clock signal is used to replace a level-triggered undervoltage protection circuit, and various undervoltage faults are adapted to by changing the duration and frequency of the clock signal, thereby improving the stability and accuracy of the undervoltage protection.

Description

Technical Field

[0001] The present invention relates to the technical field of undervoltage protection, in particular to a relaxation oscillator, an undervoltage protection circuit and a high-voltage integrated circuit. Background Art

[0002] A high-voltage integrated circuit (HVIC) converts MCU signals into signals to drive IGBTs or MOS transistors. An HVIC integrates PMOS transistors, NMOS transistors, triodes, diodes, voltage regulators, resistors, and capacitors to form circuits such as Schmitt transistors, low-voltage level switches, high-voltage level switches, pulse generators, delay circuits, filters, overcurrent and thermal protection circuits, undervoltage protection circuits, and bootstrap circuits. In this integrated environment, the power supply voltage (VCC) is affected by various circuits, and some glitches (such as switching noise) are inevitable. For example, when the power supply voltage fluctuates significantly (i.e., the voltage change) and width (i.e., the duration), when the power supply voltage drops below the trigger threshold of the undervoltage protection circuit, the voltage during this period is not filtered, causing frequent undervoltage protection triggering. This can lead to instability in subsequent circuits and reduce the efficiency of the high-voltage integrated circuit.

[0003] Considering that the commonly used undervoltage protection uses level triggering, which will lead to the need for undervoltage filtering, it is preferred to use a clock signal instead of a level as the undervoltage protection trigger signal to achieve the purpose of filtering, avoid frequent triggering of undervoltage protection, and improve work efficiency.

[0004] However, how to match the clock signal with the duration of the undervoltage fault and different undervoltage values ​​to perform targeted undervoltage protection actions, improve the accuracy of undervoltage protection, and, under this premise, how to ensure the high tuning linearity of the clock signal that adapts to different undervoltage faults, are issues that need to be urgently addressed in the current undervoltage protection technology field. Summary of the Invention

[0005] In response to the above-mentioned defects, the purpose of the present invention is to propose a relaxation oscillator, an undervoltage protection circuit and a high-voltage integrated circuit, which replace the level-triggered undervoltage protection with a clock signal with high tuning linearity, and adapt to various undervoltage faults by changing the duration and frequency of the clock signal, thereby improving the stability and accuracy of the undervoltage protection.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A relaxation oscillator includes an RS trigger RS3, a comparator CMP1, a comparator CMP2, a first charge-discharge circuit, and a second charge-discharge circuit; the Q1 terminal of the RS trigger RS3 serves as the input terminal of the relaxation oscillator, the / Q1 terminal of the RS trigger RS3 serves as the output terminal of the relaxation oscillator, the power supply terminal of the first charge-discharge circuit serves as the first current source terminal of the relaxation oscillator, and the power supply terminal of the second charge-discharge circuit serves as the second current source terminal of the relaxation oscillator;

[0008] The Q1 terminal and / Q1 terminal of the RS trigger RS3 are electrically connected to the input terminal of the first charge and discharge circuit and the input terminal of the second charge and discharge circuit, respectively; the S terminal and R terminal of the RS trigger RS3 are electrically connected to the output terminal of the comparator CMP1 and the output terminal of the comparator CMP2, respectively; the positive input terminal of the comparator CMP1 and the positive input terminal of the comparator CMP2 are electrically connected to the output terminal of the first charge and discharge circuit and the output terminal of the second charge and discharge circuit, respectively; the negative input terminal of the comparator CMP1 and the negative input terminal of the comparator CMP2 are both connected to the VH voltage;

[0009] When the RS trigger RS3 is triggered, the first charge and discharge circuit enters the first pre-charge region, and the second charge and discharge circuit enters the second effective charge region; when the first charge and discharge circuit enters the first transition charge region, the second charge and discharge circuit enters the second discharge region; when the first charge and discharge circuit enters the first effective charge region, the second charge and discharge circuit enters the second pre-charge region; when the first charge and discharge circuit enters the first discharge region, the second charge and discharge circuit enters the second transition charge region;

[0010] The first charge and discharge circuit sequentially enters the first pre-charge region, the first transition charge region, the first effective charge region and the first discharge region to cycle;

[0011] The second charge and discharge circuit sequentially enters the second pre-charge region, the second transition charge region, the second effective charge region and the second discharge region for cyclic operation.

[0012] Furthermore, the first charge and discharge circuit includes an RS trigger RS4, a comparator CMP3, a comparator CMP4, an OR gate OR1, a PNP MOS transistor S1, a PNP MOS transistor S3, an NPN MOS transistor S5, a capacitor C1, a NOT gate U21, a NOT gate U22, a NOT gate U23, and an AND gate U24; the second input end of the OR gate OR1 serves as the input end of the first charge and discharge circuit, the source end of the PNP MOS transistor S3 serves as the power supply end of the first charge and discharge circuit, and the drain end of the PNP MOS transistor S3 serves as the output end of the first charge and discharge circuit;

[0013] The first input terminal of the OR gate OR1 is electrically connected to the / Q2 terminal of the RS trigger RS4, the Q2 terminal of the RS trigger RS4 is electrically connected to the gate of the PNP MOS transistor S1, the S terminal and the R terminal of the RS trigger RS4 are electrically connected to the output terminal of the comparator CMP3 and the output terminal of the comparator CMP4, respectively, the negative input terminal of the comparator CMP3 is connected to the VL voltage, the positive input terminal of the comparator CMP4 is connected to the VM voltage, the positive input terminal of the comparator CMP3, the negative input terminal of the comparator CMP4, the drain of the PNP MOS transistor S1, the drain of the PNP MOS transistor S3, and the drain of the NPN MOS transistor S5 are all electrically connected to one end of the capacitor C1, and the OR gate OR1 is electrically connected to the / Q2 terminal of the RS trigger RS4. The output end of the gate OR1 is electrically connected to the gate of the PNP MOS transistor S3, the source of the PNP MOS transistor S1 is electrically connected to the source of the PNP MOS transistor S3, the second input end of the OR gate OR1 and the input end of the NOT gate U21 are both electrically connected to the first input end of the AND gate U24, the output end of the NOT gate U21 is electrically connected to the input end of the NOT gate U22, the output end of the NOT gate U22 is electrically connected to the input end of the NOT gate U23, the output end of the NOT gate U23 is electrically connected to the second input end of the AND gate U24, the output end of the AND gate U24 is electrically connected to the gate of the NPN MOS transistor S5, and the source of the NPN MOS transistor S5 and the other end of the capacitor C1 are both grounded.

[0014] Furthermore, the first charge and discharge circuit and the second charge and discharge circuit have the same circuit structure.

[0015] Furthermore, the magnitude relationship among the VH voltage, the VL voltage, and the VM voltage is VM<VL<VH.

[0016] An undervoltage protection circuit includes an undervoltage fault judgment module, an undervoltage time adaptation module, an undervoltage frequency selection module, and an undervoltage protection trigger module; the undervoltage time adaptation module includes an RS trigger RS1, an oscillating current source, a relaxation oscillator, and a startup circuit; the relaxation oscillator is the relaxation oscillator described above;

[0017] The input end of the undervoltage fault judgment module is connected to the VCC power supply, the output end of the undervoltage fault judgment module, the first reset end of the undervoltage frequency selection module, and the first reset end of the undervoltage protection trigger module are all electrically connected to the input end of the undervoltage time adaptation module, the first input end and the second input end of the undervoltage frequency selection module are both electrically connected to the output end of the undervoltage time adaptation module, the selection end of the undervoltage frequency selection module is connected to the VCC power supply, the first output end and the second output end of the undervoltage frequency selection module are respectively electrically connected to the first input end and the second input end of the undervoltage protection trigger module, the second reset end of the undervoltage frequency selection module is electrically connected to the output end of the undervoltage protection trigger module, the second reset end of the undervoltage protection trigger module is electrically connected to the reset end of the undervoltage time adaptation module, and the output end of the undervoltage protection trigger module is connected to a subsequent undervoltage protection action circuit;

[0018] The undervoltage fault judgment module is used to compare the external power supply voltage with the undervoltage threshold, and generate an undervoltage fault signal when the power supply voltage is lower than the undervoltage threshold;

[0019] The undervoltage time adaptation module is used to receive the undervoltage fault signal and generate a clock signal according to the duration of the undervoltage fault signal;

[0020] The undervoltage frequency selection module is used to receive the clock signal and the power supply voltage, reduce the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage, and generate a filtered clock signal; the undervoltage value is proportional to the frequency of the filtered clock signal;

[0021] The undervoltage protection trigger module is configured to not operate when the duration of the received filtering clock signal is less than the filtering triggering moment; and to start filtering from the filtering triggering moment and generate an undervoltage protection action signal when the duration of the received filtering clock signal is greater than or equal to the filtering triggering moment;

[0022] The S terminal of the RS trigger RS1 is used as the input terminal of the brown-out time adaptation module, the R terminal of the RS trigger RS1 is used as the reset terminal of the brown-out time adaptation module, and the output terminal of the relaxation oscillator is used as the output terminal of the brown-out time adaptation module;

[0023] The Q terminal of the RS trigger RS1 is electrically connected to the input terminal of the startup circuit, the output terminal of the startup circuit is electrically connected to the input terminal of the relaxation oscillator, and the first output terminal and the second output terminal of the oscillation current source are electrically connected to the first current source terminal and the second current source terminal of the relaxation oscillator respectively;

[0024] The waveform of the oscillating current source is opposite to the waveform of the power supply voltage;

[0025] The RS trigger RS1 is used to start the startup circuit when receiving the undervoltage fault signal;

[0026] When the startup circuit is turned on, the startup circuit drives the relaxation oscillator to generate the clock signal.

[0027] Furthermore, the frequency of the clock signal is F1, the frequency of the filtered clock signal is F2, and the undervoltage value is divided into n stages from large to small;

[0028] The relationship between the frequency F1 of the clock signal and the frequency F2 of the filtered clock signal is F2=F1*( ), where N is any value from 1 to n.

[0029] Furthermore, the undervoltage frequency selection module includes a first frequency divider and a second frequency divider; the clock end of the first frequency divider is used as the first input end of the undervoltage frequency selection module, the reset end of the first frequency divider is used as the first reset end of the undervoltage frequency selection module, the output end of the first frequency divider is used as the first output end of the undervoltage frequency selection module, the clock end of the second frequency divider is used as the second input end of the undervoltage frequency selection module, the reset end of the second frequency divider is used as the second reset end of the undervoltage frequency selection module, the output end of the second frequency divider is used as the second output end of the undervoltage frequency selection module, and the selection end of the first frequency divider or the second frequency divider is used as the selection end of the undervoltage frequency selection module;

[0030] The first frequency divider and the second frequency divider are both used to receive the clock signal and the power supply voltage, determine the stage of the undervoltage value, and correspondingly reduce the frequency of the clock signal to generate the filtered clock signal;

[0031] The first frequency divider generates the filtered clock signal earlier than the second frequency divider.

[0032] Furthermore, the first frequency divider and the second frequency divider have the same circuit structure;

[0033] The first frequency divider includes a selection unit and n D flip-flops D3; the input end and the output end of the selection unit are respectively used as the selection end and the output end of the first frequency divider, and the clock end and the reset end of the first D flip-flop D3 are respectively used as the clock end and the reset end of the first frequency divider;

[0034] The Q terminal of the preceding D flip-flop D3 is electrically connected to the clock terminal of the succeeding D flip-flop D3, the reset terminals of all the D flip-flops D3 are electrically connected in common, the D terminal and the / Q terminal of each D flip-flop D3 are electrically connected, and the Q terminals of the first to nth D flip-flops D3 are electrically connected to the first to nth selection terminals of the selection unit, respectively;

[0035] The selection unit is used to receive the power supply voltage to determine the stage of the undervoltage value; when the undervoltage value is in any stage from the first to the nth stage, the corresponding selection end from the first selection end to the nth selection end of the selection unit is connected to the output end of the selection unit.

[0036] Furthermore, the undervoltage protection trigger module includes a D flip-flop D1, a D flip-flop D2, an RS flip-flop RS2, a NOT gate U2, a NOT gate U4, a NAND gate U3, a NAND gate U5, a NAND gate U7 and an AND gate U6; the clock terminal and the reset terminal of the D flip-flop D1 are respectively used as the first input terminal and the first reset terminal of the undervoltage protection trigger module, the clock terminal of the D flip-flop D2 is used as the second input terminal of the undervoltage protection trigger module, the output terminal of the AND gate U6 is used as the second reset terminal of the undervoltage protection trigger module, and the Q terminal of the RS flip-flop RS2 is used as the output terminal of the undervoltage protection trigger module;

[0037] The / Q terminal of the D flip-flop D1 is electrically connected to the first input terminal of the NAND gate U3, the reset terminal of the D flip-flop D1, the input terminal of the NAND gate U2, and the first input terminal of the NAND gate U5 are all electrically connected to the first input terminal of the NAND gate U7, the output terminal of the NAND gate U2 is electrically connected to the second input terminal of the NAND gate U3, the / Q terminal of the D flip-flop D2 is electrically connected to the third input terminal of the NAND gate U5, the reset terminal of the D flip-flop D2, the second input terminal of the NAND gate U7, and the input terminal of the NAND gate U4 are all electrically connected to the R The Q end of the S trigger RS2 is electrically connected, the second input end of the NAND gate U5 is electrically connected to the output end of the NAND gate U4, the output end of the NAND gate U3 is electrically connected to the S end of the RS trigger RS2, the output end of the NAND gate U5 is electrically connected to the first input end of the AND gate U6, the output end of the NAND gate U7 is electrically connected to the second input end of the AND gate U6, the output end of the AND gate U6 is electrically connected to the R end of the RS trigger RS2, and the D end of the D trigger D1 and the D end of the D trigger D2 are both connected to the VCC power supply.

[0038] A high-voltage integrated circuit comprises the above-mentioned undervoltage protection circuit, a fault logic control circuit, and a plurality of fault detection circuits; the input terminal of the undervoltage protection circuit serves as the VCC terminal of the high-voltage integrated circuit, and the output terminal of the undervoltage protection circuit and the output terminals of the plurality of fault detection circuits are electrically connected to the input terminal of the fault logic control circuit respectively;

[0039] The fault logic control circuit is used to shut down the high-voltage integrated circuit when the undervoltage protection circuit or any one of the multiple fault detection circuits feeds back a valid signal.

[0040] The technical solution provided by the present invention can have the following beneficial effects:

[0041] 1. When the RS trigger RS3 of the relaxation oscillator is triggered, the relaxation oscillator starts to oscillate and generates a clock signal output. The principle of oscillating and generating the clock signal is realized by the first charge and discharge circuit and the second charge and discharge circuit respectively cyclically operating in the pre-charge region, the transition charge region, the effective charge region and the discharge region. Specifically, when the RS trigger RS3 is triggered, the level conversion of the Q1 terminal and the / Q1 terminal will form a discharge pulse, so that one of the charging and discharging circuits is in the effective charging area while the other is in the pre-charging area, thereby generating a clock signal; more importantly, the first charging and discharging circuit or the second charging and discharging circuit does not need to start from zero when jumping to a high level like a traditional relaxation oscillator when jumping from the discharge area to the effective charging area. When one circuit is in the effective charging area, the other circuit uses the pre-charging area for a boost transition; and when one circuit is in the discharge area, the other circuit uses the transition charging area for transition, and there will be no obvious jump breakpoints; ultimately, the two jumps within a cycle can be well connected, the voltage continuity is better, and there is no obvious jump breakpoint, so that the charging current and oscillation frequency curves of the relaxation oscillator are closer to a proportional relationship, and then the relaxation oscillator is less affected by temperature and voltage changes than the traditional oscillator, and has better stability, reflecting the high tuning linearity of the relaxation oscillator.

[0042] 2. The relaxation oscillator with high tuning linearity is applied to the undervoltage protection circuit to generate a clock signal to replace the level-triggered undervoltage protection. At the same time, the duration and frequency of the clock signal are changed to adapt to various undervoltage faults, making the undervoltage protection circuit more stable and accurate.

[0043] 3. Integrating the above-mentioned undervoltage protection circuit with higher stability and accuracy into a high-voltage integrated circuit enables the high-voltage integrated circuit to filter out glitch noise in the internal environment of multi-circuit integration, avoid frequent false triggering of undervoltage protection, and improve the stability and accuracy of the undervoltage protection of the high-voltage integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a circuit schematic diagram of a relaxation oscillator according to one embodiment of the present invention.

[0045] Figure 2 Yes Figure 1 The output voltage-time waveform diagram of the first charge and discharge circuit or the second charge and discharge circuit shown.

[0046] Figure 3 Yes Figure 1 The waveform diagram of the oscillation principle of a relaxation oscillator is shown.

[0047] Figure 4 Yes Figure 1 The comparison waveforms of a relaxation oscillator and a traditional oscillator are shown Figure 1 .

[0048] Figure 5 Yes Figure 1 The comparison waveforms of a relaxation oscillator and a traditional oscillator are shown Figure 2 .

[0049] Figure 6 Yes Figure 1 The comparison waveforms of a relaxation oscillator and a traditional oscillator are shown Figure 3 .

[0050] Figure 7 This is a circuit schematic diagram of an undervoltage protection circuit according to one embodiment of the present invention.

[0051] Figure 8 Yes Figure 7 The waveform diagram of an undervoltage protection circuit is shown.

[0052] Figure 9 Yes Figure 7 The circuit schematic diagram of the first frequency divider or the second frequency divider is shown.

[0053] Figure 10 This is a partial schematic diagram of a high-voltage integrated circuit according to one embodiment of the present invention.

[0054] Among them: RS trigger RS3, comparator CMP1, comparator CMP2, first charge and discharge circuit 221, second charge and discharge circuit 222, RS trigger RS4, comparator CMP3, comparator CMP4, OR gate OR1, PNP MOS transistor S1, PNP MOS transistor S3, NPN MOS transistor S5, capacitor C1, NOT gate U21, NOT gate U22, NOT gate U23, AND gate U24, undervoltage fault judgment module 1, undervoltage time adaptation module 2, undervoltage frequency selection module Block 3, undervoltage protection trigger module 4, RS trigger RS1, oscillation current source 21, relaxation oscillator 22, first frequency divider 31, second frequency divider 32, selection unit 33, D trigger D3, D trigger D1, D trigger D2, RS trigger RS2, NOT gate U2, NOT gate U4, NAND gate U3, NAND gate U5, NAND gate U7, AND gate U6, voltage divider circuit 11, reference circuit 12, comparator U1, startup circuit 23, fault logic control circuit 5, fault detection circuit 6. DETAILED DESCRIPTION

[0055] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0056] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the embodiments of the present invention, "plurality" means two or more, unless otherwise specifically specified.

[0057] In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections or indirect connections through an intermediate medium; they may refer to internal communication between two components or an interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the embodiments of the present invention based on specific circumstances.

[0058] The following combination Figures 1 to 10 , describing a relaxation oscillator, undervoltage protection circuit and high-voltage integrated circuit according to embodiments of the present invention.

[0059] Example 1

[0060] A relaxation oscillator includes an RS trigger RS3, a comparator CMP1, a comparator CMP2, a first charge-discharge circuit 221, and a second charge-discharge circuit 222; the Q1 terminal of the RS trigger RS3 serves as an input terminal of the relaxation oscillator, the / Q1 terminal of the RS trigger RS3 serves as an output terminal of the relaxation oscillator, the power supply terminal of the first charge-discharge circuit 221 serves as a first current source terminal of the relaxation oscillator, and the power supply terminal of the second charge-discharge circuit 222 serves as a second current source terminal of the relaxation oscillator;

[0061] The Q1 terminal and / Q1 terminal of the RS flip-flop RS3 are electrically connected to the input terminal of the first charge-discharge circuit 221 and the input terminal of the second charge-discharge circuit 222, respectively. The S terminal and R terminal of the RS flip-flop RS3 are electrically connected to the output terminal of the comparator CMP1 and the output terminal of the comparator CMP2, respectively. The positive input terminal of the comparator CMP1 and the positive input terminal of the comparator CMP2 are electrically connected to the output terminal of the first charge-discharge circuit 221 and the output terminal of the second charge-discharge circuit 222, respectively. The negative input terminal of the comparator CMP1 and the negative input terminal of the comparator CMP2 are both connected to the VH voltage.

[0062] When the RS trigger RS3 is triggered, the first charge and discharge circuit 221 enters the first pre-charge region, and the second charge and discharge circuit 222 enters the second effective charge region; when the first charge and discharge circuit 221 enters the first transition charge region, the second charge and discharge circuit 222 enters the second discharge region; when the first charge and discharge circuit 221 enters the first effective charge region, the second charge and discharge circuit 222 enters the second pre-charge region; when the first charge and discharge circuit 221 enters the first discharge region, the second charge and discharge circuit 222 enters the second transition charge region;

[0063] The first charge and discharge circuit 221 sequentially enters the first pre-charge region, the first transition charge region, the first effective charge region and the first discharge region for cyclic operation;

[0064] The second charge and discharge circuit 222 sequentially enters the second pre-charge region, the second transition charge region, the second effective charge region and the second discharge region for cyclic operation.

[0065] The present invention proposes a preferred embodiment of a relaxation oscillator, such as Figures 1 to 3 As shown, when the RS trigger RS3 is triggered, it means that the relaxation oscillator needs to start oscillating and generate a clock signal output. The principle of starting oscillating and generating a clock signal is realized by the first charge and discharge circuit 221 and the second charge and discharge circuit 222 respectively working in a cycle in the pre-charge region, the transition charge region, the effective charge region and the discharge region. Specifically, the change of the output voltage during the charge and discharge process of the first charge and discharge circuit 221 or the second charge and discharge circuit 222 is as shown in FIG. Figure 2 As shown, the coordination relationship between the cyclic working areas of the first charge and discharge circuit 221 and the second charge and discharge circuit 222 (implemented by the trigger logic of the RS trigger RS3) is as follows: Figure 3As shown, when the RS trigger RS3 is triggered, the level conversion of the Q1 terminal and the / Q1 terminal will form a discharge pulse (i.e., Vc1_Disharge, Vc2_Disharge in the figure), so that one of the charge and discharge circuits (Vc1 in the figure) is in the effective charging area (relatively high level of the clock signal) while the other (Vc2 in the figure) is in the pre-charging area (relatively low level of the clock signal), thereby generating a clock signal; more importantly, the first charge and discharge circuit 221 or the second charge and discharge circuit 222 does not need to start from zero when jumping to a high level like a traditional relaxation oscillator when jumping from the discharge area to the effective charging area. When one path is in the effective charging area, the other path uses the pre-charging area for a boost transition (but is still at a relatively low level); and when one path is in the discharge area, the other path uses the transition charging area for transition, and there will be no obvious jump breakpoint; ultimately, the two jumps in one cycle can be well connected, the voltage continuity is better, and there is no obvious jump breakpoint, so that the charging current and oscillation frequency curve of the relaxation oscillator are more closely proportional (as shown in FIG. Figure 4 As shown, the linearity reaches 99% and above), which makes the relaxation oscillator less affected by temperature and voltage changes (the frequency change is less than 1%) and more stable than the traditional oscillator (such as Figure 5 and 6 As shown in FIG5 ), it reflects the high tuning linearity of the relaxation oscillator, which can well solve the signal stability and signal accuracy problems of the integrated circuit using the relaxation oscillator.

[0066] Furthermore, the first charge and discharge circuit 221 includes an RS trigger RS4, a comparator CMP3, a comparator CMP4, an OR gate OR1, a PNP MOS transistor S1, a PNP MOS transistor S3, an NPN MOS transistor S5, a capacitor C1, a NOT gate U21, a NOT gate U22, a NOT gate U23, and an AND gate U24; the second input end of the OR gate OR1 serves as the input end of the first charge and discharge circuit 221, the source end of the PNP MOS transistor S3 serves as the power supply end of the first charge and discharge circuit 221, and the drain end of the PNP MOS transistor S3 serves as the output end of the first charge and discharge circuit 221;

[0067] A first input terminal of the OR gate OR1 is electrically connected to a / Q2 terminal of an RS flip-flop RS4. A Q2 terminal of the RS flip-flop RS4 is electrically connected to a gate of a PNP MOS transistor S1. An S terminal and an R terminal of the RS flip-flop RS4 are electrically connected to an output terminal of a comparator CMP3 and an output terminal of a comparator CMP4, respectively. A negative input terminal of the comparator CMP3 is connected to a voltage VL. A positive input terminal of the comparator CMP4 is connected to a voltage VM. The positive input terminal of the comparator CMP3, the negative input terminal of the comparator CMP4, the drain of the PNP MOS transistor S1, the drain of the PNP MOS transistor S3, and the drain of the NPN MOS transistor S5 are all electrically connected to one end of the capacitor C1. An output end of the OR gate OR1 is electrically connected to the gate of the PNP MOS transistor S3, a source of the PNP MOS transistor S1 is electrically connected to the source of the PNP MOS transistor S3, a second input end of the OR gate OR1 and an input end of the NOT gate U21 are electrically connected to a first input end of the AND gate U24, an output end of the NOT gate U21 is electrically connected to an input end of the NOT gate U22, an output end of the NOT gate U22 is electrically connected to an input end of the NOT gate U23, an output end of the NOT gate U23 is electrically connected to a second input end of the AND gate U24, an output end of the AND gate U24 is electrically connected to the gate of the NPN MOS transistor S5, and a source of the NPN MOS transistor S5 and the other end of the capacitor C1 are both grounded.

[0068] In this embodiment, taking the first charge and discharge circuit 221 as an example, under the trigger logic of the RS trigger RS3, its working principle is as follows:

[0069] like Figure 2 As shown, assuming that the voltage on capacitor C1 is 0 in the initial state, Q1=1, / Q1=0, the pre-charge circuit (composed of NOT gates U21 to U23 and AND gate U24) starts charging C1. When the voltage on C1 reaches VL (at time t1), the output of the pre-charge circuit will ideally flip to terminate charging. However, due to the offset voltage of the comparator (CMP1 / CMP2) and the delay of the RS trigger RS3, capacitor C1 will actually continue to be charged for td time. It is not until time t2 that the pre-charge circuit stops charging C1 and enters the waiting state (i.e., the transition charging region). At this time, the voltage of capacitor C1 is:

[0070] Vc1=VL+△V(1)

[0071] Charging time of capacitor C1:

[0072] t1=C1*VL / Iref+td(2);

[0073] Where C1 is the capacitance value of capacitor C1, Iref is the charging current of the current source connected to the relaxation oscillator;

[0074] At time t3, the voltage on capacitor C2 in the other second charge-discharge circuit 222 is triggered by the RS trigger RS3 of the oscillator main circuit, causing it to begin discharging (discharging region). RS trigger RS4 then turns on PNP MOS transistor S3 (active charging region), continuing to charge capacitor C1 until time t4. At this point, the charge on capacitor C2 in the second charge-discharge circuit 222 is released by NPN MOS transistor S6, allowing the next pre-charge cycle to begin. When the voltage on capacitor C1 reaches VH, due to the offset voltage of the comparator (CMP1 / CMP2) and the delay of RS trigger RS3, it cannot respond immediately and continues to charge until time t4, where it stops. At this point, the voltage on capacitor C1 is:

[0075] Vc1'=VH+△V(3)

[0076] By subtracting equation (3) from equation (1), we can get the voltage effect of the effective charging area on capacitor C1:

[0077] Vc1'-Vc1=(VH+△V)-(VL+△V)=VH-VL=Vref(4);

[0078] Where Vref is the charging voltage of the current source connected to the relaxation oscillator;

[0079] At the same time, the effective charging time in the effective charging area is:

[0080] t4-t3=C1(VH-VL) / Iref+td-td=C1*Vref / Iref(5);

[0081] After that, capacitor C1 starts to discharge and enters the discharge region, starting the next cycle. This cycle repeats. It can be seen that the charging time of the effective charging region is half the oscillation period of the entire relaxation oscillator. Therefore, according to formula (5), the entire cycle is:

[0082] T=2*C1*Vref / Iref(6)

[0083] By converting formula (6), we can know that the operating frequency of the relaxation oscillator is:

[0084] f=1 / T=Iref / (2*C1*Vref)(7);

[0085] It can be seen from formula (7) that when the enable signal is valid, the oscillator will complete the oscillation within one cycle, and the oscillation frequency is only related to the charging current and is in direct proportion.

[0086] Furthermore, the first charge and discharge circuit 221 and the second charge and discharge circuit 222 have the same circuit structure.

[0087] In this embodiment, based on the working principle of the above-mentioned first charge and discharge circuit 221, in order to further improve the linearity of the relaxation oscillator, it is preferred to set the circuit structure of the first charge and discharge circuit 221 and the second charge and discharge circuit 222 to be the same, and to drive the RS trigger RS3 in a symmetrical design, thereby obtaining a clock signal with high tuning linearity.

[0088] Furthermore, the magnitude relationship among the VH voltage, the VL voltage, and the VM voltage is VM<VL<VH.

[0089] In this embodiment, it is easy to know from the working principle of the charge and discharge circuit that the magnitude relationship between the VH voltage, the VL voltage and the VM voltage is set to VM<VL<VH so that the oscillation frequency and the charging current are proportional to each other, and the VH voltage is correlated with the current source connected to the oscillator. The difference between the VH voltage and the VL voltage is the voltage value of the current source, VH=VL+Vref. The value of Vref can also be modified according to the requirements of the actual application environment.

[0090] Example 2

[0091] An undervoltage protection circuit includes an undervoltage fault judgment module 1, an undervoltage time adaptation module 2, an undervoltage frequency selection module 3, and an undervoltage protection trigger module 4; the undervoltage time adaptation module 2 includes an RS trigger RS1, an oscillating current source 21, a relaxation oscillator 22, and a startup circuit 23; the relaxation oscillator 22 is the relaxation oscillator described above;

[0092] The input end of the undervoltage fault judgment module 1 is connected to the VCC power supply, the output end of the undervoltage fault judgment module 1, the first reset end of the undervoltage frequency selection module 3, and the first reset end of the undervoltage protection trigger module 4 are all electrically connected to the input end of the undervoltage time adaptation module 2, the first input end and the second input end of the undervoltage frequency selection module 3 are both electrically connected to the output end of the undervoltage time adaptation module 2, the selection end of the undervoltage frequency selection module 3 is connected to the VCC power supply, the first output end and the second output end of the undervoltage frequency selection module 3 are respectively electrically connected to the first input end and the second input end of the undervoltage protection trigger module 4, the second reset end of the undervoltage frequency selection module 3 is electrically connected to the output end of the undervoltage protection trigger module 4, the second reset end of the undervoltage protection trigger module 4 is electrically connected to the reset end of the undervoltage time adaptation module 2, and the output end of the undervoltage protection trigger module 4 is connected to the subsequent undervoltage protection action circuit;

[0093] The undervoltage fault judgment module 1 is used to compare the external power supply voltage with the undervoltage threshold value, and generate an undervoltage fault signal when the power supply voltage is lower than the undervoltage threshold value;

[0094] The undervoltage time adaptation module 2 is used to receive the undervoltage fault signal and generate a clock signal according to the duration of the undervoltage fault signal;

[0095] The undervoltage frequency selection module 3 is used to receive the clock signal and the power supply voltage, and reduce the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage to generate a filtered clock signal; the undervoltage value is proportional to the frequency of the filtered clock signal;

[0096] The undervoltage protection trigger module 4 is configured to not operate when the duration of the received filter clock signal is less than the filter trigger moment; and to start filtering from the filter trigger moment and generate an undervoltage protection action signal when the duration of the received filter clock signal is greater than or equal to the filter trigger moment.

[0097] The S terminal of the RS trigger RS1 is used as the input terminal of the undervoltage time adaptation module 2, the R terminal of the RS trigger RS1 is used as the reset terminal of the undervoltage time adaptation module 2, and the output terminal of the relaxation oscillator 22 is used as the output terminal of the undervoltage time adaptation module 2;

[0098] The Q terminal of the RS trigger RS1 is electrically connected to the input terminal of the startup circuit 23, the output terminal of the startup circuit is electrically connected to the input terminal of the relaxation oscillator 22, and the first output terminal and the second output terminal of the oscillation current source 21 are electrically connected to the first current source terminal and the second current source terminal of the relaxation oscillator 22 respectively;

[0099] The waveform of the oscillating current source 21 is opposite to that of the power supply voltage;

[0100] The RS trigger RS1 is used to start the startup circuit 23 when receiving an undervoltage fault signal;

[0101] When the startup circuit 23 is turned on, the startup circuit 23 drives the relaxation oscillator 22 to generate a clock signal.

[0102] In this embodiment, a preferred embodiment of an undervoltage protection circuit is also proposed, such as Figure 7As shown, when an undervoltage fault occurs, the power supply voltage (VCC power supply) is smaller than that during normal operation, so an undervoltage threshold is provided in the undervoltage fault judgment module 1 for comparison with the external power supply voltage of the undervoltage fault judgment module 1. When the power supply voltage is less than the undervoltage threshold, an undervoltage fault signal is generated; the duration of the undervoltage fault signal represents the duration of the undervoltage fault, so the undervoltage time adaptation module 2 generates a clock signal according to the duration of the undervoltage fault signal, so as to match the duration of the undervoltage fault; therefore, the undervoltage frequency selection module 3 receives the power supply voltage under the premise of being driven by the clock signal to determine the difference between the power supply voltage and the undervoltage value (i.e., the difference) during normal operation. The larger the undervoltage value, the more serious the undervoltage fault, and the longer the filtering time is required, so the frequency of the clock signal needs to be reduced accordingly. The undervoltage frequency selection module 3 reduces the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage to generate a filtered clock signal, so that the filtered clock signal is adapted to the undervoltage fault at the same time. duration and undervoltage value of the undervoltage fault; finally, the high or low level of the conventional undervoltage fault protection circuit is replaced by the filtered clock signal to drive the undervoltage protection trigger module 4 to trigger the undervoltage protection action, thereby achieving the purpose of undervoltage filtering; at the same time, in order to avoid the undervoltage fault duration being too short and to match the filtering time of different undervoltage values, the undervoltage protection trigger module 4 sets a filtering triggering moment. If the duration of the filtered clock signal does not reach the filtering triggering moment, it proves that the undervoltage fault duration is too short, and the undervoltage protection and filtering are meaningless. If the duration of the filtered clock signal is greater than the filtering triggering moment, it proves that filtering is required according to the duration of the undervoltage fault and the undervoltage value, that is, the time period after the filtering triggering moment is the filtering time (because different undervoltage values ​​correspond to filtering clock signals of different frequencies, this means that the filtering triggering moment changes with the filtering clock signal, thereby adapting the filtering time, that is, the undervoltage value and the filtering time are proportional), so the filtering time represents the effective time of the undervoltage protection, such as Figure 8 shown.

[0103] Specifically, the undervoltage fault judgment module 1 includes a voltage divider circuit 11, a reference circuit 12 and a comparator U1; the input end of the voltage divider circuit 11 is used as the input end of the undervoltage fault judgment module 1, and the output end of the comparator U1 is used as the output end of the undervoltage fault judgment module 1; the input end of the voltage divider circuit 11 is electrically connected to the input end of the reference circuit 12, the output end of the voltage divider circuit 11 is electrically connected to the negative input end of the comparator U1, and the output end of the reference circuit 12 is electrically connected to the positive input end of the comparator U1; the voltage divider circuit 11 is used to collect the power supply voltage; the reference circuit 12 is used to generate an undervoltage threshold. The undervoltage fault judgment module 1 mainly judges whether an undervoltage fault occurs. Therefore, the undervoltage fault judgment module 1 is composed of a voltage divider circuit 11, a reference circuit 12 and a comparator U1. The voltage divider circuit 11 (such as a resistor in series) collects the power supply voltage through voltage division and provides it to the negative input terminal of the comparator U1. The reference circuit 12 (such as a Zener diode) generates a clamping voltage through the power supply voltage as an undervoltage threshold to the positive input terminal of the comparator U1. When the collected power supply voltage is higher than the undervoltage threshold, it is an undervoltage fault, and the comparator U1 outputs an undervoltage fault signal (high level is valid).

[0104] In summary, the filtering principle of the undervoltage protection circuit is to use a clock signal instead of the high or low level active in the conventional undervoltage protection circuit to trigger the undervoltage protection action. The generated clock signal has no glitch noise compared to the high or low level, which can completely eliminate the impact of power supply voltage glitch noise on the undervoltage protection triggering, avoid frequent undervoltage protection action, and improve the working efficiency of the integrated circuit. At the same time, the duration and frequency of the clock signal can be changed to adapt to various undervoltage fault situations, thereby improving the accuracy of the undervoltage protection.

[0105] It should be noted that while the undervoltage fault signal (active high) output by undervoltage fault determination module 1 triggers RS trigger RS1, and startup circuit 23 (e.g., a switch circuit) drives relaxation oscillator 22 to generate a clock signal for subsequent undervoltage protection, achieving a filtering effect, to further enhance the filtering effect, relaxation oscillator 22 is started by an oscillating current source 21, whose waveform is opposite to that of the power supply voltage, thereby neutralizing the undervoltage fault. Furthermore, the use of a highly tuned and linear relaxation oscillator in relaxation oscillator 22 enhances the stability and accuracy of the undervoltage protection circuit.

[0106] Furthermore, the frequency of the clock signal is F1, the frequency of the filtered clock signal is F2, and the undervoltage value is divided into n stages from large to small;

[0107] The relationship between the frequency F1 of the clock signal and the frequency F2 of the filtered clock signal is F2=F1*( ), where N is any value from 1 to n.

[0108] In this embodiment, the frequency reduction of the undervoltage value is divided into n stages from large to small according to the size of the undervoltage value. The undervoltage value of each stage corresponds to a frequency, so that the frequency can be proportional to the undervoltage value, which meets the setting requirements of the filter clock signal. The preferred frequency reduction scheme is F2=F1*( ), where N is the stage of undervoltage value.

[0109] Furthermore, the undervoltage frequency selection module 3 includes a first frequency divider 31 and a second frequency divider 32; the clock end of the first frequency divider 31 is used as the first input end of the undervoltage frequency selection module 3, the reset end of the first frequency divider 31 is used as the first reset end of the undervoltage frequency selection module 3, the output end of the first frequency divider 31 is used as the first output end of the undervoltage frequency selection module 3, the clock end of the second frequency divider 32 is used as the second input end of the undervoltage frequency selection module 3, the reset end of the second frequency divider 32 is used as the second reset end of the undervoltage frequency selection module 3, the output end of the second frequency divider 32 is used as the second output end of the undervoltage frequency selection module 3, and the selection end of the first frequency divider 31 or the second frequency divider 32 is used as the selection end of the undervoltage frequency selection module 3;

[0110] The first frequency divider 31 and the second frequency divider 32 are both used to receive the clock signal and the power supply voltage, determine the stage of the undervoltage value, and correspondingly reduce the frequency of the clock signal to generate a filtered clock signal;

[0111] The first frequency divider 31 generates the filtered clock signal earlier than the second frequency divider 32 .

[0112] In this embodiment, the undervoltage frequency selection module 3 implements the function of phased frequency reduction of the clock signal according to different undervoltage values ​​by the first frequency divider 31 and the second frequency divider 32. The filtered clock signal actually includes the filtered clock signal output by the first frequency divider 31 and the filtered clock signal output by the second frequency divider 32. The undervoltage protection trigger module 4 first receives the filtered clock signal output by the first frequency divider 31. After the filtering trigger moment is reached, the undervoltage protection trigger module 4 resets the second frequency divider 32 so that the second frequency divider 32 outputs the filtered clock signal. At this time, the undervoltage protection trigger module 4 will start filtering from the filtering trigger moment and generate an undervoltage protection action signal to trigger undervoltage protection, thereby meeting the logic design requirements of the undervoltage protection trigger module 4.

[0113] Furthermore, the first frequency divider 31 and the second frequency divider 32 have the same circuit structure;

[0114] The first frequency divider 31 includes a selection unit 33 and n D flip-flops D3; the input terminal and output terminal of the selection unit 33 are respectively used as the selection terminal and output terminal of the first frequency divider 31, and the clock terminal and reset terminal of the first D flip-flop D3 are respectively used as the clock terminal and reset terminal of the first frequency divider 31;

[0115] The Q terminal of the preceding D flip-flop D3 is electrically connected to the clock terminal of the succeeding D flip-flop D3, the reset terminals of all the D flip-flops D3 are electrically connected in common, the D terminal and the / Q terminal of each D flip-flop D3 are electrically connected, and the Q terminals of the first to nth D flip-flops D3 are electrically connected to the first selection terminal to the nth selection terminal of the selection unit 33, respectively;

[0116] The selection unit 33 is used to receive the power supply voltage to determine the stage of the undervoltage value; when the undervoltage value is in any stage from the first to the nth stage, the corresponding selection end from the first selection end to the nth selection end of the selection unit 33 is connected to the output end of the selection unit 33.

[0117] In this embodiment, the undervoltage frequency selection module 3 is as follows: Figure 9 As shown, taking four D flip-flops D3 as an example, the first frequency divider 31 and the second frequency divider 32 implement the same principle of reducing the frequency of the clock signal according to different undervoltage values. The circuit is composed of multiple D flip-flops D3. After the clock signal is input, the output frequency will be reduced by half every time it passes through a D flip-flop D3. Therefore, by setting a selection unit 33 (for example, composed of a switch circuit and an MCU), the undervoltage value stage is determined, and then the corresponding selection terminals (Q1 to Qn) and the output terminal of the selection unit 33 are turned on, so that the frequency of the filtered clock signal finally output by the undervoltage frequency selection module 3 satisfies F2=F1*( ), to achieve frequency reduction based on undervoltage value.

[0118] Furthermore, the undervoltage protection trigger module 4 includes a D flip-flop D1, a D flip-flop D2, an RS flip-flop RS2, a NOT gate U2, a NOT gate U4, a NAND gate U3, a NAND gate U5, a NAND gate U7, and an AND gate U6; the clock terminal and the reset terminal of the D flip-flop D1 are respectively used as the first input terminal and the first reset terminal of the undervoltage protection trigger module 4, the clock terminal of the D flip-flop D2 is used as the second input terminal of the undervoltage protection trigger module 4, the output terminal of the AND gate U6 is used as the second reset terminal of the undervoltage protection trigger module 4, and the Q terminal of the RS flip-flop RS2 is used as the output terminal of the undervoltage protection trigger module 4;

[0119] The / Q terminal of D flip-flop D1 is electrically connected to the first input terminal of NAND gate U3, the reset terminal of D flip-flop D1, the input terminal of NAND gate U2, and the first input terminal of NAND gate U5 are all electrically connected to the first input terminal of NAND gate U7, the output terminal of NAND gate U2 is electrically connected to the second input terminal of NAND gate U3, the / Q terminal of D flip-flop D2 is electrically connected to the third input terminal of NAND gate U5, the reset terminal of D flip-flop D2, the second input terminal of NAND gate U7, and the input terminal of NAND gate U4 are all electrically connected to the Q terminal of RS flip-flop RS2, the second input terminal of NAND gate U5 and the output terminal of NAND gate U4 are electrically connected, the output terminal of NAND gate U3 is electrically connected to the S terminal of RS flip-flop RS2, the output terminal of NAND gate U5 is electrically connected to the first input terminal of AND gate U6, the output terminal of NAND gate U7 is electrically connected to the second input terminal of AND gate U6, the output terminal of AND gate U6 is electrically connected to the R terminal of RS flip-flop RS2, and the D terminal of D flip-flop D1 and the D terminal of D flip-flop D2 are both connected to the VCC power supply.

[0120] In this embodiment, when an undervoltage fault occurs, only the D flip-flop D1 is released and reset by the undervoltage fault judgment module 1 ( Figure 7 Point A is high), which can be triggered by the filtered clock signal. After passing through the logic network composed of logic components, the RS trigger RS2 is triggered. If the D trigger D1 has not triggered the RS trigger RS2, the undervoltage fault will disappear, the filtered clock signal will disappear, the D trigger D1 will be reset, and the RS trigger RS2 will not be triggered. Figure 7 Points E and F remain unchanged (low level off), so this process is the case where the duration of the filter clock signal is less than the filter triggering moment.

[0121] When the duration of the filter clock signal is greater than or equal to the filter triggering moment, the D flip-flop D1 is released and reset by the undervoltage fault judgment module 1 ( Figure 7 A point high level), can be triggered by the filtered clock signal, D flip-flop D1 continues to output the signal, after a few cycles of rising edge, it is still in undervoltage fault, then Figure 7 The high level at point D in the circuit will trigger the RS trigger RS2. Figure 7 Point F in is at a high level, thereby triggering the D flip-flop D2 as well, so that the D flip-flops D1 and D flip-flops D2 remain in the triggered state, causing the RS flip-flop RS2 to remain triggered and send out an undervoltage protection action signal.

[0122] In summary, the triggering of the RS trigger RS2 is used as the filtering triggering moment, and the trigger signal of the RS trigger RS2 is used as the undervoltage protection action signal without any glitch noise, thus achieving the filtering purpose; more importantly, the undervoltage value and the filtering time (undervoltage protection effective time) are in a proportional relationship. The larger the undervoltage value, the higher the frequency of the filtering signal, and the faster the filtering triggering moment is reached, and the filtering output undervoltage protection action signal is output.

[0123] Example 3

[0124] A high-voltage integrated circuit includes the above-mentioned undervoltage protection circuit, a fault logic control circuit 5, and multiple fault detection circuits 6; the input end of the undervoltage protection circuit serves as the VCC terminal of the high-voltage integrated circuit, and the output end of the undervoltage protection circuit and the output ends of the multiple fault detection circuits 6 are respectively electrically connected to the input end of the fault logic control circuit 5;

[0125] The fault logic control circuit 5 is used to shut down the high-voltage integrated circuit when the undervoltage protection circuit or any one of the multiple fault detection circuits 6 feeds back a valid signal.

[0126] In this embodiment, a preferred embodiment of a high voltage integrated circuit is also proposed, such as Figure 10 As shown, the above-mentioned undervoltage protection circuit can be conveniently integrated into a high-voltage integrated circuit to realize undervoltage protection of the high-voltage integrated circuit, so that the high-voltage integrated circuit can filter out glitch noise in the internal environment of multi-circuit integration, avoid frequent false triggering of undervoltage protection, and improve the stability and accuracy of the undervoltage protection of the high-voltage integrated circuit.

[0127] Other structures and operations of a relaxation oscillator, an undervoltage protection circuit, and a high-voltage integrated circuit according to the embodiments of the present invention are well known to those skilled in the art and will not be described in detail here.

[0128] Throughout this specification, reference to terms such as "embodiment" or "example" indicates that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0129] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

Claims

1. A relaxation oscillator, characterized in that: The relaxation oscillator comprises an RS trigger RS3, a comparator CMP1, a comparator CMP2, a first charge-discharge circuit, and a second charge-discharge circuit; the Q1 terminal of the RS trigger RS3 is used as the input terminal of the relaxation oscillator, the / Q1 terminal of the RS trigger RS3 is used as the output terminal of the relaxation oscillator, the power supply terminal of the first charge-discharge circuit is used as the first current source terminal of the relaxation oscillator, and the power supply terminal of the second charge-discharge circuit is used as the second current source terminal of the relaxation oscillator; The Q1 terminal and / Q1 terminal of the RS trigger RS3 are electrically connected to the input terminal of the first charge and discharge circuit and the input terminal of the second charge and discharge circuit, respectively; the S terminal and R terminal of the RS trigger RS3 are electrically connected to the output terminal of the comparator CMP1 and the output terminal of the comparator CMP2, respectively; the positive input terminal of the comparator CMP1 and the positive input terminal of the comparator CMP2 are electrically connected to the output terminal of the first charge and discharge circuit and the output terminal of the second charge and discharge circuit, respectively; the negative input terminal of the comparator CMP1 and the negative input terminal of the comparator CMP2 are both connected to the VH voltage; When the RS trigger RS3 is triggered, the first charge and discharge circuit enters the first pre-charge region, and the second charge and discharge circuit enters the second effective charge region; when the first charge and discharge circuit enters the first transition charge region, the second charge and discharge circuit enters the second discharge region; when the first charge and discharge circuit enters the first effective charge region, the second charge and discharge circuit enters the second pre-charge region; when the first charge and discharge circuit enters the first discharge region, the second charge and discharge circuit enters the second transition charge region; The first charge and discharge circuit sequentially enters the first pre-charge region, the first transition charge region, the first effective charge region and the first discharge region to cycle; The second charge and discharge circuit sequentially enters the second pre-charge region, the second transition charge region, the second effective charge region and the second discharge region for cyclic operation.

2. A relaxation oscillator according to claim 1, characterized in that: The first charge and discharge circuit includes an RS trigger RS4, a comparator CMP3, a comparator CMP4, an OR gate OR1, a PNP MOS transistor S1, a PNP MOS transistor S3, an NPN MOS transistor S5, a capacitor C1, a NOT gate U21, a NOT gate U22, a NOT gate U23, and an AND gate U24; the second input end of the OR gate OR1 serves as an input end of the first charge and discharge circuit, the source of the PNP MOS transistor S3 serves as a power supply end of the first charge and discharge circuit, and the drain of the PNP MOS transistor S3 serves as an output end of the first charge and discharge circuit; The first input terminal of the OR gate OR1 is electrically connected to the / Q2 terminal of the RS trigger RS4, the Q2 terminal of the RS trigger RS4 is electrically connected to the gate of the PNP MOS transistor S1, the S terminal and the R terminal of the RS trigger RS4 are electrically connected to the output terminal of the comparator CMP3 and the output terminal of the comparator CMP4, respectively, the negative input terminal of the comparator CMP3 is connected to the VL voltage, the positive input terminal of the comparator CMP4 is connected to the VM voltage, the positive input terminal of the comparator CMP3, the negative input terminal of the comparator CMP4, the drain of the PNP MOS transistor S1, the drain of the PNP MOS transistor S3, and the drain of the NPN MOS transistor S5 are all electrically connected to one end of the capacitor C1, and the OR gate OR1 is electrically connected to the / Q2 terminal of the RS trigger RS4. The output end of the gate OR1 is electrically connected to the gate of the PNP MOS transistor S3, the source of the PNP MOS transistor S1 is electrically connected to the source of the PNP MOS transistor S3, the second input end of the OR gate OR1 and the input end of the NOT gate U21 are both electrically connected to the first input end of the AND gate U24, the output end of the NOT gate U21 is electrically connected to the input end of the NOT gate U22, the output end of the NOT gate U22 is electrically connected to the input end of the NOT gate U23, the output end of the NOT gate U23 is electrically connected to the second input end of the AND gate U24, the output end of the AND gate U24 is electrically connected to the gate of the NPN MOS transistor S5, and the source of the NPN MOS transistor S5 and the other end of the capacitor C1 are both grounded.

3. A relaxation oscillator according to claim 2, characterized in that: The first charge and discharge circuit and the second charge and discharge circuit have the same circuit structure.

4. A relaxation oscillator according to claim 3, characterized in that: The magnitude relationship among the VH voltage, the VL voltage, and the VM voltage is VM<VL<VH.

5. An undervoltage protection circuit, characterized in that: It includes an undervoltage fault judgment module, an undervoltage time adaptation module, an undervoltage frequency selection module and an undervoltage protection trigger module; the undervoltage time adaptation module includes an RS trigger RS1, an oscillation current source, a relaxation oscillator and a startup circuit; the relaxation oscillator is the relaxation oscillator according to any one of claims 1 to 4; The input end of the undervoltage fault judgment module is connected to the VCC power supply, the output end of the undervoltage fault judgment module, the first reset end of the undervoltage frequency selection module, and the first reset end of the undervoltage protection trigger module are all electrically connected to the input end of the undervoltage time adaptation module, the first input end and the second input end of the undervoltage frequency selection module are both electrically connected to the output end of the undervoltage time adaptation module, the selection end of the undervoltage frequency selection module is connected to the VCC power supply, the first output end and the second output end of the undervoltage frequency selection module are respectively electrically connected to the first input end and the second input end of the undervoltage protection trigger module, the second reset end of the undervoltage frequency selection module is electrically connected to the output end of the undervoltage protection trigger module, the second reset end of the undervoltage protection trigger module is electrically connected to the reset end of the undervoltage time adaptation module, and the output end of the undervoltage protection trigger module is connected to a subsequent undervoltage protection action circuit; The undervoltage fault judgment module is used to compare the external power supply voltage with the undervoltage threshold, and generate an undervoltage fault signal when the power supply voltage is lower than the undervoltage threshold; The undervoltage time adaptation module is used to receive the undervoltage fault signal and generate a clock signal according to the duration of the undervoltage fault signal; The undervoltage frequency selection module is used to receive the clock signal and the power supply voltage, reduce the frequency of the clock signal in stages according to the undervoltage value of the power supply voltage, and generate a filtered clock signal; the undervoltage value is proportional to the frequency of the filtered clock signal; The undervoltage protection trigger module is configured to not operate when the duration of the received filtering clock signal is less than the filtering triggering moment; and to start filtering from the filtering triggering moment and generate an undervoltage protection action signal when the duration of the received filtering clock signal is greater than or equal to the filtering triggering moment; The S terminal of the RS trigger RS1 is used as the input terminal of the brown-out time adaptation module, the R terminal of the RS trigger RS1 is used as the reset terminal of the brown-out time adaptation module, and the output terminal of the relaxation oscillator is used as the output terminal of the brown-out time adaptation module; The Q terminal of the RS trigger RS1 is electrically connected to the input terminal of the startup circuit, the output terminal of the startup circuit is electrically connected to the input terminal of the relaxation oscillator, and the first output terminal and the second output terminal of the oscillation current source are electrically connected to the first current source terminal and the second current source terminal of the relaxation oscillator respectively; The waveform of the oscillating current source is opposite to the waveform of the power supply voltage; The RS trigger RS1 is used to start the startup circuit when receiving the undervoltage fault signal; When the startup circuit is turned on, the startup circuit drives the relaxation oscillator to generate the clock signal.

6. The undervoltage protection circuit according to claim 5, characterized in that: The frequency of the clock signal is F1, the frequency of the filtered clock signal is F2, and the undervoltage value is divided into n stages from large to small; The relationship between the frequency F1 of the clock signal and the frequency F2 of the filtered clock signal is F2=F1*( ), where N is any value from 1 to n.

7. The undervoltage protection circuit according to claim 5, characterized in that: The undervoltage frequency selection module includes a first frequency divider and a second frequency divider; the clock end of the first frequency divider is used as the first input end of the undervoltage frequency selection module, the reset end of the first frequency divider is used as the first reset end of the undervoltage frequency selection module, the output end of the first frequency divider is used as the first output end of the undervoltage frequency selection module, the clock end of the second frequency divider is used as the second input end of the undervoltage frequency selection module, the reset end of the second frequency divider is used as the second reset end of the undervoltage frequency selection module, the output end of the second frequency divider is used as the second output end of the undervoltage frequency selection module, and the selection end of the first frequency divider or the second frequency divider is used as the selection end of the undervoltage frequency selection module; The first frequency divider and the second frequency divider are both used to receive the clock signal and the power supply voltage, determine the stage of the undervoltage value, and correspondingly reduce the frequency of the clock signal to generate the filtered clock signal; The first frequency divider generates the filtered clock signal earlier than the second frequency divider.

8. The undervoltage protection circuit according to claim 7, characterized in that: The first frequency divider and the second frequency divider have the same circuit structure; The first frequency divider includes a selection unit and n D flip-flops D3; the input end and the output end of the selection unit are respectively used as the selection end and the output end of the first frequency divider, and the clock end and the reset end of the first D flip-flop D3 are respectively used as the clock end and the reset end of the first frequency divider; The Q terminal of the preceding D flip-flop D3 is electrically connected to the clock terminal of the succeeding D flip-flop D3, the reset terminals of all the D flip-flops D3 are electrically connected in common, the D terminal and the / Q terminal of each D flip-flop D3 are electrically connected, and the Q terminals of the first to nth D flip-flops D3 are electrically connected to the first to nth selection terminals of the selection unit, respectively; The selection unit is used to receive the power supply voltage and determine the stage of the undervoltage value; When the undervoltage value is in any stage from the first to the nth stage, the corresponding selection end from the first selection end to the nth selection end of the selection unit is conductively connected to the output end of the selection unit.

9. The undervoltage protection circuit according to claim 5, characterized in that: The undervoltage protection trigger module includes a D flip-flop D1, a D flip-flop D2, an RS flip-flop RS2, a NOT gate U2, a NOT gate U4, a NAND gate U3, a NAND gate U5, a NAND gate U7 and an AND gate U6; the clock terminal and the reset terminal of the D flip-flop D1 are respectively used as the first input terminal and the first reset terminal of the undervoltage protection trigger module, the clock terminal of the D flip-flop D2 is used as the second input terminal of the undervoltage protection trigger module, the output terminal of the AND gate U6 is used as the second reset terminal of the undervoltage protection trigger module, and the Q terminal of the RS flip-flop RS2 is used as the output terminal of the undervoltage protection trigger module; The / Q terminal of the D flip-flop D1 is electrically connected to the first input terminal of the NAND gate U3, the reset terminal of the D flip-flop D1, the input terminal of the NAND gate U2, and the first input terminal of the NAND gate U5 are all electrically connected to the first input terminal of the NAND gate U7, the output terminal of the NAND gate U2 is electrically connected to the second input terminal of the NAND gate U3, the / Q terminal of the D flip-flop D2 is electrically connected to the third input terminal of the NAND gate U5, the reset terminal of the D flip-flop D2, the second input terminal of the NAND gate U7, and the input terminal of the NAND gate U4 are all electrically connected to the R The Q end of the S trigger RS2 is electrically connected, the second input end of the NAND gate U5 is electrically connected to the output end of the NAND gate U4, the output end of the NAND gate U3 is electrically connected to the S end of the RS trigger RS2, the output end of the NAND gate U5 is electrically connected to the first input end of the AND gate U6, the output end of the NAND gate U7 is electrically connected to the second input end of the AND gate U6, the output end of the AND gate U6 is electrically connected to the R end of the RS trigger RS2, and the D end of the D trigger D1 and the D end of the D trigger D2 are both connected to the VCC power supply.

10. A high-voltage integrated circuit, characterized in that: The device comprises an undervoltage protection circuit, a fault logic control circuit, and a plurality of fault detection circuits according to any one of claims 5 to 9; the input terminal of the undervoltage protection circuit serves as the VCC terminal of the high-voltage integrated circuit, and the output terminal of the undervoltage protection circuit and the output terminals of the plurality of fault detection circuits are electrically connected to the input terminal of the fault logic control circuit respectively; The fault logic control circuit is used to shut down the high-voltage integrated circuit when the undervoltage protection circuit or any one of the multiple fault detection circuits feeds back a valid signal.

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