Multi-cycle accumulated dual-granularity collaborative quantizer circuit

Abstract

The invention discloses a multi-cycle accumulation dual-granularity collaborative quantizer circuit, belongs to the field of integrated circuits, and is used for high-energy-efficiency quantization circuit design. The circuit is composed of an accumulated voltage temporary storage circuit, a coarse-grained quantization circuit, a fine-grained quantization circuit and a post-processing unit circuit, analog calculation results are input into the accumulated voltage temporary storage circuit, coarse-grained quantization is carried out by the coarse-grained quantization circuit in a plurality of cycles, and fine-grained quantization is carried out by the fine-grained quantization circuit in a plurality of cycles. After multi-cycle calculation is completed, the fine granularity quantization circuit quantizes the residual accumulated voltage, and coarse and fine granularity results are added proportionally in the post-processing circuit to obtain a final quantization result. Compared with a traditional single-cycle quantizer, the circuit adopts a multi-cycle quantization design, the problem of single-cycle quantization truncation error accumulation is avoided, the quantization precision is improved, and meanwhile, the power consumption of the quantization circuit is remarkably reduced and the energy efficiency of the circuit is improved on the premise of ensuring the precision by utilizing a dual-granularity collaborative quantization design.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a multi-cycle accumulated dual-granularity cooperative quantizer circuit. Background Art

[0002] The massive data processing brought about by the rapid development of artificial intelligence (AI) today has caused the traditional von Neumann architecture to gradually face the problems of "power wall" and "storage wall". The high power consumption and bandwidth limitation caused by the frequent movement of data between the processor and storage urgently require a new computing volume architecture, and the computing-in-memory (CIM) technology came into being. In addition to the basic storage and read-write access functions of the memory, the computing-in-memory also puts the multiply and accumulate (MAC) operation into the storage array, effectively reducing the repeated movement of data between the processor and storage, saving a lot of energy, and greatly improving computing energy efficiency. According to the calculation method, the computing-in-memory can be divided into analog domain, digital domain, hybrid domain, and time domain computing.

[0003] In both the mixed domain and analog domain CIM, the multiplication and accumulation operations need to be converted into analog calculations, and the input data and storage data are represented by analog quantities such as voltage, current or charge, and finally the calculated analog results are quantized into digital quantities for subsequent processing in the digital domain. With the high-precision requirements for in-memory calculations, the signal margin of analog signals is further reduced due to the operating voltage limit of the circuit, which further increases the accuracy requirements for analog-to-digital converters (ADCs). However, high-precision ADCs usually consume more energy and bring greater delays, which becomes a major limitation in low-power scenarios.

[0004] The traditional analog quantization scheme converts the analog result into digital quantity through ADC in each cycle, and then accumulates the result of each cycle through digital circuit. This method is not friendly to cycles with small computational complexity, and increases the number of quantization times, resulting in higher power consumption and additional storage overhead of the partial sum accumulator (PSUM). At the same time, due to the inherent conversion error introduced by the ADC, a large number of quantization times causes the error of PSUM to accumulate gradually, resulting in the deviation of the final result. In order to meet the requirements of energy-efficient in-memory computing analog quantization, a new ADC design is needed to solve the problem of single-cycle analog quantization. Summary of the invention

[0005] The present invention provides a multi-cycle accumulation dual-granularity cooperative quantizer (DGCQ) circuit, which realizes multi-cycle accumulation quantization of analog quantities, reduces the number of analog quantization times, reduces the inherent conversion error accumulation of ADC, reduces the power consumption of the quantization circuit while ensuring the calculation accuracy of the analog quantization, and improves the overall energy efficiency.

[0006] The embodiment of the present invention provides a multi-cycle accumulated dual-granularity cooperative quantizer circuit, including: an accumulated voltage temporary storage circuit, a coarse-grained quantizer, a fine-grained quantizer, and a post-processing unit circuit;

[0007] The accumulated voltage temporary storage circuit is composed of a control logic unit, four identical capacitors and four groups of corresponding switches, and is used to accumulate voltages of different periods, and output the accumulated voltage to the coarse-grained quantizer and the fine-grained quantizer according to the control logic;

[0008] The coarse-grained quantizer is composed of a comparator circuit, a 4-bit counter circuit and a voltage subtraction circuit, and is used to perform coarse-grained quantization according to the accumulated voltage of the accumulated voltage temporary storage circuit to obtain a coarse-grained quantization result;

[0009] The fine-grained quantizer is an 8-bit successive approximation register type analog-to-digital converter, which is used to perform fine-grained quantization according to the residual accumulated voltage of the accumulated voltage temporary storage circuit to obtain a fine-grained quantization result;

[0010] The post-processing unit circuit is used to receive the coarse-grained quantization result of the coarse-grained quantizer and the fine-grained quantization result of the fine-grained quantizer, and quantize the coarse-grained quantization result and the coarse-grained quantization result to obtain a simulated quantization result.

[0011] Optionally, in one embodiment of the present invention, when the accumulated voltage storage circuit is working, the voltages of different periods are accumulated in four capacitors C1 of the same capacitance size in the accumulated voltage storage circuit through the control logic unit, the four capacitors are composed of four branches in parallel, each branch is composed of a capacitor and a MOS tube for capacitor discharge, four groups of switches SW0 and switches SW1 respectively control the voltage input and voltage output of the capacitors in the corresponding branches, and only one of the four branches can be input at the same time, wherein the voltage input comes from the calculated voltage of different periods, and when the voltage Vs of the new period is ready, it will be transferred to the accumulated voltage storage circuit and share charge with the old accumulated voltage Vacc, and the voltage Vs of the new period will be stored in the capacitor C1 of the same capacitance size, and the voltage output will be output to the subsequent circuit for quantized output according to the control logic.

[0012] Optionally, in one embodiment of the present invention, when the coarse-grained quantizer is working, the switch SW2 in the voltage subtraction circuit is turned on to input the new accumulated voltage Vacc into the voltage subtraction circuit, and the new accumulated voltage Vacc is compared with Vcm through a comparator circuit to determine the behavior of the counter and the voltage subtraction circuit, where Vcm is 1 / 4 of the power supply voltage Vdd; if the new accumulated voltage Vacc is not greater than Vcm, the output voltage Vota=2×Vacc is realized through the voltage subtraction circuit, and Vacc is updated to Vota; if Vacc is greater than Vcm, the counter clock obtains a rising edge, the counter value is increased by one, and Vota=2×Vacc-Vref is realized through the voltage subtraction circuit, where Vref=1 / 2Vdd, and Vacc is updated to Vota; this is repeated multiple times in multiple cycles until it is determined that the multi-cycle calculation is completed.

[0013] Optionally, in one embodiment of the present invention, the fine-grained quantization circuit is started once after the coarse-grained quantization stage is completed, and there is still a residual charge value in the capacitor in the voltage storage circuit, represented by Vacc. After multiple cycles of calculation are completed, the fine-grained quantization stage is entered, and the remaining Vacc is sent to an 8-bit successive approximation register-type analog-to-digital converter to realize fine-grained quantization of the residual charge.

[0014] Optionally, in one embodiment of the present invention, after both the coarse-grained quantization and the fine-grained quantization are completed, the coarse-grained and fine-grained results are passed to the post-processing unit, and the post-processing unit adds the coarse-grained quantization result Qcg[3:0] and the fine-grained quantization result Qfg[7:0] generated by the counter in proportion to obtain the final analog quantization result.

[0015] The multi-cycle accumulation dual-granularity collaborative quantizer circuit of the embodiment of the present invention realizes the quantization of the multi-cycle accumulation result of the analog quantity in the analog domain or the hybrid domain, reduces the activation times of the ADC, and reduces the inherent conversion error accumulation of the ADC. At the same time, the dual-granularity collaboration of coarse-grained quantization and fine-grained quantization is utilized to significantly reduce the power consumption of the quantization circuit while ensuring the accuracy requirement, thereby improving the circuit energy efficiency.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram of a dual-granularity cooperative quantizer circuit with multi-cycle accumulation according to an embodiment of the present invention;

[0019] Figure 2 The diagram is a schematic diagram of the working process and working waveform of the multi-cycle accumulation analog storage quantizer circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0021] Figure 1 The present invention is a schematic diagram of a dual-granularity cooperative quantizer circuit with multi-cycle accumulation according to an embodiment of the present invention.

[0022] like Figure 1 As shown, the multi-cycle accumulation dual-granularity collaborative quantizer circuit includes four parts: an accumulated voltage (Vacc) temporary storage circuit, a coarse-grained quantizer (CGQ), a fine-grained quantizer (FGQ) and a post-processing unit (PPU).

[0023] The accumulated voltage temporary storage circuit is composed of a control logic unit, four identical capacitors and four groups of corresponding switches, which is used to accumulate voltages of different periods and output the accumulated voltage to the coarse-grained quantizer and the fine-grained quantizer according to the control logic.

[0024] The coarse-grained quantizer is composed of a comparator circuit (Comparator), a 4-bit counter circuit (Counter) and a voltage subtraction circuit (VSC), and is used to perform coarse-grained quantization according to the accumulated voltage of the accumulated voltage temporary storage circuit to obtain a coarse-grained quantization result.

[0025] The fine-grained quantizer is an 8-bit successive approximation register analog-to-digital converter (SAR ADC), which is used for performing fine-grained quantization according to the residual accumulated voltage of the accumulated voltage temporary storage circuit to obtain a fine-grained quantization result.

[0026] The post-processing unit circuit is used to receive the coarse-grained quantization result of the coarse-grained quantizer and the fine-grained quantization result of the fine-grained quantizer, and quantize the coarse-grained quantization result and the coarse-grained quantization result to obtain a simulated quantization result.

[0027] The output end of the accumulated voltage temporary storage circuit is connected to the non-inverting input end of the amplifier in the voltage subtraction circuit, and the inverting input end is connected to the reference voltage V through a resistor. ref connected, and connected to the output of the operational amplifier through a resistor to form a feedback loop; at the same time, the output of the accumulated voltage temporary storage circuit is also connected to the non-inverting input of the amplifier in the comparator, and the inverting input is connected to the comparison voltage V cm The output end controls the reference voltage input and is connected to the clock end of the first D flip-flop in the counter to realize the counting operation; the output end of the accumulated voltage temporary storage circuit is also connected to the successive approximation register type analog-to-digital converter for fine-grained quantization.

[0028] In one embodiment of the present invention, when the accumulated voltage temporary storage circuit is working, the voltages of different periods are accumulated in four capacitors C1 of the same capacitance size in the circuit through the control logic unit. The four capacitors are composed of four branches in parallel, each branch is composed of a capacitor and a MOS tube for capacitor discharge, and four groups of switches SW0 and switch SW1 respectively control the voltage input and voltage output of the capacitors in the corresponding branches. Only one of the four branches can be input at the same time, and the voltage input comes from the calculated voltage of different periods. When the voltage Vs of the new period is ready, it will be transferred to the voltage temporary storage circuit and share the charge with the old accumulated voltage Vacc. The voltage Vs of the new period is stored in C1 of the same capacitance size, and the voltage output is output to the subsequent circuit according to the control logic for quantized output.

[0029] like Figure 2 As shown, the workflow of the dual-granularity collaborative quantizer circuit DGCQ is mainly divided into two parts: a coarse-grained quantization stage and a fine-grained quantization stage.

[0030] In one embodiment of the present invention, when the coarse-grained quantizer is working, SW2 is turned on to input the new Vacc into the voltage subtraction circuit, and the new Vacc is compared with Vcm (1 / 4 of the power supply voltage Vdd) through the comparator circuit to determine the behavior of the counter and the voltage subtraction circuit. If Vacc is not greater than Vcm, the output voltage Vota=2×Vacc is realized through the voltage subtraction circuit, and Vacc is updated to Vota; if Vacc is greater than Vcm, the counter clock obtains a rising edge to realize the counter value plus one, and Vota=2×Vacc-Vref is realized through the voltage subtraction circuit, where Vref=1 / 2Vdd, and Vacc is updated to Vota; the above process is repeated multiple times in multiple cycles until it is determined that the multi-cycle calculation is completed.

[0031] In one embodiment of the present invention, the fine-grained quantization circuit is started once after the coarse-grained quantization stage is completed. There is still a residual charge value in the capacitor in the accumulated voltage temporary storage circuit, represented by Vacc. After the multi-cycle calculation is completed, the fine-grained quantization stage is entered, and the remaining Vacc is sent to the 8-bit successive approximation register type analog-to-digital converter to realize the fine-grained quantization of the residual charge.

[0032] In one embodiment of the present invention, after both the coarse-grained quantization and the fine-grained quantization are completed, the coarse-grained and fine-grained results are transmitted to a post-processing unit, which processes the coarse-grained quantization result Q generated by the counter. cg [3:0] and fine-grained quantization result Q fg [7:0] are added in proportion (224:1) to obtain the final analog quantization result.

[0033] The multi-cycle accumulation dual-granularity collaborative quantizer circuit proposed in the embodiment of the present invention reduces the activation times of the ADC and reduces the inherent conversion error accumulation of the ADC by realizing the quantization of the multi-cycle accumulation results of the analog quantity in the analog domain or the hybrid domain. At the same time, a new type of coarse-grained quantization circuit is proposed, which utilizes the dual-granularity collaboration of coarse-grained quantization and fine-grained quantization to significantly reduce the power consumption of the quantization circuit while ensuring the accuracy requirement and improve the circuit energy efficiency.

[0034] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A multi-cycle accumulation dual-granularity cooperative quantizer circuit, characterized in that: include: Accumulated voltage temporary storage circuit, coarse-grained quantizer, fine-grained quantizer and post-processing unit circuit; The accumulated voltage temporary storage circuit is composed of a control logic unit, four identical capacitors and four groups of corresponding switches, and is used to accumulate voltages of different periods, and output the accumulated voltage to the coarse-grained quantizer and the fine-grained quantizer according to the control logic; The coarse-grained quantizer is composed of a comparator circuit, a 4-bit counter circuit and a voltage subtraction circuit, and is used to perform coarse-grained quantization according to the accumulated voltage of the accumulated voltage temporary storage circuit to obtain a coarse-grained quantization result; The fine-grained quantizer is an 8-bit successive approximation register type analog-to-digital converter, which is used to perform fine-grained quantization according to the residual accumulated voltage of the accumulated voltage temporary storage circuit to obtain a fine-grained quantization result; The post-processing unit circuit is used to receive the coarse-grained quantization result of the coarse-grained quantizer and the fine-grained quantization result of the fine-grained quantizer, and quantize the coarse-grained quantization result and the coarse-grained quantization result to obtain a simulated quantization result.

2. The multi-cycle accumulation dual-granularity cooperative quantizer circuit according to claim 1, characterized in that: When the accumulated voltage temporary storage circuit is working, the voltages of different periods are accumulated in four capacitors C1 of the same capacitance size in the accumulated voltage temporary storage circuit through the control logic unit. The four capacitors are composed of four branches in parallel, and each branch is composed of a capacitor and a MOS tube for capacitor discharge. Four groups of switches SW0 and switches SW1 respectively control the voltage input and voltage output of the capacitors in the corresponding branches. Only one of the four branches can be input at the same time, wherein the voltage input comes from the calculated voltage of different periods. When the voltage Vs of the new period is ready, it will be transferred to the accumulated voltage temporary storage circuit and share the charge with the old accumulated voltage Vacc. The voltage Vs of the new period is stored in the capacitor C1 of the same capacitance size, and the voltage output is output to the subsequent circuit according to the control logic for quantized output.

3. The multi-cycle accumulation dual-granularity cooperative quantizer circuit according to claim 2, characterized in that: When the coarse-grained quantizer is working, the switch SW2 in the voltage subtraction circuit is turned on to input the new accumulated voltage Vacc into the voltage subtraction circuit, and the new accumulated voltage Vacc is compared with Vcm through the comparator circuit to determine the behavior of the counter and the voltage subtraction circuit, and Vcm is 1 / 4 of the power supply voltage Vdd; if the new accumulated voltage Vacc is not greater than Vcm, the output voltage Vota=2×Vacc is realized through the voltage subtraction circuit, and Vacc is updated to Vota; if Vacc is greater than Vcm, the counter clock obtains a rising edge to realize the counter value plus one, and Vota=2×Vacc-Vref is realized through the voltage subtraction circuit, where Vref=1 / 2Vdd, and Vacc is updated to Vota; this is repeated multiple times in multiple cycles until it is determined that the multi-cycle calculation is completed.

4. The multi-cycle accumulation dual-granularity cooperative quantizer circuit according to claim 2, characterized in that: The fine-grained quantization circuit is started once after the coarse-grained quantization stage is completed. There is still a residual charge value in the capacitor in the voltage storage circuit, represented by Vacc. After multiple cycles of calculation are completed, the fine-grained quantization stage is entered, and the remaining Vacc is sent to an 8-bit successive approximation register analog-to-digital converter to realize fine-grained quantization of the residual charge.

5. The multi-cycle accumulation dual-granularity cooperative quantizer circuit according to claim 1, characterized in that: After the coarse-grained quantization and the fine-grained quantization are completed, the coarse-grained and fine-grained results are passed to the post-processing unit, and the post-processing unit adds the coarse-grained quantization result Qcg[3:0] and the fine-grained quantization result Qfg[7:0] generated by the counter in proportion to obtain the final analog quantization result.

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