A method for stabilizing reference power supply fluctuations of successive approximation analog-to-digital converters

Abstract

The present invention discloses a method for stabilizing the fluctuation of the reference power supply of a successive approximation analog-to-digital converter, which is applied to a segmented successive approximation analog-to-digital converter; a linear charge compensation circuit is designed to improve the reference power supply circuit of the fine quantization ADC; the reference power supply circuit of the fine quantization ADC includes a buffer and a linear charge compensation circuit; the linear charge compensation circuit includes a binary capacitor array and a control circuit for providing compensation charge, which serves as an auxiliary power supply circuit to quickly stabilize the reference power supply fluctuation generated by the switching of the most significant bit of the fine quantization ADC before the least significant bit is compared, thereby improving the conversion accuracy of the fine quantization. The use of the present invention can not only reduce the influence of the reference power supply fluctuation on the conversion accuracy, but also help improve the conversion speed and conversion accuracy of the SAR ADC; at the same time, it greatly reduces the demand for high-power on-chip reference power supply drivers and large-area on-chip decoupling capacitors, thereby reducing the power consumption and area overhead of the SAR ADC.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design, relates to analog-to-digital converter integrated circuit design technology, and specifically relates to a method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter. Background Art

[0002] In recent years, the development of mobile communications, the Internet of Things and other application fields has brought new challenges to the design of analog-to-digital converters (ADCs), requiring them to achieve high speed and high precision while taking into account power consumption and chip area overhead. Among the many types of ADCs, the successive approximation register (SAR) ADC has shown strong advantages in low power consumption and area due to its highly digital characteristics. However, due to the principle of binary search of SAR ADC, a complete analog-to-digital conversion of an N-bit SAR ADC requires N conversion cycles, so it has been mainly used in medium-speed and medium-precision occasions.

[0003] With the evolution of technology, the intrinsic frequency of transistors under advanced technology continues to increase, the time for SAR ADC to complete a conversion is gradually shortened, and the operating frequency is gradually increased. Therefore, it is expected to bring its low power consumption characteristics into the field of high-speed applications, attracting more and more researchers to explore the design of high-speed SAR ADC. In the process of research, researchers found that a key challenge that limits SAR ADC to achieve both high speed and high precision is that the reference level fluctuation is difficult to stabilize. In SAR ADC, the reference power supply of the capacitor digital-to-analog converter (CDAC) needs to provide transient current during the switching process of the capacitor array, which will cause reference level fluctuation. In high-speed application scenarios, since the time of each SAR conversion is extremely short, the reference level fluctuation generated is difficult to be completely stabilized within a conversion cycle, which in turn affects the next SAR conversion result and significantly reduces the overall conversion accuracy. At the same time, since the capacitance of the capacitor array is limited by the sampling noise of the ADC and cannot be reduced proportionally with the evolution of the process, in the design of high-speed SAR ADC, the problem of the difficulty in stabilizing the reference level fluctuation of the capacitor DAC has become a difficult problem that researchers need to solve urgently.

[0004] The traditional method to solve the problem of reference level fluctuation of high-speed SAR ADC is to use on-chip buffer or add on-chip decoupling capacitor. Using on-chip buffer with strong driving capability can make the reference power supply quickly stabilize within a conversion cycle, but the on-chip buffer with strong driving capability is also accompanied by greater power consumption. The power consumption of the driver even exceeds the power consumption of the ADC itself, losing the low power consumption advantage of the SAR ADC itself. Adding on-chip decoupling capacitor can reduce the amplitude of fluctuation. Although this does not require a lot of power consumption, the fluctuation of the reference power supply is strongly related to the input signal. Therefore, a large-capacitance decoupling capacitor is required to ensure the constant reference level. The large-capacitance decoupling capacitor occupies a large chip area, losing the area advantage of the SAR ADC.

[0005] In summary, the existing solutions to the problem of unstable reference power supply in high-speed SAR ADC design have certain limitations. How to solve this problem while maintaining the advantages of SAR ADC such as small area and low power consumption still needs to be studied urgently. Summary of the invention

[0006] In view of the deficiencies in the above-mentioned prior art, the present invention provides a method for stabilizing the reference power supply fluctuation of a successive approximation analog-to-digital converter (SAR ADC), which is a SAR ADC reference power supply stabilization technology based on linear charge compensation, which helps stabilize the SAR ADC reference level fluctuation with low area and power consumption overhead and improves quantization accuracy.

[0007] For convenience, the present invention defines the following terms and their corresponding Chinese names:

[0008] Analog-to-digital converter (ADC); Successive approximation analog-to-digital converter (SAR ADC);

[0009] Detection Skip (DAS);

[0010] Capacitive digital-to-analog converter (CDAC);

[0011] MSB (MostSignificantBit, most significant bit);

[0012] LSB (Least Significant Bit).

[0013] The present invention first constructs a segmented SAR ADC, including a multi-bit SAR ADC1 (a first multi-bit SAR ADC or a coarse quantization ADC) and a multi-bit SAR ADC2 (a second multi-bit SAR ADC, a fine quantization ADC), a DAS logic circuit and a reference power supply circuit; the reference power supply circuit part includes a reference power supply circuit of a coarse quantization ADC and a reference power supply circuit of a fine quantization ADC; the reference power supply circuit of the coarse quantization ADC includes a buffer; a linear charge compensation circuit is designed to improve the reference power supply circuit of the fine quantization ADC; the reference power supply circuit of the fine quantization ADC includes a buffer and an auxiliary power supply circuit based on linear charge compensation (i.e., a linear charge compensation circuit); the linear charge compensation circuit includes a binary capacitor array and a control circuit for providing compensation charge, which is used to quickly stabilize the reference power supply fluctuation generated by the switching of the most significant bits MSBs of the fine quantization ADC before the comparison of the LSBs, thereby improving the conversion accuracy of the fine quantization. According to the capacitance value of CDAC in the fine quantization ADC, the size of the binary capacitor array in the auxiliary power supply circuit is designed, so that the auxiliary power supply circuit can provide the charge required for the switching of the previous CDAC at the junction of coarse quantization and fine quantization, so that the reference level fluctuation can be restored.

[0014] The present invention designs a linear charge compensation technology, which is applied to a segmented SAR ADC structure, locates the problem of unstable reference level to a certain bit in the SAR conversion process, and then combines the DAS algorithm and the linear charge compensation technology to solve the unstable reference power problem of the bit. Compared with other existing power stabilization technologies, the SAR ADC reference power stabilization solution provided by the present invention provides protection for the conversion of MSBs in the SAR conversion process with a very small area and power consumption, greatly reduces the influence of reference level fluctuation on the conversion accuracy of SAR ADC, can simultaneously improve the accuracy and conversion speed of SAR ADC, and reduce the system's demand for a strong driving capability reference power driver or a large area decoupling capacitor. The segmented SAR ADC performs two-step conversion when working. First, SAR ADC1 performs the first step of coarse quantization, and the result of the coarse quantization of SAR ADC1 is deployed to SAR ADC2 using a detection skip algorithm, and then SAR ADC2 performs the second step of fine quantization; when the first step is connected with the second step, the linear charge compensation circuit is triggered, so that the reference power fluctuation caused by the first step of conversion is stabilized before the second step of conversion.

[0015] The reference power supply fluctuation stabilization method is applied to the SAR ADC to stabilize the reference power supply fluctuation. When the SAR ADC is working, the following steps are included:

[0016] 1) SAR ADC1 and SAR ADC2 sample the input signal at the same time.

[0017] 2) After sampling is completed, in the conversion process, SAR ADC1 is first used for the first step of coarse quantization. When SAR ADC1 obtains the quantization result, the MSB capacitor switching of CDAC in SAR ADC2 is controlled based on the quantization result of SAR ADC1 and combined with the detection skip algorithm.

[0018] 3) Design a linear charge compensation circuit and improve the reference power supply circuit;

[0019] After the coarse quantization of SAR ADC1 in the segmented SAR ADC using the detection skip algorithm is completed, the charge amount provided by the reference power supply required for the MSB last bit switching of CDAC in SAR ADC2 under this structure is linearly correlated with the coarse quantization result of SAR ADC1. Therefore, the linear charge compensation circuit designed by the present invention is triggered to work, and the linear charge compensation circuit includes a binary capacitor array and a control circuit. When working, according to the coarse quantization result of SAR ADC1, the control circuit selects the capacitor in the binary capacitor array, switches the bottom plate of the selected capacitor from a low level to a high level, thereby quickly providing the charge amount required for the MSB last bit switching of CDAC in SAR ADC2, helping the reference power supply fluctuation generated by the MSB capacitor switching of CDAC in SAR ADC2 to stabilize before the LSB conversion of CDAC in SAR ADC2 starts, thereby improving the quantization accuracy.

[0020] 4) Continue the second step of fine quantization on the LSB capacitance of CDAC in SAR ADC2.

[0021] According to the above working process, the quantization of the entire SAR ADC includes coarse quantization performed on SAR ADC1 and fine quantization performed on the LSB of CDAC in SAR ADC2. Both steps of quantization switch small capacitance values, so the fluctuation of the reference power supply is small, and it can be ensured to be fast and stable by designing a low-cost reference power buffer. The switching of the MSB capacitance of CDAC in SAR ADC2 produces large reference power fluctuations, but after the MSB switching of CDAC in SAR ADC2 is completed, the linear charge compensation technology provided by the present invention helps the fluctuations generated to be quickly stabilized, so it will not affect the fine quantization accuracy performed on the LSB of CDAC in SAR ADC2, which is beneficial to improving the conversion accuracy and speed of SAR ADC. Compared with the existing reference power stabilization technology, the reference power stabilization technology provided by the present invention only requires a small area binary capacitor array for charge compensation and a low-power weak driving capability buffer, so it has lower area and power consumption overhead.

[0022] The segmented SAR ADC structure used in the method of the present invention includes a multi-bit coarse quantization ADC, a multi-bit fine quantization ADC, a DAS logic circuit and a reference power supply circuit. Among them, the multi-bit coarse quantization ADC includes four parts: a sampling circuit, a CDAC, a comparator and a digital logic; the multi-bit fine quantization ADC also includes four parts: a sampling circuit, a CDAC, a comparator and a digital logic. The number of CDAC bits in the fine quantization ADC is greater than the number of CDAC bits in the coarse quantization ADC. The coarse quantization and fine quantization ADCs are connected through the DAS logic circuit. The reference power supply circuit part includes a reference power supply circuit of the coarse quantization ADC and a reference power supply circuit of the fine quantization ADC, wherein the reference power supply circuit of the fine quantization ADC includes an auxiliary power supply circuit based on linear charge compensation, which is used to help it complete the reference level fluctuation recovery.

[0023] In a specific implementation, the multi-bit coarse quantization ADC is a 5-bit coarse quantization ADC, and the multi-bit fine quantization ADC is a 10-bit fine quantization ADC. It should be noted that the reference power supply stabilization technology provided by the present invention can also be applied to other coarse quantization ADC and fine quantization ADC bit situations. Taking a 5-bit coarse quantization ADC and a 10-bit fine quantization ADC as examples, the components in the segmented SAR ADC structure and the reference power supply stabilization technology provided by the present invention are described in detail:

[0024] A. Multi-bit coarse quantization ADC and multi-bit fine quantization ADC

[0025] The fluctuation of the reference power supply in the SAR ADC is proportional to the size of the capacitor. The size of the binary capacitor DAC is limited by the sampling accuracy requirements and the minimum achievable capacitor size. The MSB capacitance will increase exponentially with the increase in the number of bits. Therefore, the fluctuation caused by the capacitor switching at the MSBs position is greater, which is the main reason why the reference power supply is difficult to stabilize.

[0026] In order to reduce the impact of the switching fluctuation of the MSBs capacitor on the comparison, this paper adopts a two-step segmented SAR ADC structure, which divides the quantization process of the ADC into two steps, namely coarse quantization and fine quantization, which are performed on two CDACs with independent reference power supplies. During sampling, the same input voltage value is sampled on the coarse quantization and fine quantization CDACs. After the sampling is completed, when the ADC performs conversion, the sampled input value is first coarsely quantized by the coarse quantization ADC, and the coarse quantization code obtained by the coarse quantization is copied to the MSBs control bit of the fine quantization ADC. Since the coarse quantization ADC requires lower accuracy, it can use a small CDAC, the current required to be provided by the reference power supply is small, the fluctuation of the reference level is easy to stabilize, and the reference power supply circuit overhead can be ignored. After the coarse quantization is completed, the fine quantization is continued on the LSBs of the fine quantization ADC. In this way, the entire quantization process is performed on the LSBs of the coarse quantization ADC and the fine quantization ADC respectively, and the capacitor arrays corresponding to the two parts have small capacitance values, so there will be no great pressure on the recovery of the reference power supply.

[0027] When the coarse quantization code is copied to the MSBs of the fine quantization ADC, since the CDAC of the coarse quantization ADC and the fine quantization ADC use independent reference power supplies, the reference level errors between the two will not interfere with each other. Therefore, the fluctuations on the reference power supply of the fine quantization ADC that have not stabilized will not affect the conversion result of the coarse quantization ADC. It only needs to stabilize before the fine quantization ADC performs LSBs conversion. This makes the fluctuations of the reference power supply during the MSBs conversion of the fine quantization ADC have a longer stabilization time, allowing it to use a low-overhead reference power supply circuit. Analysis found that the reference level fluctuations generated by the switching of the capacitor before the handover between coarse quantization and fine quantization are the most difficult to stabilize before the LSBs conversion. Solving the problem of unstable reference level of this bit can solve the problem of unstable reference level of the entire segmented SAR ADC. The present invention uses the DAS algorithm introduced below combined with the linear charge compensation technology to ensure that this bit can be stabilized before the fine quantization ADC performs LSBs conversion.

[0028] B. DAS logic circuit

[0029] In order to further reduce the power consumption of the segmented SAR ADC, this design introduces the DAS algorithm to reduce the dynamic power consumption of the capacitor DAC of the fine ADC when copying the quantization result of the coarse ADC to the MSBs of the fine ADC. In the traditional binary CDAC switching method, since the next comparison and switching can only be performed after the previous CDAC is switched, the adjacent bits will switch in the opposite direction, wasting the switching power. In the segmented SAR ADC, after adding the coarse ADC, all the quantization codes are predicted, so the DAS algorithm can be used to eliminate this switching in the opposite direction and further reduce the dynamic power consumption of the capacitor switching. When the DAS algorithm detects a switch in the opposite direction, it skips the switching of the bit by keeping the capacitor bottom plate voltage unchanged, reducing the switching power consumption while obtaining the same DAC output voltage as the traditional switching method.

[0030] The DAS logic circuit switches the MSBs of the fine quantization ADC bit by bit according to the quantization result of the coarse quantization ADC. If the quantization result of the 5-bit coarse quantization ADC is B[4:0] and the control code of the fine quantization is D[9:0], the output Dout of the fine quantization CDAC is:

[0031]

[0032] According to formula (1), when the MSBs of the fine quantization ADC are switched according to the obtained coarse quantization code B[4:0], the control code switching order is D[5], D[9], D[8], D[7], D[6]. That is, the control code D[5] of C5 can be obtained according to the coarse quantization code B[4], and the control code D[9] of C9 can be obtained according to the coarse quantization code B[3], and so on.

[0033] The DAS logic circuit further reduces the switching power consumption of CDAC, and alleviates the power supply pressure and reference power fluctuation of the reference power circuit. At the same time, after the introduction of the DAS logic circuit, according to the above analysis, the reference power fluctuation caused by the switching of D[5], D[9], D[8] and D[7] has a long stabilization time before the fine quantization ADC performs LSBs conversion, and basically has no effect on the quantization result of LSBs. Only the switching of the control bit D[6] is difficult to stabilize before the fine quantization ADC performs LSBs conversion due to its short stabilization time and large capacitance value. The present invention provides an auxiliary power supply circuit based on linear charge compensation to stabilize the reference power fluctuation caused by the bit switching.

[0034] C. Reference power supply circuit

[0035] The reference circuit includes a reference power supply circuit for a coarse quantization ADC and a reference power supply circuit for a fine quantization ADC, wherein the reference power supply circuit for the fine quantization ADC includes an auxiliary power supply circuit based on linear charge compensation, so that the reference power supply fluctuation generated by the MSB switching controlled by D[6] can be quickly stabilized before the LSBs conversion.

[0036] In a SAR ADC, for a reference power supply using a traditional buffer, the process of reference level fluctuation stabilization is the process of charging the load capacitor, which is essentially the output resistance of the buffer. With load capacitance To ensure that the generated fluctuations can be stabilized within a conversion cycle, the output resistor of the buffer In order to reduce the output impedance of the buffer while ensuring low buffer power consumption, the auxiliary power supply circuit in the present invention adopts a switched capacitor circuit with a completely capacitive output impedance. The process of charging the load capacitor by the auxiliary power supply circuit with capacitive output impedance is a charge sharing process between capacitors, and the stabilization speed is much faster than the RC stabilization process of traditional buffer charging.

[0037] The auxiliary power supply circuit of the capacitive output impedance includes two stages when working: in the reset stage, the capacitor The bottom plate is reset to the ground level (GND), and the top plate is connected to the reference power supply to charge the capacitor; in the working stage, according to the control code S of the bottom plate switch, S is 0 and keeps The bottom plate is connected to the ground level, and S is 1, which will The bottom plate of the reference power supply switches to high level (VDD), and the reference power supply keeps its top plate voltage unchanged, thus transferring the charge to the The load capacitor, CDAC, is quickly charged. By adjusting the capacitance of the power supply capacitor, the amount of charge charged into CDAC can be equal to the amount of charge required for its switching, thereby achieving rapid stabilization of the reference power supply fluctuation.

[0038] After adopting the above-mentioned segmented SAR ADC structure and adding the DAS algorithm, the bit that needs to be assisted in stabilizing the reference level is the bit before the intersection of the coarse quantization and fine quantization ADC (that is, the bit controlled by the fine quantization control code D[6]). After the charge compensation of this bit is performed to ensure its reference level stability, a low-power reference power buffer with weak driving capability can be used to meet the reference level stability of all bits in the SARADC. During the stabilization process, the amount of charge required by the reference power supply for the CDAC switching controlled by the control bit D[6] includes two parts. One part is the amount of charge required by the bottom plate of the capacitor of this bit after it is switched to the reference power supply. The other part is the amount of charge required by the capacitor connected to the reference power supply due to the switching of the capacitor. , so the total charge that the reference power supply needs to provide is ( ). Due to the charge The size of is related to the coarse quantization result (B[4:0]), so the total charge is also related to the coarse quantization code. Simulation and calculation found that, except for the case of being skipped by the DAS algorithm, the total charge required for the CDAC switching controlled by the control code D[6] during the stabilization process increases and decreases linearly with the increase of the coarse quantization result B[4:0].

[0039] The present invention provides a binary capacitor array as an auxiliary power supply circuit, which realizes the linear charge compensation capability, and is used to provide the charge that has a linear increase and decrease relationship with the growth of the coarse quantization result B[4:0]. By controlling the number of bits of the binary capacitor array, all possible charge amounts can be covered, so that the reference level fluctuation caused by the CDAC switching controlled by the control code D[6] is fast and stable. If the MSBs capacitance size of the fine quantization ADC is 256C, 128C, 64C, 32C, and 16C respectively, where C is the unit capacitance size, then the binary capacitance value of the auxiliary power supply circuit is 8C, 4C, and 2C, and the corresponding control code (S[2:0], used to control the bottom plate switch switching of the linear charge compensation capacitor) and the coarse quantization result B[4:0] correspond to:

[0040]

[0041] The linear charge compensation circuit provided by the present invention comprises a binary capacitor array and a control circuit for providing compensation charge. Its working process comprises the following steps:

[0042] 1) During the sampling and coarse quantization process, the bottom plates of the binary capacitor array used to provide compensation charge are all connected to the ground level (GND) for reset.

[0043] 2) When the coarse quantization ADC completes the last bit comparison, the capacitance control code of the fine quantization ADC is obtained according to the last bit of the coarse quantization code, and the CDAC switching in the fine quantization ADC is controlled. At the same time, the control circuit generates a control code S according to the coarse quantization code, controls the corresponding capacitor bottom plate in the compensation capacitor array to be connected to the high level (VDD), and provides the required charge for the CDAC switching in the fine quantization ADC, helping the reference power supply to stabilize quickly.

[0044] In the linear charge compensation technology provided by the present invention, when the fine quantization ADC is used to deploy the last bit result of coarse quantization, the amount of charge required for CDAC switching has a linear relationship with the coarse quantization code. Therefore, the capacitor array used to provide compensation charge can be a small-area binary capacitor array, which solves the problem of unstable reference power supply while almost no additional hardware overhead and power consumption.

[0045] The above-mentioned segmented SAR ADC implementation method of the present invention comprises the following steps:

[0046] 1) Prepare the first multi-bit SAR ADC, which includes four parts: sampling circuit, CDAC, comparator and digital logic. Structurally, the multi-bit SAR ADC performs coarse quantization.

[0047] 2) Prepare a second multi-bit SAR ADC, which includes a sampling circuit, a CDAC, a comparator, and a digital logic. Structurally, the SAR ADC is finely quantized.

[0048] The first SAR ADC is used for the first step conversion, and the second SAR ADC is used for both the first step conversion and the second step conversion. Therefore, the first SAR ADC has fewer bits, and the second SAR ADC has more bits.

[0049] 3) Prepare a DAS logic circuit for controlling the switching of the MSBs of the CDAC in the fine quantization ADC according to the quantization result of the coarse quantization, and the control and switching methods are as described above.

[0050] 4) Prepare a reference power supply circuit, which is a reference power supply auxiliary power supply circuit based on linear charge compensation designed by the present invention, including a reference power supply circuit for a coarse quantization ADC and a reference power supply circuit for a fine quantization ADC, wherein the reference power supply circuit for the fine quantization ADC includes an auxiliary power supply circuit, which is composed of a binary capacitor array and a control circuit, and is used to quickly stabilize the reference power supply fluctuation generated by the switching of the MSBs of the fine quantization ADC before the LSBs are compared, thereby improving the conversion accuracy of the fine quantization. According to the capacitance value of CDAC in the fine quantization ADC, the size of the binary capacitor array in the auxiliary power supply circuit is designed so that the auxiliary power supply circuit can provide the amount of charge required for the switching of the previous CDAC at the junction of coarse quantization and fine quantization.

[0051] 5) The segmented SAR ADC provided by the present invention can be completed by connecting a SAR ADC with fewer bits and a SAR ADC with more bits through a DAS logic circuit, and connecting the output port of the reference power supply circuit to the reference power supplies of the two ADCs respectively.

[0052] Compared with the prior art, the present invention has the following beneficial effects:

[0053] The present invention provides a SAR ADC reference power supply stabilization technology, which is applicable to a segmented SAR ADC structure. The quantization process includes two steps, namely, coarse quantization and fine quantization. The MSBs switching of the fine quantization ADC is controlled according to the result of the coarse quantization, thereby providing a longer reference power supply fluctuation stabilization time for the MSBs switching of the fine quantization. In addition, the present invention provides a linear charge compensation technology, which is used to provide the charge required for one bit switching before the handover between coarse quantization and fine quantization, thereby ensuring that the reference power supply fluctuation of the MSBs switching of the fine quantization ADC is quickly stabilized before the LSBs conversion, thereby improving the conversion accuracy of the LSBs in the ADC.

[0054] Compared with other reference power supply stabilization technologies, the reference power supply stabilization technology provided by the present invention can not only reduce the influence of reference power supply fluctuations caused by switching of multiple MSBs of SARADC on conversion accuracy, but also help to improve the conversion speed and conversion accuracy of SAR ADC; at the same time, the linear charge compensation technology only requires a very small hardware area and power consumption overhead, greatly reducing the demand for high-power on-chip reference power supply drivers and large-area on-chip decoupling capacitors, which is helpful to reduce the power consumption and area overhead of SARADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of the structure of the segmented SAR ADC designed for the present invention;

[0056] Among them, Vin is the input signal, B[4:0] is the coarse quantization result, and D[9:0] is the fine quantization result.

[0057] Figure 2 Schematic diagram of the segmented SAR ADC circuit of the present invention.

[0058] Figure 3 This is a working timing diagram of the segmented SAR ADC of the present invention.

[0059] Figure 4 Schematic diagram of the reference power supply design with linear charge compensation of the present invention.

[0060] Figure 5 A schematic diagram of the working principle of a compensation capacitor in the linear charge compensation technology designed for the present invention. DETAILED DESCRIPTION

[0061] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but the scope of the present invention is not limited in any way.

[0062] The present invention provides a reference power supply fluctuation stabilization method applied to a SAR ADC, wherein the applicable SAR ADC is a segmented SAR ADC structure. The segmented SAR ADC structure comprises a multi-bit coarse quantization ADC, a multi-bit fine quantization ADC, a DAS logic circuit and a reference power supply circuit. The multi-bit coarse quantization ADC comprises four parts: a sampling circuit, a CDAC, a comparator and a digital logic; the multi-bit fine quantization ADC also comprises four parts: a sampling circuit, a CDAC, a comparator and a digital logic. The number of CDAC bits in the fine quantization ADC is greater than the number of CDAC bits in the coarse quantization ADC. The coarse quantization ADC and the fine quantization ADC are connected through a DAS logic circuit. The reference power supply circuit part comprises a reference power supply circuit of the coarse quantization ADC and a reference power supply circuit of the fine quantization ADC, wherein the reference power supply circuit of the fine quantization ADC comprises an auxiliary power supply circuit based on linear charge compensation, which is used to help it complete the reference level fluctuation recovery.

[0063] In a specific implementation, the multi-bit coarse quantization ADC is a 5-bit coarse quantization ADC, and the multi-bit fine quantization ADC is a 10-bit fine quantization ADC. It should be noted that the reference power supply stabilization technology provided by the present invention can also be applied to other coarse quantization ADC and fine quantization ADC bit situations. Taking a 5-bit coarse quantization ADC and a 10-bit fine quantization ADC as examples, the components in the segmented SAR ADC structure and the reference power supply stabilization technology provided by the present invention are described in detail:

[0064] A. Multi-bit coarse quantization ADC and multi-bit fine quantization ADC

[0065] The fluctuation of the reference power supply in the SAR ADC is proportional to the size of the capacitor. The size of the binary capacitor DAC is limited by the sampling accuracy requirements and the minimum achievable capacitor size. The MSB capacitance will increase exponentially with the increase in the number of bits. Therefore, the fluctuation caused by the capacitor switching at the MSBs position is greater, which is the main reason why the reference power supply is difficult to stabilize.

[0066] In order to reduce the impact of the switching fluctuation of the MSBs capacitor on the comparison, this paper adopts a two-step segmented SAR ADC structure, which divides the quantization process of the ADC into two steps, namely coarse quantization and fine quantization, which are performed on two CDACs with independent reference power supplies. During sampling, the same input voltage value is sampled on the coarse quantization and fine quantization CDACs. After the sampling is completed, when the ADC performs conversion, the sampled input value is first coarsely quantized by the coarse quantization ADC, and the coarse quantization code obtained by the coarse quantization is copied to the MSBs control bit of the fine quantization ADC. Since the coarse quantization ADC requires lower accuracy, it can use a small CDAC, the current required to be provided by the reference power supply is small, the fluctuation of the reference level is easy to stabilize, and the reference power supply circuit overhead can be ignored. After the coarse quantization is completed, the fine quantization is continued on the LSBs of the fine quantization ADC. In this way, the entire quantization process is performed on the LSBs of the coarse quantization ADC and the fine quantization ADC respectively, and the capacitor arrays corresponding to the two parts have small capacitance values, so there will be no great pressure on the recovery of the reference power supply.

[0067] When the coarse quantization code is copied to the MSBs of the fine quantization ADC, since the CDAC of the coarse quantization ADC and the fine quantization ADC use independent reference power supplies, the reference level errors between the two will not interfere with each other. Therefore, the fluctuations on the reference power supply of the fine quantization ADC that have not stabilized will not affect the conversion result of the coarse quantization ADC. It only needs to stabilize before the fine quantization ADC performs LSBs conversion. This makes the fluctuations of the reference power supply during the MSBs conversion of the fine quantization ADC have a longer stabilization time, allowing it to use a low-overhead reference power supply circuit. Analysis found that the reference level fluctuations generated by the switching of the capacitor before the handover between coarse quantization and fine quantization are the most difficult to stabilize before the LSBs conversion. Solving the problem of unstable reference level of this bit can solve the problem of unstable reference level of the entire segmented SAR ADC. The present invention uses the DAS algorithm introduced below combined with the linear charge compensation technology to ensure that this bit can be stabilized before the fine quantization ADC performs LSBs conversion.

[0068] B. DAS Logic

[0069] In order to further reduce the power consumption of the segmented SAR ADC, this design introduces the DAS algorithm to reduce the dynamic power consumption of the capacitor DAC of the fine ADC when copying the quantization result of the coarse ADC to the MSBs of the fine ADC. In the traditional binary CDAC switching method, since the next comparison and switching can only be performed after the previous CDAC is switched, the adjacent bits will switch in the opposite direction, wasting the switching power. In the segmented SAR ADC, after adding the coarse ADC, all the quantization codes are predicted, so the DAS algorithm can be used to eliminate this switching in the opposite direction and further reduce the dynamic power consumption of the capacitor switching. When the DAS algorithm detects a switch in the opposite direction, it skips the switching of the bit by keeping the capacitor bottom plate voltage unchanged, reducing the switching power consumption while obtaining the same DAC output voltage as the traditional switching method.

[0070] The DAS logic switches the MSBs of the fine quantization ADC bit by bit according to the quantization result of the coarse quantization ADC. If the quantization result of the 5-bit coarse quantization ADC is B[4:0] and the control code of the fine quantization is D[9:0], the output Dout of the fine quantization CDAC is:

[0071]

[0072] According to formula (1), when the MSBs of the fine quantization ADC are switched according to the obtained coarse quantization code B[4:0], the control code switching order is D[5], D[9], D[8], D[7], D[6]. That is, the control code D[5] of C5 can be obtained according to the coarse quantization code B[4], and the control code D[9] of C9 can be obtained according to the coarse quantization code B[3], and so on.

[0073] DAS logic further reduces the switching power consumption of CDAC, and alleviates the power supply pressure and reference power fluctuation of the reference power supply circuit. At the same time, after the introduction of DAS logic, according to the above analysis, the reference power supply fluctuation caused by the switching of D[5], D[9], D[8] and D[7] has a long stabilization time before the fine quantization ADC performs LSBs conversion, and basically has no effect on the quantization result of LSBs. Only the switching of the control bit D[6] is difficult to stabilize before the fine quantization ADC performs LSBs conversion due to its short stabilization time and large capacitance value. The present invention provides an auxiliary power supply circuit based on linear charge compensation to stabilize the reference power supply fluctuation caused by the bit switching.

[0074] C. Reference power supply circuit

[0075] The reference circuit includes a reference power supply circuit for a coarse quantization ADC and a reference power supply circuit for a fine quantization ADC, wherein the reference power supply circuit for the fine quantization ADC includes an auxiliary power supply circuit based on linear charge compensation, so that the reference power supply fluctuation generated by the MSB switching controlled by D[6] can be quickly stabilized before the LSBs conversion.

[0076] In a SAR ADC, for a reference power supply using a traditional buffer, the process of reference level fluctuation stabilization is the process of charging the load capacitor, which is essentially the output resistance of the buffer. With load capacitance To ensure that the generated fluctuations can be stabilized within a conversion cycle, the output resistor of the buffer In order to reduce the output impedance of the buffer while ensuring low buffer power consumption, the auxiliary power supply circuit in the present invention adopts a switched capacitor circuit with a completely capacitive output impedance. The process of charging the load capacitor by the auxiliary power supply circuit with capacitive output impedance is a charge sharing process between capacitors, and the stabilization speed is much faster than the RC stabilization process of traditional buffer charging.

[0077] The auxiliary power supply circuit of the capacitive output impedance includes two stages when working: in the reset stage, the capacitor The bottom plate is reset to the ground level (GND), and the top plate is connected to the reference power supply to charge the capacitor; in the working stage, according to the control code S of the bottom plate switch, S is 0 and keeps The bottom plate is connected to the ground level, and S is 1, which will The bottom plate of the reference power supply switches to high level (VDD), and the reference power supply keeps its top plate voltage unchanged, thus transferring the charge to the The load capacitor, CDAC, is quickly charged. By adjusting the capacitance of the power supply capacitor, the amount of charge charged into CDAC can be equal to the amount of charge required for its switching, thereby achieving rapid stabilization of the reference power supply fluctuation.

[0078] After adopting the above-mentioned segmented SAR ADC structure and adding the DAS algorithm, the bit that needs to be assisted in stabilizing the reference level is the bit before the intersection of the coarse quantization and fine quantization ADC (that is, the bit controlled by the fine quantization control code D[6]). After the charge compensation of this bit is performed to ensure its reference level stability, a low-power reference power buffer with weak driving capability can be used to meet the reference level stability of all bits in the SARADC. During the stabilization process, the amount of charge required by the reference power supply for the CDAC switching controlled by the control bit D[6] includes two parts. One part is the amount of charge required by the bottom plate of the capacitor of this bit after it is switched to the reference power supply. The other part is the amount of charge required by the capacitor connected to the reference power supply due to the switching of the capacitor. , so the total charge that the reference power supply needs to provide is ( ). Due to the charge The size of is related to the coarse quantization result B[4:0], so the total charge is also related to the coarse quantization code. Simulation and calculation found that, except for the case of being skipped by the DAS algorithm, the total charge required for the CDAC switching controlled by the control code D[6] during the stabilization process increases and decreases linearly with the growth of the coarse quantization result B[4:0].

[0079] The present invention provides a binary capacitor array as an auxiliary power supply circuit, which realizes the linear charge compensation capability, and is used to provide the charge that has a linear increase and decrease relationship with the growth of the coarse quantization result B[4:0]. By controlling the number of bits of the binary capacitor array, all possible charge amounts can be covered, so that the reference level fluctuation caused by the CDAC switching controlled by the control code D[6] is fast and stable. If the MSBs capacitance size of the fine quantization ADC is 256C, 128C, 64C, 32C, and 16C respectively, where C is the unit capacitance size, then the binary capacitance value of the auxiliary power supply circuit is 8C, 4C, and 2C, and the corresponding control code (S[2:0], used to control the bottom plate switch switching of the linear charge compensation capacitor) and the coarse quantization result B[4:0] correspond to:

[0080]

[0081] After adding the binary capacitor array for auxiliary power supply, the bottom plate of the binary capacitor array is connected to the ground level (GND) for reset before sampling and switching. When the coarse quantization ADC completes the last bit comparison, the capacitor control code D[6] is obtained according to the coarse quantization code B[0] to control the CDAC switching and turn on the auxiliary power supply circuit. The bottom plate of the capacitor corresponding to the coarse quantization code B[4:0] is connected to the high level (VDD) to provide the capacitor DAC with the amount of charge required for its stability, while the reference power buffer only needs to provide a small amount of charge, thereby greatly reducing the fluctuation amplitude of the reference level and improving the stabilization speed. The linear charge compensation technology provided by the present invention only adds a small-area binary capacitor array, which solves the problem of unstable reference power supply and has almost no additional hardware overhead and power consumption.

[0082] The above-mentioned segmented SAR ADC implementation method of the present invention comprises the following steps:

[0083] 1) Prepare the first multi-bit SAR ADC, which includes four parts: sampling circuit, CDAC, comparator and digital logic. Structurally, the multi-bit SAR ADC performs coarse quantization.

[0084] 2) Prepare a second multi-bit SAR ADC, which includes a sampling circuit, a CDAC, a comparator, and a digital logic. Structurally, the SAR ADC is finely quantized.

[0085] 3) Prepare a DAS logic circuit for controlling the switching of the MSBs of the CDAC in the fine quantization ADC according to the quantization result of the coarse quantization, and the control and switching methods are as described above.

[0086] 4) Prepare a reference power supply circuit, which is a reference power supply auxiliary power supply circuit based on linear charge compensation designed by the present invention, including a reference power supply circuit for a coarse quantization ADC and a reference power supply circuit for a fine quantization ADC, wherein the reference power supply circuit for the fine quantization ADC includes an auxiliary power supply circuit, which is composed of a binary capacitor array and a control circuit, and is used to quickly stabilize the reference power supply fluctuation generated by the switching of the MSBs of the fine quantization ADC before the LSBs are compared, thereby improving the conversion accuracy of the fine quantization. According to the capacitance value of CDAC in the fine quantization ADC, the size of the binary capacitor array in the auxiliary power supply circuit is designed so that the auxiliary power supply circuit can provide the amount of charge required for the switching of the previous CDAC at the junction of coarse quantization and fine quantization.

[0087] 5) The segmented SAR ADC provided by the present invention can be completed by connecting a SAR ADC with fewer bits and a SAR ADC with more bits through a DAS logic circuit, and connecting the output port of the reference power supply circuit to the reference power supplies of the two ADCs respectively.

[0088] The accompanying drawings show a specific implementation of the reference power supply stabilization technology proposed by the present invention applied to a segmented SAR ADC. Figure 1 As shown, the segmented SAR ADC includes four parts, namely: a 5-bit coarse quantization ADC, a 10-bit fine quantization ADC, a DAS logic circuit and a reference power supply circuit. The coarse quantization conversion result B[4:0] is input into the DAS logic circuit to generate the control code D[9:5] of the 5-bit MSBs in the fine quantization ADC, the conversion result of the 5-bit LSBs in the fine quantization ADC is D[4:0], and the final output of the system is D[9:0]. The reference power supply circuit includes a reference power supply circuit of the coarse quantization ADC and a reference power supply circuit of the fine quantization ADC, wherein the linear charge compensation circuit provided by the present invention is added to the reference power supply circuit of the fine quantization ADC to stabilize the fluctuation of the reference power supply before the LSBs of the fine quantization ADC start to be converted, improve the fine quantization accuracy, and reduce the demand for a high-power consumption and strong driving capability reference power supply buffer.

[0089] A circuit implementation and timing diagram of the segmented SAR ADC are shown in Figure 2 and Figure 3As shown. When the segmented SAR ADC is working, first in the sampling stage, switches S1 and S2 are closed, and the input signal is sampled to the 5-bit coarse quantization DAC and the 10-bit fine quantization ADC at the same time. After the sampling is completed, switches S1 and S2 are opened, triggering the comparator for coarse quantization. According to the comparison result of the comparator, the bottom plate switch of the 5-bit coarse quantization DAC is switched through the SAR logic, and the switching order is C9a, C8a, C7a, C6a, C5a. Since the capacitance value of the coarse quantization switching is small, the current required to be provided by the reference power supply is also small, so the design requirements of the coarse quantization reference power supply buffer are loose and consume very little power. In the coarse quantization process, according to the quantization result of the coarse quantization, the DAS logic circuit switches the MSBs of the fine quantization DAC at the same time, and the switching order is C5, C9, C8, C7, C6. Since the conversion occurs on the coarse quantization DAC at this time, the reference power supply fluctuation caused by the switching of C5, C9, C8 and C7 does not affect the conversion accuracy, and a longer stabilization time can be tolerated. Only the reference power supply fluctuation caused by the switching of C6 needs to be stabilized before the fine quantization starts. When C6 switches, the linear charge compensation technology provided by the present invention is triggered, and the compensation capacitor quickly provides the charge required for the bit switching, so that the fluctuation of the reference power supply is quickly stabilized. Analysis and simulation show that the charge required for the bit switching has a linear relationship with the coarse quantization result B[4:0], so charge compensation can be achieved using a 3-bit small-capacitance binary capacitor array.

[0090] The reference power supply circuit schematic diagram and working principle diagram with linear charge compensation provided by the present invention are as follows Figure 4 and Figure 5 As shown, the buffer is used to ensure the constant level of the reference power supply, and the auxiliary power supply circuit based on linear charge compensation is used to quickly provide the charge required for C6 switching to reduce the fluctuation of the reference power supply. In the reset stage, the bottom plate of the capacitor Cmsb to Clsb is connected to the ground level (GND), and the top plate is the reference power supply (Vrefp) voltage, and the capacitor is charged; in the working stage, according to the result of coarse quantization, the corresponding bottom plate of the capacitor is switched to the high level (VDD), so that the charge stored on the capacitor flows out quickly to CDAC to provide the required charge. After adding this auxiliary power supply circuit, not only can the fluctuation of the reference power supply be reduced, the speed and accuracy of the ADC be improved, but also the design requirements for the reference power supply buffer can be greatly reduced, the power consumption of the fine quantization reference power supply buffer can be reduced, and the energy efficiency of the system can be improved.

[0091] After the coarse quantization is completed, due to the DAS algorithm, the top plate voltage of the coarse quantization DAC and the fine quantization DAC is the same. At this time, switch S2 is turned on, connecting the coarse quantization DAC with the fine quantization DAC to form an overall binary capacitor array, and reuses the coarse quantization comparator to continue fine quantization, thereby reducing the hardware overhead caused by the additional coarse quantization. At the beginning of fine quantization, capacitor Cr is used to provide inter-level redundancy between coarse quantization and fine quantization to ensure system accuracy. Then, according to the comparison result of the comparator, the LSBs of the fine quantization DAC are switched, and the switching order is C4, C3, C2, C1, C0, and finally a data readout is completed.

[0092] It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter, characterized in that: The method is applied to a segmented successive approximation analog-to-digital converter; comprising: Constructing a segmented successive approximation analog-to-digital converter SAR ADC, including a first multi-bit SAR ADC or coarse quantization ADC, a second multi-bit SAR ADC or fine quantization ADC, a detection skip algorithm DAS logic circuit and a reference power supply circuit; The reference power supply circuit includes a reference power supply circuit for a coarse quantization ADC and a reference power supply circuit for a fine quantization ADC; Design a linear charge compensation circuit to improve the reference power supply circuit of the fine quantization ADC; the reference power supply circuit of the fine quantization ADC includes a buffer and a linear charge compensation circuit; the linear charge compensation circuit serves as an auxiliary power supply circuit; The linear charge compensation circuit includes a binary capacitor array and a control circuit for providing compensation charge, so as to quickly stabilize the reference power supply fluctuation generated by the switching of the most significant bit of the fine quantization ADC before the least significant bit is compared, thereby improving the conversion accuracy of the fine quantization; The size of the binary capacitor array is determined according to the capacitance value of CDAC in the fine quantization ADC, so that the linear charge compensation circuit provides the charge required for the previous CDAC switching at the junction of coarse quantization and fine quantization, thereby quickly recovering the reference level fluctuation.

2. The method for stabilizing the reference power supply fluctuation of a successive approximation analog-to-digital converter according to claim 1, characterized in that: The linear charge compensation circuit uses a switched capacitor circuit with a completely capacitive output impedance.

3. The method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter according to claim 1, characterized in that: The working process of the linear charge compensation circuit includes the following steps: 1) During the sampling and coarse quantization process, the bottom plates of the binary capacitor array used to provide compensation charge are all connected to the ground level GND for reset; 2) When the coarse quantization ADC completes the last bit comparison, the capacitance control code of the fine quantization ADC is obtained according to the last bit of the coarse quantization code, and the CDAC switching in the fine quantization ADC is controlled; at the same time, the control circuit generates a control code S according to the coarse quantization code, and controls the corresponding capacitor bottom plate in the capacitor array to be connected to the high level VDD, providing the required charge for the CDAC switching in the fine quantization ADC, so that the reference power supply is quickly stabilized.

4. The method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter according to claim 1, characterized in that: The constructed segmented successive approximation analog-to-digital converter works in the following steps: 1) The coarse quantization ADC and the fine quantization ADC sample the input signal simultaneously; 2) During the conversion process, the first step of coarse quantization is performed using a coarse quantization ADC. While the coarse quantization ADC obtains the quantization result, the detection skip algorithm is used to control the switching of the most significant bit capacitor of the CDAC in the fine quantization ADC. 3) The amount of charge provided by the reference power supply required for the last bit switching of the most significant bit of the CDAC in the fine quantization ADC is linearly correlated with the coarse quantization result of the coarse quantization ADC, thereby triggering the operation of the linear charge compensation circuit; When the linear charge compensation circuit is working, according to the coarse quantization result, the control circuit selects a capacitor in the binary capacitor array, switches the bottom plate of the capacitor from a low level to a high level, thereby quickly providing the charge required for switching the last bit of the most significant bit of CDAC in the fine quantization ADC, so that the reference power supply fluctuation generated by the switching of the most significant bit capacitor of CDAC in the fine quantization ADC is quickly stabilized before the least significant bit conversion of CDAC in the fine quantization ADC starts, thereby improving the quantization accuracy; 4) The second step of fine quantization is continued on the least significant bit capacitance of CDAC in the fine quantization ADC.

5. The method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter as claimed in claim 4, characterized in that: In step 3), the linear charge compensation circuit operates in two stages: During the reset phase, the capacitor The bottom plate is reset to GND, and the top plate is connected to the reference power supply to charge the capacitor; During the working stage, according to the control code of the bottom plate switch, if the control code is 0, the bottom plate of the capacitor is kept connected to the ground level GND, and if the control code is 1, the bottom plate of the capacitor is switched to the high level VDD, and the reference power supply keeps the top plate voltage unchanged; the charge is quickly charged into the load capacitor, namely CDAC, through charge sharing; the capacitance value of the power supply capacitor is adjusted so that the amount of charge charged into CDAC is equal to the amount of charge required for switching.

6. The method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter as claimed in claim 5, characterized in that: The number of bits for which the auxiliary reference level is stable is the bit before the junction of the coarse quantization ADC and the fine quantization ADC; after charge compensation is performed on this bit to stabilize the reference level, a low-power reference power supply buffer is used to stabilize the reference level of all bits in the successive approximation analog-to-digital converter.

7. The method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter as claimed in claim 6, characterized in that: In the stabilization process, the charge required by the reference power supply for the CDAC switching of the fine quantization ADC controlled by the previous control code at the junction of coarse quantization and fine quantization includes two parts. One part is the charge required by the bottom plate of the capacitor after it is switched to the reference power supply. The other part is the amount of charge required by the capacitor connected to the reference power supply due to the switching of the capacitor. ; The total charge required for the reference power supply is ; Charge The size of is related to the coarse quantization result; the total charge required for the CDAC switching in the fine quantization ADC controlled by the previous control code at the junction of coarse quantization and fine quantization during the stabilization process will increase or decrease linearly with the growth of the coarse quantization result.

8. The method for stabilizing reference power supply fluctuation of a successive approximation analog-to-digital converter as claimed in claim 7, characterized in that: By controlling the number of enabled bits of the binary capacitor array and adjusting the amount of compensation charge provided, the reference level fluctuation caused by the CDAC switching controlled by the previous control code at the junction of coarse quantization and fine quantization can be quickly stabilized.

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