Recoding metric determination system and method, and order statistical decoder

Abstract

The invention discloses a recoding metric determination system and method and an order statistical decoder, and relates to the technical field of channel coding, and the system comprises the steps that a storage unit stores first to-be-coded data when the signal state type of an effective signal is a first preset state type; the combination number generation unit generates a combination number vector when the signal state type is a second preset state type; when the measurement determining unit receives the combination number vector, the stored data to be coded are read from the storage unit; the storage unit takes the output stored to-be-coded data as second to-be-coded data and returns and restores the second to-be-coded data; and the metric determination unit performs recoding based on the stored data to be coded and the combination number vector to obtain a code word metric. When the effective signal is changed into the second preset state, the storage unit outputs and returns the data at the same time, so that the data cyclic shift in the recoding process is realized, and fewer logic resources are occupied while the recoding efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of channel coding technology, and in particular to a recoding metric determination system and method, and an order statistics decoder. Background Art

[0002] Ordered Statistics Decoding (OSD) is a general decoding algorithm that can decode all linear block codes. Studies have shown that for channel coding with medium and short code lengths, the OSD algorithm generally has a lower bit error rate than traditional decoding algorithms. Currently, most of the research on OSD algorithms remains in the software simulation stage. However, in engineering implementation, in order to meet the real-time requirements of communication systems, it is necessary to use Field Programmable Gate Array (FPGA) for parallel processing to improve the decoding speed.

[0003] OSD decoding is a decoding algorithm based on the generator matrix, which mainly includes steps such as sorting, Gaussian elimination, and recoding metric calculation. For the OSD decoder based on FPGA, the sorting and Gaussian elimination processes are suitable for storing and processing the generator matrix by column, while the recoding metric calculation process is suitable for storing and processing the generator matrix by row. There are two intuitive solutions to this problem. One is to add the logic of matrix transposition between the Gaussian elimination module and the recoding module, but for matrices of larger dimensions, the transposition operation will consume a lot of logic resources. The second is that the entire decoding process uses the same matrix storage method (by row or by column), but this will reduce the operating efficiency of some modules in sorting, Gaussian elimination, and recoding metric calculation due to the use of inappropriate matrix storage formats. Summary of the invention

[0004] The main purpose of the present application is to provide a recoding metric determination system, method and order statistics decoder, aiming to solve the technical problems of the existing order statistics decoder consuming a lot of logical resources and having low operating efficiency when calculating the recoding metric.

[0005] To achieve the above-mentioned object, the present application proposes a recoding metric determination system, the recoding metric determination system comprising: a storage unit, a combination number generation unit and a metric determination unit; The storage unit is used to store the first data to be encoded when the signal state type of the valid signal is the first preset state type; The combination number generating unit is used to generate a combination number vector when the signal state type is a second preset state type; The metric determination unit is configured to read the stored data to be encoded from the storage unit when receiving the combination number vector, wherein the stored data to be encoded includes the first data to be encoded; The storage unit is further used to transmit the outputted stored data to be encoded as second data to be encoded back for re-storage; The metric determination unit is used to perform re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0006] In one embodiment, the storage unit includes a plurality of storage subunits; The number of the storage subunits is the same as the number of data types included in the data to be encoded; The storage subunit is composed of a selector and a shift register; The input ports of the selector are respectively connected to the effective signal input, the coded data input and the shift register output; The selector is used to obtain the data to be encoded from the data to be encoded input and store the data to be encoded in the shift register when detecting that the valid signal is of the first preset state type; The selector is further used to obtain the stored data to be encoded from the shift register output when it is detected that the valid signal is of the second preset state type, and return the stored data to be encoded as the second data to be encoded to the shift register for re-storage.

[0007] In one embodiment, the metric calculation unit is composed of a plurality of metric coding calculation subunits having the same structure connected in sequence; The number of the metric calculation subunits is the same as the code length value of the order statistics decoder applied by the re-encoding metric determination system; Each of the metric calculation subunits has a common input port, and the common input port is connected to the storage unit and is used to read the stored data to be encoded from the storage unit.

[0008] In one embodiment, the metric calculation subunit further includes two independent input ports and independent output ports corresponding to the independent input ports, which are respectively a first independent input port, a first independent output port, a second independent input port and a second independent output port; Wherein, the first independent input port of the first metric calculation subunit is connected to the combination number generation unit, and the input of the second independent input port of the first metric calculation subunit is fixed to a preset fixed input; The first independent output port of the Nth metric calculation subunit is suspended, and the independent output result of the second independent output port of the Nth metric calculation subunit is the codeword metric; Between the second metric calculation subunit to the Nth calculation subunit, the first independent input port of the subsequent metric calculation subunit is connected to the first independent output port of the preceding metric calculation subunit, and the second independent input port of the subsequent metric calculation subunit is connected to the second independent output port of the preceding metric calculation subunit.

[0009] In one embodiment, the data type of the data to be encoded includes: MRB codeword, hard decision, soft information and generator matrix; Correspondingly, the storage subunit includes: an MRB codeword subunit for storing data to be encoded whose data type is an MRB codeword, a hard decision subunit for storing data to be encoded whose data type is a hard decision, a soft information subunit for storing data to be encoded whose data type is soft information, and a generation matrix subunit for storing data to be encoded whose data type is a generation matrix.

[0010] In one embodiment, the second independent output port includes: a bit selector, a bit XOR area, a real number selection area, and a real number addition area; wherein the number of the bit selectors is the same as the decoding order value of the order statistics decoder applied by the recoding metric determination system; The bit selector is used to select a matrix element in the generated matrix data as output when an input condition of the input generated matrix data meets a preset input condition; The bit XOR area is used to perform an XOR operation on the output of the bit selector, the MRB codeword data, and the hard decision data to obtain a bit XOR result; The real number selection area is used to select the soft information element in the soft information data as output when the bit XOR result is the first XOR result; The real number addition area is used to add real numbers based on the output of the real number selection area and the input data of the second independent input port to obtain an independent output result of the second independent output port.

[0011] In one embodiment, the bit selection area is further used to select a preset element as output when an input condition of the inputted generation matrix data does not satisfy a preset condition; The real number selection area is also used to select a preset real number as output when the bit XOR result is a second XOR result.

[0012] In one embodiment, the system further comprises: a control unit; The control unit is connected to the storage unit and the combination number generating unit respectively; The control unit is used to monitor the effective signal; The control unit is further configured to generate a start signal when the signal state type is a second preset state type, and send the start signal to the combination number generating unit; The combination number generating unit is further configured to trigger the generation of a combination number vector based on the start signal.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a recoding metric determination method, which is applied to the recoding metric determination system as described above, and the recoding metric determination system includes: a storage unit, a combination number generation unit and a metric determination unit, and the method includes: The storage unit stores the first data to be encoded when the signal state type of the valid signal is a first preset state type; The combination number generating unit generates a combination number vector when the signal state type is changed to a second preset state type; When receiving the combination number vector, the metric determination unit reads the stored data to be encoded from the storage unit, wherein the stored data to be encoded includes the first data to be encoded; The storage unit transmits the outputted stored data to be encoded as second data to be encoded back for re-storage; The metric determination unit performs re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides an order statistics decoder, in which the order statistics decoder is provided with the re-encoding metric determination system as described above.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: The recoding metric determination system of the present application includes: a storage unit, a combination number generation unit and a metric determination unit; the storage unit stores the first data to be encoded when the signal state type of the valid signal is the first preset state type; the combination number generation unit generates a combination number vector when the signal state type is the second preset state type; the metric determination unit reads the stored data to be encoded from the storage unit when receiving the combination number vector, and the stored data to be encoded includes the first data to be encoded; the storage unit transmits the output stored data to be encoded as the second data to be encoded and re-stores it; the metric determination unit recodes based on the stored data to be encoded and the combination number vector to obtain the codeword metric. Because the valid signal is monitored, and when the valid signal changes to the second preset state, the storage unit outputs and transmits the data simultaneously, the data cyclic shift in the recoding process is realized, and multiple recoding operations are completed simultaneously as much as possible, which improves the recoding efficiency while occupying less logical resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 This is a schematic diagram of the system structure of the recoding metric determination system in the first embodiment of the present application; Figure 2 This is a schematic diagram of the storage unit structure in Embodiment 2 of the recoding metric determination system of the present application; Figure 3 This is a schematic diagram of the structure of the metric calculation unit in Embodiment 3 of the recoding metric determination system of the present application; Figure 4 This is a schematic diagram of the structure of a second independent output port of a metric calculation subunit in one implementation of the present application; Figure 5 A flowchart of a method for determining a recoding metric according to an embodiment of the present application is shown.

[0019] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0021] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0022] The embodiment of the present application designs an FPGA structure (i.e., a recoding metric determination system) for implementing recoding metric calculation in an order-order statistical decoder. The structure stores the generated matrix by column, which is convenient for adapting the needs of the sorting and Gaussian elimination modules. During the operation process, by designing the operation steps, the module can perform recoding metric calculation in a pipeline manner, ensuring the operation efficiency. At the same time, after experiments, the structure proposed in the present application occupies less logic resources than the structure with matrix transposition logic added.

[0023] In the first embodiment of the present application, the recoding metric determination system of the present application can be as follows: Figure 1 As shown, Figure 1This is a schematic diagram of the system structure of the recoding metric determination system in the first embodiment of the present application.

[0024] Specifically, in an embodiment of the present application, the recoding metric determination system includes: a storage unit, a combination number generation unit and a metric determination unit.

[0025] The storage unit is used to store the first data to be encoded when the signal state type of the valid signal is the first preset state type.

[0026] It should be noted that in FPGA, a storage unit is a basic component that can be used to store data. In the embodiment of the present application, the storage device used by the storage unit can be a random access memory, a read-only memory, a shift register, etc., and the embodiment of the present application does not limit this.

[0027] In the recoding metric determination system of the embodiment of the present application, the input of the system may include data to be encoded and a valid signal, wherein the data to be encoded may be data involved in the recoding and recoding metric of the system, and the valid signal may be a signal used by the system to identify the validity of the data to be encoded.

[0028] It can be understood that the order statistical decoding algorithm is a decoding method based on a probability decoding criterion. In the embodiment of the present application, the above-mentioned data to be encoded may include data of data types such as MRB codewords, hard decisions, soft information, and generator matrices.

[0029] In some implementations of the embodiments of the present application, it can be assumed that the code length of the applied order statistics decoder is N ( N The value of can be 128 or other values, which is not limited in the present embodiment of the application), the information bit length is K ( K The value of can be 64 or other values, which is not limited in the embodiment of the present application). The decoding order is D ( D The value of can be 3 or other values, which is not limited in the present embodiment). Specifically, the MRB codeword is the codeword determined based on the most reliable information set, where the MRB codeword can be N dimensional bit vector (the dimension value is the same as the code length value of the order statistics decoder), denoted as m ; Hard decisions can be N Dimensional bit vector, denoted as h ; Soft information can be N dimensional UI number vector, denoted as r ; The generator matrix can be N List KThe row matrix (the number of columns of the generator matrix is ​​the same as the code length value of the order statistics decoder, and the number of rows of the generator matrix is ​​the same as the information length value of the order statistics decoder), denoted as G In the embodiment of the present application, the input data to be encoded can be N The generation matrix can be input column by column, and the MRB codeword, hard decision, and soft information can be input element by element. t The inputs are: Bit , the hard judgment Bit , the first element , generating the matrix List .

[0030] It can be understood that the process of calculating the recoding metric can be summarized as follows: XOR the specified number of rows in the generator matrix with the input original codeword (MRB codeword), and according to the result of the XOR, select the bit metric corresponding to bit 1 to add and obtain the codeword metric. When the generator matrix is ​​stored by row, the XOR operation can be completed within one clock cycle, but when the generator matrix is ​​stored by column, the XOR operation is performed bit by bit, and the number of clock cycles required is equal to the code length of the order statistics decoder (that is, the number of columns of the generator matrix).

[0031] In some implementations of the embodiments of the present application, the valid signal in the embodiments of the present application may be a level signal. Specifically, the signal state type in the embodiments of the present application may include a high level state and a low level state. Through the signal state type of the valid signal, the validity identification of the data to be encoded input to the system can be realized.

[0032] In some implementations of the embodiments of the present application, the high level state can be used as the first preset state type of the valid signal, and the low level state can be used as the second preset state type of the valid signal. When the signal state of the valid signal is the first preset state type, it can be said that the input data to be encoded is valid, and the data to be encoded can be stored at this time; when the signal state type of the valid signal is the second preset state type, it can be said that the input data to be encoded is invalid, and the data to be encoded is not stored at this time.

[0033] It should be noted that, in the implementation of the present application, the first data to be encoded is also the data to be encoded input from outside the system to the storage unit.

[0034] In a specific implementation, the embodiment of the present application can realize the recognition of the first data to be encoded inputted from the system to the system by monitoring the signal state type of the valid signal. When the signal state type of the valid signal is a high level state, the first data to be encoded is stored in the storage unit; when the signal type of the valid signal is a low level state, the first data to be encoded is not stored.

[0035] The combination number generating unit is used to generate a combination number vector when the signal state type is a second preset state type; The metric determination unit is configured to read the stored data to be encoded from the storage unit when receiving the combination number vector, wherein the stored data to be encoded includes the first data to be encoded; The metric determination unit is used to perform re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0036] It should be noted that when the signal state type is the second preset state type, the combination number unit of the embodiment of the present application can generate a combination number vector (specifically D dimensional integer vector, denoted by c ), based on the combination number vector, the data to be encoded can be re-encoded and the codeword metric can be obtained at the same time.

[0037] It should be explained that when the metric determination unit receives the combination number vector sent by the combination number generation unit, the data to be encoded can be read in the storage unit. The data to be encoded read by the metric determination unit can be part of the data to be encoded stored in the storage unit, or can be all of the data to be encoded stored in the storage unit. The specific selection can be based on the actual application situation, and the embodiment of the present application is not limited to this.

[0038] In the embodiment of the present application, the stored data to be encoded includes first data to be encoded and may also include second data to be encoded.

[0039] It should be noted that the first data to be encoded is data to be encoded input from outside the system, and the second data to be encoded is data to be encoded circulated within the system.

[0040] It should be understood that the metric determination unit can perform a recoding operation based on the stored data to be encoded and the combination number vector read from the storage unit, thereby realizing recoding and obtaining a codeword metric, which can be a parameter for evaluating the similarity between the recoded codeword and the original codeword.

[0041] It is understandable that when the metric determination unit reads the storage unit, the valid signal monitored by the storage unit is also of the second preset state type. At this time, the storage unit will not store the first data to be encoded input from the outside, but will send back the data output by the storage unit as the second data to be encoded to realize the internal circulation of the data to be encoded, which is convenient for the next re-encoding task. That is, the storage unit is also used to send back the output stored data to be encoded as the second data to be encoded for re-storage.

[0042] It should be noted that, through the above-mentioned method of the present application, the generation matrix can be stored by column, and by returning the output data to be encoded, the storage shift of the data to be encoded in the storage unit is realized, and the order of each recoding operation is changed. For example, the first recoding task calculates the order of the 1st to nth bits, and the second recoding task calculates the order of the 2nd to nth bits, and finally calculates the 1st bit. Since the arrival time of the second recoding task is 1 clock cycle later than the first recoding task, when the second recoding task calculates the 2nd bit, the first recoding task is also calculating the 2nd bit, which allows these two operations to be completed at the same time. By designing the operation steps in a similar way, the scheme of the present application can enable multiple recoding tasks to be performed simultaneously, thereby ensuring that the module can work in a pipeline manner, improving the operating efficiency, and occupying less logic resources than the structure with matrix transposition logic added.

[0043] In some implementations of the embodiments of the present application, in order to achieve better generation of a combination number vector, the recoding metric determination system of the embodiments of the present application may further include a control unit, wherein the control unit is respectively connected to the storage unit and the combination number generation unit; The control unit is used to monitor the effective signal; The control unit is further configured to generate a start signal when the signal state type is a second preset state type, and send the start signal to the combination number generating unit; The combination number generating unit is further configured to trigger the generation of a combination number vector based on the start signal.

[0044] In some implementation schemes of the embodiments of the present application, the overall workflow of the recoding metric determination system of the present application can be described as: when the valid signal is at a high level, the storage unit first stores the input data to be encoded; at the same time, the control unit can continuously monitor the valid signal, and when the valid signal is at a low level, a start signal is generated and input to the combination number generation unit; the combination number generation unit is triggered by the start signal, generates a combination number vector in each clock cycle and inputs the combination number vector to the metric calculation unit; the metric calculation unit can implement recoding according to the data to be encoded stored in the storage unit and the generated combination number vector, and calculate the codeword metric.

[0045] The recoding metric determination system of the embodiment of the present application includes: a storage unit, a combination number generation unit and a metric determination unit; the storage unit stores the first data to be encoded when the signal state type of the valid signal is the first preset state type; the combination number generation unit generates a combination number vector when the signal state type is the second preset state type; the metric determination unit reads the stored data to be encoded from the storage unit when receiving the combination number vector, and the stored data to be encoded includes the first data to be encoded; the storage unit transmits the output stored data to be encoded as the second data to be encoded and re-stores it; the metric determination unit recodes based on the stored data to be encoded and the combination number vector to obtain the codeword metric. Since the valid signal is monitored, and when the valid signal changes to the second preset state, the storage unit outputs and transmits the data simultaneously, the data cyclic shift in the recoding process is realized, and multiple recoding operations are completed simultaneously as much as possible, which improves the recoding efficiency while occupying less logical resources.

[0046] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can be referred to the above introduction, and will not be repeated in the following. Figure 2 , Figure 2 This is a schematic diagram of the storage unit structure in Embodiment 2 of the recoding metric determination system of the present application.

[0047] In the embodiment of the present application, the storage unit may include a plurality of storage subunits, wherein the number of the storage subunits is the same as the number of data types involved in the data to be encoded.

[0048] In some implementation manners of the embodiments of the present application, the data to be encoded in the embodiments of the present application may include data to be encoded of four data types: MRB codeword, hard decision, soft information and generator matrix.

[0049] Correspondingly, the storage subunit includes: an MRB codeword subunit for storing data to be encoded whose data type is an MRB codeword, a hard decision subunit for storing data to be encoded whose data type is a hard decision, a soft information subunit for storing data to be encoded whose data type is soft information, and a generating matrix subunit for storing data to be encoded whose data type is a generating matrix.

[0050] It should be noted that each storage subunit may be composed of a selector and a shift register, wherein the input port of the selector is respectively connected to the valid signal input, the coded data input and the shift register output, and the output port of the selector is connected to the input of the shift register for inputting data into the shift register for storage.

[0051] The selector is used to obtain the data to be encoded from the data to be encoded input and store the data to be encoded in the shift register when detecting that the valid signal is of the first preset state type; The selector is further used to obtain the stored data to be encoded from the shift register output when it is detected that the valid signal is of the second preset state type, and return the stored data to be encoded as the second data to be encoded to the shift register for re-storage.

[0052] In some implementations of the embodiments of the present application, the above storage unit may be composed of 4 storage elements with the number of N The four shift registers (the specific number of shift registers is related to the data type of the data to be encoded) are composed of four shift registers, which store MRB codewords, hard decisions, soft information and generation matrices respectively. Among them, the input end of each shift register is connected to a 2-input selector, which can monitor the valid signal. When the valid signal is in a high-level state, the external input data to be encoded is selected as the input of the shift register. At this time, the shift register can load and store the external input data to be encoded; when the valid signal is in a low-level state, the selector can select the output of the shift register as the input of the shift register, thereby realizing that the shift register continuously shifts the stored data in a circular manner.

[0053] It should be noted that when the input is completed, the effective signal can be converted to a low level state, and the control unit and the selector can detect the level state change of the effective signal. The control unit can generate a start signal to input to the combination number generation unit. When the combination number generation unit receives the start signal, it enables the internal counter from 0 to Counting is performed, and the value of the internal counter increases by 1 in each clock cycle.

[0054] It should be explained that the combination number generating unit can generate the combination number according to the value of the internal counter. s Calculate the combination number vector c , where the first i The calculation of the elements can be as follows: ; Among them, floor is the rounding function, and mod is the remainder function.

[0055] In the embodiment of the present application, when the selector detects that the valid signal is of the first preset state type, the data to be encoded is obtained from the data input to be encoded, and the data to be encoded is stored in the shift register; when the selector detects that the valid signal is of the second preset state type, the stored data to be encoded is obtained from the output of the shift register, and the stored data to be encoded is returned to the shift register as the second data to be encoded for re-storage. Since the cyclic shift of the data to be encoded in the shift register is realized by the selector, the system can perform re-encoding metric calculation in a pipeline manner, ensuring the operation efficiency.

[0056] Based on the first embodiment and / or the second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those of the above-mentioned first embodiment and / or the second embodiment can refer to the above introduction, and will not be repeated later. Figure 3 , Figure 3 This is a schematic diagram of the structure of the metric calculation unit in Embodiment 3 of the recoding metric determination system of the present application.

[0057] like Figure 3 As shown, in the embodiment of the present application, the metric calculation unit is composed of a plurality of metric coding calculation subunits with the same structure connected in sequence, and the serial number of each metric calculation subunit increases in sequence (specifically, it can increase in sequence from 0, that is, the serial number of the first metric subunit is 0). Among them, the number of the metric calculation subunits is the same as the code length value of the order statistics decoder used by the re-encoding metric determination system, that is, the number of the metric calculation subunits is N .

[0058] It should be noted that, for each of the metric calculation subunits, there is a common input port, and the common input port can be connected to the storage unit. Through the common input port, the metric calculation subunit can read the stored data to be encoded from the storage unit.

[0059] It should be explained that, for each of the metric calculation subunits, there may also be two independent input ports and independent output ports corresponding to the independent input ports, namely, a first independent input port, a first independent output port, a second independent input port and a second independent output port.

[0060] The input of the first input port and the output of the first output port can be D dimensional integer vector (the dimension is the same as the order of the order statistics decoder), the input of the second input port and the output of the second output port can be real numbers.

[0061] In some implementations of the embodiments of the present application, the first independent input port of the first metric calculation subunit (that is, the metric calculation subunit with serial number 0) is connected to the combination number generation unit, and the input of the second independent input port of the first metric calculation subunit is fixed to a preset fixed input (the preset fixed input can specifically be "0"). N Metric calculation subunit (that is, serial number N -1 metric calculation subunit) is left unconnected, N The independent output result of the second independent output port of the metric calculation subunit is the codeword metric.

[0062] In some implementations of the present application, the serial number is p (0< p < N ) is connected to the first input port of the metric calculation subunit numbered p -1's first output port of the metric calculation subunit, numbered p The second input port of the metric calculation subunit is connected to p -1. That is, between the second metric calculation subunit and the first N Between the calculation subunits, the first independent input port of the subsequent metric calculation subunit is connected to the first independent output port of the preceding metric calculation subunit, and the second independent input port of the subsequent metric calculation subunit is connected to the second independent output port of the preceding metric calculation subunit.

[0063] It should be understood that, through the above connection method, the output of the first independent output port of the preceding metric calculation subunit can be used as the input of the first independent input port of the subsequent metric calculation subunit, and the output of the second independent output port of the preceding metric calculation subunit can be used as the input of the second independent input port of the subsequent metric calculation subunit. T , the input of the first independent input port of the metric calculation subunit with serial number 0 A (-1, T )= c ( T ), the input of the second independent input port B (-1, T ) = 0, where c ( T )for T After recoding the metric calculation subunit with sequence number 0, the output of the first independent output port can be obtained. A (0, T+1 ) and the output of the second independent output port B (0, T+1), these outputs can be used as inputs of the independent input ports corresponding to the metric calculation subunit with sequence number 1 at the next moment.

[0064] It can be understood that, for the convenience of description, for adjacent metric calculation subunits, the metric calculation subunit with the previous sequence number can be regarded as the previous metric calculation subunit, and the metric calculation subunit with the subsequent sequence number can be regarded as the subsequent metric calculation subunit. Exemplarily, for the ninth metric calculation subunit with the sequence number 8 and the tenth metric calculation subunit with the sequence number 9, the ninth metric calculation subunit can be regarded as the previous metric calculation subunit, and the tenth metric calculation subunit can be regarded as the subsequent metric calculation subunit.

[0065] In some implementations of the embodiments of the present application, at a time corresponding to a certain clock cycle, T , the value of the first independent input port of the metric calculation subunit with serial number p can be recorded as , the value of the second independent input port can be recorded as Since the storage unit can continuously cyclically shift the stored data to be encoded, the input of the common input port is the MRB codeword bit. , hard decision bit , soft information elements , generating the matrix columns .

[0066] It should be noted that each metric calculation subunit can calculate the output at the next moment based on the input at the current moment. T , serial number is p The metric calculation subunit can be based on , and the value of the common input port is calculated and The A output port is calculated as follows: .

[0067] It should be noted that since the XOR operation is performed bit by bit when the matrix is ​​stored in columns, the number of clock cycles required is equal to the value of the code length. N , and in this application, by designing a recoding metric determination system N The metric calculation subunits are used as metric calculation units, so that each metric calculation subunit can be based on the input data bits to be encoded (such as MRB codeword bits) , hard decision bit , soft information elements , generating the matrix ) is calculated, and the time required for each metric calculation subunit to calculate is one clock cycle. Therefore, for the moment corresponding to one clock cycle TThe output of the preceding metric calculation subunit is the time at which the succeeding metric calculation subunit corresponds to the next clock cycle. T +1 for the corresponding input.

[0068] It should be explained that, in order to calculate the output of the second output port, part of the structure of the metric calculation subunit in the embodiment of the present application can be as follows: Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a second independent output port of a metric calculation subunit in one implementation of the present application.

[0069] Reference Figure 4 , the second independent output port in the metric calculation subunit of the embodiment of the present application may include: a plurality of bit selectors, a bit XOR area, a real number selection area, and a real number addition area; The number of bit selectors and the recoding metric determine the encoding order value of the successive statistical encoder used by the system. D same.

[0070] Specifically, the embodiments of the present application can be D indivual K The bit selector generates the matrix for the input Make your selection. i (0≤ i ≤ D )indivual K The bit selector can be configured to select the first independent input port according to the i Elements Select the generator matrix. Less than K When you select Generate Matrix The Elements As the output of the bit selector; Not less than K That is, the bit selector is used to select the matrix element in the generated matrix data as output when the input condition of the input generated matrix data meets the preset input condition; the bit selection area is also used to select the preset element as output when the input condition of the input generated matrix data does not meet the preset condition.

[0071] Furthermore, we can D indivual K The bit selected in the D bits (i.e., the output of each bit selector) and the MRB codeword bits , hard decision bit An XOR operation is performed to obtain a bit XOR result. That is, the bit XOR area is used to perform an XOR operation on the output of the bit selector, the MRB codeword data, and the hard decision data to obtain a bit XOR result.

[0072] Furthermore, a real number selection can be performed based on the bit XOR result. If the bit XOR result is the first XOR result (a "1" bit), the soft information element can be selected. As the real number selection result, it is output to the real number addition area; if the bit XOR result is the second XOR result ("0" bit), the preset real number "0" can be selected as the real number selection result and output to the real number addition area. That is, the real number selection area is used to select the soft information element in the soft information data as the output when the bit XOR result is the first XOR result; the real number selection area is also used to select the preset real number as the output when the bit XOR result is the second XOR result.

[0073] Furthermore, the output of the real number selection area can be connected to the input of the second independent input port. By adding real numbers, you can get the independent output result of the second independent output port. , the independent output result is also the next moment ( T +1 moment) serial number is p The real number addition area is used to add real numbers based on the output of the real number selection area and the input data of the second independent input port to obtain an independent output result of the second independent output port.

[0074] It should be noted that, through the above system, the serial number is N -1's second independent output interface is connected to the codeword metric output. Each metric calculation subunit introduces a clock cycle delay. N The metric calculation subunits introduce N The delay of clock cycles, so for the measurement output subunit, arrive is the effective output of the codeword metric.

[0075] The second independent output port of the metric calculation subunit of the embodiment of the present application includes: a bit selector, a bit XOR area, a real number selection area, and a real number addition area; when the input condition of the input generation matrix data meets the preset input condition, the bit selector selects the matrix element in the generation matrix data as the output; the bit XOR area performs an XOR operation on the output of the bit selector and the MRB codeword data and the hard decision data to obtain a bit XOR result; when the bit XOR result is the first XOR result, the real number selection area selects the soft information element in the soft information data as the output; the real number addition area adds the real number based on the output of the real number selection area and the input data of the second independent input port to obtain the independent output result of the second independent output port. Since N metric calculation subunits are designed, each metric calculation subunit obtains the independent output result of the second independent output port through one clock cycle, and recoding is achieved through N metric calculation subunits, which improves the recoding efficiency.

[0076] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the recoding metric determination system of the present application. More forms of simple transformations based on this technical concept are all within the scope of protection of the present application.

[0077] This application also provides a method for determining a recoding metric, please refer to Figure 5 , Figure 5 This is a flow chart of a method for determining a recoding metric according to an embodiment of the present application. The method for determining a recoding metric is applied to the recoding metric determination system as described above. The recoding metric determination system includes: a storage unit, a combination number generation unit, and a metric determination unit. The method includes: Step S10, the storage unit stores the first data to be encoded when the signal state type of the valid signal is a first preset state type; Step S20, the combination number generating unit generates a combination number vector when the signal state type is changed to a second preset state type; Step S30, when receiving the combination number vector, the metric determination unit reads the stored data to be encoded from the storage unit, where the stored data to be encoded includes the first data to be encoded; Step S40, the storage unit transmits the outputted stored data to be encoded as second data to be encoded back for re-storage; Step S50: the metric determination unit re-encodes based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

[0078] The recoding metric determination method provided by the present application is based on the recoding metric determination system in the above-mentioned embodiment, and can solve the technical problem that the existing order statistics decoder consumes a lot of logical resources and has low operating efficiency when calculating the recoding metric. Compared with the prior art, the beneficial effects of the recoding metric determination method provided by the present application are the same as the beneficial effects of the recoding metric determination system provided by the above-mentioned embodiment, and other technical features in the recoding metric determination method are the same as the features disclosed in the above-mentioned embodiment system, which will not be repeated here.

[0079] The present application also provides an order statistics decoder, in which at least one recoding metric calculation module is provided. The recoding metric calculation module implements recoding and codeword metric calculation functions based on the recoding metric determination system in the above-mentioned embodiment.

[0080] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A recoding metric determination system, characterized in that: The recoding metric determination system comprises: a storage unit, a combination number generation unit and a metric determination unit; The storage unit is used to store the first data to be encoded when the signal state type of the valid signal is the first preset state type; The combination number generating unit is used to generate a combination number vector when the signal state type is a second preset state type; The metric determination unit is configured to read the stored data to be encoded from the storage unit when receiving the combination number vector, wherein the stored data to be encoded includes the first data to be encoded; The storage unit is further used to transmit the outputted stored data to be encoded as second data to be encoded back for re-storage; The metric determination unit is used to perform re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

2. The recoding metric determination system according to claim 1, wherein: The storage unit includes a plurality of storage subunits; The number of the storage subunits is the same as the number of data types included in the data to be encoded; The storage subunit is composed of a selector and a shift register; The input ports of the selector are respectively connected to the effective signal input, the coded data input and the shift register output; The selector is used to obtain the data to be encoded from the data to be encoded input and store the data to be encoded in the shift register when detecting that the valid signal is of the first preset state type; The selector is further used to obtain the stored data to be encoded from the shift register output when it is detected that the valid signal is of the second preset state type, and return the stored data to be encoded as the second data to be encoded to the shift register for re-storage.

3. The recoding metric determination system according to claim 2, wherein: The metric calculation unit is composed of a plurality of metric coding calculation subunits with the same structure connected in sequence; The number of the metric calculation subunits is the same as the code length value of the order statistics decoder applied by the re-encoding metric determination system; Each of the metric calculation subunits has a common input port, and the common input port is connected to the storage unit and is used to read the stored data to be encoded from the storage unit.

4. The recoding metric determination system according to claim 3, wherein: The metric calculation subunit further includes two independent input ports and independent output ports corresponding to the independent input ports, which are respectively a first independent input port, a first independent output port, a second independent input port and a second independent output port; Wherein, the first independent input port of the first metric calculation subunit is connected to the combination number generation unit, and the input of the second independent input port of the first metric calculation subunit is fixed to a preset fixed input; No. N The first independent output port of the metric calculation subunit is left unconnected. N The independent output result of the second independent output port of the metric calculation subunit is the codeword metric; In the second metric calculation subunit to the N Between the calculation subunits, the first independent input port of the subsequent metric calculation subunit is connected to the first independent output port of the preceding metric calculation subunit, and the second independent input port of the subsequent metric calculation subunit is connected to the second independent output port of the preceding metric calculation subunit.

5. The recoding metric determination system according to claim 4, wherein: The data types of the data to be encoded include: MRB codewords, hard decisions, soft information and generator matrices; Correspondingly, the storage subunit includes: an MRB codeword subunit for storing data to be encoded whose data type is an MRB codeword, a hard decision subunit for storing data to be encoded whose data type is a hard decision, a soft information subunit for storing data to be encoded whose data type is soft information, and a generation matrix subunit for storing data to be encoded whose data type is a generation matrix.

6. The recoding metric determination system according to claim 5, wherein: The second independent output port includes: a bit selector, a bit XOR area, a real number selection area and a real number addition area; wherein the number of the bit selectors is the same as the decoding order value of the order statistics decoder applied by the recoding metric determination system; The bit selector is used to select a matrix element in the generated matrix data as output when an input condition of the input generated matrix data meets a preset input condition; The bit XOR area is used to perform an XOR operation on the output of the bit selector, the MRB codeword data, and the hard decision data to obtain a bit XOR result; The real number selection area is used to select the soft information element in the soft information data as output when the bit XOR result is the first XOR result; The real number addition area is used to add real numbers based on the output of the real number selection area and the input data of the second independent input port to obtain an independent output result of the second independent output port.

7. The recoding metric determination system of claim 6, wherein: The bit selection area is further used to select a preset element as output when the input condition of the input generation matrix data does not meet the preset condition; The real number selection area is also used to select a preset real number as output when the bit XOR result is a second XOR result.

8. The recoding metric determination system of claim 1, wherein: The system further comprises: a control unit; The control unit is connected to the storage unit and the combination number generating unit respectively; The control unit is used to monitor the effective signal; The control unit is further configured to generate a start signal when the signal state type is a second preset state type, and send the start signal to the combination number generating unit; The combination number generating unit is further configured to trigger the generation of a combination number vector based on the start signal.

9. A method for determining a recoding metric, characterized in that: The method is applied to a recoding metric determination system according to any one of claims 1 to 8, wherein the recoding metric determination system comprises: a storage unit, a combination number generation unit and a metric determination unit, and the method comprises: The storage unit stores the first data to be encoded when the signal state type of the valid signal is a first preset state type; The combination number generating unit generates a combination number vector when the signal state type is changed to a second preset state type; When receiving the combination number vector, the metric determination unit reads the stored data to be encoded from the storage unit, wherein the stored data to be encoded includes the first data to be encoded; The storage unit transmits the outputted stored data to be encoded as second data to be encoded back for re-storage; The metric determination unit performs re-encoding based on the stored data to be encoded and the combination number vector to obtain a codeword metric.

10. An order statistical decoder, characterized in that: The order statistics decoder is provided with a re-encoding metric determination system as described in any one of claims 1-8.

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