Network port extension method and system
By using processors and Ethernet transceivers in the network interface expansion system, combining RGMII and SRGMII interfaces, the expansion of a single RGMII interface is achieved, solving the problem of insufficient network ports and control isolation in traditional expansion methods, and improving the flexibility and security of network expansion.
Patent Information
- Application Number
- CN202411665148.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-03-14
AI Technical Summary
The traditional network interface expansion method is limited by hardware, so it cannot achieve efficient gigabit network interface expansion, and it cannot independently control and isolate each network interface, and it cannot screen and intercept external data.
Through a network port expansion method and system, the processor, the first Ethernet transceiver and the second Ethernet transceiver are used to achieve the expansion of a single RGMII interface. Through the combination of RGMII and SRGMII interfaces, data packets are divided and distributed to multiple terminal groups to achieve independent control and isolation of each network port.
It realizes the expansion of a single RGMII interface into 7 independently controlled gigabit network ports, which improves the flexibility, reliability and transmission efficiency of network expansion, adapts to more complex network environments and higher application requirements, and improves information security.
Smart Images
Figure CN119629136A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of network communication technology, and in particular to a network port expansion method and system. Background Art
[0002] With the continuous development of network technology, Gigabit network has become a standard configuration in many application scenarios. However, traditional network interface expansion methods are often limited by hardware and cannot achieve efficient Gigabit network port expansion. Therefore, developing a Gigabit network port expansion method, system and device for a single RMII interface is of great significance for improving the flexibility and efficiency of network interface expansion.
[0003] The products in the related technology only extend to the switch through a single network port to forward the network. The disadvantages of this method are high cost, inability to control and isolate each network port, and inability to screen and intercept external data. Summary of the invention
[0004] In view of this, an object of an embodiment of the present invention is to provide a network port expansion method and system, aiming to improve the flexibility, reliability and transmission efficiency of a single RGMII interface in gigabit network expansion.
[0005] On the one hand, an embodiment of the present invention provides a network port expansion method, the method is applied to a network port expansion system, the network port expansion system includes a processor, a first Ethernet transceiver, and a second Ethernet transceiver; the first Ethernet transceiver is connected to the processor through an RGMII interface, and is connected to the second Ethernet transceiver through an SRGMII interface; the first Ethernet transceiver is connected to a first terminal group through an MDI interface, and the second Ethernet transceiver is connected to a second terminal group through an MDI interface; the first terminal group includes 5 terminals, and the second terminal group includes 2 terminals; The method comprises the following steps: The first Ethernet transceiver receives the total data packet sent by the processor through the RGMII interface; The processor determines a first data flow direction of the total data packet, the first Ethernet transceiver divides the total data packet into a first data packet and a second data packet according to the first data flow direction, the first Ethernet transceiver distributes the first data packet to the first terminal group, and distributes the second data packet to the second Ethernet transceiver through the SRGMII interface; The processor determines a second data flow direction of the second data packet, and the second Ethernet transceiver distributes the second data packet to the second terminal group according to the second data flow.
[0006] Optionally, distributing the second data packet to the second Ethernet transceiver through the SRGMII interface includes: The data of the MAC layer of the first Ethernet transceiver is converted into a serial data stream after being encoded, and sent to the PHY layer of the second Ethernet transceiver through the SRGMII interface; The serial data stream received by the PHY layer of the second Ethernet transceiver is restored to the second data packet of the MAC layer after being decoded.
[0007] Optionally, the second Ethernet transceiver distributes the second data packet to the second terminal group according to the second data stream, comprising: The second Ethernet transceiver converts the second data stream into an RGMII signal through a PHY module, and distributes the RGMII signal to two terminals in the second terminal group.
[0008] Optionally, the processor determines the first data flow direction of the total data packet, including: The processor obtains the type, source address and destination address of the total data packet, and determines to distribute the total data packet to the SRGMII interface or the first terminal group according to the type, source address and destination address of the total data packet; The preset priority of each of the total data packets is obtained, and the distribution order of each of the total data packets is determined in descending order according to the priority.
[0009] Optionally, the method further comprises: The processor obtains the type, source address and destination address of the first data packet, and determines to distribute the first data packet to five terminals in the first terminal group according to the type, source address and destination address of the first data packet; The processor obtains the type, source address and destination address of the second data packet, and determines to distribute the second data packet to two terminals in the second terminal group according to the type, source address and destination address of the second data packet; The preset priority of each of the first data packet and the second data packet is obtained, and the distribution order of each of the first data packet and the second data packet is determined in descending order according to the priority.
[0010] On the other hand, an embodiment of the present invention provides a network port expansion system, the network port expansion system comprising a processor, a first Ethernet transceiver, and a second Ethernet transceiver; the first Ethernet transceiver is connected to the processor through an RGMII interface, and is connected to the second Ethernet transceiver through an SRGMII interface; the first Ethernet transceiver is connected to a first terminal group through an MDI interface, and the second Ethernet transceiver is connected to a second terminal group through an MDI interface; the first terminal group includes 5 terminals, and the second terminal group includes 2 terminals; The processor is used to determine a first data flow direction of the total data packet and a second data flow direction of the second data packet; The first Ethernet transceiver is used to receive a total data packet sent by the processor through the RGMII interface; divide the total data packet into a first data packet and a second data packet according to the first data flow direction, distribute the first data packet to the first terminal group, and distribute the second data packet to the second Ethernet transceiver through the SRGMII interface; The second Ethernet transceiver is used to distribute the second data packet to the second terminal group according to the second data flow.
[0011] Optionally, distributing the second data packet to the second Ethernet transceiver through the SRGMII interface includes: The data of the MAC layer of the first Ethernet transceiver is converted into a serial data stream after being encoded, and sent to the PHY layer of the second Ethernet transceiver through the SRGMII interface; The serial data stream received by the PHY layer of the second Ethernet transceiver is restored to the second data packet of the MAC layer after being decoded.
[0012] Optionally, the second Ethernet transceiver is specifically used for: The RGMII signal is converted by the PHY module, and the corresponding second data packet is distributed to two terminals in the second terminal group.
[0013] Optionally, the processor determines the first data flow direction of the total data packet, including: The processor obtains the type, source address and destination address of the total data packet, and determines to distribute the total data packet to the SRGMII interface or the first terminal group according to the type, source address and destination address of the total data packet; The preset priority of each of the total data packets is obtained, and the distribution order of each of the total data packets is determined in descending order according to the priority.
[0014] Optionally, the processor is further configured to: Obtaining a type, a source address, and a destination address of a first data packet, and determining to distribute the first data packet to five terminals in the first terminal group according to the type, the source address, and the destination address of the first data packet; Obtaining a type, a source address, and a destination address of a second data packet, and determining to distribute the second data packet to two terminals in the second terminal group according to the type, the source address, and the destination address of the second data packet; The preset priority of each of the first data packet and the second data packet is obtained, and the distribution order of each of the first data packet and the second data packet is determined in descending order according to the priority.
[0015] The embodiments of the present invention include the following beneficial effects: The present invention can realize the expansion of a single RGMII interface into 7 independently controlled Gigabit network ports through the first Ethernet transceiver and the second Ethernet transceiver, which solves the demand for insufficient network ports of traditional devices, and will significantly improve the flexibility, reliability and transmission efficiency of a single RGMII interface in Gigabit network expansion, so that a single interface can adapt to more complex network environments and higher application requirements. At the same time, it can achieve control and isolation of each network port to improve the information security of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0017] Figure 1 It is a schematic diagram of the steps of a network port expansion method provided by an embodiment of the present invention; Figure 2 The invention discloses a structural block diagram of a network port expansion system. DETAILED DESCRIPTION
[0018] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.
[0019] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".
[0020] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0022] like Figure 1 As shown, an embodiment of the present invention provides a network port expansion method, which is applied to a network port expansion system, wherein the network port expansion system includes a processor, a first Ethernet transceiver, and a second Ethernet transceiver; the first Ethernet transceiver is connected to the processor through an RGMII interface, and is connected to the second Ethernet transceiver through an SRGMII interface; the first Ethernet transceiver is connected to a first terminal group through an MDI interface, and the second Ethernet transceiver is connected to a second terminal group through an MDI interface; the first terminal group includes 5 terminals, and the second terminal group includes 2 terminals; The method comprises the following steps: S100, the first Ethernet transceiver receives a total data packet sent by the processor through the RGMII interface; S200, the processor determines a first data flow direction of the total data packet, the first Ethernet transceiver divides the total data packet into a first data packet and a second data packet according to the first data flow direction, the first Ethernet transceiver distributes the first data packet to the first terminal group, and distributes the second data packet to the second Ethernet transceiver through the SRGMII interface; In this embodiment, by distributing the first data packet to the first terminal group, efficient management of multiple terminals is achieved, and the stability of data transmission is guaranteed. By distributing the second data packet to the SRGMII interface, data diversion processing is achieved, network congestion is effectively reduced, and data processing efficiency is improved.
[0023] S300: The processor determines a second data flow direction of a second data packet, and the second Ethernet transceiver distributes the second data packet to a second terminal group according to the second data flow.
[0024] It should be noted that, in this embodiment, the model of the first Ethernet transceiver and the second Ethernet transceiver is YT9215S, the manufacturer is Yutai Micro, the interface type of the processor is RGMII, the interface types of the first Ethernet transceiver include RGMII and SRGMII, and the interface type of the second Ethernet transceiver is SRGMII; RGMII (Reduced Gigabit Media Independent Interface) is Reduced GMII (Gigabit Media Independent Interface). RGMII uses a 4-bit data interface, a working clock of 125MHz, and transmits data simultaneously on the rising and falling edges, so the transmission rate can reach 1000Mbps. It is generally used for communication between MAC and PHY. SRGMII (Serial Reduced Gigabit Media Independent Interface) is an Ethernet interface standard for connecting the MAC (Media Access Control) layer and PHY (Physical Layer) chip of Gigabit Ethernet. It is a serial interface. Compared with the traditional GMII (Gigabit Media Independent Interface), SRGMII uses fewer pins to achieve data transmission, thereby reducing the number of pins required and is suitable for high-density design. The first data flow direction and the second data flow direction are determined by the processor through the flow control algorithm; the intelligent flow control algorithm can automatically switch the interface protocol according to the device connection status. For example, if a low-speed device is connected, the system will automatically reduce the transmission rate; when a high-speed device is connected, the system will restore the gigabit transmission rate to achieve dynamic adaptation.
[0025] The present invention can realize the expansion of a single RGMII interface into 7 independently controlled Gigabit network ports through the first Ethernet transceiver and the second Ethernet transceiver, which solves the demand for insufficient network ports of traditional devices and significantly improves the flexibility, reliability and transmission efficiency of a single RGMII interface in Gigabit network expansion, so that a single interface can adapt to more complex network environments and higher application requirements. At the same time, it can achieve control and isolation of each network port to improve the information security of the device.
[0026] In some embodiments, distributing the second data packet to the second Ethernet transceiver via the SRGMII interface includes: The data of the MAC layer of the first Ethernet transceiver is converted into a serial data stream after being encoded, and sent to the PHY layer of the second Ethernet transceiver through the SRGMII interface; The serial data stream received by the PHY layer of the second Ethernet transceiver is restored to the second data packet of the MAC layer after being decoded.
[0027] In this embodiment, after being decoded and verified, the second data packet is further processed and distributed to the corresponding independent network port according to the preset flow control strategy, ensuring the optimization of data transmission and smooth communication between terminal devices. The second Ethernet transceiver then accurately sends the processed second data packet to the corresponding terminal group according to the preset data flow direction, ensuring the accuracy and efficiency of data transmission.
[0028] In some embodiments, the second Ethernet transceiver distributes the second data packet to the second terminal group according to the second data flow, including: The second Ethernet transceiver converts the second data stream into an RGMII signal through a PHY module, and distributes the RGMII signal to two terminals in the second terminal group.
[0029] In this embodiment, through the processing of two terminals, not only the bandwidth allocation is optimized, but also the response speed of the network is improved. At the same time, this design can also dynamically adjust the data flow according to the network status to ensure the rational use of network resources and the efficient operation of the system.
[0030] In some embodiments, the processor determines the first data flow direction of the total data packet, including: The processor obtains the type, source address and destination address of the total data packet, and determines to distribute the total data packet to the SRGMII interface or the first terminal group according to the type, source address and destination address of the total data packet; The preset priority of each of the total data packets is obtained, and the distribution order of each of the total data packets is determined in descending order according to the priority.
[0031] In this embodiment, through the distribution strategy of the total data packet, the entire data processing system ensures that high-priority data packets are processed first while also taking into account the effective transmission of low-priority data packets, thereby achieving flexible response to different business needs.
[0032] In some embodiments, the method further comprises: The processor obtains the type, source address and destination address of the first data packet, and determines to distribute the first data packet to five terminals in the first terminal group according to the type, source address and destination address of the first data packet; The processor obtains the type, source address and destination address of the second data packet, and determines to distribute the second data packet to two terminals in the second terminal group according to the type, source address and destination address of the second data packet; The preset priority of each of the first data packet and the second data packet is obtained, and the distribution order of each of the first data packet and the second data packet is determined in descending order according to the priority.
[0033] It should be noted that for the intelligent flow control algorithm, multi-gigabit network port expansion requires flexible flow control, which usually adopts dynamic bandwidth allocation, priority scheduling and other methods. After the total data packet enters the first Ethernet transceiver, the flow control algorithm analyzes the type, source address and destination address of each data packet, and allocates resources according to the preset priority. After the second data packet enters the second Ethernet transceiver, it is also processed by the flow control algorithm to ensure the efficiency and stability of data transmission.
[0034] The following is a specific embodiment of the working process of the present invention: Data reception: The first Ethernet transceiver receives the total data packet sent by the processor through the RGMII interface, and the size of the total data packet is in the gigabit level.
[0035] Data processing and distribution: The first Ethernet transceiver analyzes the total data packet, and the processor determines the data flow direction of the total data packet through an intelligent flow control algorithm, divides the total data packet into a first data packet and a second data packet, and distributes the first data packet to the SRGMII interface and the gigabit interfaces of terminal 1 to terminal 5.
[0036] SRGMII data packaging: The data of the MAC layer of the first Ethernet transceiver is converted into a serial data stream after encoding and sent to the PHY layer of the second Ethernet transceiver through the SRGMII interface. The serial data stream received by the PHY layer of the second Ethernet transceiver is decoded and restored to the second data packet of the MAC layer. The SRGMII interface supports a rate of up to 2.5Gbps, which meets the gigabit rate requirements of Terminal 6 and Terminal 7.
[0037] Distribution of SRGMII interface extended data: The second Ethernet transceiver analyzes the second data packet, the processor determines the data flow through an intelligent flow control algorithm, and distributes the second data packet to the Gigabit interfaces of terminal 6 and terminal 7.
[0038] Signal transmission: The RGMII signal is converted through the PHY module to complete the final transmission of the data packet.
[0039] Monitoring and feedback: The processor continuously monitors the chip transmission link through the standard management protocol (MDIO). Once an error or abnormality is detected, it will initiate fault processing and generate feedback, and automatically cut off the link or switch to the backup link when necessary.
[0040] See also Figure 2 , Figure 2A network port expansion system is provided in an embodiment of the present invention, the network port expansion system comprises a processor, a first Ethernet transceiver, and a second Ethernet transceiver; the first Ethernet transceiver is connected to the processor through an RGMII interface, and is connected to the second Ethernet transceiver through an SRGMII interface; the first Ethernet transceiver is connected to a first terminal group through an MDI interface, and the second Ethernet transceiver is connected to a second terminal group through an MDI interface; the first terminal group includes 5 terminals, and the second terminal group includes 2 terminals; The processor is used to determine a first data flow direction of the total data packet and a second data flow direction of the second data packet; The first Ethernet transceiver is used to receive a total data packet sent by the processor through the RGMII interface; divide the total data packet into a first data packet and a second data packet according to the first data flow direction, distribute the first data packet to the first terminal group, and distribute the second data packet to the second Ethernet transceiver through the SRGMII interface; The second Ethernet transceiver is used to distribute the second data packet to the second terminal group according to the second data flow.
[0041] In some embodiments, distributing the second data packet to the second Ethernet transceiver via the SRGMII interface includes: The data of the MAC layer of the first Ethernet transceiver is converted into a serial data stream after being encoded, and sent to the PHY layer of the second Ethernet transceiver through the SRGMII interface; The serial data stream received by the PHY layer of the second Ethernet transceiver is restored to the second data packet of the MAC layer after being decoded.
[0042] In some embodiments, the second Ethernet transceiver is specifically configured to: The second Ethernet transceiver converts the RGMII signal through the PHY module and distributes the corresponding second data packet to two terminals in the second terminal group.
[0043] In some embodiments, the processor determines the first data flow direction of the total data packet, including: Acquire the type, source address and destination address of the total data packet, and determine to distribute the total data packet to the SRGMII interface or the first terminal group according to the type, source address and destination address of the total data packet; The preset priority of each of the total data packets is obtained, and the distribution order of each of the total data packets is determined in descending order according to the priority.
[0044] In some embodiments, the processor is further configured to: Obtaining a type, a source address, and a destination address of a first data packet, and determining to distribute the first data packet to five terminals in the first terminal group according to the type, the source address, and the destination address of the first data packet; Obtaining a type, a source address, and a destination address of a second data packet, and determining to distribute the second data packet to two terminals in the second terminal group according to the type, the source address, and the destination address of the second data packet; The preset priority of each of the first data packet and the second data packet is obtained, and the distribution order of each of the first data packet and the second data packet is determined in descending order according to the priority.
[0045] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.
[0046] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0047] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.
[0048] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0049] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.
[0050] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0051] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0052] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0053] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0054] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0055] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.
[0056] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but the scope of the rights of the present application is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present application should be within the scope of the rights of the present application.
Claims
1. A network port expansion method, characterized in that: The method is applied to a network port expansion system, which includes a processor, a first Ethernet transceiver, and a second Ethernet transceiver; the first Ethernet transceiver is connected to the processor through an RGMII interface, and is connected to the second Ethernet transceiver through an SRGMII interface; the first Ethernet transceiver is connected to a first terminal group through an MDI interface, and the second Ethernet transceiver is connected to a second terminal group through an MDI interface; the first terminal group includes 5 terminals, and the second terminal group includes 2 terminals; The method comprises the following steps: The first Ethernet transceiver receives the total data packet sent by the processor through the RGMII interface; The processor determines a first data flow direction of the total data packet, the first Ethernet transceiver divides the total data packet into a first data packet and a second data packet according to the first data flow direction, the first Ethernet transceiver distributes the first data packet to the first terminal group, and distributes the second data packet to the second Ethernet transceiver through the SRGMII interface; The processor determines a second data flow direction of the second data packet, and the second Ethernet transceiver distributes the second data packet to the second terminal group according to the second data flow.
2. The method according to claim 1, characterized in that: The distributing the second data packet to the second Ethernet transceiver through the SRGMII interface includes: The data of the MAC layer of the first Ethernet transceiver is converted into a serial data stream after being encoded, and sent to the PHY layer of the second Ethernet transceiver through the SRGMII interface; The serial data stream received by the PHY layer of the second Ethernet transceiver is restored to the second data packet of the MAC layer after being decoded.
3. The method according to claim 1, characterized in that The second Ethernet transceiver distributes the second data packet to the second terminal group according to the second data stream, including: The second Ethernet transceiver converts the second data stream into an RGMII signal through a PHY module, and distributes the RGMII signal to two terminals in the second terminal group.
4. The method according to claim 1, characterized in that: The processor determines a first data flow direction of the total data packet, including: The processor obtains the type, source address and destination address of the total data packet, and determines to distribute the total data packet to the SRGMII interface or the first terminal group according to the type, source address and destination address of the total data packet; The preset priority of each of the total data packets is obtained, and the distribution order of each of the total data packets is determined in descending order according to the priority.
5. The method according to claim 1, characterized in that The method further comprises: The processor obtains the type, source address and destination address of the first data packet, and determines to distribute the first data packet to five terminals in the first terminal group according to the type, source address and destination address of the first data packet; The processor obtains the type, source address and destination address of the second data packet, and determines to distribute the second data packet to two terminals in the second terminal group according to the type, source address and destination address of the second data packet; The preset priority of each of the first data packet and the second data packet is obtained, and the distribution order of each of the first data packet and the second data packet is determined in descending order according to the priority.
6. A network port expansion system, characterized in that: The network port expansion system includes a processor, a first Ethernet transceiver, and a second Ethernet transceiver; the first Ethernet transceiver is connected to the processor via an RGMII interface, and is connected to the second Ethernet transceiver via an SRGMII interface; the first Ethernet transceiver is connected to a first terminal group via an MDI interface, and the second Ethernet transceiver is connected to a second terminal group via an MDI interface; the first terminal group includes 5 terminals, and the second terminal group includes 2 terminals; The processor is used to determine a first data flow direction of the total data packet and a second data flow direction of the second data packet; The first Ethernet transceiver is used to receive a total data packet sent by the processor through the RGMII interface; divide the total data packet into a first data packet and a second data packet according to the first data flow direction, distribute the first data packet to the first terminal group, and distribute the second data packet to the second Ethernet transceiver through the SRGMII interface; The second Ethernet transceiver is used to distribute the second data packet to the second terminal group according to the second data flow.
7. The system according to claim 6, characterized in that The distributing the second data packet to the second Ethernet transceiver through the SRGMII interface includes: The data of the MAC layer of the first Ethernet transceiver is converted into a serial data stream after being encoded, and sent to the PHY layer of the second Ethernet transceiver through the SRGMII interface; The serial data stream received by the PHY layer of the second Ethernet transceiver is restored to the second data packet of the MAC layer after being decoded.
8. The system according to claim 6, characterized in that The second Ethernet transceiver is specifically used for: The RGMII signal is converted by the PHY module, and the corresponding second data packet is distributed to two terminals in the second terminal group.
9. The system according to claim 6, characterized in that Determining the first data flow direction of the total data packet includes: Acquire the type, source address and destination address of the total data packet, and determine to distribute the total data packet to the SRGMII interface or the first terminal group according to the type, source address and destination address of the total data packet; The preset priority of each of the total data packets is obtained, and the distribution order of each of the total data packets is determined in descending order according to the priority.
10. The system according to claim 8, characterized in that The processor is further configured to: Obtaining a type, a source address, and a destination address of a first data packet, and determining to distribute the first data packet to five terminals in the first terminal group according to the type, the source address, and the destination address of the first data packet; Obtaining a type, a source address, and a destination address of a second data packet, and determining to distribute the second data packet to two terminals in the second terminal group according to the type, the source address, and the destination address of the second data packet; The preset priority of each of the first data packet and the second data packet is obtained, and the distribution order of each of the first data packet and the second data packet is determined in descending order according to the priority.