Industrial control system based on fused memory architecture and redundant data communication method

Abstract

The invention provides an industrial control system based on a fused memory architecture and a redundant data communication method, and is applied to the technical field of industrial control. The industrial control system comprises a main controller and a standby controller, and accesses the external memory through a high-speed interface. According to the redundant data communication method, the redundant data are classified and synchronized to the external memory to ensure that the standby controller acquires the data in real time, so that the industrial control system can quickly synchronize necessary redundant data between the main controller and the standby controller, thereby realizing real-time and reliable synchronization of the redundant data, effectively shortening the control period and improving the control efficiency. And the overall performance of the industrial controller is improved.

Description

Technical Field

[0001] The present invention relates to the field of industrial control technology, and in particular to an industrial control system and a redundant data communication method based on a fused memory architecture. Background Art

[0002] In traditional industrial control systems, the main controller and the backup controller synchronize redundant data through serial ports, USB (Universal Serial Bus), and high-speed serdes (Serializer / Deserializer) channels. When a system fails, it is crucial to ensure the synchronization of important data to avoid affecting the connected IO (Input / Output) and instruments. Therefore, the system has higher requirements for the speed, reliability, and real-time performance of redundant communication.

[0003] However, in the traditional architecture, the main controller needs to split, package and send redundant data, and the backup controller needs to receive and process the data, and then move the important information to DDR (Double Data Rate). This process is complicated and time-consuming, which reduces system reliability and makes it difficult to achieve real-time redundancy. At the same time, it occupies CPU (Central Processing Unit) resources, prolongs the control cycle, and increases the burden on the controller.

[0004] Therefore, how to solve the problem of slow synchronization of redundant data transmission in traditional control systems and improve the real-time and reliability of redundant data has become the key to further shortening the control cycle and improving the overall performance of industrial controllers. Summary of the invention

[0005] In view of the above problems, the present invention provides an industrial control system and a redundant data communication method based on a fusion memory architecture that overcome the above problems or at least partially solve the above problems. The technical solution is as follows:

[0006] An industrial control system based on a fusion memory architecture comprises: at least one main controller and at least one backup controller, wherein the main controller and the backup controller are configured to access an external memory through a high-speed signal interface.

[0007] Optionally, the main controller and the standby controller are pluggably installed on the same base via a hot-swap interface;

[0008] A fusion memory circuit is arranged on the base;

[0009] The fusion memory circuit includes a programmable logic chip and the external memory;

[0010] The programmable logic chip is connected to the main controller and the backup controller through the high-speed signal interface to control the access logic of the main controller and the backup controller to the external memory, monitor the operating status of the main controller and the backup controller, and adjust the access of the main controller and the backup controller to the external memory according to different situations to ensure data security.

[0011] Optionally, the main controller and the standby controller are physically located on the same printed circuit board, and the CPUs of the main controller and the standby controller are connected to the same external memory via a T-type topology;

[0012] The T-type topology includes a high-speed bypass switch control chip, wherein the control signal of the high-speed bypass switch control chip, the redundant switching signal of the controller and the active access signal are connected to a logic reset circuit for controlling the access of the main controller and the backup controller to the external memory to avoid access conflicts.

[0013] Optionally, the number of the fusion memory circuit and / or the external memory can be configured as dual backup to prevent the impact of failure of a single storage circuit on system performance.

[0014] Optionally, the programmable logic chip is a field programmable gate array.

[0015] Optionally, the high-speed bypass switch control chip is a MEMS optical switch.

[0016] A redundant data communication method is applied to any of the above industrial control systems, the method comprising:

[0017] Classifying the first redundant data generated by the main controller into controller basic information data, user program redundant data, IO bit number redundant data and non-periodic redundant data in real time;

[0018] Dividing the user program redundant data and the IO bit number redundant data into regular cycle redundant data and fast cycle redundant data;

[0019] Synchronizing the basic information data of the controller to the external memory in each controller cycle, so that the standby controller obtains the basic information data of the controller from the external memory;

[0020] Synchronizing the fast cycle redundant data to the external memory in each fast cycle, so that the standby controller obtains the fast cycle redundant data from the external memory;

[0021] Synchronizing the normal cycle redundant data to the external memory in each controller cycle, so that the standby controller obtains the normal cycle redundant data from the external memory;

[0022] In each controller cycle, it is checked whether there is redundant data to be synchronized in the non-periodic redundant data. If yes, the redundant data to be synchronized is synchronized to the external memory, so that the standby controller obtains the non-periodic redundant data from the external memory.

[0023] Optionally, the external memory is divided into a non-periodic redundant data area, a fast cycle data area and a regular cycle data area, wherein the non-periodic redundant data area is used to store the redundant data to be synchronized, the fast cycle data area is used to store the fast cycle redundant data, and the regular cycle data area is used to store the controller basic information data and the regular cycle redundant data.

[0024] Optionally, the method further includes:

[0025] When the main controller is operating normally, various types of data in the first redundant data generated by the main controller are periodically updated to the programmable logic chip, so that the programmable logic chip stores the data in the external memory and performs verification and protection on the data. The standby controller obtains the first redundant data in the external memory when its CPU is idle; after processing the first redundant data, the standby controller sends the second redundant data generated in real time to the external memory;

[0026] When the main controller fails and a control switch occurs, the programmable logic chip closes the main controller's operating channel to the external memory, while maintaining the refresh operation on the external memory, and opens the backup controller's operating channel to the external memory, to ensure that the control of the external memory is seamlessly switched and that the data in the external memory is not disturbed during the switching process.

[0027] Optionally, the method further includes:

[0028] Connecting the control signal of the high-speed bypass switch control chip, the main controller signal, the standby controller signal and the reserved signal to the logic reset circuit to control the access to the external memory;

[0029] Based on the logic circuit truth table of the logic reset circuit, the authority and path for the external memory are determined according to the control signal of the high-speed bypass switch control chip, the main controller signal, the standby controller signal and the reserved signal.

[0030] By means of the above technical solution, the present invention provides an industrial control system and a redundant data communication method based on a fused memory architecture, wherein the industrial control system includes: at least one main controller and at least one backup controller, and the main controller and the backup controller are configured to access an external memory through a high-speed signal interface. The redundant data communication method includes: classifying the first redundant data generated by the main controller into controller basic information data, user program redundant data, IO bit number redundant data and non-periodic redundant data in real time; dividing the user program redundant data and IO bit number redundant data into regular cycle redundant data and fast cycle redundant data; synchronizing the controller basic information data to the external memory in each controller cycle, so that the standby controller obtains the controller basic information data from the external memory; synchronizing the fast cycle redundant data to the external memory in each fast cycle, so that the standby controller obtains the fast cycle redundant data from the external memory; synchronizing the regular cycle redundant data to the external memory in each controller cycle, so that the standby controller obtains the regular cycle redundant data from the external memory; checking whether there is the first redundant data to be synchronized in the non-periodic redundant data in each controller cycle, and if there is, synchronizing the redundant data to be synchronized to the external memory, so that the standby controller obtains the non-periodic redundant data from the external memory. The present invention can effectively solve the problem of slow synchronization of redundant data transmission in traditional control systems by adopting a fusion memory architecture and an innovative redundant data communication method, realize the real-time and reliability synchronization of redundant data, shorten the control cycle, and thus improve the overall performance of industrial controllers.

[0031] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0033] Figure 1 A schematic diagram showing a system architecture of an industrial control system based on a fusion memory architecture provided by an embodiment of the present invention is shown;

[0034] Figure 2 A schematic diagram showing another system architecture of an industrial control system based on a fusion memory architecture provided by an embodiment of the present invention is shown;

[0035] Figure 3A schematic diagram showing another system architecture of an industrial control system based on a fusion memory architecture provided by an embodiment of the present invention is shown;

[0036] Figure 4 A schematic diagram showing a flow chart of an implementation of a redundant data communication method provided by an embodiment of the present invention;

[0037] Figure 5 A circuit diagram of a logic reset circuit provided by an embodiment of the present invention is shown;

[0038] Figure 6 A schematic diagram showing a truth table of a logic reset circuit provided in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0039] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0040] In traditional industrial control systems, the main controller and the standby controller usually synchronize data through redundant data channels, such as serial ports, USB (Universal Serial Bus), and high-speed serdes (Serializer / Deserializer) channels. When a system failure occurs and redundant switching is required, it is particularly important to ensure the synchronization of important real-time data and fast-cycle data to avoid adverse effects on the downstream IO (Input / Output) and instruments. Therefore, the control system places higher requirements on the rate, reliability, and real-time performance of redundant communication between the main and standby cards.

[0041] Under the traditional controller hardware architecture, the main controller needs to split and package the redundant data, and then send it out through the communication interface of the CPU (Central Processing Unit); the standby controller receives the redundant data through the communication interface of its CPU, and performs parsing, verification and splitting. Subsequently, the CPU of the standby card needs to move the important data to the DDR (Double Data Rate) so that redundant switching can be performed when necessary. This process is time-consuming and complex, resulting in low system reliability and difficulty in achieving true real-time redundancy. In addition, this redundant data synchronization method occupies a certain amount of CPU resources and prolongs the control cycle time, increasing the burden on the controller.

[0042] In the existing technical solutions, the main and standby cards of traditional industrial controllers use independent memories. When redundant backup is required, the data must be packaged and transferred from the memory of the main controller to the memory of the standby controller, and then the standby controller processes and transfers it to DDR. This process not only occupies system resources, but also consumes control cycle time. Therefore, there is an urgent need for a communication method that can effectively improve the efficiency of redundant communication to achieve fast and effective synchronization of redundant data.

[0043] The current general solution has the disadvantages of limited transmission bandwidth due to the transmission channel rate and large delay, and cannot achieve true real-time redundancy. The redundancy cycle takes too long, taking up a lot of control cycle time, making it difficult to further shorten the control cycle, thus limiting the application of control systems in some scenarios with high control cycle requirements.

[0044] Based on this, the embodiment of the present invention realizes fast and efficient synchronization of redundant data by introducing an innovative fusion memory architecture and an improved redundant communication data processing method. While retaining the traditional redundant communication method as a backup channel, the fusion memory hardware architecture is adopted to enable the industrial control system to quickly synchronize the necessary redundant data between the main controller and the backup controller, thereby ensuring the timeliness of the redundant data and effectively shortening the control cycle.

[0045] like Figure 1 As shown, a schematic diagram of a system architecture of an industrial control system based on a fused memory architecture provided by an embodiment of the present invention, the system may include: at least one main controller and at least one backup controller, the main controller and the backup controller are configured to access an external memory through a high-speed signal interface.

[0046] Among them, the main controller is the core control unit of the system, which is used to perform major control tasks and logical operations. The main controller processes input signals, executes control algorithms, and generates output signals to operate the equipment. The main controller can process data at high speed and efficiency to ensure the normal operation and performance optimization of the system.

[0047] The backup controller is a redundant component of the system, which is used to improve the reliability and fault tolerance of the system. When the main controller fails or needs maintenance, the backup controller can take over the control task to ensure the continuous operation of the system. The backup controller is usually synchronized with the main controller to be ready to take over its responsibilities at any time.

[0048] Among them, the high-speed signal interface is the communication channel between the main controller and the backup controller and the external memory. The high-speed signal interface provides fast data transmission capability, ensures that the controller can access the required data in real time, and supports high-frequency data exchange. Optionally, the high-speed signal interface can be an interface such as PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus) and USART (Universal Synchronous / Asynchronous Receiver / Transmitter) that allows the main controller and the backup controller to exchange data with the external memory in a high-bandwidth and low-latency manner.

[0049] Among them, the external memory is a random access memory (RAM), which is used to store various types of data required in the control system, including program code, real-time operation data, etc. Due to its high-speed read and write characteristics, the external memory allows the controller to quickly access and update data, thereby improving the response speed and processing power of the system. In the embodiment of the present invention, the external memory is used as a fusion memory between the main controller and the backup controller, thereby directly integrating the traditional redundant data replication function into the fusion memory, which not only improves the real-time performance of the data, but also shortens the redundant switching time and control cycle, thereby significantly improving the control performance. The external memory can include various types of memory chips, such as DDR (Double Data Rate) chips, SRAM (Static Random-Access Memory) chips, etc.

[0050] Optionally, the main controller and the backup controller may be connected via a backup redundant channel to prevent system downtime.

[0051] Among them, the standby redundant channel is a communication path directly connected between the main controller and the standby controller. It is used to achieve data synchronization through the standby redundant channel when the main channel composed of the external memory or high-speed signal interface fails or is under maintenance. When a main channel failure is detected, the system can quickly switch to the standby channel. This fast switching mechanism reduces the downtime caused by communication interruption and improves the continuity and reliability of the system. The standby redundant channel significantly improves the reliability and stability of the system by providing additional communication paths and fast fault switching capabilities, thereby preventing system downtime at critical moments.

[0052] Optional, based on Figure 1 The system architecture shown in Figure 2As shown, a schematic diagram of another system architecture of an industrial control system based on a fused memory architecture provided by an embodiment of the present invention is shown, wherein a main controller and a backup controller are pluggably installed on the same base through a hot-swap interface; a fused memory circuit is arranged on the base; the fused memory circuit includes a programmable logic chip and an external memory; the programmable logic chip is connected to the main controller and the backup controller through a high-speed signal interface to control the access logic of the main controller and the backup controller to the external memory, and monitor the operating status of the main controller and the backup controller, and adjust the access of the main controller and the backup controller to the external memory according to different situations to ensure data security.

[0053] Among them, the hot-swap interface is an interface technology that allows devices to be inserted or removed during system operation without turning off the system power, making the addition, replacement or maintenance of devices more flexible and convenient. In industrial control systems, the use of hot-swap interfaces can reduce system downtime and improve the maintainability and availability of equipment. For example, when a controller needs to be replaced or upgraded, the operation can be performed without affecting the overall operation of the system.

[0054] Optionally, the number of fusion memory circuits and / or external memories can be configured as dual backup to prevent the impact of failure of a single storage circuit on system performance.

[0055] Among them, a programmable logic chip is an integrated circuit containing configurable logic units, and users can define its functions through programming as needed. Programmable logic chips can include various types of chips, such as FPGA (Field-Programmable Gate Array), CPLD (Complex Programmable Logic Device), and some SoC (System on Chip) that meet the requirements. These chips all have programmable features, allowing users to define and configure their functions according to specific needs to achieve flexible logic control and management.

[0056] The main controller and backup controller in the industrial control system can be conveniently installed on the same base through the hot-swap interface. The base integrates a fusion memory circuit, which is composed of a programmable logic chip (such as FPGA) and an external RAM (such as DDR). In addition to having independent RAM, the main controller and the backup controller are also connected to the programmable logic chip through a high-speed signal interface (such as PCIe or high-speed USB). This logic chip is responsible for managing the access logic of the main controller and the backup controller to the fusion memory and monitoring their operating status in real time. According to the operation of the system, the logic chip can dynamically adjust the access path to the external RAM to ensure data security. Through this architecture, the main controller and the backup controller can be flexibly hot-swapped and replaced through a high-speed interface to meet the needs of field applications. At the same time, multiple backup fusion memories can be set according to the requirements of the system to prevent the impact of memory circuit failure on controller performance.

[0057] Optional, based on Figure 1 The system architecture shown in Figure 3 As shown, a schematic diagram of another system architecture of an industrial control system based on a fusion memory architecture provided by an embodiment of the present invention is shown, wherein the main controller and the backup controller are physically located on the same printed circuit board, and the CPUs of the main controller and the backup controller are connected to the same external memory through a T-type topology; the T-type topology includes a high-speed bypass switch control chip, wherein the control signal of the high-speed bypass switch control chip, the redundant switching signal of the controller, and the active access signal are connected to a logic reset circuit for controlling the access of the main controller and the backup controller to the external memory to avoid access conflicts.

[0058] Among them, the printed circuit board is a board used to support and connect electronic components. It has pre-laid conductive paths on it, which can realize the electrical connection between electronic components. The printed circuit board provides the basic structure required for mechanical support and wiring.

[0059] Among them, the high-speed bypass switch control chip is a chip used to switch access paths between different controllers. The high-speed bypass switch control chip can quickly manage and control the switch of the data channel, thereby allowing one controller to access the external memory while the other controller is on standby to avoid conflicts caused by simultaneous access. Optionally, the high-speed bypass switch control chip can be a MEMS (Micro-Electro-Mechanical Systems) optical switch.

[0060] Among them, the control signal is an electrical signal used to manage the operation of the device on the circuit board. It can transmit instructions or conditions to coordinate and control the functions and states of different components in the system.

[0061] The redundant switching signal is a signal for switching between the main controller and the standby controller. When the main controller fails, the redundant switching signal triggers the standby controller to take over the task to ensure the continuity and reliability of the system.

[0062] The active access signal is used to indicate that a controller is currently accessing the external memory. The active access signal ensures that when one controller performs an access operation, other controllers will not interfere or attempt to access at the same time, thereby avoiding data conflicts.

[0063] The logic reset circuit is used to manage the initialization and reset operations of the system. The logic reset circuit is configured to dynamically adjust the access path to the external memory according to the control signal. By receiving the control signal, the redundant switching signal and the active access signal, the logic reset circuit can ensure that the system is in a known state during the startup or switching process, preventing unnecessary access conflicts and data corruption.

[0064] The main controller and the backup controller are physically integrated on the same printed circuit board, and the CPUs of the main controller and the backup controller are connected to the same external memory through a T-type topology. The T-type topology includes a high-speed bypass switch control chip, and the control signal of the chip, the redundant switching signal of the controller, and the active access signal are all connected to the logic reset circuit. This design is used to manage the access of the main controller and the backup controller to the external memory to prevent access conflicts.

[0065] The embodiment of the present invention provides a redundant data communication method, which is applied to the above industrial control system. Figure 4 As shown, a flowchart of an implementation of a redundant data communication method provided by an embodiment of the present invention is provided. The method may include:

[0066] S400, classifying the first redundant data generated by the main controller into controller basic information data, user program redundant data, IO bit number redundant data and non-periodic redundant data in real time.

[0067] The controller basic information data is the core data related to the operation of the controller itself. The controller basic information data may include basic information such as hardware status, system configuration, firmware version and operation status to ensure the basic operation and maintenance management of the system.

[0068] The user program redundant data is a backup of the program or logic control information configured by the user on the controller. The user program redundant data may include user-defined control logic, algorithms, and configuration parameters, etc., to ensure the integrity of the user-defined program in the event of a failure or when recovery is required.

[0069] The IO bit number redundant data is the status information of the external device connected to the controller. The IO bit number redundant data may include the status of sensors and actuators, the numbers and corresponding relationships of input and output signals, to ensure that the IO signals can be correctly identified and processed when the redundant system switches.

[0070] Among them, non-periodic redundant data refers to redundant information that is not updated at a fixed period. Non-periodic redundant data can include event-driven data, historical records, and alarm logs. Non-periodic redundant data is usually generated under specific events or conditions to ensure that the system can obtain the required additional information when an abnormality or specific operation occurs.

[0071] S410, dividing the user program redundant data and the IO bit number redundant data into normal cycle redundant data and fast cycle redundant data.

[0072] The embodiment of the present invention can determine the synchronization frequency of data according to the importance and change speed of data in the industrial control system, and further divide the user program redundant data and IO bit number redundant data into regular cycle redundant data and fast cycle redundant data.

[0073] Among them, regular cycle redundant data is synchronized and updated according to the standard operating cycle of the controller. It usually refers to the data synchronized in each complete controller cycle (for example: 100 milliseconds, 500 milliseconds, etc.). Regular cycle redundant data is usually used for parameters and status information that change slowly or do not need to be updated immediately, such as some user program logic, set parameters, configuration status, etc. This synchronization frequency is suitable for the operation requirements of most control systems to ensure the stability of the system and the efficient use of resources.

[0074] Among them, fast cycle redundant data needs to be synchronized in a shorter time interval, usually updated in each fast control cycle (for example, within a few milliseconds). Fast cycle redundant data is used for those parts that change rapidly and have high requirements for system real-time performance, such as high-frequency changing sensor readings, emergency control signals, etc., to ensure that the system can respond quickly to external changes and improve the real-time control performance of the system.

[0075] S420, synchronizing the basic information data of the controller to the external memory in each controller cycle, so that the standby controller obtains the basic information data of the controller from the external memory.

[0076] S430 , synchronizing the fast cycle redundant data to the external memory in each fast cycle, so that the standby controller obtains the fast cycle redundant data from the external memory.

[0077] S440, synchronizing the normal cycle redundant data to the external memory in each controller cycle, so that the standby controller obtains the normal cycle redundant data from the external memory.

[0078] S450 . Check in each controller cycle whether there is redundant data to be synchronized in the non-periodic redundant data. If yes, execute step S460 .

[0079] S460: Synchronize the redundant data to be synchronized to the external memory, so that the standby controller obtains the non-periodic redundant data from the external memory.

[0080] Specifically, in each controller cycle, the embodiment of the present invention checks whether there is redundant data to be synchronized in the non-periodic redundant data. If redundant data to be synchronized is found, it will be synchronized to the external memory. In this way, the standby controller can obtain these non-periodic redundant data from the external memory.

[0081] The embodiment of the present invention can achieve a more efficient synchronization mechanism for the industrial control system by carefully classifying and processing the first redundant data generated by the main controller, that is, dividing it into controller basic information data, user program redundant data, IO bit number redundant data and non-periodic redundant data, and further dividing the user program redundant data and IO bit number redundant data into regular cycle redundant data and fast cycle redundant data. In each control cycle, the basic information data of the controller and the regular cycle redundant data are synchronized, and the fast cycle redundant data is synchronized in each fast cycle, ensuring that the standby controller can obtain the latest data in a timely manner. In addition, by regularly checking and synchronizing the non-periodic redundant data, the standby controller can quickly obtain the necessary information when it detects the need. This strategy enables the synchronization of the real-time and reliability of redundant data, thereby effectively shortening the control cycle and significantly improving the overall performance of the industrial controller.

[0082] Optionally, the embodiment of the present invention can process 1000 pieces of non-periodic redundant data in one controller cycle. In each control cycle, the embodiment of the present invention checks whether there is redundant data that needs to be synchronized in the non-periodic redundant data, and can process up to an upper limit of 1000 pieces. In each control cycle, the redundancy module extracts as much redundant data to be synchronized as possible from the data buffer for synchronization.

[0083] Optionally, the embodiment of the present invention removes the redundant data that has been sent from the data buffer only after the standby controller confirms the received non-periodic redundant data in the next controller cycle, so as to ensure the accuracy and consistency of the data.

[0084] Optionally, the external memory is divided into a non-periodic redundant data area, a fast cycle data area and a regular cycle data area, wherein the non-periodic redundant data area is used to store redundant data to be synchronized, the fast cycle data area is used to store fast cycle redundant data, and the regular cycle data area is used to store controller basic information data and regular cycle redundant data.

[0085] In the embodiment of the present invention, the storage space can be divided into three different areas in advance in the external memory: a non-periodic redundant data area, a fast cycle data area and a regular cycle data area. The redundant data to be synchronized detected from the non-periodic redundant data in each controller cycle is stored in the non-periodic redundant data area. The regular cycle redundant data is stored in the regular cycle data area in each controller cycle. The fast cycle redundant data is stored in the fast cycle data area in each fast cycle.

[0086] The embodiment of the present invention can effectively manage and access different types of redundant data by dividing the storage space of the external memory, and reasonably allocate resources according to the update frequency and importance of the redundant data.

[0087] Optionally, in an embodiment of the present invention, when the main controller is operating normally, various types of data in the first redundant data generated by the main controller can be periodically updated to the programmable logic chip, so that the programmable logic chip stores the data in an external memory and verifies and protects the data. The backup controller obtains the first redundant data in the external memory when its CPU is idle; after processing the first redundant data, the backup controller sends the second redundant data generated in real time to the external memory.

[0088] When the main controller is working normally, various redundant data will be periodically updated to the programmable logic chip. The programmable logic chip is responsible for storing these data in the external memory and verifying and protecting the data. The standby controller will obtain the first redundant data from the external memory during the idle time of its CPU.

[0089] After processing the first redundant data, the standby controller sends the generated second redundant data to the external memory in real time. The second redundant data mainly includes the configuration status, fault diagnosis status and other relevant information of the standby controller. After each cycle, the main controller will prepare and send real-time redundant data to the programmable logic chip, and the standby controller will ensure that the reception and processing of these data are completed before the next cycle arrives. In this way, the standby controller can process the real-time redundant data from the main controller shortly after the start of the cycle, and send its own real-time redundant data after processing.

[0090] To facilitate understanding of the control logic of programmable logic chips, Xilinx FPGA is used as an example for explanation: When the hardware is configured as data redundancy, the FPGA chip uses the MIG IP core to control the DDR interface to achieve data interaction with DDR storage. After power-on, the FPGA completes the initialization of DDR and enters the working state, and the hardware pins determine whether it is in the working or standby state.

[0091] The CPU of the main controller can write real-time data to the internal cache of the FPGA and notify the FPGA to move data by writing the starting address, length, and data move enable of the data frame in the register space. The FPGA then moves the data from the internal cache to the DDR. The CPU of the backup controller can also write real-time data to the internal cache of the FPGA, but the data move function cannot be enabled.

[0092] For the CPUs of the main and standby controllers, the configuration of the external memory is determined at power-on, so during normal operation, the FPGA needs to simulate a normally started external memory to prevent the CPU from reporting errors. When the main controller is working normally, the FPGA receives various types of data sent by the main CPU and fills them into the corresponding external RAM area. During this period, the FPGA also simulates the CPU of the standby controller as a normally working external memory, allowing it to perform read and write operations. However, the FPGA will block the data operation of the standby controller and only allow the main controller to perform actual data reading and writing. To prevent errors in the operation of the standby controller, the FPGA will provide correct feedback on the operation instructions issued by the standby controller.

[0093] When the main controller fails and a control switch occurs, the programmable logic chip closes the main controller's operating channel to the external memory, while maintaining the refresh operation on the external memory, and opens the backup controller's operating channel to the external memory, to ensure that the control of the external memory is seamlessly switched and the data in the external memory is not disturbed during the switching process.

[0094] When the main controller fails and control switching is required, the programmable logic chip will close the main controller's operating channel to the external memory. At the same time, the programmable logic chip will continue to perform refresh operations on the external memory (for example, for memories such as DDR that require periodic refresh). Then, the operating channel of the backup controller is opened, thereby ensuring that the control of the external memory can be seamlessly switched, and during the switching process, the data in the external memory will not be disturbed.

[0095] The embodiment of the present invention ensures the consistency and integrity of the data by periodically updating the first redundant data generated by the main controller to the programmable logic chip during normal operation of the main controller, storing the data in an external memory, and performing data verification and protection at the same time. This enables the backup controller to obtain the redundant data from the external memory when the CPU is idle, and to process and update the second redundant data generated by itself to the external memory when necessary. When the main controller fails and needs to switch control, the programmable logic chip effectively shuts down the main controller's access to the external memory, while maintaining its refresh operation and opening the operation channel of the backup controller. This mechanism ensures that the control of the external memory can be seamlessly switched and that the data will not be disturbed during the switching process. Through this method, the industrial control system achieves rapid synchronization between the main and standby controllers, ensures the real-time and reliability synchronization of redundant data, thereby effectively shortening the control cycle and improving the overall performance of the industrial controller.

[0096] Optionally, an embodiment of the present invention can connect the control signal of the high-speed bypass switch control chip, the main controller signal, the backup controller signal and the reserved signal to the logic reset circuit to control access to the external memory; based on the logic circuit truth table of the logic reset circuit, the permissions and paths for the external memory are determined according to the combination of the control signal of the high-speed bypass switch control chip, the main controller signal, the backup controller signal and the reserved signal.

[0097] Figure 5 The figure shows a circuit diagram of a logic reset circuit, in which the control signal of the high-speed bypass switch control chip, the main controller signal, the standby controller signal and the reserved signal are connected to the logic reset circuit to manage access rights to the external memory.

[0098] Figure 6 The figure shows the truth table of the logic reset circuit. Through the truth table of the logic reset circuit, the access path and permission settings for the external memory can be clearly defined according to different combinations of these signals. In practical applications, the logic configuration of these control signals can be flexibly adjusted according to specific needs to optimize system performance.

[0099] In the embodiment of the present invention, by connecting the control signal of the high-speed bypass switch control chip, the main controller signal, the backup controller signal and the reserved signal to the logic reset circuit, the system can effectively manage the access rights to the external memory. The logic reset circuit uses a truth table to determine the access rights and paths according to the combination of these signals. This method ensures that the access rights of the external memory can be quickly adjusted under different operating conditions to meet the needs of the main controller and the backup controller. This mechanism significantly improves the efficiency of data synchronization, so that the redundant data between the main controller and the backup controller can be quickly and accurately updated and shared, ensuring the real-time and reliability of the data. This optimization not only shortens the control cycle, but also improves the performance of the entire industrial control system.

[0100] Although operations are depicted in a particular order, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order.Multitasking and parallel processing may be advantageous under certain circumstances.

[0101] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0102] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatuses, electronic devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable device to generate a machine, so that the instructions executed by the processor of the computer or other programmable device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0103] In the description of the present invention, it should be understood that the terms "up", "down", "front", "back", "left" and "right" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the positions or elements referred to must have specific directions, be constructed and operate in specific directions. Therefore, they should not be understood as limitations of the present invention.

[0104] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. It should also be noted that the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0105] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0106] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An industrial control system based on a fusion memory architecture, characterized in that: include: At least one main controller and at least one backup controller, the main controller and the backup controller are configured to access an external memory through a high-speed signal interface.

2. The industrial control system according to claim 1, characterized in that: The main controller and the standby controller are pluggably installed on the same base via a hot-swap interface; A fusion memory circuit is arranged on the base; The fusion memory circuit includes a programmable logic chip and the external memory; The programmable logic chip is connected to the main controller and the backup controller through the high-speed signal interface to control the access logic of the main controller and the backup controller to the external memory, monitor the operating status of the main controller and the backup controller, and adjust the access of the main controller and the backup controller to the external memory according to different situations to ensure data security.

3. The industrial control system according to claim 1, characterized in that: The main controller and the standby controller are physically located on the same printed circuit board, and the CPUs of the main controller and the standby controller are connected to the same external memory via a T-type topology; The T-type topology includes a high-speed bypass switch control chip, wherein the control signal of the high-speed bypass switch control chip, the redundant switching signal of the controller and the active access signal are connected to a logic reset circuit for controlling the access of the main controller and the backup controller to the external memory to avoid access conflicts.

4. The industrial control system according to claim 2, characterized in that: The number of the fusion memory circuit and / or the external memory can be configured as double backup to prevent the impact of failure of a single storage circuit on system performance.

5. The industrial control system according to claim 2, characterized in that: The programmable logic chip is a field programmable gate array.

6. The industrial control system according to claim 3, characterized in that: The high-speed bypass switch control chip is a MEMS optical switch.

7. A redundant data communication method, characterized in that: Applied to the industrial control system according to any one of claims 1 to 6, the method comprises: Classifying the first redundant data generated by the main controller into controller basic information data, user program redundant data, IO bit number redundant data and non-periodic redundant data in real time; Dividing the user program redundant data and the IO bit number redundant data into regular cycle redundant data and fast cycle redundant data; Synchronizing the basic information data of the controller to the external memory in each controller cycle, so that the standby controller obtains the basic information data of the controller from the external memory; Synchronizing the fast cycle redundant data to the external memory in each fast cycle, so that the standby controller obtains the fast cycle redundant data from the external memory; Synchronizing the normal cycle redundant data to the external memory in each controller cycle, so that the standby controller obtains the normal cycle redundant data from the external memory; In each controller cycle, it is checked whether there is redundant data to be synchronized in the non-periodic redundant data. If yes, the redundant data to be synchronized is synchronized to the external memory, so that the standby controller obtains the non-periodic redundant data from the external memory.

8. The method according to claim 7, characterized in that The external memory is divided into a non-periodic redundant data area, a fast cycle data area and a regular cycle data area, wherein the non-periodic redundant data area is used to store the redundant data to be synchronized, the fast cycle data area is used to store the fast cycle redundant data, and the regular cycle data area is used to store the controller basic information data and the regular cycle redundant data.

9. The method according to any one of claims 7 to 8, characterized in that Also includes: When the main controller is operating normally, various types of data in the first redundant data generated by the main controller are periodically updated to the programmable logic chip, so that the programmable logic chip stores the data in the external memory and performs verification and protection on the data. The standby controller obtains the first redundant data in the external memory when its CPU is idle; after processing the first redundant data, the standby controller sends the second redundant data generated in real time to the external memory; When the main controller fails and a control switch occurs, the programmable logic chip closes the main controller's operating channel to the external memory, while maintaining the refresh operation on the external memory, and opens the backup controller's operating channel to the external memory, to ensure that the control of the external memory is seamlessly switched and that the data in the external memory is not disturbed during the switching process.

10. The method according to any one of claims 7 to 8, characterized in that Also includes: Connecting the control signal of the high-speed bypass switch control chip, the main controller signal, the standby controller signal and the reserved signal to the logic reset circuit to control the access to the external memory; Based on the logic circuit truth table of the logic reset circuit, the authority and path for the external memory are determined according to the control signal of the high-speed bypass switch control chip, the main controller signal, the standby controller signal and the reserved signal.

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