Multi-path PAL system video data transmission system, method and terminal

Abstract

The invention belongs to the technical field of data transmission, and particularly discloses a multipath PAL system video data transmission system and method, and a terminal. According to the method and the device, the multi-channel video data with the first bit width and the synchronizing signal are obtained by analyzing the original multi-channel PAL system video data, and the clock frequency of the multi-channel video data with the first bit width is improved by using the first cross-clock domain processing module to obtain the multi-channel synchronous video data stream with the second clock frequency; and combining the multiple paths of synchronous video data streams into the same channel for transmission. And finally, in combination with a data analysis cache module, a PAL system video synchronization information reconstruction module and a second cross-clock domain processing module, performing data analysis ping-pong cache, PAL system video synchronization information reconstruction and clock reduction processing on the merged synchronization video data stream to complete inter-board high-speed serial transmission of multiple paths of PAL system videos. The transmission rate between multi-path PAL system video boards is effectively improved, and the number of IO interfaces is reduced.

Description

Technical Field

[0001] The present application belongs to the technical field of data transmission, and more specifically, relates to a multi-channel PAL format video data transmission system, method and terminal. Background Art

[0002] Phase Alteration Line (PAL) belongs to the simultaneous system. It adopts phase alternation line by line for one of the two color difference signals transmitted simultaneously, and performs orthogonal modulation on the other color difference signal. In this way, if phase distortion occurs during signal transmission, the two adjacent lines of signals will compensate each other due to the opposite phases, thereby effectively overcoming the color change caused by phase distortion. Therefore, the PAL system is not sensitive to phase distortion and the image color error is small. At present, the PAL system still plays an important role in the field of multi-channel low-resolution analog video transmission and military infrared video. Since PAL video data is often used in the field of multi-channel integrated optical frequency and vehicle-mounted video splicing, the research on high-speed transmission methods of multi-channel PAL video is still of great significance.

[0003] At present, multi-channel PAL video data transmission is usually achieved through multi-channel parallel IO interfaces. The video transmission rate is limited to 27M, the random clock of the PAL video data, and a large amount of IO interface resources are consumed. Summary of the invention

[0004] In view of the defects of the prior art, the purpose of this application is to provide a multi-channel PAL video data transmission system and terminal, aiming to solve the problems of low multi-channel PAL video data transmission rate and large number of IO interfaces occupied in the prior art.

[0005] To achieve the above objectives, in a first aspect, the present application provides a multi-channel PAL video data transmission system, comprising:

[0006] The interface protocol analysis module is used to analyze the original multi-channel PAL video data to obtain the first-bit width multi-channel video data and synchronization signal;

[0007] A first cross-clock domain processing module is used to increase the clock frequency of the received multi-channel video data of the first bit width from the first clock frequency to the second clock frequency to obtain a multi-channel synchronous video data stream of the second clock frequency;

[0008] A multi-channel contention transmission processing module, used for merging multiple synchronous video data streams of the second clock frequency into the same channel for transmission to obtain a merged synchronous video data stream;

[0009] A data parsing and caching module is used to obtain and cache multi-channel video payload data according to the combined synchronous video data stream and the channel number and line number of the original multi-channel PAL format video data;

[0010] A PAL video synchronization information reconstruction module is used to read multiple video payload data and embed synchronization signals and blanking period data to obtain multiple PAL video data of a second clock frequency;

[0011] The second cross-clock domain processing module is used to reduce the clock frequency of the received multi-channel PAL video data with the second clock frequency to the first clock frequency to obtain original multi-channel PAL video data.

[0012] In some embodiments, it also includes:

[0013] The bit width expansion module is used to expand the bit width of the multi-channel synchronous video data stream of the second clock frequency from the first bit width to the second bit width, obtain the multi-channel synchronous video data stream of the second bit width at the second clock frequency, and transmit the multi-channel synchronous video data stream of the second bit width at the second clock frequency to the multi-channel competition transmission processing module.

[0014] In some embodiments, it also includes:

[0015] The bit width reduction module is used to reduce the bit width of the received merged synchronous video data stream from the second bit width to the first bit width, obtain the merged synchronous video data stream of the first bit width, and transmit the merged synchronous video data stream of the first bit width to the data parsing cache module.

[0016] In some embodiments, it also includes:

[0017] A SERDES protocol encoding and sending module is used to encode the received merged synchronous video data stream to obtain encoded data, and transmit the encoded data to a SERDES protocol decoding and receiving module;

[0018] The SERDES protocol decoding and receiving module is used to decode the encoded data to obtain a combined synchronous video data stream, and transmit the combined synchronous video data stream to the bit width reduction module.

[0019] In some embodiments, the first cross-clock domain processing module is further configured to:

[0020] The clock frequency of the multi-channel video data with the first bit width is increased from the first clock frequency to the second clock frequency to obtain a multi-channel video data stream with the second clock frequency, and according to the synchronization signal, the frame header information including the channel number and the line number is embedded into the multi-channel video data stream with the second clock frequency, and the blanking period data is stripped to obtain a multi-channel synchronous video data stream with the second clock frequency.

[0021] In some embodiments, the multi-channel contention transmission processing module is further configured to:

[0022] Multiple synchronous FIFO buffers are used to cache multiple synchronous video data streams with a second clock frequency, and read enable signals of multiple synchronous FIFO buffers are controlled by a multi-channel competitive transmission processing state machine to merge the multiple synchronous video data streams with the second clock frequency into the same channel for transmission, thereby obtaining a merged synchronous video data stream.

[0023] In some embodiments, the multi-channel contention transmission processing module is further configured to:

[0024] Generate a K code and an idle code, embed the K code and the idle code into the combined synchronous video data stream, and then transmit it to the SERDES protocol encoding and sending module.

[0025] In some embodiments, the synchronization signal includes:

[0026] Line synchronization signal, field synchronization signal, data enable signal and parity field signal.

[0027] In a second aspect, the present application provides a multi-channel PAL video data transmission method, which is applied to the multi-channel PAL video data transmission system described in the first aspect or any of the embodiments of the first aspect, comprising: parsing original multi-channel PAL video data through an interface protocol parsing module to obtain multi-channel video data and a synchronization signal with a first bit width;

[0028] The clock frequency of the received multi-channel video data of the first bit width is increased from the first clock frequency to the second clock frequency by the first cross-clock domain processing module to obtain a multi-channel synchronous video data stream of the second clock frequency;

[0029] The multi-channel competition transmission processing module combines the multiple synchronous video data streams of the second clock frequency into the same channel for transmission to obtain a combined synchronous video data stream;

[0030] The data parsing and caching module obtains and caches the multi-channel video payload data according to the merged synchronous video data stream, the channel number and the line number of the original multi-channel PAL format video data;

[0031] The PAL video synchronization information reconstruction module reads the multi-channel video payload data and embeds the synchronization signal and the blanking period data to obtain the multi-channel PAL video data of the second clock frequency;

[0032] The second cross-clock domain processing module is used to reduce the clock frequency of the received multi-channel PAL video data with the second clock frequency to the first clock frequency to obtain the original multi-channel PAL video data.

[0033] In a third aspect, the present application provides a terminal, comprising a multi-channel PAL video data transmission system as described in the first aspect or any embodiments of the first aspect.

[0034] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0035] The multi-channel PAL video data transmission system method and terminal provided in the embodiment of the present application parse the original multi-channel PAL video data to obtain the multi-channel video data and synchronization signal of the first bit width, use the first cross-clock domain processing module to increase the clock frequency of the multi-channel video data of the first bit width, obtain the multi-channel synchronous video data stream of the second clock frequency, and merge the multi-channel synchronous video data stream into the same channel for transmission. Finally, in combination with the data parsing cache module, the PAL video synchronization information reconstruction module and the second cross-clock domain processing module, the merged synchronous video data stream is subjected to data parsing ping-pong cache, PAL video synchronization information reconstruction and clock reduction processing to complete the high-speed serial transmission between boards of multi-channel PAL video. Effectively improve the transmission rate between boards of multi-channel PAL video and reduce the number of IO interfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is one of the structural schematic diagrams of the multi-channel PAL video data transmission system provided in the embodiment of the present application;

[0037] Figure 2 This is the second structural diagram of the multi-channel PAL video data transmission system provided in the embodiment of the present application;

[0038] Figure 3 This is the third structural diagram of the multi-channel PAL video data transmission system provided in the embodiment of the present application;

[0039] Figure 4 It is a state jump diagram of a 2-channel contention transmission processing state machine provided in an embodiment of the present application;

[0040] Figure 5 It is a schematic diagram of a PAL video data synchronization information reconstruction process provided by an embodiment of the present application;

[0041] Figure 6 It is a flowchart of a multi-channel PAL video data transmission method provided in an embodiment of the present application;

[0042] Figure 7 It is a schematic diagram of the structure of the terminal provided in the embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0045] The terms "first", "second", etc. in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first clock frequency and a second clock frequency are used to distinguish different clock frequencies rather than to describe a specific order of the clock frequencies.

[0046] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0047] In the description of the embodiments of the present application, unless otherwise specified, "multi-channel" means two or more channels. For example, multiple channels of PAL video data refer to two or more channels of PAL video data.

[0048] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0049] See also Figure 1 The embodiment of the present application provides a multi-channel PAL video data transmission system, including: an interface protocol analysis module 10, a first cross-clock domain processing module 20, a multi-channel competition transmission processing module 30, a data analysis and cache module 40, a PAL video synchronization information reconstruction module 50 and a second cross-clock domain processing module 60.

[0050] The interface protocol analysis module 10 is used to analyze the original multi-channel PAL video data to obtain the first bit width multi-channel video data and synchronization signal;

[0051] A first cross-clock domain processing module 20 is used to increase the clock frequency of the received multi-channel video data of the first bit width from the first clock frequency to the second clock frequency to obtain a multi-channel synchronous video data stream of the second clock frequency;

[0052] A multi-channel contention transmission processing module 30, used for merging multiple synchronous video data streams of the second clock frequency into a same channel for transmission to obtain a merged synchronous video data stream;

[0053] The data parsing and caching module 40 is used to obtain and cache the multi-channel video payload data according to the merged synchronous video data stream and the channel number and line number of the original multi-channel PAL format video data;

[0054] A PAL video synchronization information reconstruction module 50 is used to read multiple video payload data and embed synchronization signals and blanking period data to obtain multiple PAL video data of a second clock frequency;

[0055] The second cross-clock domain processing module 60 is used to reduce the clock frequency of the received multi-channel PAL video data with the second clock frequency to the first clock frequency to obtain original multi-channel PAL video data.

[0056] In the embodiment of the present application, it is assumed that original N channels of PAL video data are accessed, where N is an integer greater than or equal to 2. The clock frequency of the original N channels of PAL video data is a first clock frequency, and illustratively, the first clock frequency is 27 MHz.

[0057] Please see further Figure 2 , the interface protocol parsing module can be a BT656 interface protocol parsing module.

[0058] The received original N-channel PAL video data is transmitted to the BT656 interface protocol parsing module, and the BT656 interface protocol parsing module parses the original N-channel PAL video data into N-channel video data and synchronization signals of the first parallel bit width. In the embodiment of the present application, the first bit width is 8 bits.

[0059] Further, in some embodiments, the synchronization signal includes:

[0060] Line synchronization signal, field synchronization signal, data enable signal and parity field signal.

[0061] In an embodiment of the present application, the synchronization signals obtained after the BT656 interface protocol parsing module parses the original N-channel PAL video data include a line synchronization signal HS, a field synchronization signal VS, an odd and even field signal FID, and a data enable signal DE.

[0062] The BT656 interface protocol parsing module transmits the N-channel standard video data and synchronization signal of the first bit width to the first cross-clock domain processing module. The first cross-clock domain processing module increases the clock frequency of the N-channel standard video data of the first bit width from the first clock frequency 27MHz to the second clock frequency, and obtains the N-channel synchronous video data stream of the second clock frequency. Exemplarily, the second clock frequency is 125MHz, and the first cross-clock domain processing module is a 27M->125M cross-clock domain processing module.

[0063] It should be noted that the bit width of the N-channel synchronous video data streams at the second clock frequency obtained after being processed by the above 27M->125M cross-clock domain processing module is still the first bit width.

[0064] Furthermore, in some embodiments, the first cross-clock domain processing module is further configured to:

[0065] The clock frequency of the multi-channel video data with the first bit width is increased from the first clock frequency to the second clock frequency to obtain a multi-channel video data stream with the second clock frequency, and according to the synchronization signal, the frame header information including the channel number and the line number is embedded into the multi-channel video data stream with the second clock frequency, and the blanking period data is stripped to obtain a multi-channel synchronous video data stream with the second clock frequency.

[0066] Please continue to see Figure 2 After the obtained N-channel PAL video data with the first bit width in parallel are sent to the 27M->125M cross-clock domain processing module, the 27M->125M cross-clock domain processing module increases the clock frequency of the N-channel PAL video data with the first bit width from the original first clock frequency (i.e., 27MHz) to the second clock frequency (i.e., 125MHz) through an asynchronous first-in, first-out (FIFO) buffer, obtains N-channel second data with the second clock frequency, and embeds the frame header information including the channel number and line number of the original N-channel PAL video data into the above-mentioned N-channel second data, strips the blanking period data through the data enable signal DE in the synchronization signal, removes invalid data transmission, and finally obtains the N-channel synchronous video data stream with the second clock frequency.

[0067] The 27M->125M cross-clock domain processing module transmits the N-channel synchronous video data streams of the second clock frequency to the multi-channel competitive transmission processing module. The multi-channel competitive transmission processing module merges the N-channel synchronous video data streams of the second clock frequency into the same channel for transmission to obtain a merged synchronous video data stream.

[0068] Furthermore, in some embodiments, the multi-channel contention transmission processing module is further configured to:

[0069] Multiple synchronous FIFO buffers are used to cache multiple synchronous video data streams with a second clock frequency, and read enable signals of multiple synchronous FIFO buffers are controlled by a multi-channel competitive transmission processing state machine to merge the multiple synchronous video data streams with the second clock frequency into the same channel for transmission, thereby obtaining a merged synchronous video data stream.

[0070] In an embodiment of the present application, N synchronous FIFOs are used to cache N synchronous video data streams of the second clock frequency, and the read enable signals of the N synchronous FIFOs are controlled by a multi-channel competitive transmission processing state machine to merge the 32-bit N synchronous video data streams into the same channel for transmission, with a data bit width of 32 bits.

[0071] The data parsing and caching module parses out multi-channel video payload data from the merged synchronous video data stream received from the multi-channel competitive transmission processing module according to the channel number and line number of the original multi-channel PAL video data, and performs ping-pong caching through 2N FIFOs, waiting for the PAL video data synchronization information reconstruction module to read it.

[0072] The PAL video synchronization information reconstruction module reads multi-channel video payload data from 2N FIFOs, embeds synchronization signals and blanking period data, obtains multi-channel PAL video data of the second clock frequency, and transmits it to the second cross-clock domain processing module.

[0073] The second cross-clock domain processing module is used to reduce the clock frequency of the received multi-channel PAL video data of the second clock frequency from the second clock frequency 125MHz to the first clock frequency 27MHz to obtain the original multi-channel PAL video data. Exemplarily, the second cross-clock domain processing module can be a 125M->27M cross-clock domain processing module.

[0074] The multi-channel PAL video data transmission system provided by the embodiment of the present application parses the original multi-channel PAL video data to obtain the first-bit width multi-channel video data and synchronization signal, uses the first cross-clock domain processing module to increase the clock frequency of the first-bit width multi-channel video data, obtains the second clock frequency multi-channel synchronous video data stream, and merges the multi-channel synchronous video data stream into the same channel for transmission. Finally, in combination with the data parsing cache module, the PAL video synchronization information reconstruction module and the second cross-clock domain processing module, the merged synchronous video data stream is subjected to data parsing ping-pong cache, PAL video synchronization information reconstruction and clock reduction processing, to complete the high-speed serial transmission between boards of multi-channel PAL video. Effectively improve the transmission rate between boards of multi-channel PAL video and reduce the number of IO interfaces.

[0075] Furthermore, in some embodiments, the multi-channel PAL video data transmission system further includes:

[0076] The bit width expansion module is used to expand the bit width of the multi-channel synchronous video data stream of the second clock frequency from the first bit width to the second bit width, obtain the multi-channel synchronous video data stream of the second bit width at the second clock frequency, and transmit the multi-channel synchronous video data stream of the second bit width at the second clock frequency to the multi-channel competition transmission processing module.

[0077] Please continue to see Figure 2 In order to further improve the transmission rate between multi-channel PAL video boards, in the embodiment of the present application, the multi-channel PAL video data transmission system further includes a bit width expansion module. The input end of the bit width expansion module is connected to the output end of the 27M->125M cross-clock domain processing module, and the output end of the bit width expansion module is connected to the input end of the multi-channel competition processing module.

[0078] As can be seen from the above, the bit width of the N-channel synchronous video data stream of the second clock frequency output by the 27M->125M cross-clock domain processing module is the first bit width, that is, 8-bit bit width. In the embodiment of the present application, the bit width expansion module can adopt an 8bit-32bit bit width conversion module. The bit width of the N-channel synchronous video data stream of the second clock frequency is converted from the first bit width (8bit bit width) to the second bit width (32bit bit width) by the 8bit-32bit bit width conversion module, increasing the data transmission bandwidth, and obtaining an N-channel synchronous video data stream with a bit width of 32bit at 125MHz.

[0079] The 8-bit to 32-bit bit width conversion module transmits the N-channel synchronous video data streams with a bit width of 32 bits at 125 MHz to the multi-channel competition transmission processing module. The multi-channel competition transmission processing module merges the N-channel synchronous video data streams with a bit width of 32 bits at 125 MHz into the same channel for transmission, and obtains the merged synchronous video data stream.

[0080] Furthermore, in some embodiments, the multi-channel PAL video data transmission system further includes:

[0081] The bit width reduction module is used to reduce the bit width of the received merged synchronous video data stream from the second bit width to the first bit width, obtain the merged synchronous video data stream of the first bit width, and transmit the merged synchronous video data stream of the first bit width to the data parsing cache module.

[0082] In the embodiment of the present application, the multi-channel PAL video data transmission system further includes a bit width reduction module.

[0083] The bit width reduction module is connected to the multi-channel contention transmission processing module, and can be used to reduce the bit width of the merged synchronous video data stream sent by the received multi-channel contention transmission processing module from the second bit width (32 bits) to the first bit width (8 bits), thereby obtaining an 8-bit merged synchronous video data stream. Exemplarily, the bit width reduction module can be a 32-bit to 8-bit bit width conversion module.

[0084] The 32-bit-8-bit bit width conversion module transmits the obtained 8-bit merged synchronous video data stream to the data parsing cache module.

[0085] The multi-channel PAL video data transmission system provided in the embodiment of the present application increases the data transmission bandwidth by adding a bit width expansion module, thereby further improving the transmission rate of the multi-channel PAL video data.

[0086] Furthermore, in some embodiments, the multi-channel PAL video data transmission system further includes:

[0087] A SERDES protocol encoding and sending module is used to encode the received merged synchronous video data stream to obtain encoded data, and transmit the encoded data to a SERDES protocol decoding and receiving module;

[0088] The SERDES protocol decoding and receiving module is used to decode the encoded data to obtain a combined synchronous video data stream, and transmit the combined synchronous video data stream to the bit width reduction module.

[0089] Please continue to see Figure 2 The multi-channel PAL video data transmission system also includes a SERDES protocol encoding and sending module and a SERDES protocol decoding and receiving module.

[0090] Among them, the input end of the SERDES protocol encoding and sending module is connected to the output end of the multi-channel competition transmission processing module, the output end of the SERDES protocol encoding and sending module is connected to the input end of the SERDES protocol decoding and receiving module, and the output end of the SERDES protocol decoding and receiving module is connected to the input end of the bit width reduction module.

[0091] The SERDES protocol encoding and sending module can be used to encode the combined synchronous video data stream sent by the received multi-channel competition processing module to obtain encoded data, and transmit the encoded data to the SERDES protocol decoding and receiving module through the GTX high-speed interface.

[0092] The SERDES protocol decoding and receiving module can be used to perform SERDES protocol analysis on the received coded data to obtain a merged synchronous video data stream, and send the merged synchronous video data stream to the above-mentioned bit width reduction module.

[0093] Furthermore, in some embodiments, the multi-channel contention transmission processing module is further configured to:

[0094] Generate a K code and an idle code, embed the K code and the idle code into the combined synchronous video data stream, and then transmit it to the SERDES protocol encoding and sending module.

[0095] In the embodiment of the present application, the K code and idle code required by the SERDES protocol encoding and sending module to encode the merged synchronous video data stream are generated by the above-mentioned multi-channel competition transmission processing module according to the enable signal. In the embodiment of the present application, the K code and the idle code are both 4 bits wide. Among them, the K code refers to a special character used to control and indicate the protocol level, and the idle code refers to a special code used to indicate "no data transmission" in SERDES transmission.

[0096] The multi-channel contention transmission processing module embeds the generated K code and idle code into the merged synchronous video data stream and transmits it to the SERDES protocol encoding and sending module. The SERDES protocol encoding and sending module performs 8B / 10B encoding on the received K code and idle code in the merged synchronous video data stream to obtain encoded data.

[0097] The multi-channel PAL video transmission system provided by the embodiment of the present application aims at the problems of low inter-board transmission rate and large IO interface occupation of traditional multi-channel PAL video. After the sending board performs 27M->125M clock acceleration, 8-32 bit width expansion, and multi-channel PAL video data competition merging into one high-speed serial processing on the original PAL video, the inter-board transmission is performed, and 32-8 bit width conversion, multi-channel data analysis and multi-channel ping-pong buffering, PAL video data synchronization information, clock, and bit width reconstruction are performed in the receiving board, and finally the original multi-channel PAL video is restored, and the inter-board high-speed serial transmission of the multi-channel PAL video is completed. The inter-board transmission rate of the multi-channel PAL video is effectively improved, and the number of IO interfaces is reduced.

[0098] Exemplarily, the present application provides a multi-channel PAL video data transmission system. A preferred embodiment of the present application is given below in conjunction with the accompanying drawings. The embodiment is completed by two boards (board A and board B), where board A is a sending board and board B is a receiving board. Both boards are equipped with Fudan Micro JFM7K325T900-2FPGA. The FPGAs between the two boards are connected via a high-speed connector FMA-060-01-LD-DP-AZ. All modules are integrated in two FPGAs. The specific scheme is as follows: Figure 3 As shown, the specific plan includes the following parts:

[0099] 1.BT656 interface protocol parsing module;

[0100] 2.27M->125M cross-clock domain processing module;

[0101] 3.8bit-32bit bit width conversion module;

[0102] 4. Multi-channel competition transmission processing module;

[0103] 5.SERDES protocol encoding sending module;

[0104] 6. Complete inter-board transmission of SERDES protocol through GTX high-speed interface;

[0105] 7.SERDES protocol decoding receiving module;

[0106] 8.32bit-8bit bit width conversion;

[0107] 9.Data parsing cache module;

[0108] 10. PAL video data synchronization information reconstruction module;

[0109] 11.125M->27M cross-clock domain processing module;

[0110] 12. Complete inter-board high-speed serial transmission of multi-channel PAL video data.

[0111] in:

[0112] Please continue to see Figure 3 , BT656 interface protocol parsing module:

[0113] In the FPGA of board A, the BT656 interface protocol parsing module receives the original 2-channel PAL video data, and parses the original 2-channel PAL video data into parallel 8-bit width video data (PAL1 and PAL2) and 2 groups of 4 synchronization information with a bit width of 1, the synchronization information includes: the first line synchronization signal HS1, the first field synchronization signal VS1, the first data enable signal DE1 and the first parity field signal FID1, the second line synchronization signal HS2, the second field synchronization signal VS2, the second data enable signal DE2 and the second parity field signal FID2;

[0114] 27M->125M cross-clock domain processing module:

[0115] In the FPGA of board A, an asynchronous clock FIFO is added for the first video data PLA1 and the second video data PLA2. The write clock signal interface of the FIFO is connected to the 27MHz on-chip clock of the original PAL video data, and the read clock signal interface of the FIFO is connected to the 125MHz clock. The line synchronization signal, field synchronization signal, and odd and even field signal obtained in the BT656 interface protocol parsing module are used to obtain the line number by counting, and the frame header information including the channel number and the line number is embedded in the data. The blanking period data is stripped through the data enable signal DE, and invalid data transmission is removed to obtain two synchronous video data streams.

[0116] 8bit-32bit bit width conversion module:

[0117] In the FPGA of board A, a FIFO with a clock of 125M, a write bit width of 8bit, and a read bit width of 32bit is added to the first and second synchronous video data streams to complete the bit width expansion from 8bit to 32bit. The write enable signal is controlled by the enable signal in the 27M->125M cross-clock domain processing module, and the read clock is controlled by the empty signal. The data transmission bandwidth is increased through the 8bit-32bit bit width conversion module.

[0118] Multi-channel contention transmission processing module:

[0119] Add two synchronous FIFOs with a clock frequency of 125M to the FPGA of board A to cache two channels of video data after bit width expansion. The design is as follows: Figure 4 The multi-channel contention transmission processing state machine shown controls the read enable signals of two synchronous FIFOs. The multi-channel contention transmission processing state machine is divided into three states, namely, an idle state, a one-channel transmission and two-channel waiting state, and a one-channel waiting and two-channel transmission state.

[0120] (1) Idle state: The read enable signals of the two synchronous FIFOs output by the state machine are all low. If the empty signal of the first channel FIFO has a falling edge and the empty signal of the second channel FIFO is high in this state, the state machine will enter the (2) one channel transmission and two channels waiting state. If the empty signal of the second channel FIFO has a falling edge and the empty signal of the first channel FIFO is high in this state, the state machine will enter the (3) one channel waiting and two channels transmission state.

[0121] (2) One channel transmits, two channels wait state: The state machine outputs the one channel FIFO read enable high, and the two channel FIFO read enable low. If in this state, the empty signal of the one channel FIFO has a rising edge and the empty signal of the two channel FIFO is high, the state machine enters the (1) idle state. If in this state, the empty signal of the one channel FIFO has a rising edge and the empty signal of the two channel FIFO is low, the state machine enters the (3) one channel waits for two channels to transmit state.

[0122] (3) One channel waiting for two channels to transmit: The state machine outputs the read enable of the FIFO of the first channel, which is pulled low, and the read enable of the FIFO of the second channel, which is pulled high. If the empty signal of the FIFO of the second channel has a rising edge in this state and the empty signal of the FIFO of the first channel is high, the state machine enters the (1) idle state. If the empty signal of the FIFO of the second channel has a rising edge in this state and the empty signal of the FIFO of the first channel is low, the state machine enters the (2) one channel waiting for two channels to transmit.

[0123] Combine 2 channels of PAL video data into the same channel for transmission, with a data width of 32 bits, and generate 4-bit wide K code and idle code according to the enable signal, with the K code set to 3 and the idle code set to 060504BC;

[0124] SERDES protocol encoding sending module:

[0125] The SERDES protocol encoding and sending function is completed with the help of the hard core resource GT_wizard IP core in the JFM7K325T900-2FPGA.

[0126] Complete inter-board transmission of SERDES protocol through GTX high-speed interface;

[0127] The SERDES protocol data stream is transmitted through the inter-board connector FMA-060-01-LD-DP-AZ.

[0128] SERDES protocol decoding receiving module:

[0129] The SERDES protocol decoding and receiving function is completed with the help of the hard core resource GT_wizard IP core in the JFM7K325T900-2FPGA. The data stream is transmitted into board B to obtain a 32-bit wide data stream and the corresponding enable signal.

[0130] 32bit-8bit bit width conversion module:

[0131] In the FPGA of board B, a FIFO with a clock of 125M, a write bit width of 32 bits, and a read bit width of 8 bits is added to each of the two video channels to complete the bit width expansion from 8 bits to 32 bits. The write enable signal is controlled by the enable signal decoded in the SERDES protocol decoding receiving module, and the read clock is controlled by the empty signal. The data transmission bandwidth is increased by bit width conversion.

[0132] Data parsing cache module:

[0133] In the FPGA of board B, the channel number and line number in the frame header information of the data stream obtained by the 32-bit-8-bit bit width conversion module are parsed to obtain two channels of PAL video data, and four FIFOs are added to form two groups of ping-pong caches. The write enable is controlled by the empty signal in the 32-bit-8-bit bit width conversion module to cache the two channels of video payload data.

[0134] PAL video data synchronization information reconstruction module:

[0135] In the FPGA of board B, if Figure 5 As shown, according to the standard PAL video data protocol, the write enable signal is controlled, the video payload data of each channel is read from the FIFO in the data parsing cache module, and the synchronization signal and blanking period data are embedded to obtain two channels of PAL video data at 125MHz.

[0136] 125M->27M cross-clock domain processing module:

[0137] In the FPGA of board B, an asynchronous clock FIFO is added for the first PAL video data and the second PAL video data at 125MHz. The write clock signal interface of the FIFO is connected to the on-channel clock 125M of the PAL video data, and the read clock signal interface of the FIFO is connected to the 27M clock. The write enable signal of the FIFO is controlled by the FIFO read signal in the data analysis cache module, and the write enable is controlled by the empty signal of the FIFO.

[0138] Finally, high-speed serial transmission of multiple PAL video data between boards is completed.

[0139] The multi-channel PAL video data transmission system provided in the embodiment of the present application encodes and decodes data through a SERDES protocol encoding and sending module and a SERDES protocol decoding and receiving module to ensure that the data can be transmitted stably, accurately and efficiently.

[0140] The following describes a multi-channel PAL video data transmission method provided in an embodiment of the present application. The multi-channel PAL video data transmission method described below can be applied to the multi-channel PAL video data transmission system described above.

[0141] Please see further Figure 6 The embodiment of the present application provides a multi-channel PAL video data transmission method, which may include: steps 110 to 160.

[0142] Step 110: parse the original multi-channel PAL video data through the interface protocol parsing module to obtain the first bit width multi-channel video data and synchronization signal;

[0143] Step 120: The clock frequency of the received multi-channel video data of the first bit width is increased from the first clock frequency to the second clock frequency by the first cross-clock domain processing module, so as to obtain a multi-channel synchronous video data stream of the second clock frequency;

[0144] Step 130 combines the multiple synchronous video data streams of the second clock frequency into the same channel for transmission through the multi-channel competition transmission processing module to obtain a combined synchronous video data stream;

[0145] Step 140: Obtain and cache the multi-channel video payload data according to the merged synchronous video data stream, the channel number and the line number of the original multi-channel PAL format video data through the data parsing and caching module;

[0146] Step 150 reads the multi-channel video payload data and embeds the synchronization signal and the blanking period data through the PAL video synchronization information reconstruction module to obtain the multi-channel PAL video data of the second clock frequency;

[0147] Step 160 uses a second cross-clock domain processing module to reduce the clock frequency of the received multi-channel PAL video data with the second clock frequency to the first clock frequency to obtain original multi-channel PAL video data.

[0148] The multi-channel PAL video data transmission method provided in the embodiment of the present application parses the original multi-channel PAL video data to obtain the first-bit width multi-channel video data and synchronization signal, uses the first cross-clock domain processing module to increase the clock frequency of the first-bit width multi-channel video data, obtains the second clock frequency multi-channel synchronous video data stream, and merges the multi-channel synchronous video data stream into the same channel for transmission. Finally, in combination with the data parsing cache module, the PAL video synchronization information reconstruction module and the second cross-clock domain processing module, the merged synchronous video data stream is subjected to data parsing ping-pong cache, PAL video synchronization information reconstruction and clock reduction processing, to complete the high-speed serial transmission between boards of multi-channel PAL video. Effectively improve the transmission rate between boards of multi-channel PAL video and reduce the number of IO interfaces.

[0149] Please see further Figure 7 , an embodiment of the present application provides a terminal 70, which may include the multi-channel PAL video data transmission system described above.

[0150] A terminal provided by an embodiment of the present application parses the original multi-channel PAL video data to obtain the first-bit width multi-channel video data and synchronization signal, uses the first cross-clock domain processing module to increase the clock frequency of the first-bit width multi-channel video data, obtains the second clock frequency multi-channel synchronous video data stream, and merges the multi-channel synchronous video data stream into the same channel for transmission. Finally, in combination with the data parsing cache module, the PAL video synchronization information reconstruction module and the second cross-clock domain processing module, the merged synchronous video data stream is subjected to data parsing ping-pong cache, PAL video synchronization information reconstruction and clock reduction processing, to complete the high-speed serial transmission between boards of multi-channel PAL video. Effectively improve the transmission rate between boards of multi-channel PAL video, and reduce the number of IO interfaces.

[0151] It should be understood that expressions such as "including" and "may include" that may be used in the present application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In the present application, terms such as "including" and / or "having" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0152] In addition, in the present application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0153] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the relative position relationship after connection remains unchanged. "Rotational connection" means that the two are connected to each other and can rotate relative to each other after connection. "Sliding connection" means that the two are connected to each other and can slide relative to each other after connection. The directional terms mentioned in the embodiments of the present application, such as "top", "bottom", "inside", "outside", "left", "right", etc., are only reference directions of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0154] In addition, in the embodiments of the present application, the mathematical concepts mentioned are symmetry, equality, parallelism, verticality, etc. These limitations are all for the current state of the art, rather than being absolutely strict definitions in a mathematical sense, and allow a small amount of deviation, approximation to symmetry, approximation to equality, approximation to parallelism, approximation to verticality, etc. are all possible. For example, A and B are parallel, which means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. A and B are perpendicular, which means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0155] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A multi-channel PAL video data transmission system, characterized in that: include: The interface protocol analysis module is used to analyze the original multi-channel PAL video data to obtain the first-bit width multi-channel video data and synchronization signal; A first cross-clock domain processing module, used for increasing the clock frequency of the received multi-channel video data of the first bit width from a first clock frequency to a second clock frequency, so as to obtain a multi-channel synchronous video data stream of the second clock frequency; A multi-channel contention transmission processing module, used for merging multiple synchronous video data streams of the second clock frequency into a same channel for transmission to obtain a merged synchronous video data stream; A data parsing and caching module, used to obtain and cache multi-channel video payload data according to the merged synchronous video data stream and the channel number and line number of the original multi-channel PAL format video data; A PAL video synchronization information reconstruction module, used for reading the multi-channel video payload data and embedding the synchronization signal and the blanking period data to obtain the multi-channel PAL video data of the second clock frequency; The second cross-clock domain processing module is used to reduce the clock frequency of the received multi-channel PAL video data with the second clock frequency to the first clock frequency to obtain the original multi-channel PAL video data.

2. The multi-channel PAL video data transmission system as claimed in claim 1, characterized in that: Also includes: The bit width expansion module is used to expand the bit width of the multi-channel synchronous video data stream of the second clock frequency from the first bit width to the second bit width, obtain the multi-channel synchronous video data stream of the second bit width at the second clock frequency, and transmit the multi-channel synchronous video data stream of the second bit width at the second clock frequency to the multi-channel competition transmission processing module.

3. The multi-channel PAL video data transmission system as claimed in claim 2, characterized in that: Also includes: The bit width reduction module is used to reduce the bit width of the received merged synchronous video data stream from the second bit width to the first bit width to obtain the merged synchronous video data stream of the first bit width, and transmit the merged synchronous video data stream of the first bit width to the data parsing cache module.

4. The multi-channel PAL video data transmission system as claimed in claim 3, characterized in that: Also includes: A SERDES protocol encoding and sending module is used to encode the received merged synchronous video data stream to obtain encoded data, and transmit the encoded data to a SERDES protocol decoding and receiving module; The SERDES protocol decoding and receiving module is used to decode the encoded data to obtain the merged synchronous video data stream, and transmit the merged synchronous video data stream to the bit width reduction module.

5. The multi-channel PAL video data transmission system as claimed in claim 1, characterized in that: The first cross-clock domain processing module is also used for: The clock frequency of the multi-channel video data of the first bit width is increased from the first clock frequency to the second clock frequency to obtain a multi-channel video data stream of the second clock frequency, and according to the synchronization signal, the frame header information including the channel number and the row number is embedded into the multi-channel video data stream of the second clock frequency, and the blanking period data is stripped to obtain a multi-channel synchronous video data stream of the second clock frequency.

6. The multi-channel PAL video data transmission system as claimed in claim 1, characterized in that: The multi-channel contention transmission processing module is also used for: The multi-channel synchronous video data streams of the second clock frequency are cached through multiple synchronous FIFO buffers, and the read enable signals of the multiple synchronous FIFO buffers are controlled through a multi-channel competitive transmission processing state machine to merge the multi-channel synchronous video data streams of the second clock frequency into the same channel for transmission, thereby obtaining the merged synchronous video data stream.

7. The multi-channel PAL video data transmission system as claimed in claim 4, characterized in that: The multi-channel contention transmission processing module is also used for: A K code and an idle code are generated, and the K code and the idle code are embedded into the merged synchronous video data stream and then transmitted to the SERDES protocol encoding and sending module.

8. The multi-channel PAL video data transmission system as claimed in claim 1, characterized in that: The synchronization signal includes: Line synchronization signal, field synchronization signal, data enable signal and parity field signal.

9. A method for transmitting multi-channel PAL video data, characterized in that: The multi-channel PAL video data transmission system according to any one of claims 1 to 8 comprises: The original multi-channel PAL video data is parsed through the interface protocol parsing module to obtain the first-bit width multi-channel video data and synchronization signal; The clock frequency of the received multi-channel video data of the first bit width is increased from a first clock frequency to a second clock frequency by a first cross-clock domain processing module to obtain a multi-channel synchronous video data stream of the second clock frequency; Merging the multiple synchronous video data streams of the second clock frequency into the same channel for transmission through a multi-channel competition transmission processing module to obtain a merged synchronous video data stream; Obtain and cache the multi-channel video payload data according to the merged synchronous video data stream and the channel number and line number of the original multi-channel PAL format video data through the data parsing and caching module; The PAL video synchronization information reconstruction module reads the multi-channel video payload data and embeds the synchronization signal and the blanking period data to obtain the multi-channel PAL video data of the second clock frequency; The second cross-clock domain processing module is used to reduce the clock frequency of the received multi-channel PAL video data with the second clock frequency to the first clock frequency to obtain the original multi-channel PAL video data.

10. A terminal, characterized in that: It comprises a multi-channel PAL video data transmission system as claimed in any one of claims 1 to 8.

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