Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a frame area surrounding the display area. The display panel comprises a first wiring structure and at least one second wiring structure. The first wiring structure comprises a first signal line and a second signal line. The first signal line is arranged in the display area and extends from the display area to the frame area. The second signal line and the first signal line are arranged on the same layer and are arranged in the frame area. The second wiring structure comprises a third signal line, and the third signal line is arranged in the frame area and arranged on one side of the second signal line in an insulating mode. At least part of the first signal lines are electrically connected with the second signal lines, and at least part of the first signal lines are electrically connected with the third signal lines. The area occupied by the signal lines in the width direction is reduced by increasing the number of layers of the signal lines in the thickness direction of the display panel, so that the narrow frame design is realized, and the impression of the display device is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As display technology continues to mature and develop, consumers have increasingly stringent requirements for the visual effects of display panels. Not only do they have diversified requirements for the appearance design of display panels, but they also have higher and higher requirements for the screen-to-body ratio of display panels. Full-screen technology has emerged in response to this trend. Full-screen technology refers to maximizing the display area and improving the visual effects of the display panel through ultra-narrow or even borderless designs while keeping the total area of ​​the body unchanged. However, it is difficult for existing display panels to achieve narrow-border designs. Summary of the invention

[0003] An object of the present invention is to provide a display panel and a display device to solve the problem that it is difficult to achieve a narrow frame design for existing display panels.

[0004] To achieve the above-mentioned object, the present invention provides a display panel, comprising a display area and a frame area surrounding the display area. The display panel comprises a first routing structure and at least one second routing structure. The first routing structure comprises a first signal line, a second signal line and a first insulating layer. The first signal line is arranged in the display area and extends from the display area to the frame area. The second signal line is arranged in the same layer as the first signal line and is arranged in the frame area. The second routing structure is stacked with the first routing structure and comprises a third signal line. The third signal line is arranged in the frame area and is located on one side of the second signal line and is insulated from the second signal line. At least part of the first signal line is electrically connected to the second signal line, and at least part of the first signal line is electrically connected to the third signal line.

[0005] Furthermore, the display panel further comprises a plurality of first vias, wherein the first vias penetrate the film layer between the first signal line and the corresponding third signal line, and the first signal line passes through the corresponding first vias and is electrically connected to the third signal line. Preferably, the overlapping portion of the orthographic projections of the first signal line and the third signal line on the first plane covers the orthographic projection of the corresponding first via on the first plane, and the first plane is perpendicular to the stacking direction of the display panel. Preferably, the axial center line of the first via intersects with the bottom surface of the second insulating layer to form a first internal angle, and the angle of the first internal angle is 90°-160°.

[0006] Further, there is a gap between the orthographic projection of the second signal line on the second insulating layer and the orthographic projection of the first via hole on the second insulating layer. Preferably, the length of the second signal line is shorter than the length of the third signal line.

[0007] Furthermore, the number of the second wiring structures in the display panel is at least two, and at least two groups of the second wiring structures are stacked in sequence on the same side of the first wiring structure. Preferably, the number of the first signal lines is equal to the sum of the number of the second signal lines and the third signal lines.

[0008] Further, the first routing structure further includes a first insulating layer, and the first insulating layer is arranged between the layer where the first signal line and the second signal line are located and the third signal line. Preferably, the second routing structure further includes a second insulating layer, and the second insulating layer is arranged on a side of the third signal line away from the first routing structure. Preferably, the first routing structure further includes a third insulating layer, and the third insulating layer is arranged on a side of the first signal line and the second signal line away from the first insulating layer. Preferably, the second routing structure further includes a fourth insulating layer, and the fourth insulating layer is arranged on a side of the third signal line away from the second insulating layer.

[0009] Further, the display panel also includes a third routing structure, which is arranged on a side of the first routing structure away from the second routing structure. The third routing structure includes a fourth signal line, and the fourth signal line is located on a side of the layer where the first signal line and the second signal line are located away from the third signal line, and is insulated from the second signal line. Preferably, the third routing structure also includes a fifth insulating layer, and the fifth insulating layer is arranged on a side of the fourth signal line away from the fourth signal line. Preferably, the number of the first signal lines is equal to the sum of the numbers of the second signal lines, the third signal lines and the fourth signal lines. Preferably, the third routing structure also includes a sixth insulating layer, and the sixth insulating layer is arranged on a side of the fourth signal line away from the fifth insulating layer.

[0010] Furthermore, the display panel further comprises a plurality of second via holes, the second via holes penetrating the film layer between the first signal line and the corresponding fourth signal line, and the first signal line passing through the corresponding second via holes is electrically connected to the fourth signal line. Preferably, the overlapping portion of the orthographic projections of the first signal line and the fourth signal line on the fifth insulating layer covers the orthographic projections of the corresponding second via holes on the fifth insulating layer. Preferably, the axial centerline of the second via hole intersects with the bottom surface of the fifth insulating layer to form a second internal angle, and the angle of the second internal angle is 90°-160°.

[0011] Further, there is a gap between the orthographic projection of the second signal line on the fifth insulating layer and the orthographic projection of the second via hole on the fifth insulating layer. Preferably, the length of the second signal line is shorter than the length of the fourth signal line.

[0012] Furthermore, the display panel further comprises a binding area disposed on a side of the frame area away from the display area. The display panel further comprises a substrate and a driver chip. The substrate is disposed on a side of the first wiring structure away from the at least one second wiring structure. The driver chip is located in the binding area. The second signal line and the third signal line extend from the frame area to the binding area and are electrically connected to the driver chip.

[0013] The present invention further provides a display device, which includes the display panel as described above.

[0014] The advantages of the present invention are: in a display panel and a display device of the present invention, the area occupied by the signal line in the width direction of the display panel frame is reduced by increasing the number of signal line layers in the thickness direction of the display panel, thereby reducing the frame width without affecting the various performances of the display panel, thereby realizing a narrow frame design and improving the viewing experience of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 This is a schematic diagram of the planar structure of the display panel in Examples 1-3 of the present application;

[0017] Figure 2 for Figure 1 The cross-sectional structure diagram of the display panel at line AA' in Embodiment 1;

[0018] Figure 3 for Figure 1 The cross-sectional structure diagram of the display panel at line AA' in other embodiments;

[0019] Figure 4 for Figure 1 The cross-sectional structure diagram of the display panel at line AA' in Embodiment 2;

[0020] Figure 5 for Figure 1 The cross-sectional structure diagram of the display panel at line AA' in other embodiments;

[0021] Figure 6 for Figure 1 The cross-sectional structure diagram of the display panel at line AA' in Embodiment 3 is shown in FIG.

[0022] The components in the figure are shown as follows:

[0023] Display panel 100; Display area 110;

[0024] Border area 120; Binding area 130;

[0025] Substrate 1; First wiring structure 2;

[0026] A first signal line 21; A second signal line 22;

[0027] A first insulating layer 23; A third insulating layer 24;

[0028] A second wiring structure 3; A third signal line 31;

[0029] A second insulating layer 32; A fourth insulating layer 33;

[0030] A third wiring structure 4; A fourth signal line 41;

[0031] A fifth insulating layer 42; A sixth insulating layer 43;

[0032] A first via hole 51; A second via hole 52;

[0033] Driver chip 6. DETAILED DESCRIPTION

[0034] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0035] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0036] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0037] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted on" or "connected to" another component, the two may be understood to be directly "mounted on" or "connected", or one component may be indirectly "mounted on" or "connected to" another component via an intermediate component.

[0038] Example 1

[0039] In related display technologies, many signal lines for transmitting display signals are arranged around the display area of ​​the display panel. In order to reduce the impedance of these signal lines and prevent these signal lines from interfering with each other, it is usually necessary to reserve sufficient space outside the display area of ​​the display panel to arrange these lines. Therefore, these signal lines occupy a larger position in the border area of ​​the display panel, thereby increasing the border width of the display panel, which is not conducive to reducing the width of the border area, and further cannot achieve a narrow border display effect.

[0040] In order to solve the above problems, a display panel 100 is provided in an embodiment of the present invention. Figure 1 As shown, the display panel 100 has a display area 110, a frame area 120 and a binding area 130. The display area 110 is used to present a display image, the frame area 120 surrounds the display area 110, and the binding area 130 is located on the side of the frame area 120 away from the display area 110. Figure 1 and Figure 2 As shown, the display panel 100 includes a substrate 1 , a first wiring structure 2 , a second wiring structure 3 and a driving chip 6 .

[0041] The first wiring structure 2 is arranged on one side of the substrate 1, and includes a plurality of first signal lines 21, a plurality of second signal lines 22, and a first insulating layer 23. The first insulating layer 23 is arranged on one side of the substrate 1 and covers the display area 110 and the frame area 120. The first signal lines 21 and the second signal lines 22 are both arranged on a surface of the first insulating layer 23 away from the substrate 1. The first signal lines 21 are arranged in the display area 110, and the second signal lines 22 are arranged in the frame area 120.

[0042] The second wiring structure 3 is arranged on the side of the first wiring structure 2 facing the substrate 1, and includes a plurality of third signal lines 31 and a second insulating layer 32. The third signal lines 31 are arranged on the side of the first insulating layer 23 away from the second signal lines 22 (i.e., insulated and arranged on the side of the second signal lines 22), and are arranged in the border area 120. The second insulating layer 32 is arranged on the side of the third signal lines 31 away from the first wiring structure 2.

[0043] Further, in other embodiments of the present invention, the first insulating layer 23 and the fourth insulating layer 33 can be made of the same material and prepared in the same process, that is, the first insulating layer 23 and the fourth insulating layer 33 can be combined to form a film layer, and only a single insulating layer can be set between the layer where the first signal line 21 and the second signal line 22 are located and the adjacent third signal line 31, thereby reducing the overall thickness of the display panel 100, reducing the preparation steps of the display panel 100, and improving production efficiency. The driver chip 6 is arranged in the binding area 130, and the ends of the second signal line 22 and the third signal line 31 away from the first signal line 21 are electrically connected to the driver chip 6, and the ends of the second signal line 22 and the third signal line 31 away from the driver chip 6 are respectively electrically connected to the corresponding first signal line 21, thereby establishing an electrical connection between the first signal line 21 and the driver chip 6. Among them, the first signal line 21, the second signal line 22 and the third signal line 31 can be used as scanning lines, touch lines or other types of signal lines to transmit data and signals between the display device and the driver chip 6.

[0044] Specifically, the first signal line 21 extends from the display area 110 to the frame area 120, and one end thereof located in the display area 110 is electrically connected to a device in the display panel 100, such as a thin film transistor device, a touch control device, etc., and one end thereof located in the frame area 120 is electrically connected to the second signal line 22 or the third signal line 31. Part of the first signal line 21 is electrically connected to the second signal line 22, and another part of the first signal line 21 is electrically connected to the third signal line 31. Each first signal line 21 is electrically connected to the corresponding second signal line 22 or the corresponding third signal line 31, and is electrically connected to the driver chip 6 through the second signal line 22 or the third signal line 31.

[0045] Figure 2FIG. 2 shows a schematic diagram of a layered structure in which the first signal line 21 is electrically connected to the second signal line 22 and the third signal line 31. Figure 2 As shown, the first signal line 21 and the second signal line 22 are arranged in the same layer, and the first signal directly extends from the display area 110 to the frame area 120, and is directly connected to the corresponding second signal line 22 in the frame area 120. Among them, the first signal line 21 and the second signal line 22 can be prepared simultaneously by the same process. The third signal line 31 is insulated from the second signal line 22 and arranged in a stacked layer, and the third signal line 31 and the first signal line 21 are arranged in a staggered layer. The display panel 100 is also provided with a plurality of first vias 51, and each third signal line 31 is provided with at least one first via 51 corresponding to one end of the corresponding first signal line 21, that is, the overlapping part of the orthographic projection of the first signal line 21 and the third signal line 31 on the first plane (the first plane is perpendicular to the stacking direction of the display panel and is parallel to the surface of the first insulating layer 23 or the second insulating layer 32 facing away from the substrate 10) covers the orthographic projection of the corresponding first via 51 on the first plane. The first via hole 51 penetrates the insulating film layer (i.e., the first insulating layer 23 and the fourth insulating layer 33) between the first signal line 21 and the third signal line 31 from the bottom of the first signal line 21 to the top surface of the third signal line 31, so that part of the top surface of the third signal line 31 is exposed in the first via hole 51, and the first signal line 21 is electrically connected to the third signal line 31 by filling the first via hole 51. Among them, the axial center line of the first via hole 51 intersects with the bottom surface of the second insulating layer 32 and forms a first internal angle α, and the angle of the first internal angle α is 90°-160°. Preferably, since the patterning process of the vertical via hole is simpler and easier to operate than the patterning process of the via hole with a large angle tilt (i.e., the internal angle is greater than 90°), the preferred angle of the first internal angle α is 90°.

[0046] Further, there is a gap between the orthographic projection of the second signal line 22 on the first plane and the orthographic projection of the first via 51 on the first plane, and the width of the gap is greater than or equal to 0, so that the first via 51 and the second signal line 22 can be staggered, thereby reducing the risk of short circuit of the second signal line 22. Preferably, the length of the second signal line 22 is less than the length of the third signal line 31, wherein the second signal line 22 is connected to the first signal line 21 close to the driver chip 6, and the third signal line 31 is connected to the first signal line 21 far from the driver chip 6.

[0047] In an embodiment of the present invention, the signal lines connected to the first signal lines 21 in the border area 120 are arranged in layers, part of the first signal lines 21 are connected to the second signal lines 22 arranged in the same layer, and the remaining first signal lines 21 are connected to the third signal lines 31 arranged on one side of the second signal lines 22 through the first vias 51. This can reduce the number of second signal lines 22 while ensuring data and signal transmission, and reduce the number of signal lines arranged in the border area 120 in the width direction of the display panel 100 by increasing the number of signal lines arranged in the border area 120 in the thickness direction of the display panel 100, thereby narrowing the width of the border area 120 of the display panel 100.

[0048] Furthermore, the sum of the number of the second signal lines 22 and the third signal lines 31 is equal to the number of the first signal lines 21, thereby ensuring that each first signal line 21 can be electrically connected to the corresponding second signal line 22 and third signal line 31. Preferably, the number of the second signal lines 22 is equal to the number of the third signal lines 31, or the difference between the number of the second signal lines 22 and the number of the third signal lines 31 is equal to 1, which is equivalent to reducing the number of the second signal lines 22 by about half and increasing the corresponding number of the third signal lines 31, thereby reducing the area occupied by the second signal lines 22 by half on the basis of the existing signal line arrangement, and further narrowing the width of the frame area 120 by half on the basis of the existing display panel.

[0049] In the embodiment of the present invention, the first wiring structure 2 further includes a third insulating layer 24, which is disposed on a side of the first signal line 21 and the second signal line 22 away from the first insulating layer 23, and is used to insulate and protect the first signal line 21 and the second signal line 22. The second wiring structure 3 further includes a fourth insulating layer 33, which is disposed on a side of the third signal line 31 close to the first wiring structure 2, and is used to increase the insulation thickness between the second signal line 22 and the third signal line 31, to prevent crosstalk between the second signal line 22 and the third signal line 31, and also to reduce the risk of short circuit between the second signal line 22 and the third signal line 31.

[0050] A display device is also provided in an embodiment of the present invention, which may be an OLED (Organic Light-Emitting Diode) display device, comprising the display panel 100 as described above. The display device may be any display device with a display function, such as a mobile phone, a laptop computer, a tablet computer, a car display, etc.

[0051] In the embodiment of the present invention, the second wiring structure 3 is disposed between the substrate 1 and the first wiring structure 2. However, in other embodiments of the present invention, the second wiring structure 3 may also be disposed between the substrate 1 and the first wiring structure 2. Figure 3As shown in the figure, the first signal line 21 and the third signal line 31 are connected by the first via 51 on the side of the first wiring structure 2 away from the substrate 1, and the circuit connection structure is similar to that in this proposal, so it is not described in detail here. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] In the display panel provided in the embodiment of the present invention, the area occupied by the second signal lines in the frame area is reduced by reducing the number of the second signal lines in the frame area, thereby reducing the width of the frame area of ​​the display panel. At the same time, in the embodiment of the present invention, a third signal line is added in layers with the first signal line, and the remaining first signal line is electrically connected to the driver chip through the third signal line, thereby ensuring the integrity of the signal and data transmission in the display panel and ensuring that each device in the display panel can be connected to the driver chip, that is, by increasing the number of signal line layers in the thickness direction of the display panel, the area occupied by the signal line in the width direction is reduced, thereby reducing the frame width of the display panel without affecting the various performances of the display panel, realizing a narrow frame design, and improving the appearance of the display device.

[0053] Example 2

[0054] In an embodiment of the present invention, a display panel 100 is provided. Figure 1 As shown, the display panel 100 has a display area 110, a frame area 120 and a binding area 130. The display area 110 is used to present a display image, the frame area 120 surrounds the display area 110, and the binding area 130 is located on the side of the frame area 120 away from the display area 110. Figure 1 and Figure 4 As shown, the display panel 100 includes a substrate 1 , a first wiring structure 2 , a plurality of groups of second wiring structures 3 and a driving chip 6 .

[0055] The first wiring structure 2 is arranged on one side of the substrate 1, and includes a plurality of first signal lines 21, a plurality of second signal lines 22, and a first insulating layer 23. The first insulating layer 23 is arranged on one side of the substrate 1, and covers the display area 110 and the frame area 120. The first signal lines 21 and the second signal lines 22 are both arranged on a surface of the first insulating layer 23 away from the substrate 1. The first signal lines 21 are arranged in the display area 110, and the second signal lines 22 are arranged in the frame area 120. Preferably, the first wiring structure 2 also includes a third insulating layer 24, which is arranged on a side of the first signal lines 21 and the second signal lines 22 away from the first insulating layer 23, and is used to insulate and protect the first signal lines 21 and the second signal lines 22.

[0056] A plurality of groups of second routing structures 3 are arranged on the side of the first routing structure 2 facing the substrate 1, and the plurality of groups of second routing structures 3 are stacked in sequence on the same side of the first routing structure 2. In the embodiment of the present invention, the number of the second routing structures 3 is two groups, and in other embodiments of the present invention, the number of the second routing structures 3 is not limited, and it can be three groups, four groups, or more than four groups. Each group of second routing structures 3 includes a plurality of third signal lines 31 and a second insulating layer 32. The third signal line 31 is arranged on the side of the first insulating layer 23 away from the second signal line 22 (that is, the insulation is arranged on the side of the second signal line 22), and is arranged in the border area 120. The second insulating layer 32 is arranged on the side of the third signal line 31 away from the first routing structure 2. Preferably, each group of second routing structures 3 also includes a fourth insulating layer 33, which is arranged on the side of the third signal line 31 away from the second insulating layer 32. The fourth insulating layer 33 is used to increase the insulation thickness between the third signal line 31 and the adjacent signal line to prevent crosstalk between the third signal line 31 and the adjacent signal line, and also can reduce the risk of short circuit between the third signal line 31 and the adjacent signal line.

[0057] In other embodiments of the present invention, the first insulating layer 23 and the fourth insulating layer 33 can be made of the same material and prepared in the same process, that is, the first insulating layer 23 and the fourth insulating layer 33 can be combined to form a film layer, and only a single insulating layer can be set between the layer where the first signal line 21 and the second signal line 22 are located and the adjacent third signal line 31. Furthermore, the second insulating layer 32 and the fourth insulating layer 33 located between two adjacent third signal lines 31 can also be made of the same material and prepared in the same process, that is, the second insulating layer 32 and the fourth insulating layer 33 can also be combined to form a film layer, and only a single insulating layer can be set between two adjacent third signal lines 31, thereby reducing the overall thickness of the display panel 100, reducing the preparation steps of the display panel 100, and improving production efficiency.

[0058] The driver chip 6 is disposed in the binding area 130, and the ends of the second signal line 22 and the third signal line 31 away from the first signal line 21 are electrically connected to the driver chip 6, and the ends of the second signal line 22 and the third signal line 31 away from the driver chip 6 are electrically connected to the corresponding first signal line 21, thereby establishing an electrical connection between the first signal line 21 and the driver chip 6. The first signal line 21, the second signal line 22, and the third signal line 31 can be used as scan lines, touch lines, or other types of signal lines to transmit data and signals between the display device and the driver chip 6.

[0059] Specifically, the first signal line 21 extends from the display area 110 to the frame area 120, and one end thereof located in the display area 110 is electrically connected to a device in the display panel 100, such as a thin film transistor device, a touch control device, etc., and one end thereof located in the frame area 120 is electrically connected to the second signal line 22 or the third signal line 31. Part of the first signal line 21 is electrically connected to the second signal line 22, and another part of the first signal line 21 is electrically connected to the third signal line 31. Each first signal line 21 is electrically connected to the corresponding second signal line 22 or the corresponding third signal line 31, and is electrically connected to the driver chip 6 through the second signal line 22 or the third signal line 31.

[0060] Figure 4 FIG. 2 shows a schematic diagram of a layered structure in which the first signal line 21 is electrically connected to the second signal line 22 and the third signal line 31. Figure 4 As shown, the first signal line 21 and the second signal line 22 are arranged in the same layer, and the first signal directly extends from the display area 110 to the frame area 120, and is directly connected to the corresponding second signal line 22 in the frame area 120. Among them, the first signal line 21 and the second signal line 22 can be prepared simultaneously by the same process. The third signal line 31 is insulated from the second signal line 22 and is stacked. The display panel 100 is also provided with a plurality of first vias 51, and each third signal line 31 is provided with at least one first via 51 corresponding to one end close to the corresponding first signal line 21, that is, the overlapping part of the orthographic projection of the first signal line 21 and the third signal line 31 on the first plane (the first plane is perpendicular to the stacking direction of the display panel and is parallel to the surface of the first insulating layer 23 or the second insulating layer 32 away from the substrate 10) covers the orthographic projection of the corresponding first via 51 on the first plane, and there is a gap between the orthographic projections of two adjacent first vias 51 on the substrate 1, and the gap is greater than 0. The first via hole 51 penetrates the insulating film layer (i.e., the first insulating layer 23 and the fourth insulating layer 33) between the first signal line 21 and the corresponding third signal line 31 from the bottom of the first signal line 21 to the top surface of the corresponding third signal line 31, so that part of the top surface of the third signal line 31 is exposed in the first via hole 51, and the first signal line 21 is electrically connected to the third signal line 31 by filling the first via hole 51. Among them, the axial center line of the first via hole 51 intersects with the bottom surface of the second insulating layer 32 and forms a first internal angle α, and the angle of the first internal angle α is 90°-160°. Preferably, since the patterning process of the vertical via hole is simpler and easier to operate than the patterning process of the via hole with a large angle tilt (i.e., the internal angle is greater than 90°), the preferred angle of the first internal angle α is 90°.

[0061] Furthermore, the lengths of the third signal lines 31 in different second structures are different. Preferably, in two adjacent groups of second wiring structures 3, the smaller the spacing with the first wiring structure 2, the shorter the length of the third signal line 31, that is, the length of the third signal line 31 increases with the increase of the spacing between it and the first wiring structure 2; at the same time, the third signal line 31 with a smaller spacing with the first wiring structure 2 is connected to the first signal line 21 close to the driver chip 6, and the third signal line 31 with a larger spacing with the first wiring structure 2 is connected to the first signal line 21 far from the driver chip 6, so that the first vias 51 connecting different second wiring structures 3 can be staggered, thereby preventing the third signal lines 31 in different second wiring structures 3 from short-circuiting when connected to the first signal line 21.

[0062] In an embodiment of the present invention, the signal lines connected to the first signal lines 21 in the border area 120 are arranged in layers, part of the first signal lines 21 are connected to the second signal lines 22 arranged in the same layer, and the remaining first signal lines 21 are connected to multiple groups of third signal lines 31 stacked on the same side of the second signal lines 22 through first vias 51. This can reduce the number of second signal lines 22 while ensuring data and signal transmission, and reduce the number of signal lines arranged in the border area 120 in the width direction of the display panel 100 by increasing the number of signal lines arranged in the border area 120 in the thickness direction of the display panel 100, thereby narrowing the width of the border area 120 of the display panel 100.

[0063] Furthermore, the sum of the number of the second signal lines 22 and the third signal lines 31 is equal to the number of the first signal lines 21, thereby ensuring that each first signal line 21 can be electrically connected to the corresponding second signal line 22 and third signal line 31. Preferably, the number of the third signal lines 31 in the same group of second wiring structures 3 is equal to the number of the second signal lines 22, or the difference between the number of the third signal lines 31 and the number of the second signal lines 22 in the same group of second wiring structures 3 is equal to 1, which is equivalent to reducing the number of the second signal lines 22 by two-thirds and increasing the corresponding number of the third signal lines 31, and arranging them on the same side of the second signal lines 22 in a multi-group stacked structure, so that the area occupied by the second signal lines 22 can be further reduced on the basis of Example 1 of the present invention, and then the width of the border area 120 can be further narrowed on the basis of Example 1 of the present invention.

[0064] In the embodiment of the present invention, the plurality of second wiring structures 3 are arranged between the substrate 1 and the first wiring structure 2. However, in other embodiments of the present invention, the second wiring structure 3 may also be arranged as follows. Figure 5As shown in the figure, the first signal line 21 and the third signal line 31 are connected by the first via 51 on the side of the first wiring structure 2 away from the substrate 1, and the circuit connection structure is similar to that in this proposal, so it is not described in detail here. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0065] In the display panel provided in the embodiment of the present invention, the number of second signal lines in the border area is reduced while a third signal line is added in layer with the first signal line. The remaining first signal lines are electrically connected to the driving chip through the third signal lines. That is, the area occupied by the signal lines in the width direction is reduced by increasing the number of signal line layers in the thickness direction of the display panel, thereby reducing the border width without affecting the performance of the display panel, thereby realizing a narrow border design and improving the look and feel of the display device.

[0066] Example 3

[0067] In an embodiment of the present invention, a display panel 100 is provided. Figure 1 As shown, the display panel 100 has a display area 110, a frame area 120 and a binding area 130. The display area 110 is used to present a display image, the frame area 120 surrounds the display area 110, and the binding area 130 is located on the side of the frame area 120 away from the display area 110. Figure 1 and Figure 6 As shown, the display panel 100 includes a substrate 1 , a first wiring structure 2 , a second wiring structure 3 , a third wiring structure 4 and a driving chip 6 .

[0068] The first wiring structure 2 is arranged on one side of the substrate 1, and includes a plurality of first signal lines 21, a plurality of second signal lines 22, a first insulating layer 23, and a third insulating layer 24. The first insulating layer 23 is arranged on one side of the substrate 1, and covers the display area 110 and the frame area 120. The first signal lines 21 and the second signal lines 22 are both arranged on a surface of the first insulating layer 23 away from the substrate 1. The first signal lines 21 are arranged in the display area 110, and the second signal lines 22 are arranged in the frame area 120. The third insulating layer 24 is arranged on a side of the first signal lines 21 and the second signal lines 22 away from the first insulating layer 23, and is used to insulate and protect the first signal lines 21 and the second signal lines 22.

[0069] The second wiring structure 3 is arranged on the side of the first wiring structure 2 facing the substrate 1, and includes a plurality of third signal lines 31 and a second insulating layer 32. The third signal line 31 is arranged on the side of the first insulating layer 23 away from the second signal line 22 (i.e., the insulation is arranged on the side of the second signal line 22), and is arranged in the border area 120. The second insulating layer 32 is arranged on the side of the third signal line 31 away from the first wiring structure 2. Preferably, the second wiring structure 3 also includes a fourth insulating layer 33, which is arranged on the side of the third signal line 31 away from the second insulating layer 32, and is used to increase the insulation thickness between the third signal line 31 and the adjacent signal line, prevent the third signal line 31 from generating crosstalk with the adjacent signal line, and also reduce the risk of short circuit between the third signal line 31 and the adjacent signal line.

[0070] The third wiring structure 4 is arranged on the side of the first wiring structure 2 away from the substrate 1, and includes a plurality of fourth signal lines 41 and a fifth insulating layer 42. The fourth signal line 41 is arranged on the side of the third insulating layer 24 away from the first signal line 21 and the second signal line 22 (i.e., the insulation is arranged on the side of the layer where the first signal line 21 and the second signal line 22 are located), and is arranged in the border area 120. The fifth insulating layer 42 is arranged on the side of the fourth signal line 41 away from the first wiring structure 2. Preferably, the third wiring structure 4 also includes a sixth insulating layer 43, which is arranged on the side of the fourth signal line 41 away from the fifth insulating layer 42, and is used for the insulation thickness between the fourth signal line 41 and the adjacent signal line to prevent crosstalk between the fourth signal line 41 and the adjacent signal line, and also reduce the risk of short circuit between the fourth signal line 41 and the adjacent signal line.

[0071] In other embodiments of the present invention, the first insulating layer 23 and the fourth insulating layer 33 may be made of the same material and prepared in the same process, that is, the first insulating layer 23 and the fourth insulating layer 33 may be combined to form a film layer, and only a single insulating layer may be provided between the layer where the first signal line 21 and the second signal line 22 are located and the adjacent third signal line 31. Further, the third insulating layer 24 and the sixth insulating layer 43 may also be made of the same material and prepared in the same process, that is, the third insulating layer 24 and the sixth insulating layer 43 may also be combined to form a film layer, and only a single insulating layer may be provided between the layer where the first signal line 21 and the second signal line 22 are located and the adjacent fourth signal line 41, thereby reducing the overall thickness of the display panel 100, reducing the steps for preparing the display panel 100, and improving production efficiency.

[0072] Furthermore, in other embodiments of the present invention, the surfaces of the first signal line 21, the second signal line 22, the third signal line 31, and the fourth signal line 41 may be covered with an insulating coating or an insulating film, thereby ensuring that adjacent signal lines will not be turned on even when they are closely stacked. At the same time, the connection ends of the first signal line 21, the second signal line 22, the third signal line 31, and the fourth signal line 41 remain exposed, thereby ensuring that the circuit in the display panel 100 is turned on normally.

[0073] The driver chip 6 is arranged in the binding area 130, and the ends of the second signal line 22, the third signal line 31 and the fourth signal line 41 away from the first signal line 21 are electrically connected to the driver chip 6, and the ends of the second signal line 22, the third signal line 31 and the fourth signal line 41 away from the driver chip 6 are electrically connected to the corresponding first signal line 21, respectively, so as to establish an electrical connection between the first signal line 21 and the driver chip 6. Among them, the first signal line 21, the second signal line 22, the third signal line 31 and the fourth signal line 41 can be used as scanning lines, touch lines or other types of signal lines to transmit data and signals between the display device and the driver chip 6.

[0074] Specifically, the first signal line 21 extends from the display area 110 to the frame area 120, and one end thereof located in the display area 110 is electrically connected to a device in the display panel 100, such as a thin film transistor device, a touch control device, etc., and one end thereof located in the frame area 120 is electrically connected to the second signal line 22, the third signal line 31, or the fourth signal line 41. Part of the first signal line 21 is electrically connected to the second signal line 22, part of the first signal line 21 is electrically connected to the third signal line 31, and the remaining part of the first signal line 21 is electrically connected to the fourth signal line 41. Each first signal line 21 is electrically connected to the corresponding second signal line 22, the corresponding third signal line 31, or the corresponding fourth signal line 41, and is electrically connected to the driver chip 6 through the second signal line 22, the third signal line 31, or the fourth signal line 41.

[0075] Figure 6 Schematic diagram of a layered structure in which the first signal line 21 is electrically connected to the second signal line 22, the third signal line 31 and the fourth signal line 41. Figure 6 As shown, the first signal line 21 and the second signal line 22 are arranged in the same layer, and the first signal directly extends from the display area 110 to the frame area 120, and is directly connected to the corresponding second signal line 22 in the frame area 120. The first signal line 21 and the second signal line 22 can be prepared simultaneously through the same process.

[0076] The third signal line 31 is insulated from the second signal line 22 and is stacked. The display panel 100 is further provided with a plurality of first vias 51, and each third signal line 31 is provided with at least one first via 51 corresponding to one end close to the corresponding first signal line 21, that is, the orthographic projections of the first signal line 21 and the third signal line 31 on the first plane (the first plane is perpendicular to the stacking direction of the display panel and is parallel to the surface of the first insulating layer 23 or the second insulating layer 32 facing away from the substrate 10) cover the orthographic projections of the corresponding first vias 51 on the first plane. The first vias 51 penetrate the insulating film layer (that is, the first insulating layer 23 and the fourth insulating layer 33) between the first signal line 21 and the corresponding third signal line 31 from the bottom of the first signal line 21 to the top surface of the corresponding third signal line 31, so that part of the top surface of the third signal line 31 is exposed in the first vias 51, and the first signal line 21 is electrically connected to the third signal line 31 by filling the first vias 51. The axial center line of the first via hole 51 intersects with the bottom surface of the second insulating layer 32 and forms a first internal angle α, and the angle of the first internal angle α is 90°-160°. Preferably, since the patterning process of the vertical via hole is simpler and easier to operate than the patterning process of the via hole with a large angle tilt (i.e., the internal angle is greater than 90°), the preferred angle of the first internal angle α is 90°.

[0077] The fourth signal line 41 is insulated from the second signal line 22 and is stacked. The display panel 100 is further provided with a plurality of second vias 52, and each fourth signal line 41 is provided with at least one second via 52 at one end close to the corresponding first signal line 21, that is, the orthographic projections of the first signal line 21 and the fourth signal line 41 on the fifth insulating layer 42 cover the orthographic projections of the corresponding second via 52 on the fifth insulating layer 42. The second via 52 penetrates the insulating film layer (that is, the third insulating layer 24 and the sixth insulating layer 43) between the fourth signal line 41 and the corresponding first signal line 21 from the bottom of the fourth signal line 41 to the top surface of the corresponding first signal line 21, so that part of the top surface of the first signal line 21 is exposed in the second via 52, and the fourth signal line 41 is electrically connected to the corresponding first signal line 21 by filling the second via 52. Among them, the axial center line of the second via 52 intersects with the bottom surface of the fifth insulating layer 42 and forms a second internal angle β, and the angle of the second internal angle β is 90°-160°. Preferably, since the patterning process of the vertical via hole is simpler and easier to operate than the patterning process of the via hole with a large angle inclination (ie, the inner angle is greater than 90°), the preferred angle of the second inner angle β is 90°.

[0078] Further, there is a gap between the orthographic projection of the second signal line 22 on the second insulating layer 32 and the fifth insulating layer 42 and the orthographic projection of the first via 51 on the second insulating layer 32 and the orthographic projection of the second via 52 on the fifth insulating layer 42, and the width of the gap is greater than or equal to 0, so that the first via 51 and the second via 52 can be staggered with the second signal line 22, thereby reducing the risk of short circuit of the second signal line 22. Preferably, the length of the second signal line 22 is less than the length of the third signal line 31 and the fourth signal line 41. The second signal line 22 is connected to the first signal line 21 close to the driver chip 6, and the third signal line 31 and the fourth signal are connected to the first signal line 21 far from the driver chip 6.

[0079] In an embodiment of the present invention, the signal lines connected to the first signal lines 21 in the border area 120 are arranged in layers, part of the first signal lines 21 are connected to the second signal lines 22 arranged in the same layer, and the remaining first signal lines 21 are connected to the third signal lines 31 and the fourth signal lines 41 stacked on the upper and lower sides of the second signal lines 22 through the first vias 51. This can reduce the number of second signal lines 22 while ensuring data and signal transmission, and reduce the number of signal lines arranged in the border area 120 in the width direction of the display panel 100 by increasing the number of signal lines arranged in the border area 120 in the thickness direction of the display panel 100, thereby narrowing the width of the border area 120 of the display panel 100.

[0080] Furthermore, the sum of the number of the second signal lines 22, the third signal lines 31 and the fourth signal lines 41 is equal to the number of the first signal lines 21, thereby ensuring that each first signal line 21 can be electrically connected to the corresponding second signal line 22 and the third signal line 31. Preferably, the number of the third signal lines 31 and the number of the fourth signal lines 41 are equal to the number of the second signal lines 22, or the difference between the number of the third signal lines 31, the number of the fourth signal lines 41 and the number of the second signal lines 22 is equal to 1, which is equivalent to reducing the number of the second signal lines 22 by two-thirds and increasing the corresponding number of the third signal lines 31 and the fourth signal lines 41, and arranging them on the upper and lower sides of the second signal lines 22 in a multi-group stacked structure, so that the area occupied by the second signal lines 22 can be further reduced on the basis of Example 1 of the present invention, and then the width of the border area 120 can be further narrowed on the basis of Example 1 of the present invention.

[0081] In the display panel provided in the embodiment of the present invention, while reducing the number of second signal lines in the border area, a third signal line and a fourth signal line which are layered with the first signal line are added, and the remaining first signal lines are electrically connected to the driving chip through the third signal line and the fourth signal line, respectively. That is, the area occupied by the signal line in the width direction is reduced by increasing the number of signal line layers in the thickness direction of the display panel, thereby reducing the border width without affecting the performance of the display panel, thereby realizing a narrow border design and improving the viewing experience of the display device.

[0082] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. A display panel, characterized in that: The display panel comprises a display area and a frame area surrounding the display area; The display panel comprises: The first routing structure includes: A first signal line is provided in the display area and extends from the display area to the frame area; A second signal line is arranged in the same layer as the first signal line and is arranged in the border area; At least one second routing structure is stacked with the first routing structure, and the second routing structure includes: a third signal line, disposed in the frame area, located on one side of the second signal line, and insulated from the second signal line; At least a portion of the first signal line is electrically connected to the second signal line, and at least a portion of the first signal line is electrically connected to the third signal line.

2. The display panel according to claim 1, wherein: The display panel further includes: A plurality of first via holes, penetrating the film layer between the first signal line and the corresponding third signal line, wherein the first signal line is electrically connected to the third signal line through the corresponding first via holes; Preferably, the overlapping portion of the orthographic projections of the first signal line and the third signal line on the first plane covers the orthographic projection of the corresponding first via hole on the first plane, and the first plane is perpendicular to the stacking direction of the display panel; Preferably, an axial center line of the first via hole intersects with a bottom surface of the second insulating layer to form a first inner angle, and the angle of the first inner angle is 90°-160°.

3. The display panel according to claim 2, wherein: There is a gap between the orthographic projection of the second signal line on the first plane and the orthographic projection of the first via hole on the first plane; Preferably, the length of the second signal line is shorter than the length of the third signal line.

4. The display panel according to claim 1, wherein: The number of the second wiring structures in the display panel is at least two groups, and the at least two groups of the second wiring structures are sequentially stacked and arranged on the same side of the first wiring structure; Preferably, the number of the first signal lines is equal to the sum of the number of the second signal lines and the third signal lines.

5. The display panel according to claim 1, wherein: The first wiring structure further includes: A first insulating layer, provided between the layer where the first signal line and the second signal line are located and the third signal line; Preferably, the second wiring structure further includes: A second insulating layer is provided on a side of the third signal line away from the first wiring structure; Preferably, the first wiring structure further includes: a third insulating layer, provided on a side of the first signal line and the second signal line away from the first insulating layer; Preferably, the second wiring structure further includes: The fourth insulating layer is disposed on a side of the third signal line away from the second insulating layer.

6. The display panel according to claim 1, wherein: Also includes: A third routing structure is arranged on a side of the first routing structure away from the second routing structure; The third wiring structure comprises: A fourth signal line is located at a side of the layer where the first signal line and the second signal line are located, away from the third signal line, and is insulated from the second signal line; Preferably, the third wiring structure further includes a fifth insulating layer, and the fifth insulating layer is provided on a side of the fourth signal line away from the first wiring structure; Preferably, the number of the first signal lines is equal to the sum of the number of the second signal lines, the third signal lines and the fourth signal lines; Preferably, the third wiring structure further includes a sixth insulating layer, and the sixth insulating layer is arranged on a side of the fourth signal line away from the fifth insulating layer.

7. The display panel according to claim 6, wherein: The display panel further includes: A plurality of second via holes, penetrating the film layer between the first signal line and the corresponding fourth signal line, wherein the first signal line passes through the corresponding second via holes and is electrically connected to the fourth signal line; Preferably, the overlapping portion of the orthographic projections of the first signal line and the fourth signal line on the fifth insulating layer covers the orthographic projection of the corresponding second via hole on the fifth insulating layer; Preferably, an axial center line of the second via hole intersects with the bottom surface of the fifth insulating layer to form a second inner angle, and the angle of the second inner angle is 90°-160°.

8. The display panel according to claim 7, wherein: There is a gap between the orthographic projection of the second signal line on the fifth insulating layer and the orthographic projection of the second via hole on the fifth insulating layer; Preferably, the length of the second signal line is shorter than the length of the fourth signal line.

9. The display panel according to claim 1, wherein: The display panel further comprises a binding area disposed on a side of the frame area away from the display area; The display panel further includes: A substrate, disposed on a side of the first wiring structure away from the at least one second wiring structure; A driving chip, located in the binding area; The second signal line and the third signal line extend from the frame area to the binding area and are electrically connected to the driving chip.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-9.

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