Semiconductor structure and layout, preparation method, device and equipment thereof

Abstract

The invention provides a semiconductor structure and a layout, a preparation method, a device and equipment thereof, the semiconductor structure comprises a plurality of stacked transistors, each stacked transistor comprises a front side transistor and a back side transistor which are stacked, and the layout of the semiconductor structure comprises a first area; a second region; the photoetching pattern of the first area and the photoetching pattern of the second area are arranged in a mirror symmetry manner. Through the layout of the semiconductor structure, the manufacturing cost can be reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor structure and its layout, preparation method, device, and equipment. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further improve the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size. Stacked transistor technology is an important trend in the semiconductor industry. It can not only improve the density and performance of transistors, but also provide higher computing power and lower power consumption for future electronic devices.

[0003] However, a large number of photomasks are required in the preparation process of stacked transistors, which leads to a high cost for preparing the stacked transistors. Summary of the invention

[0004] The present application provides a semiconductor structure and its layout, preparation method, device, and equipment to reduce manufacturing costs.

[0005] In a first aspect, an embodiment of the present application provides a layout of a semiconductor structure, the semiconductor structure includes a plurality of stacked transistors, the stacked transistors include front transistors and back transistors stacked, the layout of the semiconductor structure includes: a first region; a second region; a lithography pattern of the first region and a lithography pattern of the second region are arranged in mirror symmetry.

[0006] In some possible embodiments, before the semiconductor structure is flipped, the layout of the semiconductor structure is used to prepare front transistors among multiple stacked transistors; after the semiconductor structure is flipped, the layout of the semiconductor structure is used to prepare back transistors among multiple stacked transistors.

[0007] In some possible embodiments, the layout of the above-mentioned semiconductor structure includes at least one of the following: a gate layout; the gate layout is used to prepare the gates in multiple stacked transistors; a source-drain interconnection layout; the source-drain interconnection layout is used to prepare the source-drain interconnection layer in multiple stacked transistors in a later process; a first metal interconnection layout; the first metal interconnection layout is used to prepare the first metal layer in multiple stacked transistors in a later process.

[0008] In some possible implementations, multiple stacked transistors in the semiconductor structure are arranged in an array; the array formed by the multiple stacked transistors corresponding to the layout of the above semiconductor structure is an even number of columns; wherein the multiple stacked transistors are evenly distributed in the first region and the second region.

[0009] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the semiconductor structure comprising a plurality of stacked transistors, the stacked transistors comprising a front transistor and a back transistor stacked, the method for preparing the above-mentioned semiconductor structure comprising: preparing a plurality of front transistors on a substrate based on a layout as in the first aspect; flipping the plurality of front transistors and thinning the substrate; and preparing a plurality of back transistors on the flipped front transistors based on the layout as in the first aspect.

[0010] In a third aspect, an embodiment of the present application provides a semiconductor structure, which is formed by the layout preparation as described in the first aspect; the above-mentioned semiconductor structure includes: a plurality of stacked transistors; the stacked transistors include a front transistor and a back transistor stacked in a stacked manner; the plurality of stacked transistors are arranged in mirror symmetry.

[0011] In some possible implementations, the plurality of stacked transistors are distributed in an array; wherein the array formed by the plurality of stacked transistors is an even number of columns.

[0012] In some possible implementations, the front transistor and the back transistor may be any of the following: a fin field effect transistor; a nanosheet field effect transistor; a planar transistor; a vertical transistor; or a complementary field effect transistor.

[0013] In a fourth aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the third aspect above.

[0014] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the fourth aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, by setting the layout of the semiconductor structure into two mirror-symmetrical parts (i.e., the first region and the second region), multiple front-side transistors prepared based on the layout are arranged in mirror-symmetrical fashion, and multiple back-side transistors prepared based on the layout are also arranged in mirror-symmetrical fashion. Furthermore, the layout of the multiple back-side transistors prepared after flipping is the same as the lithography pattern of the layout of the multiple front-side transistors. Therefore, in the process of preparing the semiconductor structure, the same layout can be used to prepare multiple front-side transistors and multiple back-side transistors (i.e., a reused layout). The reuse of the layout can effectively reduce manufacturing costs.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A layout for stacked devices;

[0019] Figure 2 A layout of a semiconductor structure and a schematic diagram of a semiconductor structure;

[0020] Figure 3 A layout of a semiconductor structure and a first schematic diagram of a semiconductor structure in an embodiment of the present application;

[0021] Figure 4 A layout diagram of a semiconductor structure and a second schematic diagram of a semiconductor structure in an embodiment of the present application;

[0022] Figure 5 A schematic diagram of a layout corresponding to a plurality of stacked transistors in a semiconductor structure distributed in odd number of columns. DETAILED DESCRIPTION

[0023] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0024] Stacked transistor technology is an innovative approach taken by the semiconductor industry to continue Moore's Law. It improves the computing density and performance of chips by stacking transistors in a vertical direction. Compared with traditional transistors, stacked transistors have the following advantages: 1. Improve transistor density: By vertically stacking N-channel metal-oxide-semiconductor (NMOS) and P-channel metal-oxide-semiconductor (PMOS), more transistors can be integrated on the same chip area, thereby improving chip performance and energy efficiency; 2. More transistors per unit volume: In addition to making transistors smaller, stacking technology also has an additional spatial dimension, which allows transistors to be stacked to achieve the integration of more transistors per unit volume; 3. Save area: Stacked transistor technology can significantly save chip area, reduce interconnection distance and load, thereby improving transistor density and performance; 4. Improve performance and energy efficiency: Stacked transistor technology can reduce parasitic effects, improve performance and energy efficiency, and has strong adaptable design capabilities, such as the ability to balance NMOS and PMOS channel changes; 5. Improve integration: The small size and high integration of two-dimensional semiconductors help to manufacture smaller and denser integrated circuits, improving chip performance and functionality.

[0025] In some embodiments, Figure 1 Layout of stacked devices. Figure 1 The stacked device shown is a flip FET (FFET), which is a new type of stacked device. In the FFET process, the front device is first made. After the front device is made, the wafer needs to be flipped and the back device is continued to be made on the back of the wafer. Figure 1 As shown, the front and back layouts of the FFET are different, that is, two different layouts (ie, photolithography plates) need to be prepared in the process of preparing the FFET.

[0026] In some embodiments, Figure 2 It is a layout of a semiconductor structure and a schematic diagram of a semiconductor structure. Figure 2 (a) is the layout of the semiconductor structure. Figure 2 (a) is a semiconductor structure, see Figure 2 As shown, when transistors are arranged on a wafer, they are generally placed sequentially. At this time, the photolithography patterns seen on the front and back sides are different, resulting in a different set of layouts being required for each side.

[0027] Based on the above Figure 1 and Figure 2 In the process of stacking transistors, after the front-side devices are made, the wafer needs to be turned over to continue making the back-side devices. Because the devices and circuit structures on the front and back sides are not exactly the same, two different layouts need to be used before and after flipping the wafer, which increases the cost.

[0028] In order to solve the above technical problems, an embodiment of the present application provides a layout of a semiconductor structure to reduce manufacturing costs.

[0029] In some possible implementations, the semiconductor structure described in the embodiments of the present application includes a plurality of stacked transistors, and the stacked transistors include a front transistor and a back transistor that are stacked.

[0030] It is understandable that multiple transistors can be prepared simultaneously on the same substrate, and the type of transistor can be designed according to actual needs. The semiconductor structure mentioned in the embodiment of the present application is a collection of multiple stacked transistors, wherein the stacked transistor is a transistor formed by stacking at least two transistors; taking the stacking of two transistors as an example, the stacked transistor includes two stacked transistors in the vertical direction, namely a front transistor and a back transistor; the front transistor and the back transistor are arranged "back to back". Accordingly, the semiconductor structure formed based on the integration of multiple stacked transistors may include a front semiconductor structure and a back semiconductor structure, that is, multiple front transistors are integrated into a front semiconductor structure, and multiple back transistors are integrated into a back transistor structure.

[0031] In some possible implementations, the layout of the semiconductor structure may include: a first region; and a second region, wherein the photolithography pattern of the first region and the photolithography pattern of the second region are arranged in mirror symmetry.

[0032] It can be understood that the layout of the semiconductor structure can be divided into two regions, namely the first region and the second region, and the first region and the second region are bilaterally symmetrical (i.e., mirror symmetric). Correspondingly, the semiconductor structure prepared based on the layout can also be divided into two mirror symmetric regions (i.e., the first semiconductor region and the second semiconductor region), and the first semiconductor region and the second semiconductor region are mirror symmetric.

[0033] It should be noted that the size of the layout of the above semiconductor structure is the area of ​​the region exposed once during the photolithography process.

[0034] In some possible implementations, before the semiconductor structure is flipped, the layout is used to prepare front transistors among a plurality of stacked transistors; after the semiconductor structure is flipped, the layout is used to prepare back transistors among a plurality of stacked transistors.

[0035] It can be understood that the semiconductor structure described in the embodiment of the present application involves a flipping process during the preparation process. For a stacked transistor in the semiconductor structure, the preparation process is as follows: according to the front layout, a front transistor is prepared. After the front transistor is formed, the front transistor is flipped. Then, according to the back layout, a back transistor is prepared on the flipped front transistor. In this way, the obtained front transistor and back transistor are stacked in a "back-to-back" arrangement. For the semiconductor structure, the preparation process is as follows: according to the front layout, a front semiconductor structure is prepared. After the front semiconductor structure is formed, the front semiconductor structure is flipped. Then, according to the back layout, a back semiconductor structure is prepared on the flipped front semiconductor structure. In this way, the obtained front semiconductor structure and back semiconductor structure are stacked in a "back-to-back" arrangement.

[0036] In some embodiments, the front layout and the back layout are the same layout, and the back layout can be obtained by turning the front layout over.

[0037] In some embodiments, the above layout can be used to prepare the front semiconductor structure before flipping, and can also be used to prepare the back semiconductor structure after flipping, that is, during the preparation process of the semiconductor structure, the same layout can be used for the front semiconductor structure and the back semiconductor structure.

[0038] In the embodiments of the present application, the reuse of the front transistor and the back transistor in the layout can significantly reduce the manufacturing cost of the semiconductor structure.

[0039] In some embodiments, since the first region and the second region in the layout are arranged in mirror symmetry and the front semiconductor structure and the back semiconductor structure use the same layout, the front semiconductor structure and the back semiconductor structure have the same arrangement.

[0040] In some embodiments, Figure 3 The layout of the semiconductor structure and the first schematic diagram of the semiconductor structure in the embodiment of the present application are shown in FIG. Figure 3 (b) is a schematic diagram of the semiconductor structure. Figure 3 In (b), multiple transistors in the semiconductor structure are arranged in an array, and a unit in the array can represent a transistor or multiple integrated transistors, which is not specifically limited in the embodiments of the present application. Figure 3 The semiconductor structure shown in (b) in the figure corresponds to the layout of the structure after a certain area is enlarged. Figure 3 As shown in (a) in .

[0041] In some embodiments, see Figure 3 As shown in (a), when the layout is mirror-symmetrical, after the front semiconductor structure is prepared, the front semiconductor structure is turned over, and the layout of the back semiconductor structure prepared on the back is the same as the layout of the front semiconductor structure. It should be noted that Figure 3 The "F" in (a) is only a schematic representation of the photolithography pattern and does not represent the actual photolithography pattern.

[0042] In some possible embodiments, the above-mentioned layout may include at least one of the following: a gate layout; the gate layout is used to prepare the gate (gate) in multiple stacked transistors; a source-drain interconnection layout; the source-drain interconnection layout is used to prepare the source-drain interconnection layer (MD) in multiple stacked transistors in the back-end process; a first metal interconnection layout; the first metal interconnection layout is used to prepare the first metal layer in multiple stacked transistors in the back-end process.

[0043] It is understandable that in the manufacturing process of transistors, the preparation process of different structures in the transistors requires the configuration of different lithographic patterns. For example, the lithographic patterns of the layout corresponding to the gate, the layout corresponding to the source and drain, and the layout corresponding to the metal interconnection layer are all different, and each layout is used in a different process. Based on different processes, the layout described in the embodiment of the present application may include: a layout for preparing a gate, a layout for preparing a source and drain interconnection layer, and a layout for preparing a first metal layer (M0).

[0044] It should be noted that the “source and drain” mentioned in the embodiments of the present application are abbreviations for source and / or drain.

[0045] In some embodiments, Figure 4The layout of the semiconductor structure and the second schematic diagram of the semiconductor structure in the embodiment of the present application are shown in FIG. Figure 4 (a) is a layout of a semiconductor structure. Before the layout is turned over, it is used to prepare a front semiconductor structure. After the layout is turned over, it is used to prepare a back semiconductor structure. A portion of the front semiconductor structure prepared based on the layout before turning over and a portion of the back semiconductor structure prepared based on the layout after turning over are shown in FIG. Figure 4 As shown in (b) in . Figure 4 As shown, in the process of preparing the gate, the front semiconductor structure and the back semiconductor structure use the same gate layout, so that the arrangement of the gates of the front semiconductor structure and the back semiconductor structure is the same (see Figure 4 In the process of preparing the source-drain interconnection layer, the front semiconductor structure and the back semiconductor structure use the same source-drain interconnection layout, so that the arrangement of the source-drain interconnection layer of the front semiconductor structure and the back semiconductor structure is the same (see Figure 4 In the process of preparing the first metal layer, the front semiconductor structure and the back semiconductor structure use the same first metal interconnection layout, so that the arrangement of the first metal layer of the front semiconductor structure and the back semiconductor structure is the same (see Figure 4 , as shown in (b) in the figure).

[0046] It should be noted that during the preparation process of the front semiconductor structure and the back semiconductor structure, not all layouts can be reused. For example, the gate cut-off layout, the source and drain metal layer cut-off layout, and the first metal layer cut-off layout can be prepared in two sets of layouts for the front and back sides according to the front semiconductor structure and the back semiconductor structure respectively.

[0047] In some possible implementations, the plurality of stacked transistors are arranged in an array; the array formed by the plurality of stacked transistors corresponding to the layout is an even number of columns; wherein the plurality of stacked transistors are evenly distributed in the first region and the second region.

[0048] It is understandable that in order to achieve high-density integration, multiple stacked transistors can be arranged in an array in the semiconductor structure. Because the layout of the semiconductor structure is mirror-symmetrical, the array of multiple stacked transistors can be set to an even number of columns, so that the stacked transistors can be easily divided (i.e., divided into two left-right symmetrical parts).

[0049] In some embodiments, it is necessary to ensure that the stacked transistors corresponding to the layout are distributed in an even number of columns, so that the lithography patterns of the front semiconductor structure and the back semiconductor structure can be the same.

[0050] In one example, Figure 5 A schematic diagram of a layout corresponding to a plurality of stacked transistors in a semiconductor structure arranged in odd number of columns. Figure 5 As shown, the stacked transistors are divided into three columns. After turning over, the lithography patterns on the front and the back are different. In this case, the layout cannot be reused.

[0051] In an embodiment of the present application, by setting the layout of the semiconductor structure to two mirror-symmetrical parts (i.e., the first region and the second region), the multiple front-side transistors prepared based on the layout are arranged in mirror-symmetrical fashion, and the multiple back-side transistors prepared based on the layout are also arranged in mirror-symmetrical fashion. Furthermore, the layout of the multiple back-side transistors prepared after flipping is the same as the lithography pattern of the layout of the multiple front-side transistors. Therefore, in the process of preparing the semiconductor structure, the same layout can be used to prepare multiple front-side transistors and multiple back-side transistors (i.e., a reused layout). The reuse of the layout can effectively reduce manufacturing costs.

[0052] Furthermore, the layout of the semiconductor structure provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the layout of the semiconductor structure provided in the embodiment of the present application can be detected by TEM slicing. For example, it can be observed in the TEM slice that the layout is bilaterally symmetrical.

[0053] An embodiment of the present application provides a method for preparing a semiconductor structure, wherein the semiconductor structure includes a plurality of stacked transistors, wherein the stacked transistors include a front transistor and a back transistor that are stacked. The method includes: preparing a plurality of front transistors on a substrate based on a layout of the semiconductor structure; flipping the plurality of front transistors and thinning the substrate; and preparing a plurality of back transistors on the flipped front transistors based on the layout of the semiconductor structure.

[0054] It is understandable that the stacked transistors in the semiconductor structure can be prepared according to the standard process. Based on the same substrate, the front transistor is prepared first, and then the back transistor is prepared on the front transistor after flipping, and the front transistor and the back transistor are prepared using the same layout.

[0055] In some embodiments, a substrate is provided; a plurality of active structures are formed on the substrate by etching, and the height of the active structures should be sufficient to prepare two vertically arranged transistors; the active structures may include a front active structure and a back active structure; in the process of forming the active structures, a substrate of a preset height is retained, and the retained substrate is used to support the active structures; then, based on the plurality of front active structures, a plurality of front transistors are formed; the plurality of front transistors are flipped so that the substrate is placed facing upward; the substrate is thinned by chemical mechanical planarization (CMP) until the back active structure is exposed; based on the exposed plurality of back active structures, a plurality of back transistors are formed.

[0056] In some embodiments, the front transistor and the back transistor in the semiconductor structure can be transistors of the same type, such as any of the following: fin field effect transistor (FinFET), nanosheet field effect transistor (NSFET), planar transistor, vertical transistor and complementary field effect transistor (CFET), etc.

[0057] In some embodiments, the shape of the active structure formed is different depending on the type of the front transistor and the back transistor. For example, when the front transistor and the back transistor are fin-type field effect transistors, the active structure is a fin-shaped structure; when the front transistor and the back transistor are nanosheet field effect transistors, the active structure is a plurality of parallel nanosheet structures or a plurality of parallel nanowire structures.

[0058] In some embodiments, the preparation method of the above-mentioned semiconductor structure may also include: designing a front packaging substrate and a back packaging substrate according to the positions of the bumps of the front transistor and the back transistor; and packaging the semiconductor structure based on the front packaging substrate and the back packaging substrate.

[0059] The contact points (pins) at the same position on the front packaging substrate and the back packaging substrate have the same function, so that the system end can use the prepared semiconductor structure conveniently.

[0060] An embodiment of the present application provides a semiconductor structure, which is formed by using the layout preparation of the semiconductor structure as described above; the above-mentioned semiconductor structure includes: a plurality of stacked transistors; the stacked transistors include a front transistor and a back transistor stacked in a stacked manner; the plurality of stacked transistors are arranged in mirror symmetry.

[0061] It can be understood that the semiconductor structure prepared based on the above layout includes a front semiconductor structure and a back semiconductor structure, wherein a plurality of front transistors are integrated into the front semiconductor structure, and a plurality of back transistors are integrated into the back semiconductor structure. The layout is arranged in mirror symmetry, and the front semiconductor structure formed based on the layout is also arranged in mirror symmetry, and correspondingly, the back semiconductor structure formed based on the layout is also arranged in mirror symmetry.

[0062] In some possible implementations, the plurality of stacked transistors are distributed in an array; wherein the array formed by the plurality of stacked transistors is an even number of columns.

[0063] It can be understood that in order to achieve a mirror-symmetrical arrangement, multiple stacked transistors can be arranged in an even number of columns.

[0064] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0065] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 3 and Figure 4 The semiconductor structure shown will not be described in detail here.

[0066] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 3 and Figure 4 , I will not go into details here.

[0067] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0068] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A layout of a semiconductor structure, characterized in that: The semiconductor structure includes a plurality of stacked transistors, wherein the stacked transistors include a front transistor and a back transistor that are stacked. The layout includes: First region; The second region; the photolithography pattern in the first region and the photolithography pattern in the second region are arranged in mirror symmetry.

2. The layout according to claim 1, characterized in that Before flipping the semiconductor structure, the layout is used to prepare the front transistors in the plurality of stacked transistors; After the semiconductor structure is flipped, the layout is used to prepare back-side transistors in the plurality of stacked transistors.

3. The layout according to claim 1, characterized in that The layout includes at least one of the following: A gate layout; the gate layout is used to prepare the gates in the plurality of stacked transistors; A source-drain interconnection layout; the source-drain interconnection layout is used to prepare a source-drain interconnection layer in the plurality of stacked transistors in a back-end process; A first metal interconnection layout; the first metal interconnection layout is used to prepare the first metal layer in the plurality of stacked transistors in a back-end process.

4. The layout of the semiconductor structure according to claim 1, characterized in that: The plurality of stacked transistors in the semiconductor structure are arranged in an array; The array formed by the multiple stacked transistors corresponding to the layout is an even number of columns; wherein the multiple stacked transistors are evenly distributed on the first region and the second region.

5. A method for preparing a semiconductor structure, characterized in that: The semiconductor structure includes a plurality of stacked transistors, wherein the stacked transistors include a front transistor and a back transistor that are stacked. The method comprises: Based on the layout according to any one of claims 1 to 4, a plurality of front-side transistors are prepared on a substrate; Flipping the plurality of front-side transistors and thinning the substrate; Based on the layout as claimed in any one of claims 1 to 4, a plurality of back side transistors are prepared on the front side transistor after flipping.

6. A semiconductor structure, characterized in that: The semiconductor structure is formed by using the layout preparation as claimed in any one of claims 1 to 4; The semiconductor structure comprises: A plurality of stacked transistors; the stacked transistors include a front transistor and a back transistor arranged in a stacked manner; The plurality of stacked transistors are arranged in mirror symmetry.

7. The semiconductor structure according to claim 6, characterized in that: The plurality of stacked transistors are distributed in an array; wherein the array formed by the plurality of stacked transistors is an even number of columns.

8. The semiconductor structure according to claim 6, characterized in that: The front transistor and the back transistor may be any of the following; Fin field effect transistor; Nanosheet field-effect transistors; Planar transistors; vertical transistor; Complementary Field Effect Transistor.

9. A semiconductor device, characterized in that: include: A semiconductor structure as claimed in any one of claims 6 to 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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