Display panel and repairing method thereof

Abstract

The invention relates to a display panel and a repairing method thereof. A display panel may include: a first sub-pixel including a (1-1) th light emitting element and a (1-2) th light emitting element; a second sub-pixel including a 2-1-th light emitting element and a 2-2-th light emitting element; a first cathode line connected to at least one of the cathode electrode of the (1-1)-th light-emitting element and the cathode electrode of the (1-2)-th light-emitting element, and extending toward the second sub-pixel; and a second cathode line connected to at least one of the cathode electrode of the 2-1 light emitting element and the cathode electrode of the 2-2 light emitting element, and extending toward the first sub-pixel.

Description

Technical Field

[0001] The present disclosure relates to a display panel and a repair method thereof. Background Art

[0002] Organic light-emitting display devices reproduce images by emitting light using an organic light-emitting diode (OLED) placed in each pixel according to an input image signal. Organic light-emitting display devices have fast response speed and high luminous efficiency, brightness and viewing angle, and have excellent contrast and color reproducibility because it can express black grayscale as full black. These organic light-emitting display devices do not require a backlight unit.

[0003] In recent years, display devices that use light-emitting diodes (LEDs), which are inorganic light-emitting devices, as light-emitting elements of pixels have attracted attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect organic materials from moisture, and they have excellent reliability and a longer life than OLEDs. LEDs also have a fast lighting speed, excellent luminous efficiency, and are impact-resistant.

[0004] The description provided in this Background section should not be assumed to be prior art merely because it is mentioned in or related to the Background section.The Background section may include information that describes one or more aspects of the subject technology. Summary of the invention

[0005] An aspect of the present disclosure is to provide a display panel including a light emitting element and a repair method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0006] The features and aspects of the present disclosure are not limited to those mentioned above, and other features and aspects not mentioned will be clearly understood by those skilled in the art from the following description, or may be implemented and obtained by the structures pointed out or derived therefrom in the present disclosure, the attached claims, and the accompanying drawings.

[0007] To achieve these and other aspects of the inventive concept, as implemented and broadly described herein, a display panel according to an embodiment of the present disclosure may include: a first sub-pixel, which includes a 1-1th light-emitting element and a 1-2th light-emitting element; a second sub-pixel, which includes a 2-1th light-emitting element and a 2-2th light-emitting element; a first cathode line, which is connected to at least one of the cathode electrodes of the 1-1th light-emitting element and the cathode electrodes of the 1-2th light-emitting element, and extends toward the second sub-pixel; and a second cathode line, which is connected to at least one of the cathode electrodes of the 2-1th light-emitting element and the cathode electrodes of the 2-2 light-emitting element, and extends toward the first sub-pixel, wherein the first cathode line and the second cathode line partially overlap each other.

[0008] At portions where the first cathode lines and the second cathode lines overlap, the first cathode lines and the second cathode lines may be connected to or separated from each other.

[0009] At portions where the first cathode lines and the second cathode lines do not overlap, the first cathode lines or the second cathode lines may be separated to be insulated from each other.

[0010] The anode electrode of the 1-1 light emitting element may be connected to the anode electrode of the 1-2 light emitting element. The anode electrode of the 2-1 light emitting element may be connected to the anode electrode of the 2-2 light emitting element.

[0011] The first subpixel may include: a first driving transistor that provides current to the 1-1th light-emitting element and the 1-2th light-emitting element; a 1-1th switching transistor that switches the current path between the pixel driving voltage and the cathode voltage; and a 1-2th switching transistor that is connected to the anode electrode of the 1-1th light-emitting element and the anode electrode of the 1-2th light-emitting element, and is connected to at least one of the cathode electrodes of the 1-1th light-emitting element and the cathode electrode of the 1-2 light-emitting element.

[0012] The second subpixel may include: a second driving transistor that provides current to the 2-1st light-emitting element and the 2-2nd light-emitting element; a 2-1st switching transistor that switches the current path between the pixel driving voltage and the cathode voltage; and a 2-2nd switching transistor that is connected to the anode electrode of the 2-1st light-emitting element and the anode electrode of the 2-2nd light-emitting element, and is connected to at least one of the cathode electrodes of the 2-1st light-emitting element and the cathode electrode of the 2-2nd light-emitting element.

[0013] The 1-2 th switching transistor may be connected between the pixel driving voltage line and the first driving transistor, and the 2-2 th switching transistor may be connected between the pixel driving voltage line and the second driving transistor.

[0014] The cathode electrode of the 1-1 light emitting element and the cathode electrode of the 1-2 light emitting element may be electrically separated. The first cathode line and the second cathode line may be electrically separated.

[0015] The cathode electrode of the 1-1 light-emitting element and the cathode electrode of the 1-2 light-emitting element may be electrically separated. The first cathode line and the second cathode line may be electrically connected. The cathode electrode of the 1-2 light-emitting element and the cathode electrode of the 2-1 light-emitting element may be electrically connected to each other. The cathode electrode of the 1-2 light-emitting element and the cathode electrode of the 2-1 light-emitting element may be electrically separated from the cathode electrode of the 1-1 light-emitting element and the cathode electrode of the 2-2 light-emitting element.

[0016] The cathode electrode of the 1-1 light emitting element and the cathode electrode of the 1-2 light emitting element are electrically separated. The first cathode line and the second cathode line may be electrically separated. The cathode electrode of the 2-1 light emitting element and the cathode electrode of the 2-2 light emitting element may be electrically connected to each other.

[0017] The first cathode lines and the second cathode lines may be arranged with an insulating layer interposed between the first cathode lines and the second cathode lines.

[0018] There may be a hole penetrating the insulating layer, and the first cathode line and the second cathode line are connected to each other through the hole.

[0019] The first sub-pixel and the second sub-pixel may emit light of the same color and be adjacent to each other.

[0020] To achieve these and other aspects of the inventive concept, as embodied and broadly described herein, a method for repairing a display panel according to an embodiment of the present disclosure may include: electrically separating a cathode electrode of a 1-1 light-emitting element of a first sub-pixel from a cathode electrode of a 1-2 light-emitting element of the first sub-pixel; and electrically connecting a first cathode line extending from the first sub-pixel to a second cathode line extending from the second sub-pixel. The first cathode line is connected to at least one cathode electrode among the cathode electrodes of the 1-1 light-emitting element and the 1-2 light-emitting element, and extends toward the second sub-pixel. The second cathode line is connected to at least one cathode electrode among the cathode electrodes of the 2-1 light-emitting element and the 2-2 light-emitting element of the second sub-pixel, and extends toward the first sub-pixel.

[0021] The first cathode line may be electrically separated from the 1-1th light emitting element, and the repair method may further include electrically separating the cathode electrode of the 1-2th light emitting element from the first cathode line.

[0022] The cathode electrode of the 2-1st light emitting element may be connected to the cathode electrode of the 2-2nd light emitting element. The cathode electrodes of the 2-1st light emitting element and the 2-2nd light emitting element may be electrically separated from the cathode electrodes of the 1-1st light emitting element and the 1-2nd light emitting element.

[0023] The 2-1st light emitting element and the 2-2nd light emitting element may be able to emit light, while the 1-1st light emitting element and the 2-2nd light emitting element may be dark spots that do not emit light.

[0024] The 1-1st light emitting element, the 2-1st light emitting element, and the 2-2nd light emitting element may be able to emit light, and the 1-2nd light emitting element may be a dark spot that does not emit light.

[0025] The repair method may further include electrically separating the cathode electrode of the 2-1st light emitting element from the cathode electrode of the 2-2nd light emitting element.

[0026] The cathode electrode of the 1-2 light emitting element and the cathode electrode of the 2-1 light emitting element may be electrically connected. The cathode electrode of the 1-2 light emitting element and the cathode electrode of the 2-1 light emitting element may be electrically separated from the cathode electrode of the 1-1 light emitting element and the cathode electrode of the 2-2 light emitting element.

[0027] The 1-2nd light emitting element and the 2-1st light emitting element may be able to emit light, or the 1-1st light emitting element and the 2-2nd light emitting element may be dark spots that do not emit light.

[0028] According to an embodiment of the present disclosure, by using a pixel structure that facilitates improvement of dark spots, a display panel having advantages of process optimization, high efficiency, high brightness, and long lifespan may be realized.

[0029] According to the embodiments of the present disclosure, various defect states of the compensation circuit and the light-emitting element chip can be identified, and a repair process optimized for each defect state can be performed. Based on the camera shooting results of the repaired sub-pixels of the display panel, the brightness of each sub-pixel can be compensated.

[0030] In an embodiment of the present disclosure, a plurality of light emitting elements may be connected to a compensation circuit disposed in a sub-pixel. A repair process may be performed to prevent or reduce the occurrence of dark spots between the sub-pixels.

[0031] Effects according to the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned can be clearly understood by those skilled in the art from the description of the claims.

[0032] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which may be included to provide a further understanding of the disclosure and may be incorporated in and constitute a part of this disclosure, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

[0034] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0035] Figure 1 is a block diagram schematically showing a configuration of a display device according to an embodiment of the present disclosure;

[0036] Figure 2 is a partial cross-sectional view showing a pad portion and a side wiring provided on the periphery of a display panel according to an embodiment of the present disclosure;

[0037] Figure 3 is a perspective view illustrating a spliced ​​display device according to an embodiment of the present disclosure;

[0038] Figure 4 is a plan view schematically illustrating a plan structure of a display panel according to an embodiment of the present disclosure;

[0039] FIG. 5A to FIG. 6B is a circuit diagram showing an example of a pixel circuit according to an embodiment of the present disclosure;

[0040] Figures 7 to 9 is a plan view showing a data line and a gate line connected to a pixel according to an embodiment of the present disclosure;

[0041] FIG. 10A to FIG. 14C is a diagram illustrating an example of a method of repairing a display panel according to an embodiment of the present disclosure;

[0042] Fig.15 is a cross-sectional view showing an example of a laser cutting method; and

[0043] Fig.16 is a cross-sectional view illustrating an example of a laser welding method.

[0044] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, when a detailed description of a well-known function or configuration associated with this document is determined to be unnecessary to obscure the gist of the inventive concept, its detailed description will be omitted or briefly provided. The described progress of processing steps and / or operations is an example; however, the order of steps and / or operations is not limited to the order set forth herein, and may be changed as known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals designate similar elements throughout the text. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification, and therefore may be different from the names used in the actual product.

[0046] From the example embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and their implementation methods will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but can be implemented in various different forms. On the contrary, this embodiment will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure.

[0047] The shapes, sizes, proportions, angles, quantities, etc. of various example embodiments of the present disclosure shown in the accompanying drawings are given only by way of example. Therefore, the present disclosure is not limited to the illustrations in the drawings. Unless otherwise specified, the same or similar elements are indicated by the same reference numerals throughout the specification. In the following description, when a detailed description of a related known function or configuration may unnecessarily obscure the focus of the present disclosure, a detailed explanation of the known function or configuration may be omitted or briefly provided. Any implementation described herein as an "example" is not necessarily to be interpreted as being preferred or advantageous over other implementations.

[0048] When explaining the elements, the elements are interpreted as including error ranges or tolerance ranges although there is no explicit description of the error or tolerance ranges.

[0049] Unless used with a term such as “only”, terms such as “including”, “comprising” and “having” used herein are generally intended to allow for the addition of other components. References to the singular should be interpreted as including the plural unless explicitly mentioned otherwise.

[0050] When describing the position or interconnection relationship between two components, such as "on", "above", "below", "over", "under", "down", "adjacent", "close" or "adjacent", "beside", "next to", "connected or coupled", "crossed", "intersecting", etc., unless more restrictive terms such as "immediately", "close" or "directly" are used, one or more other components may be inserted between them. In addition, the terms "left", "right", "top", "bottom", "downward", "upward", "up", "down", etc. refer to an arbitrary reference system.

[0051] When describing a temporal context, such as "after", "subsequently", "next", or "previous", it may not be continuous in time scale unless a more restrictive term such as "only", "immediately", or "directly" is used.

[0052] The terms "first", "second", "A", "B", "(a)", "(b)", etc. may be used to distinguish components from each other, but the function or structure of the component is not limited by the ordinal number preceding the component or the component name. In addition, when an element or layer is described as being "connected", "coupled" or "adhered" to another element or layer, the element or layer may not only be directly connected or adhered to the other element or layer, but also be indirectly connected or adhered to the other element or layer with one or more intermediate elements or layers disposed between these elements or layers, unless otherwise specified.

[0053] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" covers the combination of all three listed elements, the combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0054] The features of the following embodiments can be combined or associated with each other in whole or in part, and various types of interlocking and driving are technically feasible. These embodiments can be implemented independently of each other, or can be implemented together in an interrelated relationship.

[0055] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that provides carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is an electrode from which carriers flow out of the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. An n-channel transistor has a current direction flowing from the drain to the source. In the case of a p-channel transistor (e.g., a p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed according to the applied voltage. Therefore, the present disclosure is not limited to the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode, respectively, and vice versa.

[0056] The gating signal may swing between a gate-on voltage and a gate-off voltage. The transistor turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH, and the gate-off voltage may be a gate low voltage VGL. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.

[0057] The “wire” mentioned in the embodiments of the present disclosure may be interpreted as a wiring to which a signal or a voltage is applied.

[0058] Unless otherwise defined, the terms (including technical and scientific terms) used in the embodiments of the present disclosure should be interpreted as the meanings commonly understood by ordinary technicians in the field to which the present invention belongs, unless otherwise specifically defined and described, and common terms (such as dictionary-defined terms) should be interpreted according to their contextual meanings in the relevant field and should not be interpreted as overly idealized or overly formal meanings, unless explicitly defined as such herein. For example, the term "component" or "unit" can be applied, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as should be understood by ordinary technicians in the field.

[0059] Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Reference Figure 1 , the display device includes a display panel PN having a plurality of pixels arranged in a display area AA and a display panel driving circuit for driving the display panel PN.

[0061] The display panel PN may be, but is not limited to, a panel having a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. A pixel includes a plurality of sub-pixels SP having different colors. A display area AA on the display panel PN displaying an input image may be a screen visible from the front surface of the display panel PN.

[0062] The display panel driving circuit includes a data driver DD, a gate driver GD, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0063] The input image is displayed by the sub-pixels SP arranged in the display area AA of the display panel PN. Each sub-pixel SP includes a light-emitting element and a pixel circuit driving the light-emitting element. The light-emitting element may be a light-emitting diode (LED) or a micro light-emitting diode (micro LED), but the present disclosure is not limited thereto.

[0064] On the display panel PN, a plurality of scan lines SL and a plurality of data lines DL are arranged to cross each other, and each sub-pixel SP is connected to the scan line SL and the data line DL. Figure 1 The power wiring omitted in the display panel PN may be connected to the sub-pixels SP, respectively. In the display panel PN, the non-display area NA may be disposed outside the display area AA. It should be noted that the size of the non-display area NA may be small enough so that the non-display area NA may not be recognized. In this case, the display panel PN may be referred to as a zero-border display panel.

[0065] The gate driver GD supplies a gate signal to the gate line SL in response to a gate control signal provided by the timing controller TC. The gate driver GD may be provided at least in the non-display area NA of the display panel PN (eg, Figure 1 as shown) or is set in the display area AA, and the present disclosure is not limited thereto.

[0066] The data driver DD converts the image data received from the timing controller TC into a gamma compensation voltage in response to a data control signal provided by the timing controller TC, and outputs a data voltage The data voltage output from the data driver DD is fed to the data lines DL.

[0067] The timing controller TC aligns the image data input from the outside and provides the aligned image data to the data driver DD. The timing controller TC may generate a gate control signal and a data control signal based on a timing signal (e.g., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) synchronized with the input image signal. The timing controller TC provides the gate control signal to the gate driver GD and the data control signal to the data driver DD to control the timing of the operation of the gate driver GD and the data driver DD.

[0068] The non-display area NA may have link wiring and pad electrodes disposed therein to transmit signals to the sub-pixels SP in the display area AA. One or more of a gate driver IC in which a circuit of a gate driver GD is integrated and a data driver IC in which a circuit of a data driver DD is integrated may be disposed in the non-display area NA. One or more of the gate driver IC and the data driver IC may be disposed on a rear surface of the display panel PN (e.g., a rear surface without the sub-pixels SP). The non-display area NA may be minimized or reduced so that the non-display area NA is not visible when an image is displayed on the display panel PN.

[0069] The display panel driving circuit may be connected to the display panel PN in various ways. For example, the gate driver GD may be provided in the non-display area NA by a gate-in-panel (GIP) method, or between sub-pixels SP in the display area AA by a gate-in-active-area (GIA) method. The data driver DD and the timing controller TC may be formed on a separate flexible film and a PCB, and the data driver DD and the timing controller TC may be electrically connected to the display panel PN by bonding a terminal of the flexible film to a pad electrode formed on the non-display area NA of the display panel PN. The flexible film bonded to the display panel PN may be connected to a PCB on which circuit elements are mounted and wiring is formed.

[0070] Side wiring for connecting the signal wiring on the front surface of the display panel PN to the pad electrode on the rear surface of the display panel PN may be formed on the side surface of the periphery of the display panel PN. This method of making electrical connections between the front and rear surfaces of the display panel PN via the side wiring may be used to minimize or significantly reduce the non-display area NA visible on the front surface of the display panel PN. Figure 2 In FIG. 1 , “SRL” refers to this side wiring. When the gate driver GD, the data driver DD, and the timing controller TC are electrically connected to the display panel PN as described above, a substantially borderless screen can be implemented on the display panel PN.

[0071] Reference Figure 2 , a plurality of pad electrodes are provided in the non-display area NA of the display panel PN to transmit various signals to the sub-pixels SP. For example, a first pad electrode PAD1 that transmits a signal to the sub-pixel SP may be provided in the non-display area NA located at the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to a circuit element such as a flexible film and a PCB is provided in the non-display area NA located at the rear surface of the display panel PN. Only the pad area where the first pad electrode PAD1 is located is arranged in the non-display area NA located at the front periphery of the display panel PN where an image is displayed, thereby minimizing or reducing the size of the non-display area.

[0072] Various signal wirings connected to the sub-pixel SP, such as the gate line SL or the data line DL, may extend into the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0073] The display panel PN may include a side wiring SRL disposed on a side surface of the periphery of the display panel PN. The side wiring SRL may electrically connect a first pad electrode PAD1 disposed on the front periphery of the display panel PN and a second pad electrode PAD2 disposed on the rear periphery of the display panel PN while crossing the side surface of the display panel PN. A signal output from a circuit component disposed on the rear surface of the display panel PN may be transmitted to the sub-pixel SP and the gate driver GD within the display area AA through the second pad electrode PAD2, the side wiring SRL, and the first pad electrode PAD1. Therefore, a signal transmission path crossing the front surface, the side surface, and the rear surface may be formed at the periphery of the display panel PN, thereby minimizing or reducing the area of ​​the non-display area NA on the front surface of the display panel PN.

[0074] Multiple display modules can be combined on a plane to realize a widescreen spliced ​​display device. Each display module can be implemented as a single display device, and the combination of multiple display modules can be implemented as a widescreen spliced ​​display device. Each display module can include a single display panel PN, a driving circuit of the display panel PN, and a circuit element connected to the rear surface of the display panel PN and a covering member of the module.

[0075] Reference Figure 3 , the widescreen spliced ​​display TD includes a plurality of display modules arranged on an XY plane. Each display module includes a display panel PN on which an input image is reproduced. When the non-display area NA is minimized or reduced at the front periphery of each display panel PN, a widescreen image can be reproduced without visible seams between adjacent display panels PN.

[0076] The display panels PN may be assembled on a plane so that a spacing D1 between an outermost pixel PX of one display panel PN and an outermost pixel PX of another display panel PN adjacent to the display panel PN is substantially the same as a spacing D2 between adjacent pixels PX within a display area AA of the display panel PN. As a result, throughout the widescreen display area of ​​the spliced ​​display device TD, the spacings D1 and D2 between adjacent pixels PX are the same, and thus the seam area is invisible.

[0077] In a spliced ​​display TD, multiple display modules can share one timing controller TC. A host system can be connected to multiple timing controllers TC, can send image signals to the timing controller TC to be reproduced on all display panels PN of a large screen implementing the spliced ​​display TD, and can synchronize the timing controllers TC.

[0078] Figure 4 is a plan view schematically illustrating a plan structure of a display panel according to an embodiment of the present disclosure.

[0079] Reference Figure 4 The display panel PN includes a substrate SUBS on which a pixel array and a circuit of a gate driver GD are disposed. The display panel 100 may be, but is not limited to, a panel having a rectangular structure having a length in a row direction (X-axis direction), a width in a column direction (Y-axis direction), and a thickness in a thickness direction (Z-axis direction).

[0080] The substrate SUBS may be an insulating substrate supporting a component disposed on an upper portion of the display device. The substrate SUBS may be a stacked structure of a plurality of substrates. The substrate SUBS may include glass, plastic, or a flexible polymer film. For example, the flexible polymer film may be made of at least one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyether sulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which are examples only and are not necessarily limited thereto.

[0081] On one surface (or front surface) of the substrate SUBS, the display area AA may include a plurality of pixel areas UPA, a plurality of gate drive areas GA, and a plurality of pad areas PA1, PA2. One or more pixels PX may be provided in each pixel area UPA. The pixel area UPA may be arranged along a plurality of row lines and a plurality of column lines. Each pixel PX includes a plurality of sub-pixels SP having different colors. Each sub-pixel SP may include a light-emitting element and a pixel circuit, and emit light independently. The sub-pixel SP may include, but is not limited to, a red sub-pixel, a blue sub-pixel, and a green sub-pixel. For example, the sub-pixel SP may also include a white sub-pixel, or include a cyan sub-pixel, a magenta sub-pixel, and a yellow sub-pixel.

[0082] The plurality of gate drive areas GA include circuits of a gate driver GD. The gate drive area GA may be formed between the plurality of pixel areas UPA along the row direction and / or the column direction. The gate driver GD formed in the gate drive area GA may provide a gate signal to the plurality of gate lines SL. The gate drive area GA may be disposed between the pixel areas UPA adjacent in the row direction (X-axis direction).

[0083] The first pad area PA1 includes a plurality of first pad electrodes PAD1 disposed on the front periphery of one side (or upper side) of the display panel PN. The first pad electrode PAD1 may send various signals to various wirings extending from the display area AA in the column direction. The first pad electrode PAD1 includes: a data pad DP connected to the data line DL for sending a data voltage from the data driver DD to the data line DL; and a gate pad GP connected to the gate driver GD for sending a clock signal, a start signal, a gate low voltage, a gate high voltage, etc. to the gate driver GD. The clock signal, the start signal, the gate low voltage, the gate high voltage, etc. for driving the gate driver GD may be generated from the timing controller TC and applied to the gate pad GP through the level shifter and the PCB. The first pad electrode PAD1 may include a plurality of power supply wirings to which a DC voltage (or a constant voltage) is applied.

[0084] The substrate SUBS of the display panel PN includes a gate drive wiring GVL connected to the gate pad GP and extending in the column direction and a plurality of gate drive wirings GVL extending in the row direction. The gate drive wiring in the column direction and the gate drive wiring GVL in the row direction may be connected through a contact hole penetrating an insulating film. The gate drive wiring GVL transmits a signal (such as a clock signal, a start signal, a gate high voltage, a gate low voltage, etc.) required to drive the gate driver GD distributed and arranged in the gate drive area GA to the circuit of the gate driver GD.

[0085] The second pad area PA2 includes a plurality of first pad electrodes PAD1 disposed on the front periphery of the other side (or lower side) of the display panel PN. The second pad area PA2 may include a plurality of low potential power pads VP2.

[0086] The DC voltage applied to the power wiring may be output from a power circuit omitted in the drawing and may be applied to power pads VP1 and VP2 connected to the power wiring through a PCB. The power circuit may be a DC-DC converter provided on a PCB or control boards CTB1 and CTB2 arranged on the rear surface of the display panel PN to convert a DC input voltage from a main power source into a DC voltage suitable for driving the display panel PN.

[0087] The power pads VP1 and VP2 connected to the power wiring may include: a plurality of high potential power pads VP1, which are arranged on the first pad area PA1 for providing a high potential power voltage to the high potential power wiring VL1; and a plurality of low potential power pads VP2, which are arranged on the second pad area PA2 for providing a low potential power voltage to the low potential power wiring VL2.

[0088] The data pads DP connected one-to-one to the data lines DL may have a relatively narrow width, while the power pads VP1 and VP2 and the gate pad GP may have a relatively wide width. The low potential power pad VP2 may have a wider width than the high potential power pad VP2.

[0089] In order to minimize or reduce the outermost non-display area NA of the display panel PN, the pixel array, wiring and pads are formed on the front surface of the substrate of the display panel PN, and then the outermost periphery outside the scribing line SCL shown by the dashed line can be removed to provide a substrate SUBS with minimized or reduced non-display area NA. After the scribing process, the rough edges of the periphery of the substrate SUBS can be ground or laser-finished. This will leave short pad electrodes PAD1 and PAD2 with reduced size on the front periphery of the substrate SUBS.

[0090] The data line DL may extend along the column direction (Y direction) on the substrate SUBS and overlap the pixel area UPA. The data line DL provides a data voltage to the corresponding pixel circuit of the sub-pixel SP. The gate line SL may extend along the row direction (X direction) on the substrate SUBS of the display panel PN and overlap the pixel area UPA and the gate drive area GA. The gate line SL may cross the pixel area UPA and the gate drive area GA to provide a gate signal from the gate driver GD to the corresponding pixel circuit of the sub-pixel SP.

[0091] The high potential power wiring VL1 extends in the column direction (Y direction), and at least one of them is connected to the auxiliary high potential power wiring AVL1 extending in the row direction (X direction) in a mesh structure. The auxiliary high potential power wiring AVL1 is connected to the sub-pixels SP arranged in the row direction (X direction). Therefore, the high potential power supply voltage applied to the high potential power wiring VL1 can be provided to the sub-pixels SP through the auxiliary high potential power wiring AVL1.

[0092] The low potential power wiring VL2 may extend in the column direction (Y direction), and at least one of them may be connected to the auxiliary low potential power wiring AVL2 extending in the row direction (X direction) in a mesh structure. The auxiliary low potential power wiring AVL2 is connected to the sub-pixels SP arranged in the row direction (X direction). Therefore, the sub-pixels SP are connected to the auxiliary low potential power wiring AVL2 to which the low potential power supply voltage is applied.

[0093] The mesh structure of the power wiring may allow the resistance of the power wiring to be reduced, which may improve the voltage drop of the high potential power voltage and the deviation of the power voltage within the display area AA.

[0094] The substrate SUBS of the display panel PN may have one or more alignment keys AK1 and AK2 arranged between the pixel areas UPA. The alignment keys AK1 and AK2 may be used for alignment in the manufacturing process of the display panel PN. The first alignment key AK1 may be provided in the gate drive area GA. The first alignment key AK1 may be used to check the alignment position of each light emitting element. The first alignment key AK1 may be formed in a cross-shaped pattern, but is not limited thereto. The second alignment key AK2 may overlap with the high potential power wiring VL1. The high potential power wiring VL1 may include a hole formed at a position overlapping with the second alignment key AK2, so that the second alignment key AK2 and the high potential power wiring VL1 may be distinguished and spaced apart from each other. The second alignment key AK2 may be used to align the display panel PN with a donor substrate. The donor substrate is an intermediate medium for mounting the light emitting element on the substrate SUBS of the display panel PN. A plurality of light emitting elements manufactured on a semiconductor wafer may be attached and transferred to a donor substrate, and the light emitting elements attached to the donor substrate may be transferred to the substrate SUBS. The second alignment key AK2 may be formed in a circular or annular pattern, but is not limited thereto. Figure 4 A detailed planar structure of the display panel is shown, but it is provided by way of example only, and the present disclosure is not limited thereto. For example, the arrangement and number of the pad areas PA1 and PA2 may be changed in various ways, one or more alignment keys AK1 and AK2 may be omitted, and / or the arrangement and shape of the gate drive area GA may be changed in various ways.

[0095] Each sub-pixel SP includes a pixel circuit that drives a light emitting element.

[0096] FIG. 5A to FIG. 6B is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure. FIG. 5A to FIG. 6B An example is shown in which the driving element DT and the switching elements M1 and M2 are implemented with p-channel transistors, but is not limited thereto.

[0097] Reference Figure 5A and Figure 5B The pixel circuit includes a light emitting element LD, a driving element DT, a first switching element M1 and a compensation circuit 500. In this embodiment, one driving element DT may be electrically connected to one compensation circuit 500 and one light emitting element LD.

[0098] The light emitting element LD may be a micro LED. The light emitting element LD may include an anode electrode and a cathode electrode. The light emitting element LD may have, but is not limited to, a vertical structure in which electrodes are provided on the upper and lower parts of a chip in which the light emitting element is integrated. The light emitting element LD may be implemented in a lateral structure or a flip chip structure.

[0099] The light emitting element LD, the driving element DT, and the switching element M1 may be connected in series between a pixel driving voltage VDD and a cathode voltage VSS.

[0100] The driving element DT adjusts the current flowing through the drain-source channel according to the gate-source voltage. The gate-source voltage of the driving element DT varies according to the data voltage Vdata of the pixel data applied to the gate electrode of the driving element DT. Therefore, the current flowing through the driving element DT varies according to the data voltage Vdata. The light-emitting element LD can be driven by the current from the driving element DT to emit light. The capacitor C can be connected between the gate electrode and the first electrode of the driving element DT. The capacitor C is charged with the gate-source voltage of the driving element DT.

[0101] like Figure 5A As shown, the driving element DT may be connected between the light emitting element LD and the first switching element M1. In this case, the driving element DT includes a gate electrode to which the data voltage Vdata is applied, a first electrode connected to the cathode electrode of the light emitting element LD, and a second electrode connected to the first electrode of the first switching element M1.

[0102] like Figure 5B As shown, the driving element DT may be connected between a node to which the pixel driving voltage VDD is applied and the first switching element M1. In this case, the driving element DT includes a gate electrode to which the data voltage Vdata is applied, a first electrode to which the pixel driving voltage VDD is applied, and a second electrode connected to the first electrode of the switching element M1.

[0103] The first switch element M1 switches the current path between the pixel driving voltage VDD and the cathode voltage VSS. The first switch element M1 can be turned on in response to the gate-on voltage of one of the selection signals GATE1, GATE2 and GATE3, and can be turned off in response to the gate-off voltage. When the switch element M1 is turned on, the driving element DT and the light emitting element LD can be electrically connected, so that current can be provided to the light emitting element LD. When the first switch element M1 is turned off, the current path between the pixel driving voltage VDD and the cathode voltage VSS is cut off, so that no current is provided to the light emitting element LD.

[0104] like Figure 5A As shown, the first switching element M1 may be connected between the driving element DT and the cathode voltage VSS. In this case, the first switching element M1 includes a gate electrode connected to the first gate line, a first electrode connected to the second electrode of the driving element DT, and a second electrode connected to a node to which the cathode voltage VSS is applied.

[0105] like Figure 5BAs shown, the first switching element M1 may be connected between the driving element DT and the light emitting element LD. In this case, the first switching element M1 includes a gate electrode connected to the first gate line, a first electrode connected to the second electrode of the driving element DT, and a second electrode connected to the anode electrode of the light emitting element LD.

[0106] The pixel driving voltage VDD and the cathode voltage VSS are applied to all pixels PX in the display panel PN. For example, the pixel driving voltage VDD may be applied to the pixel PX via a first power line connected to all pixels PX, and the cathode voltage VSS may be applied to the pixel PX via a second power line connected to all pixels PX. In addition, a third constant voltage (e.g., a reference voltage) may be commonly applied to all pixels via a third power line.

[0107] Reference Fig. 6A and Figure 6B The pixel circuit includes a first light emitting element LD1, a second light emitting element LD2, a driving element DT, a switching element M1 and a compensation circuit 500. In this embodiment, one driving element DT can be connected to one compensation circuit 500 and two light emitting elements LD1 and LD2 connected in parallel.

[0108] The first light emitting element LD1 and the second light emitting element LD2 may each be a micro LED. Each of the light emitting elements LD1 and LD2 may include an anode electrode and a cathode electrode. The light emitting element LD may have, but is not limited to, a vertical structure in which electrodes are provided on the upper and lower parts of a chip in which the light emitting element is integrated. The light emitting element LD may be implemented in a lateral structure or a flip chip structure.

[0109] The first light emitting element LD1 and the second light emitting element LD2 may be connected in parallel. Fig. 6A As shown, the first light emitting element LD1 and the second light emitting element LD2 may be connected in parallel between the pixel driving voltage VDD and the driving element DT. In this case, the anode electrodes of the first light emitting element LD1 and the second light emitting element LD2 may be connected to the node to which the pixel driving voltage VDD is applied, and the cathode electrodes of the first light emitting element LD1 and the second light emitting element LD2 may be connected to the first electrode of the driving element DT.

[0110] like Figure 6B As shown, the first light emitting element LD1 and the second light emitting element LD2 may be connected in parallel between the switch element M1 and the cathode voltage VSS. In this case, the anode electrodes of the first light emitting element LD1 and the second light emitting element LD2 may be connected to the second electrode of the first switch element M1, and the cathode electrodes of the first light emitting element LD1 and the second light emitting element LD2 may be connected to the node to which the cathode voltage VSS is applied.

[0111] The driving element DT adjusts the current flowing through the drain-source channel according to the gate-source voltage. The gate-source voltage of the driving element DT may vary according to the data voltage Vdata of the pixel data applied to the gate electrode of the driving element DT. Therefore, the current flowing through the driving element DT varies according to the data voltage Vdata. The first light emitting element LD1 and the second light emitting element LD2 may be driven by the current from the driving element DT to emit light. The capacitor C may be connected between the gate electrode and the first electrode of the driving element DT. The capacitor C is charged with the gate-source voltage of the driving element DT.

[0112] like Fig. 6A As shown, the driving element DT may be connected between the first light emitting element LD1 and the second light emitting element LD2 and the switch element M1. In this case, the driving element DT includes a gate electrode to which the data voltage Vdata is applied, a first electrode connected to cathode electrodes of the first light emitting element LD1 and the second light emitting element LD2, and a second electrode connected to the first electrode of the switch element M1.

[0113] like Figure 6B As shown, the driving element DT may be connected between the node to which the pixel driving voltage VDD is applied and the switching element M1. In this case, the driving element DT includes a gate electrode to which the data voltage Vdata is applied, a first electrode to which the pixel driving voltage VDD is applied, and a second electrode connected to the switching element M1.

[0114] like Fig. 6A As shown, the first switch element M1 may be connected between the driving element DT and the cathode voltage VSS. Figure 6B As shown, the first switching element M1 may be connected between the driving element DT and the light emitting elements LD1 and LD2 .

[0115] The pixel circuit may further include a second switching element M2. Figure 5A and Fig. 6A As shown, the second switch element M2 may be connected between the cathode electrode and the anode electrode of the light emitting element LD, LD1 or LD2, and may be turned on in response to a gate signal applied by the compensation circuit 500. When the second switch element M2 is turned on, the cathode electrode and the anode electrode of the light emitting element LD, LD1 or LD2 are short-circuited, so that the light emitting element LD, LD1 or LD2 does not emit light. The second switch element M2 may prevent the light emitting element LD, LD1 or LD2 from emitting light when the pixel circuit is initialized and when the threshold voltage of the driving element DT is sampled. The second switch element M2 includes a gate electrode connected to a second gate line, a first electrode connected to the anode electrode of the light emitting element LD, LD1 or LD2, and a second electrode connected to the cathode electrode of the light emitting element LD, LD1 or LD2.

[0116] The first switching element M1 may be turned on in response to a gate-on voltage of a light emitting signal (which may be one of one or more gate signals GATE1, GATE2, and GATE3), and may be turned off in response to a gate-off voltage of the light emitting signal, but is not limited thereto. The second switching element M2 may be turned on in response to a gate-on voltage of a first scanning signal, and may be turned off in response to a gate-off voltage of the first scanning signal, but is not limited thereto. It should be noted that in FIG. 5A to FIG. 6B The structure of the pixel circuit shown in each of the embodiments is provided by way of example only, and the present disclosure is not limited thereto. For example, more or fewer transistors and capacitors may be included in the pixel circuit of the present disclosure.

[0117] The compensation circuit 500 is connected to a data line to which a data voltage Vdata is applied, a gate line to which one or more selection signals GATE1, GATE2, and GATE3 are applied, a gate electrode of a driving element DT, and a gate electrode of a switching element M1. First to third selection signals GATE1, GATE2, and GATE3 may be applied to the compensation circuit 500. The first to third selection signals GATE1, GATE2, and GATE3 may be interpreted as, but not limited to, a first scan signal, a second scan signal, and a light emitting signal, respectively. It should be noted that the first to third selection signals GATE1, GATE2, and GATE3 are provided only by way of example, and the pixel circuit of the present disclosure may include more than one embodiment. FIG. 5A to FIG. 6B The strobe signals shown may be more or less than the strobe signals.

[0118] The compensation circuit 500 transmits a data voltage Vdata to the gate electrode of the driving element DT by using one or more transistors. The compensation circuit 500 samples the threshold voltage of the driving element DT on the capacitor C to compensate the gate voltage of the driving element DT with the same voltage as the threshold voltage of the driving element DT. The compensation circuit 500 can compensate the threshold voltage of the driving element DT by using a source follower or a diode connection circuit. However, the present disclosure is not limited to this. For example, the compensation circuit 500 can be omitted from the pixel circuit, and the threshold voltage of the driving element DT can be compensated by the following external compensation method: based on the sensing result, the input video / image data and the driving characteristics (threshold voltage, mobility, etc.) of each pixel are adjusted by an external compensation circuit outside the display panel to compensate for the change in the driving characteristics of each pixel.

[0119] FIG. 5A to FIG. 6B The pixel circuit shown can be electrically connected to the light emitting element of another sub-pixel of the same color. Fig. 6A and Figure 6BAs shown, the cathode line CL may be connected to the cathode electrodes of the first light emitting element LD1 and the second light emitting element LD2 connected in parallel. The cathode line CL may be connected to the cathode electrodes of the first light emitting element LD1 and the second light emitting element LD2 of the sub-pixel and may extend toward another sub-pixel of the same color. A welding portion WEL overlapping the cathode line CL extending from another sub-pixel may be provided at an end of the cathode line CL. In the repair process, at least one cathode among the light emitting elements included in adjacent sub-pixels of the same color may be selectively connected to the cathode of the light emitting element of another sub-pixel at the welding portion WEL.

[0120] Figure 7 is a plan view schematically showing the structure of a pixel PX according to an embodiment of the present disclosure. Figure 7 The unit pixel PX shown in FIG. 1 may be repeated along the row direction (X-axis direction) and the column direction (Y-axis direction) in the display area AA of the display panel PN. Figure 7 In the embodiment, the strobe signal GATE may include one or more strobe signals, such as FIG. 5A to FIG. 6B The first to third gate signals GATE1, GATE2, and GATE3 are shown, but the present disclosure is not limited thereto.

[0121] Reference Figure 7 , the pixel PX includes a first subpixel R1 of a first color, a second subpixel R2 of a first color, a first subpixel G1 of a second color, a second subpixel G2 of a second color, a first subpixel B1 of a third color, and a second subpixel B2 of a third color. The first color, the second color, and the third color may be red, green, and blue, respectively, but the present disclosure is not limited thereto.

[0122] Since two sub-pixels are arranged for each color in the unit pixel PX, it is beneficial to repair the defective sub-pixels. For example, when a light-emitting element or a driving element is found to be defective in the two sub-pixels R1 and R2 of the first color, the corresponding pixel PX can be driven normally by performing a repair process of appropriately adjusting the brightness of another light-emitting element arranged in the two sub-pixels R1 and R2 of the first color. The method for adjusting the brightness of the sub-pixels can use an optical compensation scheme. For example, the compensation circuit in the timing controller TC can compensate the brightness of each sub-pixel by adding or multiplying the brightness compensation value used to compensate the brightness of the defective sub-pixel with the pixel data of another sub-pixel of the same color to be written. The brightness characteristics of each sub-pixel can be measured by using the camera shooting results of the pixel. This compensation circuit can compensate the brightness of each sub-pixel by using a lookup table in which the compensation values ​​preset for each sub-pixel are listed.

[0123] In order to reduce the length of the pixel PX in the row direction (X-axis direction), the first sub-pixels and the second sub-pixels of various colors can be arranged along the column direction (Y-axis direction). The luminous efficiency of the light-emitting element of the first color may be worse than the luminous efficiency of the light-emitting element of the second color and the light-emitting element of the third color. In view of this, the light-emitting element of the first color can be implemented as a larger light-emitting element chip than the light-emitting element of the second color and the light-emitting element of the third color.

[0124] The first sub-pixel R1 and the second sub-pixel R2 of the first color are arranged adjacent to each other in the column direction (Y-axis direction). The first sub-pixel R1 of the first color may be arranged on the first pixel row PL1. The second sub-pixel R2 of the first color may be arranged on the second pixel row PL2 below the first pixel row PL1. The first sub-pixel G1 of the second color is arranged on the first pixel row PL1 so as to be adjacent to the first sub-pixel R1 of the first color in the row direction (X-axis direction). The second sub-pixel G2 of the second color may be arranged on the second pixel row PL2 so as to be adjacent to the first sub-pixel G1 of the second color in the column direction (Y-axis direction). The first sub-pixel G1 and the second sub-pixel G2 of the second color are adjacent to each other in the column direction (Y-axis direction).

[0125] The first subpixel B1 of the third color is arranged on the first pixel row PL1 so as to be adjacent to the first subpixel G1 of the second color in the row direction (X-axis direction). The second subpixel B2 of the third color is arranged on the second pixel row PL2 so as to be adjacent to the first subpixel B1 of the third color in the column direction (Y-axis direction). The first subpixel B1 and the second subpixel B2 of the third color are adjacent to each other in the column direction (Y-axis direction).

[0126] One data line and one or more gate lines may be connected to the compensation circuit 500 of the sub-pixels R1 , R2 , G1 , G2 , B1 , and B2 .

[0127] When a plurality of gate signals are applied to each of the sub-pixels R1, R2, G1, G2, B1, and B2, the gate lines to which the gate signals are independently applied are connected to the sub-pixels R1, R2, G1, G2, B1, and B2 on the first pixel row PL1 and the second pixel row PL2. For example, the first gate line to which the first gate signal GATE1 is applied may be connected to the sub-pixels R1, R2, G1, G2, B1, and B2, and the second gate line to which the second gate signal GATE2 is applied may be connected to the sub-pixels R1, R2, G1, G2, B1, and B2. In addition, the third gate line to which the third gate signal GATE3 is applied may be connected to the sub-pixels R1, R2, G1, G2, B1, and B2.

[0128] The data driver DD converts the pixel data received from the timing controller TC into data voltages suitable for driving sub-pixels. The data driver DD may convert the pixel data of the first color of the first sub-pixel R1 to be written in the first color and the pixel data of the first color of the second sub-pixel R2 to be written in the first color into the 1-1 data voltage VdataR1 and the 1-2 data voltage VdataR2, respectively, and output them. The data driver DD may convert the pixel data of the second color of the first sub-pixel G1 to be written in the second color and the pixel data of the second color of the second sub-pixel G2 to be written in the second color into the 2-1 data voltage VdataG1 and the 2-2 data voltage VdataG2, respectively, and output them. The data driver DD may convert the pixel data of the third color of the first sub-pixel B1 to be written in the third color and the pixel data of the third color of the second sub-pixel B2 to be written in the third color into the 3-1 data voltage VdataB1 and the 3-2 data voltage VdataB2, respectively, and output them.

[0129] The data lines DLR1 to DLB2 cross the gate line GL. The data lines DLR1 to DLB2 may be independently connected for each sub-pixel. The first sub-pixel R1 of the first color is connected to the 1-1 data line DLR1 and is charged with the 1-1 data voltage VdataR1 provided through the 1-1 data line DLR1. The second sub-pixel R2 of the first color is connected to the 1-2 data line DLR2 and is charged with the 1-2 data voltage VdataR2 provided through the 1-2 data line DLR2. Since the data lines DLR1 and DLR2 connected to the first sub-pixel R1 and the second sub-pixel R2 of the first color are separated, the first sub-pixel R1 and the second sub-pixel R2 may be charged with different data voltages VdataR1 and VdataR2.

[0130] The first subpixel G1 of the second color is connected to the 2-1 data line DLG1 and is charged with the 2-1 data voltage VdataG1 provided by the 2-1 data line DLG1. The second subpixel G2 of the second color is connected to the 2-2 data line DLG2 and is charged with the 2-2 data voltage VdataG2 provided by the 2-2 data line DLG2. Since the data lines DLG1 and DLG2 connected to the first subpixel G1 and the second subpixel G2 of the second color are separated, the first subpixel G1 and the second subpixel G2 can be charged with different data voltages VdataG1 and VdataG2.

[0131] The first sub-pixel B1 of the third color is connected to the 3-1 data line DLB1 and is charged with the 3-1 data voltage VdataB1 provided through the 3-1 data line DLB1. The second sub-pixel B2 of the third color is connected to the 3-2 data line DLB2 and is charged with the 3-2 data voltage VdataB2 provided through the 3-2 data line DLB2. Since the data lines DLB1 and DLB2 connected to the first sub-pixel B1 and the second sub-pixel B2 of the third color are separated, the first sub-pixel B1 and the second sub-pixel B2 can be charged with different data voltages VdataB1 and VdataB2. In other words, in Figure 7 In an embodiment, each of two sub-pixels of the same color can be driven independently.

[0132] Reference Figure 8 , the data lines DLR, DLG, and DLB may be commonly connected to sub-pixels of the same color, and may be divided between sub-pixels of different colors.

[0133] The first subpixel R1 and the second subpixel R2 of the first color are connected to the first data line DLR and are simultaneously charged with the first data voltage VdataR provided through the first data line DLR.

[0134] The first subpixel G1 and the second subpixel G2 of the second color are connected to the second data line DLG and are simultaneously charged with the second data voltage VdataG provided through the second data line DLG. The first subpixel B1 and the second subpixel B2 of the third color are connected to the third data line DLB and are simultaneously charged with the third data voltage VdataB provided through the third data line DLB.

[0135] Reference Fig. 9 , the first sub-pixel R1 of the first color is connected to the 1-1 data line DLR1 and is charged with the 1-1 data voltage VdataR1 provided through the 1-1 data line DLR1. The second sub-pixel R2 of the first color is connected to the 1-2 data line DLR2 and is charged with the 1-2 data voltage VdataR2 provided through the 1-2 data line DLR2. Since the data lines DLR1 and DLR2 connected to the first sub-pixel R1 and the second sub-pixel R2 of the first color are separated, the first sub-pixel R1 and the second sub-pixel R2 can be charged with different data voltages VdataR1 and VdataR2, thereby emitting light of different brightness.

[0136] The first subpixel G1 and the second subpixel G2 of the second color are connected to the second data line DLG and are charged with the second data voltage VdataG provided through the second data line DLG. The first subpixel B1 and the second subpixel B2 of the third color are connected to the third data line DLB and are charged with the third data voltage VdataG provided through the third data line DLB.

[0137] Figures 7 to 9 At least one of the sub-pixels R1, R2, G1, G2, B1 and B2 shown may include Fig. 6A or Figure 6B Each of the sub-pixels R1, R2, G1, G2, B1 and B2 may include light emitting elements LD1 and LD2 connected in parallel. Fig. 6A or Figure 6B The light emitting elements LD1 and LD2 are shown, but are not limited thereto. For example, each sub-pixel R1 and R2 of the first color may include Figure 5A or the light emitting element LD shown in FIG. 5B, and each of the sub-pixels G1, G2, B1, and B2 of the second color and the third color may include a light emitting element LD as shown in FIG. Fig. 6A or Figure 6B The light emitting elements LD1 and LD2 are shown.

[0138] FIG. 10A to FIG. 14C is a diagram illustrating a method for repairing a display panel according to an embodiment of the present disclosure. FIG. 10A to FIG. 14C , the first sub-pixel SP1 and the second sub-pixel SP2 may be sub-pixels of the same color. The first sub-pixel SP1 may be a sub-pixel of a pixel (Pixel (N)) disposed on a first pixel row PL1, and the second sub-pixel SP2 may be a sub-pixel of a pixel (Pixel (N+1)) disposed on a second pixel row PL2, but is not limited thereto. The first sub-pixel SP1 and the second sub-pixel SP2 may emit light of the same color and may be adjacent to each other in the column direction (Y-axis direction) of the display panel, but is not limited thereto.

[0139] The first subpixel SP1 may include a 1-1th light emitting element LD11 and a 1-2th light emitting element LD12 connected in parallel. The second subpixel SP2 may include a 2-1th light emitting element LD21 and a 2-2nd light emitting element LD22 connected in parallel.

[0140] like 6A to 14CAs shown, the first subpixel SP1 may include a first driving element DT that provides current to the 1-1th light emitting element LD11 and the 1-2th light emitting element LD12, a 1-1th switching element M1 that switches the current path between the pixel driving voltage VDD and the cathode voltage VSS, a 1-2nd switching element M2 connected between the anode electrode and the cathode electrode of the 1-1th light emitting element LD11 and the 1-2nd light emitting element LD12, and a first compensation circuit 500 connected to the first driving element DT, the 1-1th switching element M1, and the 1-2nd switching element M2. The second subpixel SP2 may include a second driving element DT that provides current to the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22, a 2-1st switching element M1 that switches a current path between a pixel driving voltage VDD and a cathode voltage VSS, a 2-2nd switching element M2 connected between the anode electrode and the cathode electrode of the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22, and a second compensation circuit 500 connected to the second driving element DT, the 2-1st switching element M1, and the 2-2nd switching element M2.

[0141] Welding portions WEL respectively disposed at ends of the first cathode line CL1 and the second cathode line CL2 extending from the first subpixel SP1 and the second subpixel SP2 may each include metal layers overlapping each other with an insulating layer interposed therebetween and may be selectively connected in a welding process.

[0142] FIG. 10A to FIG. 12C It is assumed that at least one of the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 of the first sub-pixel SP1 is defective, and the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22 of the second sub-pixel SP2 can be driven normally to emit light. Since the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 are connected in parallel, dark spots and bright spots do not appear simultaneously in the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12.

[0143] In the repair method, the sub-pixel may be inspected once or more times for defects. For example, while driving all pixels of the display panel, the dark spots and bright spots of each sub-pixel may be inspected by using a high-resolution camera or a brightness meter.

[0144] FIG. 10A to FIG. 10C is a diagram illustrating steps of a repair process applied when both the 1-1 light emitting element LD11 and the 1-2 light emitting element LD12 of the first subpixel SP1 have a short-circuit defect.

[0145] The first cathode line CL1 is connected to cathode electrodes of the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 and extends toward the second sub-pixel SP2. The second cathode line CL2 may be connected to cathode electrodes of the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22 and may extend toward the first sub-pixel SP1. Ends of the first cathode line CL1 and the second cathode line CL2 facing each other may overlap at the welding portion WEL with an insulating layer interposed therebetween.

[0146] During the initial defect identification process, such as Fig. 10A As shown, both the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 of the first sub-pixel SP1 can be initially found to be dark spot defects. At this time, the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22 of the second sub-pixel SP2 can be driven normally and can be identified as bright spots. In the initial defect identification process, it may be difficult to know which element is defective, and it may be based on the following examples: Fig. 10B The results of the first stage repair process are shown to identify defective components.

[0147] When Fig. 10A When a defect is initially identified as shown, the first stage of repair processing is performed. Fig. 10B As shown in ① in FIG. 1 , the first cathode line CL1 is cut between the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 of the first sub-pixel SP1, and the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 are thus electrically separated. Next, as Fig. 10B As shown in ② in FIG. 2 , the welding portion WEL of the first cathode line CL1 extending from the first sub-pixel SP1 and the welding portion WEL of the second cathode line CL2 extending from the second sub-pixel SP2 can be welded to each other and electrically connected. As a result, if all the light emitting elements LD11, LD12, LD21 and LD22 of the first sub-pixel SP1 and the second sub-pixel SP2 are all recognized as dark spots, in the second stage repair process, as shown in FIG. Fig. 10C As shown in ③ in FIG. 3 , the first cathode line CL1 is cut between the cathode electrode of the 1-2 light emitting element LD12 and the welding portion WEL. At this time, the cathode electrodes of the 2-1 light emitting element LD21 and the 2-2 light emitting element LD22 are electrically separated from the cathode electrodes of the 1-1 light emitting element LD11 and the 1-2 light emitting element LD12. Therefore, the 2-1 light emitting element LD21 and the 2-2 light emitting element LD22 of the second sub-pixel SP2 can be driven normally to emit light. The cathode electrodes of the 1-1 light emitting element LD11 and the 1-2 light emitting element LD12 remain as dark spots that do not emit light.

[0148] FIG. 11A to FIG. 11Cis a diagram illustrating steps of a repair process applied when the 1-1th light emitting element LD11 of the first sub-pixel SP1 is short-circuited and the 1-2nd light emitting element LD12 is a normally driven element.

[0149] During the initial defect identification process, Fig.11A As shown, the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 of the first sub-pixel SP1 may be initially found to be dark spot defects. At this time, the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22 of the second sub-pixel SP2 may be driven normally and may be identified as bright spots. In the initial defect identification process, it may be difficult to know which element is defective, and it may be possible to identify the defective element based on the following examples: Fig. 11B The results of the first stage repair process are shown to identify defective components.

[0150] When Fig.11A When a defect is initially identified as shown, a repair process is performed. In the first stage of the repair process, as shown in Fig. 11B As shown in ① in FIG. 1 , the first cathode line CL1 is cut between the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 of the first sub-pixel SP1, and the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 are thus electrically separated. Next, as Fig. 11B As shown in ② in FIG. 2 , the welding portion WEL of the first cathode line CL1 extending from the first sub-pixel SP1 and the welding portion WEL of the second cathode line CL2 extending from the second sub-pixel SP2 can be welded to each other and electrically connected. As a result of the first stage repair process, if the 1-1st light emitting element LD11 is identified as a dark spot, and each of the 1-2nd light emitting element LD12, the 2-1st light emitting element LD21, and the 2-2nd light emitting element LD22 is identified as a bright spot emitting light at a brightness of 33%, then in the second stage repair process, as shown in FIG. Fig. 11C As shown in ④, the second cathode line CL2 is cut between the cathode electrode of the 2-1st light emitting element LD21 and the cathode electrode of the 2-2nd light emitting element LD22, thereby electrically separating the corresponding cathode electrodes. At this time, while the cathode electrodes of the 1-2nd light emitting element LD12 and the 2-1st light emitting element LD21 are electrically connected to each other, these cathode electrodes are electrically separated from the cathode electrodes of the 1-1st light emitting element LD11 and the 2-2nd light emitting element LD22. As a result, the 1-2nd light emitting element LD12 and the 2-1st light emitting element LD21 of the first sub-pixel SP1 can be driven normally and emit light at the same brightness ratio. The 1-1st light emitting element LD11 and the 2-2nd light emitting element LD22 remain as dark spots that do not emit light.

[0151] In such Fig. 11BAfter the first stage repair process shown, the 1-2 light emitting element LD12, the 2-1 light emitting element LD21, and the 2-2 light emitting element LD22 can emit light, but there is a brightness difference between the sub-pixels SP1 and SP2. For example, when the brightness of the 1-1 light emitting element LD11 is 100%, and the brightness of the 2-1 light emitting element LD21 and the 2-2 light emitting element LD22 is 50%, the brightness ratio between the sub-pixels SP1 and SP2 can be made the same. This is because in a state where the cathode lines CL1 and CL2 of the sub-pixels SP1 and SP2 are connected to each other, it is difficult to drive one light emitting element LD11 connected to one compensation circuit at 100% brightness and drive two light emitting elements LD21 and LD22 connected to the other compensation circuit at 50% brightness. Therefore, by performing the above Fig. 11C In the second stage repair process shown, one light emitting element LD12 and one light emitting element LD12 in the sub-pixels SP1 and SP2, respectively, are driven at the same 100% brightness, so that the brightness difference between the sub-pixels SP1 and SP2 can be minimized or reduced.

[0152] FIG. 12A to FIG. 12C is a diagram illustrating steps of a repair process applied when the 1-2 th light emitting element LD12 of the first subpixel SP1 is short-circuited and the 1-1 th light emitting element LD11 is a normal driving element.

[0153] During the initial defect identification process, Fig. 12A As shown, both the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 of the first sub-pixel SP1 can be initially found to be dark spot defects. At this time, the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22 of the second sub-pixel SP2 can be driven normally and can be identified as bright spots. In the initial defect identification process, it may be difficult to know which element is defective, and it may be based on the following examples: Fig. 12B The results of the first stage repair process are shown to identify defective components.

[0154] When Fig. 12A When a defect is initially identified as shown, the first stage of repair processing is performed. Fig. 12B As shown in ① in FIG. 1 , the first cathode line CL1 is cut between the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 of the first sub-pixel SP1, and the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 are thus electrically separated. Next, as Fig. 12BAs shown in ② in FIG. 2 , the cathode lines CL1 and CL2 can be electrically connected to each other at a welding portion WEL where the first cathode line CL1 extending from the first sub-pixel SP1 overlaps the second cathode line CL2 extending from the second sub-pixel SP2. As a result of the first stage repair process, if the 1-2nd light emitting element LD12, the 2-1st light emitting element LD21, and the 2-2nd light emitting element LD22 are identified as dark spots, and the 1-1st light emitting element LD11 is identified as a bright spot, then in the second stage repair process, as shown in FIG. Fig. 12C As shown in ③, the first cathode line CL1 is cut between the cathode electrode of the 1-2 light emitting element LD12 and the welding portion WEL. At this time, the cathode electrodes of the 2-1 light emitting element LD21 and the 2-2 light emitting element LD22 are electrically separated from the cathode electrode of the 1-2 light emitting element LD12. As a result, the cathode lines CL1 and CL2 extending from the sub-pixels SP1 and SP2 are separated, so the 1-1 light emitting element LD11 of the first sub-pixel SP1 is driven with 100% brightness, and the 2-1 light emitting element LD21 and the 2-2 light emitting element LD22 of the second sub-pixel SP2 can each emit light with 50% brightness. Therefore, the first sub-pixel SP1 and the second sub-pixel SP2 can emit light at the same brightness ratio. The 1-2 light emitting element LD12 remains as a dark spot that does not emit light.

[0155] When the transistors of sub-pixels SP1 and SP2 are defective, current cannot flow through the light-emitting elements, so they can appear as dark spots, such as Fig.13A Alternatively, the amount of current flowing through the light-emitting elements cannot be adjusted, so they can emit light at maximum brightness, appearing as bright spots, such as Fig.14A In the case of dark spot and bright spot defects due to defective transistors, the repair processes of the first stage and the second stage are basically the same.

[0156] FIG. 13A to FIG. 13C is a diagram illustrating steps of a repair process applied when a transistor (eg, a driving element (DT) of a first sub-pixel SP1) is defective and the first sub-pixel SP1 appears as a dark spot.

[0157] During the initial defect identification process, Fig.13A As shown, both the 1-1 light emitting element LD11 and the 1-2 light emitting element LD12 of the first sub-pixel SP1 can be initially found to be dark spot defects. At this time, the 2-1 light emitting element LD21 and the 2-2 light emitting element LD22 of the second sub-pixel SP2 can be driven normally and can be identified as bright spots. In the initial defect identification process, it may be difficult to know which element is defective, and it may be based on the following examples: Fig. 13B The results of the first stage repair process are shown to identify defective components.

[0158] When Fig.13A When a defect is initially identified as shown, the first stage of repair processing is performed. Fig. 13B As shown in ① in FIG. 1 , the first cathode line CL1 is cut between the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 of the first sub-pixel SP1, and the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 are thus electrically separated. Next, as Fig. 13B As shown in ② in FIG. 2 , the cathode lines CL1 and CL2 may be electrically connected to each other at a welding portion WEL where the first cathode line CL1 extending from the first sub-pixel SP1 overlaps the second cathode line CL2 extending from the second sub-pixel SP2. As a result of the first stage repair process, if the 1-2nd light emitting element LD12, the 2-1st light emitting element LD21, and the 2-2nd light emitting element LD22 are identified as bright spots, and the 1-1st light emitting element LD11 is identified as a dark spot, then in the second stage repair process, as shown in FIG. Fig. 13C As shown in ④, the second cathode line CL2 is cut between the cathode electrode of the 2-1st light emitting element LD21 and the cathode electrode of the 2-2nd light emitting element LD22. At this time, the cathode electrodes of the 1-2nd light emitting element LD12 and the 2-1st light emitting element LD21 are electrically connected to each other, and these cathode electrodes are electrically separated from the cathode electrodes of the 1-1st light emitting element LD11 and the 2-2nd light emitting element LD22. Therefore, the 1-2nd light emitting element LD12 and the 2-1st light emitting element LD21 can be driven normally and emit light at the same brightness ratio. The 1-1st light emitting element LD11 and the 2-2nd light emitting element LD22 remain as dark spots that do not emit light.

[0159] FIG. 14A to FIG. 14C is a diagram illustrating steps of a repair process applied when a bright spot appears in the first subpixel SP1 due to a defective transistor (eg, a driving element (DT) of the first subpixel SP1 ).

[0160] During the initial defect identification process, Fig.14A As shown, the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 of the first sub-pixel SP1 can be initially found to be bright spot defects. At this time, the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22 of the second sub-pixel SP2 can be driven normally, but can be identified as bright spots with relatively low brightness. In the initial defect identification process, it may be difficult to know which element is defective, and it can be based on the following examples: Fig. 14B The results of the first stage repair process are shown to identify defective components.

[0161] When Fig.14A When a defect is initially identified as shown, the first stage of repair processing is performed. Fig. 14BAs shown in ① in FIG. 1 , the first cathode line CL1 is cut between the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 of the first sub-pixel SP1, and the cathode electrode of the 1-1 light emitting element LD11 and the cathode electrode of the 1-2 light emitting element LD12 are thus electrically separated. Next, as Fig. 14B As shown in ② in FIG. 2 , the cathode lines CL1 and CL2 may be electrically connected to each other at a welding portion WEL where the first cathode line CL1 extending from the first sub-pixel SP1 overlaps the second cathode line CL2 extending from the second sub-pixel SP2. As a result of the first-stage repair process, if the 1-2nd light emitting element LD12, the 2-1st light emitting element LD21, and the 2-2nd light emitting element LD22 are identified as bright spots, and the 1-1st light emitting element LD11 is identified as a dark spot, in the second-stage repair process, as shown in FIG. Fig. 14C As shown in ④, the second cathode line CL2 is cut between the cathode electrode of the 2-1st light emitting element LD21 and the cathode electrode of the 2-2nd light emitting element LD22. At this time, the cathode electrodes of the 1-2nd light emitting element LD12 and the 2-1st light emitting element LD21 are electrically connected to each other, and these cathode electrodes are electrically separated from the cathode electrodes of the 1-1st light emitting element LD11 and the 2-2nd light emitting element LD22. Therefore, the 1-2nd light emitting element LD12 and the 2-1st light emitting element LD21 can be driven normally and emit light at the same brightness ratio. The 1-1st light emitting element LD11 and the 2-2nd light emitting elements LD11 and LD22 remain as dark spots that do not emit light.

[0162] In the case where the first sub-pixel SP1 and the second sub-pixel SP2 have no defects and are not repaired, the cathode electrodes of the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12 are connected to the first cathode line CL1, and the cathode electrodes of the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22 are connected to the second cathode line CL2. On the other hand, in the case where the first sub-pixel SP1 is repaired due to a defect in a transistor or a light emitting element chip, such as Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C and Fig. 14C As shown, the first cathode line CL1 may be connected to at least one of the cathode electrodes of the 1-1st light emitting element and the 1-2nd light emitting element, and the second cathode line CL2 may be connected to at least one of the cathode electrodes of the 2-1st light emitting element LD21 and the 2-2nd light emitting element LD22. Depending on whether the first sub-pixel is defective, the first cathode line CL1 may be connected to one or more of the cathode electrodes of the 1-1st light emitting element LD11 and the 1-2nd light emitting element LD12, and may be connected to the second cathode line CL2 extending from the second sub-pixel SP2.

[0163] like Fig. 6A , Figure 6B , Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C and Fig. 14C As shown, the second switch element M2 of the first sub-pixel SP1 may be connected to the anode electrode of the 1-1st light emitting element LD11 and the anode electrode of the 1-2nd light emitting element LD12, and may be connected to at least one of the cathode electrode of the 1-1st light emitting element LD11 and the cathode electrode of the 1-2nd light emitting element LD12. The second switch element M2 of the second sub-pixel SP2 may be connected to the anode electrode of the 2-1st light emitting element LD21 and the anode electrode of the 2-2nd light emitting element LD22, and may be connected to at least one of the cathode electrode of the 2-1st light emitting element LD21 and the cathode electrode of the 2-2nd light emitting element LD22.

[0164] like Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C and Fig. 14C As shown, as a result of the repair process, there is no light-emitting element that has become a dark spot in the row between adjacent sub-pixels. At least one of the pixel structures that has completed the repair process (e.g., Fig. 10C , Fig. 11C , Fig. 12C , Fig. 13C and Fig. 14C The pixel structure shown) can be set on the display panel after the product is shipped.

[0165] The repair process can be performed by irradiating a laser beam onto the display panel to selectively remove metal at the desired location (laser cutting) or by connecting different layers of metal (laser welding). Fig.15 and 16 Examples of the laser cutting method and the laser welding method are described below. Fig.15 and 16 , “ML1” and “ML2” may indicate metal patterns of a first cathode line CL1 and a second cathode line CL2 extending from sub-pixels of the same color.

[0166] The first metal pattern ML1 and the second metal pattern ML2 are electrically separated by an insulating layer INS interposed therebetween. When viewed in the thickness direction (Z) of the display panel, the first metal pattern ML1 and the second metal pattern ML2 may overlap in the welding portion WEL with the insulating layer INS interposed therebetween. The insulating layer INS may include an organic insulating layer and / or an inorganic insulating layer.

[0167] Fig.15is a cross-sectional view illustrating an example of a laser cutting method.

[0168] Reference Fig.15 , laser repair equipment in Fig. 10B and Fig. 10C , Fig. 11B and Fig. 11C , Fig. 12B and Fig. 12C , Fig. 13B and Fig. 13C ,as well as Fig. 14B and Fig. 14C The laser beam is irradiated to the display panel at the cutting position shown. At the cutting position, the first metal pattern ML1 and the second metal pattern ML2 do not overlap. Due to the energy of the laser beam, the insulating layer INS and the first metal pattern (ML1) may be melted at the cutting position and become insulated from each other.

[0169] Fig.16 is a cross-sectional view illustrating an example of a laser welding method.

[0170] Reference Fig.16 , laser repair equipment in Fig. 10B and Fig. 10C , Fig. 11B and Fig. 11C , Fig. 12B and Fig. 12C , Fig. 13B and Fig. 13C ,as well as Fig. 14B and Fig. 14C A laser beam is irradiated to the display panel at a welding position as shown. At the welding position, the first metal pattern ML1 and the second metal pattern ML2 overlap and the insulating layer INS is interposed therebetween. Due to the energy of the laser beam, the insulating layer INS and the metal patterns ML1 and ML2 melt at the welding position. At this time, the overlapping metal patterns ML1 and ML2 at the welding position may be connected to each other. On the other hand, the metal patterns ML1 and ML2 may be connected at the welding position by using a laser CVD device that fills a hole penetrating the insulating layer INS with a metal such as tungsten at the welding position.

[0171] According to one or more embodiments of the present disclosure, the display device may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a variable device, an electronic notepad, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigator, a vehicle navigation, a vehicle display device, a vehicle device, a theater device, a theater display device, a television, a wallpaper device, a sign device, a game device, a laptop computer, a display, a camera, a video camera, and a home appliance, etc. Additionally, the display device according to one or more embodiments of the present disclosure may be applied to an organic light emitting lighting device or an inorganic light emitting lighting device.

[0172] The above-mentioned various aspects to be achieved by the present disclosure, means for achieving the various aspects, and effects of the present disclosure are not essential features of the specified claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0173] It will be apparent to those skilled in the art that various modifications and variations may be made to the display device of the present disclosure without departing from the technical concept or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the attached claims and their equivalents.

[0174] CROSS-REFERENCE TO RELATED APPLICATIONS

[0175] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0120515, filed on September 11, 2023, the entire disclosure of which is incorporated herein by reference for all purposes.

Claims

1. A display panel, comprising: A first sub-pixel, the first sub-pixel comprising a 1-1th light-emitting element and a 1-2th light-emitting element; a second sub-pixel, the second sub-pixel comprising a 2-1st light-emitting element and a 2-2nd light-emitting element; a first cathode line connected to at least one of the cathode electrodes of the 1-1th light emitting element and the cathode electrodes of the 1-2th light emitting element and extending toward the second sub-pixel; as well as a second cathode line connected to at least one of the cathode electrodes of the 2-1st light emitting element and the cathode electrodes of the 2-2nd light emitting element and extending toward the first sub-pixel, Wherein, the first cathode lines and the second cathode lines partially overlap each other.

2. The display panel according to claim 1, wherein: The first cathode lines and the second cathode lines are connected to or separated from each other at portions where the first cathode lines and the second cathode lines overlap.

3. The display panel according to claim 1, wherein: At portions where the first cathode lines and the second cathode lines do not overlap, the first cathode lines or the second cathode lines are separated to be insulated from each other.

4. The display panel according to claim 1, wherein: The anode electrode of the 1-1 light emitting element is connected to the anode electrode of the 1-2 light emitting element; and The anode electrode of the 2-1 light emitting element is connected to the anode electrode of the 2-2 light emitting element.

5. The display panel according to claim 1, wherein: The first sub-pixel comprises: a first driving transistor, the first driving transistor providing current to the 1-1th light emitting element and the 1-2th light emitting element; a 1-1th switching transistor, the 1-1th switching transistor switching a current path between a pixel driving voltage and a cathode voltage; and a 1-2 switching transistor, the 1-2 switching transistor being connected to an anode electrode of the 1-1 light emitting element and an anode electrode of the 1-2 light emitting element, and being connected to at least one of a cathode electrode of the 1-1 light emitting element and a cathode electrode of the 1-2 light emitting element, and Wherein, the second sub-pixel includes: a second driving transistor, the second driving transistor providing current to the 2-1st light emitting element and the 2-2nd light emitting element; a 2-1st switching transistor, the 2-1st switching transistor switching a current path between the pixel driving voltage and the cathode voltage; and A 2-2 switching transistor, the 2-2 switching transistor is connected to the anode electrode of the 2-1 light-emitting element and the anode electrode of the 2-2 light-emitting element, and is connected to at least one of the cathode electrode of the 2-1 light-emitting element and the cathode electrode of the 2-2 light-emitting element.

6. The display panel according to claim 5, wherein: The 1-2 switching transistor is connected between the pixel driving voltage line and the first driving transistor, and The 2-2nd switching transistor is connected between the pixel driving voltage line and the second driving transistor.

7. The display panel according to claim 1, wherein: The cathode electrode of the 1-1 light-emitting element and the cathode electrode of the 1-2 light-emitting element are electrically separated; and The first cathodic lines and the second cathodic lines are electrically separated.

8. The display panel according to claim 1, wherein: The cathode electrode of the 1-1 light-emitting element is electrically separated from the cathode electrode of the 1-2 light-emitting element; The first cathode line and the second cathode line are electrically connected; and The cathode electrode of the 1-2 light emitting element and the cathode electrode of the 2-1 light emitting element are electrically connected to each other.

9. The display panel according to claim 8, wherein: The cathode electrode of the 2-1 light emitting element is electrically separated from the cathode electrode of the 2-2 light emitting element.

10. The display panel according to claim 1, wherein: The cathode electrode of the 1-1 light-emitting element is electrically separated from the cathode electrode of the 1-2 light-emitting element; The first cathodic wire and the second cathodic wire are electrically separated; and The cathode electrode of the 2-1 light emitting element and the cathode electrode of the 2-2 light emitting element are electrically connected to each other.

11. The display panel according to claim 1, wherein: The first cathode lines and the second cathode lines are arranged with an insulating layer interposed between the first cathode lines and the second cathode lines.

12. The display panel according to claim 11, wherein: There is a hole penetrating the insulating layer, and the first cathode line and the second cathode line are connected to each other through the hole.

13. The display panel according to claim 1, wherein: The first sub-pixel and the second sub-pixel emit light of the same color and are adjacent to each other.

14. A method for repairing a display panel, the method comprising the following steps: electrically separating the cathode electrode of the 1-1 light-emitting element of the first sub-pixel from the cathode electrode of the 1-2 light-emitting element of the first sub-pixel; as well as electrically connecting a first cathode line extending from the first sub-pixel to a second cathode line extending from the second sub-pixel, The first cathode line is connected to at least one cathode electrode of the cathode electrodes of the 1-1 light emitting element and the 1-2 light emitting element, and extends toward the second sub-pixel, and The second cathode line is connected to at least one cathode electrode of the cathode electrodes of the 2-1st light emitting element and the 2-2nd light emitting element of the second sub-pixel, and extends toward the first sub-pixel.

15. The repair method according to claim 14, wherein: The first cathode line is electrically separated from the 1-1th light emitting element, and the repair method further comprises the following step: electrically separating the cathode electrode of the 1-2th light emitting element from the first cathode line.

16. The repair method according to claim 15, wherein: The cathode electrode of the 2-1 light emitting element is connected to the cathode electrode of the 2-2 light emitting element; and The cathode electrode of the 2-1 light emitting element and the cathode electrode of the 2-2 light emitting element are electrically separated from the cathode electrode of the 1-1 light emitting element and the cathode electrode of the 1-2 light emitting element.

17. The repair method according to claim 16, wherein: The 2-1st light emitting element and the 2-2nd light emitting element are capable of emitting light; and The 1-1st light emitting element and the 2-2nd light emitting element are dark spots that do not emit light.

18. The repair method according to claim 16, wherein: The 1-1st light emitting element, the 2-1st light emitting element and the 2-2nd light emitting element are capable of emitting light; and The first-second light-emitting element is a dark spot that does not emit light.

19. The repair method according to claim 14, further comprising the following steps: The cathode electrode of the 2-1 light-emitting element is electrically separated from the cathode electrode of the 2-2 light-emitting element.

20. The repair method according to claim 19, wherein: The cathode electrode of the 1-2 light emitting element is electrically connected to the cathode electrode of the 2-1 light emitting element; and The cathode electrode of the 1-2 light emitting element and the cathode electrode of the 2-1 light emitting element are electrically separated from the cathode electrode of the 1-1 light emitting element and the cathode electrode of the 2-2 light emitting element.

21. The repair method according to claim 20, wherein: The 1-2 light-emitting element and the 2-1 light-emitting element are capable of emitting light; and The 1-1st light emitting element and the 2-2nd light emitting element are dark spots that do not emit light.

22. The repair method according to any one of claims 14 to 21, wherein: At portions where the first cathode lines and the second cathode lines do not overlap, the first cathode lines or the second cathode lines are separated to be insulated from each other.

23. The repair method according to any one of claims 14 to 21, wherein: The first cathode line and the second cathode line are connected at an overlapping portion where the first cathode line and the second cathode line overlap.

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