Peak voltage amplitude detector allowing process variations and device mismatch and related methods

Abstract

The peak detector includes a plurality of small size amplitude detection circuits coupled in parallel to a signal input at which a signal is received from the VCO. Each amplitude detection circuit generates a voltage on an output indicative of a voltage peak or amplitude of a first signal input and a second signal input, in particular a differential output of the VCO. At a given time, only one small size amplitude detection circuit is activated to load the VCO, thereby reducing the impact on the LC resonant frequency. Multiple small-size detection circuits operate sequentially, and automatic averaging of their outputs can significantly improve peak detector fluctuations (caused by process variations and device mismatch) compared to each single small-size amplitude detection circuit.

Description

Technical Field

[0001] The technology of the present disclosure relates generally to phase locked loops (PLLs), and more particularly to maintaining a stable amplitude of a PLL output signal. Background Art

[0002] Wireless communication is used for voice communication and many other applications in smart phones and other mobile devices. In order to support the growing demand in this field, the fifth generation new radio (5G-NR) technology provides high-speed cellular communication and the Internet of Things over several different frequency bands in a wide range of frequencies. Wired transmission media also support multiple simultaneous transmissions using frequency division methods. In order to avoid interference between signals transmitted simultaneously over the same wired and wireless transmission media, the transmitted signals need to remain at frequencies within their allocated frequency bands.

[0003] In this regard, the transmitter includes a phase-locked loop (PLL) circuit to maintain the frequency of the transmitted signal within a specified frequency range. The PLL provides a control signal to a voltage-controlled oscillator (VCO) to generate a signal with a desired amplitude and frequency. A peak detector is used to monitor the amplitude of the generated signal. The peak detector detects the amplitude of the voltage oscillation of the signal and provides feedback to the PLL to adjust the control signal to the VCO to correct the amplitude when the VCO deviates from the desired amplitude range. As voltage levels are reduced with technological advances to reduce power consumption, the expected range of the peak amplitude of the signal voltage is reduced, and thus the accuracy of the peak detector becomes more important. In addition, the accuracy of the circuit (including the peak detector) often varies across manufacturing process corners, so that the operating characteristics of the device will be mismatched (e.g., inconsistent). Summary of the invention

[0004] Exemplary aspects disclosed herein include a peak voltage amplitude detector that tolerates process variations and device mismatches. A method for detecting peak voltage amplitudes is also disclosed. A peak voltage amplitude detector ("peak detector") in an integrated circuit (IC) is employed in a phase-locked loop (PLL) to monitor the peak amplitude of a signal generated by a voltage-controlled oscillator (VCO). The transistors used in the peak detectors in different devices or ICs will inevitably come from different manufacturing process corners, resulting in differences in operating characteristics, but when a higher alternating current (AC) input amplitude is provided to the input signal of the peak detector, the output variation between these devices (or ICs) is significantly reduced. The AC input amplitude depends on the ratio of the coupling capacitance and the load capacitance of the peak detector circuit. Using smaller transistors with smaller load capacitance can increase the AC input amplitude, but may result in larger variations from one IC to another due to device mismatches. In this regard, in an exemplary aspect, a peak detector is provided that includes a plurality of amplitude detection circuits coupled in parallel to a signal input at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage at an output indicating a voltage difference between a first signal input and a second signal input. For example, the amplitude detection circuits are activated one at a time (e.g., sequentially, cyclically) to capture the peak voltage of the received signal at different times. The amplitude detection circuit includes an averaging circuit for generating an average voltage based on the average of the voltages captured in the multiple amplitude detection circuits. The amplitude detection circuit of the peak detector can use smaller transistors to maintain a higher AC input amplitude, and the averaging circuit that averages the voltages of the multiple amplitude detection circuits reduces performance variations from IC to IC compared to a peak detector including a single amplitude detection circuit.

[0005] In an exemplary aspect, a peak detector is disclosed that includes a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input. Each of the plurality of amplitude detection circuits is configured to generate a peak voltage at an output that indicates an amplitude of an input signal received at the first signal input and the second signal input. The peak detector also includes an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit being configured to generate an average voltage at the peak detector output, the average voltage comprising an average of the peak voltages at the outputs of the plurality of amplitude detection circuits.

[0006] In another exemplary aspect, an IC is disclosed, comprising: a transmitter configured to generate a transmission signal and a PLL including a voltage controlled oscillator (VCO). The VCO is configured to generate an output signal having an amplitude based on a control voltage, and the PLL is configured to control the frequency of the transmission signal. The PLL also includes a peak detector, which includes: a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input. Each of the plurality of amplitude detection circuits is configured to generate a voltage indicating a voltage difference between the first signal input and the second signal input at an output. The peak detection also includes an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit being configured to generate an average voltage at the peak detector output, the average voltage including an average of the voltages generated at the outputs of the plurality of amplitude detection circuits. The PLL also includes a range sensor, the range sensor being configured to determine whether the average voltage at the peak detector output is outside a voltage range, and adjusting the control voltage in response to determining that the average voltage at the peak detector output is outside the voltage range.

[0007] In another exemplary aspect, a method of detecting amplitude in a peak detector is disclosed, the peak detector comprising a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input. Each of the plurality of amplitude detection circuits comprises an output, an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, and a peak detector output. The method comprises: generating a peak voltage at the output of each of the plurality of amplitude detection circuits, the peak voltage indicating the amplitude of an input signal received at the first signal input and the second signal input; and generating an average voltage at the peak detector output, the average voltage comprising an average of the peak voltages at the outputs of the plurality of amplitude detection circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

[0009] Figure 1 is a block diagram of a phase-locked loop (PLL) including a voltage-controlled oscillator (VCO);

[0010] Figure 2 is a schematic diagram of a VCO circuit having a regulated power supply and an exemplary peak detector for determining whether an output signal of the VCO circuit is within a desired range;

[0011] Figure 3 is a schematic diagram of a source follower circuit having a capacitor for capturing the peak voltage of an input signal and a graphical representation of an output signal compared to the input signal;

[0012] Figure 4is a schematic diagram of a source follower circuit including a coupling capacitor circuit for illustrating the ratio required to reduce output variation across process angle for a high amplitude AC input;

[0013] Figure 5 is a schematic diagram of an example of an exemplary peak detector, wherein each amplitude detection circuit includes a capacitive coupling circuit;

[0014] Figure 6 is a schematic diagram and timing diagram of another example of an exemplary peak detector, showing sequential sharing of a capacitive coupling circuit in each amplitude detection circuit;

[0015] Figure 7 yes Figure 6 a schematic diagram of an exemplary peak detector in, the peak detector being coupled to a first example of an averaging circuit for averaging the voltages generated in each amplitude detection circuit;

[0016] Figure 8 It is shown Figure 6 A schematic diagram of another view of an exemplary peak detector in the embodiment of the present invention is coupled to a peak detector used in an amplitude detection circuit Figure 7 Another example of an average circuit with fewer capacitors in the example;

[0017] Figures 9A-9D It is shown Figure 7 A series of schematic diagrams of the operation of the averaging circuit in;

[0018] Fig.10 is a flow chart illustrating a method of detecting a peak amplitude in a peak detector including a plurality of amplitude detection circuits connected in parallel; and

[0019] Fig.11 is a block diagram of an exemplary processor-based system including multiple devices coupled together by a system bus, wherein the processor-based system includes at least one integrated circuit (IC) including a VCO with a peak detector including multiple amplitude detection circuits for accommodating process variations and device mismatches. DETAILED DESCRIPTION

[0020] With reference to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0021] Exemplary aspects disclosed herein include process and mismatch tolerant peak voltage amplitude detectors. Methods for detecting peak voltage amplitudes are also disclosed. A peak voltage amplitude detector ("peak detector") in an integrated circuit (IC) is employed in a phase-locked loop (PLL) to monitor the peak amplitude of a signal generated by a voltage-controlled oscillator (VCO). The transistors used in the peak detectors in different devices or ICs will inevitably come from different manufacturing process corners, resulting in differences in operating characteristics, but when a higher alternating current (AC) input amplitude is provided to the input signal of the peak detector, the output variation between these devices (or ICs) is significantly reduced. The AC input amplitude depends on the ratio of the coupling capacitance and the load capacitance of the peak detector circuit. Using smaller transistors with smaller load capacitance can increase the AC input amplitude, but may result in larger variations from one IC to another due to device mismatch. In this regard, in an exemplary aspect, a peak detector is provided, which includes a plurality of amplitude detection circuits coupled in parallel to a signal input at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage at an output indicating a voltage difference between a first signal input and a second signal input. For example, the amplitude detection circuits are activated one at a time (e.g., sequentially, cyclically) to capture the peak voltage of the received signal at different times. The amplitude detection circuit includes an averaging circuit for generating an average voltage based on the average of the voltages captured in the multiple amplitude detection circuits. The amplitude detection circuit of the peak detector can use smaller transistors to maintain a higher AC input amplitude, and the averaging circuit that averages the voltages of the multiple amplitude detection circuits reduces performance variations from IC to IC compared to a peak detector including a single amplitude detection circuit.

[0022] Before describing an example of an exemplary peak detector according to the present disclosure, reference is made to Figure 5-8 ,refer to Figure 1 An example of a phase locked loop (PLL) 100 is briefly described. Figure 2 An example of a voltage controlled oscillator (VCO) 200 is shown in FIG. Figure 3 and 4 Examples of peak detector circuits are discussed.

[0023] Figure 1 1 is a schematic diagram of a PLL 100 including an exemplary VCO 102 and conventional components. A crystal oscillator 104 provides a signal SCO oscillating at a stable frequency. The signal SCO is provided to a phase detector 106, which converts the frequency F of the signal SCO to SCO The frequency F of the feedback signal SFB SFB Compare and based on the frequency F SCO and F SFB The phase / frequency difference between them generates a voltage signal V PD . Voltage signal VPD is provided to a low pass filter 108 which removes the voltage signal V PD The low pass filter 108 generates a voltage signal V which is provided to the VCO 102. LP , to convert the output signal V OUT Frequency F VCO Controlled at the desired frequency FOUT. Output signal V OUT Can be used to determine the frequency of a wired or wireless signal transmitted by a transmitter (not shown). Output signal V OUT is also fed back to the phase detector 106 to determine the frequency F of the signal SCO SCO is too fast or too slow, and also determines the output signal V OUT Is it out of phase with the signal SCO? Typically, as in PLL 100, the output signal V OUT is the frequency F of the signal SCO SCO multiples (e.g., N times), so the output signal V OUT Before being provided as the feedback signal SFB to the phase detector 106, it is first divided in the frequency divider 110 (eg, divided by N). Figure 1 1, but PLL 100 also includes a circuit for monitoring and adjusting the output signal V according to the desired output power level. OUT The amplitude of the circuit system.

[0024] Figure 2 Yes, it can be Figure 1 1 is a diagram of an exemplary VCO top circuit 200 of the VCO 102 in FIG. 1 and is provided as an example of a circuit in which the exemplary peak detector 202 may be employed. The VCO top circuit 200 includes a VCO core circuit 204 to generate an output signal V OUT , the output signal V OUT Can be Figure 1 The output signal of PLL 100 in VCO core circuit 204 is provided to a transmitter (not shown) for wired or wireless communication. In some examples, VCO core circuit 204 can be an LC tank circuit having an inductor (L) and a capacitor (C), as is known in the art. The output V of VCO core circuit 204 OUT The magnitude of V is affected by the regulated supply voltage VDD_VCO, which is generated by the low dropout output regulator (LDO) circuit 224. Within the range / level allowed by the process, a higher VDD_VCO results in a larger V OUT amplitude, corresponding to lower VCO output noise. Figure 1Other types of VCO circuits may be used in the PLL 100 in the embodiment of the present invention, and such VCO circuits may also employ the peak detector disclosed herein.

[0025] The power device 206 in the LDO regulator circuit 224 isolates the VCO core circuit 204 from noise that may be included in the external power supply VDD. In this example, the power device 206 includes a plurality of power circuit "slices" 208(1)-208(X) coupled in parallel to each other. Figure 2 Each of the slices 208(1)-208(X) in the embodiment includes a capacitor 210 to reduce the control signal S in the control transistor 212. SLC Depending on the power requirement, a sufficient number of slices 208(1)-208(X) are enabled to provide the required power level to the VCO circuit 204 in parallel. The supply voltage VDD_VCO is generated by the slices 208(1)-208(X), which are under the influence of the feedback circuit 214, which receives the feedback signal S generated by the peak detector 202. ADJ The operational amplifier 216 helps generate a gate control signal S for the power device 206 based on the reference voltage VREF and the feedback circuit 214. SLC .

[0026] The VCO core circuit 204 generates an output signal V as a differential signal at outputs VCO+ and VCO-. OUT Including Figure 1 In the example of the transmitter of the PLL 100, the output signal V OUT The maximum sustainable amplitude (i.e., voltage) is provided to the peak detector 202 without causing damage to the circuits therein. The maximum sustainable amplitude is determined to be a point in the high end of the voltage range of the transistor but low enough to avoid long-term device damage, which would reduce the device life expectancy. Therefore, it is preferred to be as close to the maximum sustainable amplitude as possible to maximize power and efficiency.

[0027] In this regard, the VCO top circuit 200 includes a peak detector 202 to convert the output signal V OUT The amplitude of is kept within a small range close to the maximum sustainable amplitude. The peak detector 202 stores (eg, captures) and generates an output signal indicating that OUT The maximum detection amplitude peak voltage V PK The range detector 218 determines the peak voltage V PK If the value is outside the expected range, a feedback signal S is generated to the feedback circuit 214. ADJ In response, the feedback circuit 214 causes the VCO core circuit 204 to adjust the output signal V accordingly. OUTThe range detector 218 includes comparators 220H and 220L to convert the peak voltage V PK Respectively with the high reference voltage V REFH and low reference voltage V REFL For comparison, the high reference voltage V REFH and low reference voltage V REFL is the output signal V OUT The comparators 220H and 220L can give +1 (220L gives "1", 220H gives "0"), 0 (220L and 220H both give "0"), or -1 (220L gives "0", 220H gives "1"), which respectively indicate V OUT The amplitude is above the desired range, within the desired range, or below the desired range. The accumulator circuit 222 helps accumulate the comparator results after scaling to generate a feedback signal S indicating the desired adjustment direction (ie, increase or decrease the peak amplitude). ADJ .

[0028] However, peak detectors also include circuitry that may be affected by process corners, which may result in significant performance mismatches between different peak detectors.In the exemplary aspects disclosed below, peak detector 202 is tolerant to manufacturing process variations and device mismatches.

[0029] First, refer to Figure 3 and 4 Examples of circuits that may be used in peak detector 202 are described. Figure 3 It is used to capture the input signal V IN Schematic diagram of a peak detector 300 for detecting the peak value of each oscillation of a signal. In the context of this specification, the term "peak value" refers to a measure of the maximum voltage or amplitude of a signal oscillation. The term "peak value" may be used interchangeably with "peak voltage", "amplitude", "maximum voltage" and other related terms.

[0030] The peak detector 300 includes a transistor 302 having a drain terminal DRN, a gate terminal GT, and a source terminal SRC. The transistor 302 may be a field effect transistor (FET), such as a metal oxide semiconductor (MOS) FET (MOSFET). Figure 3 In FIG. 3 , transistor 302 is an N-type MOSFET (NFET), but may also be a P-type FET. The drain terminal DRN receives the power supply voltage VDD. The source terminal SRC is coupled to an output node 304, at which a peak signal V PK The source terminal SRC is also coupled to a current source 306 and a capacitor 308. The current source 306 and the capacitor 308 are also coupled to a reference voltage VSS (eg, ground). An alternating current (AC) signal or an oscillating signal is used as an input signal V INis supplied to the gate terminal GT.

[0031] In this configuration, the peak detector 300 may be referred to as a source follower circuit, where the voltage at the source terminal SRC of the transistor 302 follows the input signal V IN Subtract the gate-to-source voltage V of transistor 302 GS When the input signal V IN As the voltage increases, the source terminal SRC follows the gate-to-source voltage V GS Since the source terminal SRC is coupled to the capacitor 308, the capacitor 308 is charged to the highest voltage level (i.e., the peak value) reached by the source terminal SRC. Therefore, the output node 304 also rises to the input signal V IN Subtract the gate-to-source voltage V GS The peak voltage V PK . Input signal V IN , source terminal SRC and peak signal V PK The relationship between Figure 3 As shown in the figure, the source terminal SRC corresponds to the input signal V IN , but is larger than the input signal V IN The difference is equal to the gate-source voltage V between the gate terminal GT and the source terminal SRC. GS The voltage V at the source terminal SRC SRC than the input signal V on the gate terminal IN Small gate to source voltage V GS As shown here, the peak signal V PK With the input signal V IN The peak signal V PK The slow decrease in is caused by current source 306 draining charge from capacitor 308. Without current source 306, capacitor 308 would remain charged to the maximum applied voltage. IN The amplitude of the subsequent oscillation decreases, and the peak signal V PK The voltage to which capacitor 308 is charged will continue to be shown and will not correspond to the lower peak voltage in subsequent oscillations.

[0032] Although the operating characteristics of transistor 302 may vary from chip to chip due to the manufacturing process corners, it has been found that even devices from different process corners exhibit similar output characteristics in response to sufficiently large AC input amplitudes. The AC input amplitude at the gate terminal GT of transistor 302 is controlled by the coupling capacitor C AC The capacitance of transistor 302 and the load capacitance C G The ratio is determined.

[0033] Figure 4 is a schematic diagram of the peak detector 400, including the addition of the coupling capacitor C AC and resistor 404 Figure 3 The peak detector 300 in FIG. 302 has a load capacitance C G For example, based on the capacitance between the gate terminal GT and the drain terminal DRN, the source terminal SRC and the body (not shown) of the transistor 302 .

[0034] As described above, the AC input amplitude is based on the coupling capacitor C AC With coupling capacitor C AC Add the load capacitance C G The ratio of the sum of AC / (C AC +C G )). Therefore, in order to obtain a higher AC input amplitude, a smaller size and a smaller load capacitance C are preferred. G However, as the size of devices (e.g., transistors) decreases, small manufacturing variations can cause relatively large performance variations between them, resulting in performance mismatches between different peak detectors. This type of mismatch can result in operational differences from one device (e.g., VCO, PLL, or transmitter) to another.

[0035] to this end, Figure 5 Peak detector 500 shown in Figure A includes multiple amplitude detection circuits 502(1)-502(N). Amplitude detection circuits 502(1)-502(N) may be referred to herein as a group of "amplitude detection circuits 502". In addition, unless a specific one of the ranges (1)-(N) is discussed, any individual one of the amplitude detection circuits 502 may be generally referred to as "amplitude detection circuit 502". Such a naming convention is also used herein for other features having the following number ranges.

[0036] The amplitude detection circuits 502 vary in performance such that there is a distribution (e.g., a random distribution) of performance characteristics among the multiple amplitude detection circuits 502. In an IC where the voltages of the multiple amplitude detection circuits are averaged together, the results have much less variation from the results of another IC of this type than would occur when comparing the results of peak detectors in two ICs that each include a single amplitude detection circuit. This improvement can be measured as a standard deviation of the average of the multiple amplitude detection devices that is much lower than the standard deviation of a single amplitude detection circuit. Figure 5 In the example of A, there are N amplitude detection circuits. The number N can be any number, such as in the range of 2 to 100 or more. The operation of the amplitude detection circuit 502 will be further explained in the circuit description below.

[0037] Further references Figure 5 A, amplitude detection circuits 502 are coupled in parallel to signal inputs 506N and 506P. Each amplitude detection circuit 502 includes a first sensing circuit 508N coupled to signal input 506N and a second sensing circuit 508P coupled to signal input 506P. In this example, the first and second sensing circuits 508N and 508P are transistors coupled between a power supply voltage source 510 (e.g., a power rail) that provides a power supply voltage VDD and an output 512. The output 512 is also coupled to a capacitor 514 and a current source 516. The outputs 512 of the amplitude detection circuits 502 (1)-502 (N) are also referred to as outputs 512 (1)-512 (N). Within each amplitude detection circuit 502, the capacitor 514 and the current source 516 are also coupled to a reference voltage source 518 that provides a reference voltage VSS (e.g., ground). In this example, the signal inputs 506N and 506P are coupled to outputs 520N and 520P of a VCO 522. Outputs 520N and 520P provide the output V from VCO 522. OUT As the voltage difference between the voltage signals VCO- and VCO+. Therefore, the signal inputs 506N and 506P receive the output V OUT As the input signal V IN .

[0038] Amplitude detection circuits 502(1)-502(N) detect the input signals V received at signal inputs 506N and 506P based on the input signals V IN The magnitude of generates a voltage V at outputs 512(1)-512(N) PK (1) -V PK (N) (not shown). Figure 7 and 8 As explained, the individual amplitude detection circuits 502 in the amplitude detection circuits 502(1)-502(N) are activated one at a time under the control of the control circuit 528. That is, all of the amplitude detection circuits 502 except one of the amplitude detection circuits 502 may be inactive, while the one activated amplitude detection circuit 502 captures the peak voltage V at its output 512. PK The amplitude detection circuits 502 may be activated (one at a time) sequentially (or in another order) until each has stored or captured the peak voltage V PK Alternatively, the average voltage may be based on a voltage that is less than the peak voltage V of all amplitude detection circuits 502(1)-502(N). PK .

[0039] To individually activate the amplitude detection circuits 502, each circuit includes a first input switch 530N coupled to the first signal input 506N and a second input switch 530P coupled to the second signal input 506P. The first and second input switches 530N, 530P are controlled by the control circuit 528 to close when the amplitude detection circuit 502 is active and to open when it is inactive. The control circuit 528 sequentially closes the first input switch 530N and the second input switch 530P in each of the plurality of amplitude detection circuits 502, one amplitude detection circuit 502 at a time. The control circuit 528 may include hardware logic circuits and storage elements for sequentially controlling the plurality of amplitude detection circuits 502.

[0040] For example, the first and second input switches 530N, 530P of the amplitude detection circuit 502(1) may be closed to detect the input signal V IN When the first and second input switches 530N, 530P of the amplitude detection circuit 502(1) are turned off, the peak voltage V PK is stored on capacitor 514 and can be detected at output 512. Next, first and second input switches 530N, 530P of amplitude detection circuit 502(2) can be closed to activate amplitude detection circuit 502(2), and so on, until amplitude detection circuit 502(N). Alternatively, amplitude detection circuits 502 can be activated in any order, and / or less than all of amplitude detection circuits 502 can be activated in sequence.

[0041] The amplitude detection circuit 502 includes a first resistor-capacitor (RC) circuit 532N coupled to the first signal input 506N when the first input switch 530N is closed, and a second RC circuit 532P coupled to the second signal input 506P when the second input switch 530P is closed. The first and second RC circuits 532N, 532P provide a coupling capacitance C AC , the coupling capacitor C AC The combined load capacitance C of the first and second sensing circuits 508N and 508P G The AC input amplitude to 508N and 508P is determined. The variation between peak detectors 500 in different devices (eg, VCO, PLL, transmitter) can be reduced by keeping the AC input amplitude to sensing circuits 508N and 508P at a high level.

[0042] Further with respect to the amplitude detection circuit 502, the first sensing circuit 508N includes a first transistor 534N, such as a field effect transistor (FET), which may be a metal oxide semiconductor (MOS) FET (MOSFET). The first transistor 534N includes a gate G1 coupled to the first signal input 506N, a first source / drain D1 coupled to the supply voltage source 510, and a second source / drain S1 coupled to the output 512. The second sensing circuit 508P includes a second transistor 534P, the second transistor 534P including a gate G2 coupled to the second signal input 506P, a first source / drain D2 coupled to the supply voltage source 510, and a second source / drain S2 coupled to the output 512. As described above, the capacitor 514 is coupled to the output 512 and the reference voltage source 518, and the current source 516 is coupled to the output 512 and the reference voltage source 518. Configured in this manner, the amplitude detection circuit 502 can be identified as a source follower circuit, where the voltage V provided to the capacitor 514 and the output 512 is PK The voltage of the input signal VCO- and VCO+ minus the voltage drop between the gate G1 and the second source / drain S1 or between the gate G2 and the second source / drain S2 (for example, the gate-to-source voltage V GS )same.

[0043] Note that the term "coupled" as used herein refers to an electrical coupling, which may include an indirect or direct conductive coupling, which may be a conductive connection, and may include a mechanical connection.

[0044] Figure 6 6 is a schematic diagram of another example of a peak detector 600 that is tolerant to process variations and mismatches, including a plurality (eg, multiple) of amplitude detection circuits 602(1)-602(N) to reduce the standard deviation of the peak detector 600. The operation of the peak detector 600 is similar to Figure 5 The peak detector 600 is the same as the peak detector 500 in FIG. 1 and will not be described again here. The structure of the peak detector 600 is different from that of the peak detector 500 only in the following aspects.

[0045] Instead of including two RC coupling circuits in each of the amplitude detection circuits 602, Figure 5The situation in the amplitude detection circuit 502 in FIG. 5 is that the peak detector 600 includes only the first RC coupling circuit 604N and the second RC coupling circuit 604P, which can be used with each of the amplitude detection circuits 602(1)-602(N) because they are activated one at a time. The RC coupling circuit 604N is coupled to the first signal input 606N and the first input switch 608N in each amplitude detection circuit 602. The RC coupling circuit 604P is coupled to the second signal input 606P and the second input switch 608P in each amplitude detection circuit 602. The first signal input 606N and the second signal input 606P are coupled to the signal generating circuit 620, which can be a VCO of a PLL. When the first and second input switches 608N, 608P are closed to activate one of the amplitude detection circuits 602 (e.g., sequentially), the first and second RC coupling circuits 604N and 604P are used. In this manner, the total number of RC coupling circuits in the peak detector 600 is reduced from 2×N to two (2) by using RC coupling circuits 604N and 604P one at a time with each amplitude detection circuit 602. Each amplitude detection circuit includes a first sensing circuit 610N, a second sensing circuit 610P, a current source 612, and a capacitor 614.

[0046] Figure 6 Also included is a timing diagram 622 that illustrates states of control signals SEL1, SEL2, SEL3, and SELN generated by a control circuit (such as control circuit 528) to, for example, control input switches 608N, 608P to sequentially activate amplitude detection circuits 602(1), 602(2), 602(3), and 602(N) (amplitude detection circuits 602(2) and 602(3) are not shown). After activating amplitude detection circuits 602(1)-602(N), the following reference is made to the timing diagram 622. Figure 7 and 8 After the described averaging process, the process begins again at amplitude detection circuit 602(1). Figure 7 and 8 Both include a peak detector corresponding to peak detector 600, but include different examples of averaging circuits that can be used to generate an average voltage that is the peak voltage V captured by amplitude detection circuit 602. PK Average.

[0047] Figure 7is a schematic diagram of a peak detector 700 that can be coupled to a VCO (not shown) at signal inputs 701N and 701P. As described above, peak detector 700 includes all of the features of peak detector 600 and also includes a plurality of amplitude detection circuits 702. Peak detector 700 also includes an averaging circuit 704 that can be used to generate an average voltage V by averaging the outputs 706 of the amplitude detection circuits 702. AVG . Because the average voltage V AVG is generated by the multiple amplitude detection circuits 702 of the peak detector 700, so it has a higher peak voltage V than that generated by the peak detector having only one amplitude detection circuit. PK Lower standard deviation.

[0048] Amplitude detection circuits 702(1)-702(N) have corresponding outputs 706(1)-706(N) at which amplitude detection circuits 706(1)-706(N) are based on input signals V received at signal inputs 701N, 701P. IN The maximum voltage generated peak voltage V PK Averaging circuit 704 includes capacitors 708(1)-708(N), each of which is coupled to output 706 of one of amplitude detection circuits 702(1)-702(N) via output switches 710(1)-710(N). Specifically, capacitor 708(1) is coupled to output 706(1) via output switch 710(1), capacitor 708(2) is coupled to output 706(2) via output switch 710(2), and so on, including capacitor 708(N) being coupled to output 706(N) via output switch 710(N). Thus, when amplitude detection circuit 702(1) is activated by closing its input switches 712N and 712P and output switch 710(1) by SEL1, capacitor 708(1) is charged to a level equal to the level of input signal V IN The peak voltage detected on V PK Subtract the gate-to-source voltage V GS (V PK =V IN -V GS ).

[0049] Averaging circuit 704 also includes averaging switches 714(1)-714(N-1), each switch 714 coupled to output 706 of two of amplitude detection circuits 702(1)-702(N). For example, averaging switch 714(1) is coupled between output 706(1) and output 706(2), averaging switch 714(2) is coupled between output 706(2) and output 706(3), and so on, including averaging switch 714(N-1) coupled between output 706(N-1) and output 706(N). Thus, averaging switches 714(1)-714(N-1) are coupled in series to couple each of outputs 706(1)-706(N) of amplitude detection circuits 702(1)-702(N) to peak detector output 716. Figure 7 In the example of FIG. 7 , peak detector output 716 is coupled to output 706 (N), but may be coupled to any one of outputs 706 ( 1 )-706 (N).

[0050] During the charging phase, as shown in timing diagram 720, each amplitude detection circuit 702 is activated one at a time as switch selection signals SEL1-SELN are sequentially activated to charge their corresponding capacitors 708(1)-708(N). For example, switch selection signal SEL1 is activated to close input switches 712N, 712P and output switch 710(1) of amplitude detection circuit 702(1). IN After a predetermined time of one or more cycles, the switch selection signal SEL1 is deactivated to open the input switches 712N, 712P, and the output switch 710(1) of the amplitude detection circuit 702(1) and the switch signal SEL2 are activated to close the input switches 712N, 712P and the output switch 710(2) of the amplitude detection circuit 702(2).

[0051] During the charging phase, averaging switches 714(1)-714(N-1) remain open to electrically isolate capacitors 708(1)-708(N) from one another. After the charging phase, when all capacitors 708(1)-708(N) have been charged, output switches 710(1)-710(N) remain open while averaging switches 714(1)-714(N-1) are closed. A pulse signal AVG is generated (e.g., by a control circuit not shown here) to briefly close averaging switches 714(1)-714(N-1) to couple capacitors 708(1)-708(N) to one another and to peak detector output 716. Closing all averaging switches 714(1)-714(N-1) couples all capacitors 708(1)-708(N) in parallel, redistributing their charge and generating an average voltage V AVG , the average voltage VAVG is the peak voltage of all storage V PK The average voltage V can be detected at the peak detector output 716 AVG .

[0052] Assuming that each amplitude detection circuit 702 has some error due to process variations, the respective errors may be random. Therefore, the effect of each individual error is reduced because the respective errors cancel each other out when they are averaged together. PK In comparison, V AVG The theoretical RMS error of may be improved by √N (due to random and uncorrelated variations). After the averaging pulse AVG, the input switches 712N and 712P of one of the amplitude detection circuits 702 are closed to start a new charging cycle.

[0053] Figure 8 is a schematic diagram of a peak detector 800, including Figure 6 The peak detector 600 in the embodiment of the present invention is coupled to the peak detector 800 using Figure 7 800. Peak detector 800 includes amplitude detection circuits 802(1)-802(N), where N is an even number. Amplitude detection circuits 802(1)-802(N) include odd amplitude detection circuits 802(1), 802(3), 802(5) ... (N-1) ("odd amplitude detection circuits 802O") and even amplitude detection circuits 802(2), 802(4), 802(6) ... 802(N) ("even amplitude detection circuits 802E").

[0054] Peak detector 800 includes averaging circuit 804 coupled to outputs 806(1)-806(N) of amplitude detection circuits 802(1)-802(N). Figure 7 Similar to the averaging circuit 704 in FIG. 8 , the averaging circuit 804 is also used to average the charge captured by each amplitude detection circuit 802 (1)-802 (N). However, instead of having N capacitors, the averaging circuit 804 only includes N / 2+1 capacitors, which are odd capacitors 808O (1)-808O (N / 2) and even capacitors 808E, as described below. Each of the odd capacitors 808O (1)-808O (N / 2) is coupled to the output 806 of one of the odd amplitude detection circuits 802O. The even capacitor 808E can be coupled to the output 806 of any of the even amplitude detection circuits 802E.

[0055] For clarity, the output 806 of each odd amplitude detection circuit 802O is coupled to a corresponding one of the odd capacitors 808O(1)-808O(N / 2). The output 806 of all even amplitude detection circuits 802E may be coupled to the even capacitor 808E. Thus, the averaging circuit 804 includes Figure 7 The number of capacitors used in the averaging circuit 704 is approximately half (ie, N / 2-1 less).

[0056] Averaging circuit 804 further includes averaging switches 810(1)-810(N / 2), each averaging switch being coupled to an output 806 of one of odd amplitude detection circuits 802O and a corresponding one of even amplitude detection circuits 802E. For example, averaging switch 810(1) is coupled to output 806(1) of amplitude detection circuit 802(1) and output 806(2) of amplitude detection circuit 802(2), averaging switch 810(2) is coupled to outputs 806(3)-806(4) of amplitude detection circuits 802(3) and 802(4), and averaging switch 810(N / 2) is coupled to outputs 806(N-1)-806(N) of amplitude detection circuits 802(N-1) and 802(N).

[0057] To couple the amplitude detection circuit 802 to the signal inputs 812N, 812P to receive the input signal V IN , each amplitude detection circuit 802 includes an input switch 814N, 814P, which corresponds to Figure 7 802. Averaging circuit 804 includes output switches 816(1)-816(N) for selective coupling to output 806 of amplitude detection circuit 802. During the charging phase of peak detector 800, input switches 814N, 814P and output switch 816 operate in the same manner as input switches 712N, 712P and output switch 710 during the charging phase of peak detector 700 described previously. In addition, averaging circuit 804 is also controlled during the charging phase, as in the following example.

[0058] Referring to timing diagram 820, starting with amplitude detection circuits 802(1)-802(2), voltage averaging is performed in the odd and even amplitude detection circuits 808O, 808E. Control circuit 818 activates switch signal SEL1 to close input switches 814N, 814P and output switch 816(1) to charge capacitor 808(1) to voltage V PK (As described above.) During this time, the averaging switch 810(1) is open. All other input switches 814N, 814P and output switches 816(2)-816(N) of the amplitude detection circuits 802 are also open.

[0059] Next, the control circuit 818 deactivates the switch signal SEL1 to open the input switches 814N, 814P and the output switch 816(1), and activates the switch signal SEL2 to close the input switches 814N, 814P and the output switch 816(2) of the amplitude detection circuit 802(2). Since the amplitude detection circuit 802(2) is one of the even-numbered amplitude detection circuits, the output switch 816(2) couples the output 806 to the capacitor 808E, which is charged to the input signal V detected at the signal inputs 812N, 812P. IN The peak voltage V PK The possible input signals include V IN After a predetermined time of several cycles of the amplitude detection circuit 802 ( 2 ), the control circuit 818 deactivates the switch signal SEL2 to disconnect the input switches 814N, 814P and the output switch 816 ( 2 ) of the amplitude detection circuit 802 ( 2 ).

[0060] Control circuit 818 then activates switch signal SEL3, which closes averaging switch 810(1), coupling odd capacitor 808O(1) to even capacitor 808E. In this manner, charge is distributed between odd capacitor 808O(1) and even capacitor 808E, and the corresponding peak voltage V detected by amplitude detection circuits 802(1)-802(2) is PK The average voltage V1 is stored in the odd capacitor 808O(1). Next, the switch signal SEL3 is deactivated to turn off the averaging switch 810(1).

[0061] The process moves to the next pair of odd and even amplitude detection circuits 802(3) and 802(4). As described above, the input switches 814N, 814P and output switch 816 in amplitude detection circuit 802(3) are closed to store the peak voltage V on odd capacitor 808O(2). PK Amplitude detection circuit 802(4) stores peak voltage V on even capacitor 808E. PK , and then open. Then, the averaging switch 810 (2) is closed to store the corresponding peak voltages V of the odd capacitor 808O (2) and the even capacitor 808E. PK The average voltage V2.

[0062] This process is performed for the odd and even amplitude detection circuits 802 until the selection signals SELN-1 and SELN are activated to control the amplitude detection circuits 802(N-1) and 802(N) to store the peak voltage V PK In response to the odd capacitor 808O(N / 2) storing the average voltage V N / 2 . Average voltage V N / 2is the peak voltage V stored on the odd capacitor 808O(N / 2) by the amplitude detection circuit 802(N-1) PK and the peak voltage V stored on the even capacitor 808E by the amplitude detection circuit 802(N) PK Average.

[0063] √N When the control circuit 818 activates the switch signal AVG, all peak voltages V detected by all amplitude detection circuits 802 PK The average voltage V AVG is coupled to the peak detector output 822. The switching signal AVG couples all odd capacitors 808O(1)-808O(N / 2) to the even capacitor 808E, thereby generating an average voltage V AVG The peak detector 800 at V AVG , has the same RMS error improvement as peak detector 700 (ie, an improvement factor of √N), but it uses only approximately half the number of sampling capacitors (ie, N / 2-1).

[0064] It will be appreciated that peak detectors comprising an odd number of amplitude detection circuits may be used with obvious modifications of the above described circuits.

[0065] refer to Figures 9A-9D The operation of the averaging circuit 804 can be more clearly understood. Fig.9A , amplitude detection circuit 802(1) is coupled to odd capacitor 808O(1) by closing output switch 816(1) when averaging switch 810(1) is open. During this state, the peak voltage V detected by amplitude detection circuit 802(1) is PK is stored on odd capacitor 808O(1). Fig. 9B In the embodiment, by opening the output switch 816(1), the amplitude detection circuit 802(1) is decoupled from the odd capacitor 808O(1), and by closing the output switch 816(2), the amplitude detection circuit 802(2) is coupled to the even capacitor 808E to store the peak voltage V on the even capacitor 808E. PK The averaging switch 810 ( 1 ) remains open.

[0066] exist Fig. 9C , amplitude detection circuit 802(2) is decoupled from even capacitor 808E by opening output switch 816(2), and averaging switch 810(1) is closed to store average voltage V1 on odd capacitor 808O(1).

[0067] In this manner, for each of the odd amplitude detection circuits 802O(1)-802O(N / 2), the control circuit 818 closes the averaging switch 810 coupled to the odd capacitor 808O.

[0068] like Fig.9D As shown, the remaining odd capacitors 808O(2)-808O(N / 2) are similarly operated to store the average voltage V2-V N / 2 Thereafter, the output switches 816(1)-816(N) of all amplitude detection circuits 802 remain open, while all average switches 810(1)-810(N / 2) are closed to provide an average voltage V of all amplitude detection circuits 802 at the peak detector output 822. AVG .

[0069] Fig.10 It shows that the Figure 7 and 8 Flow chart of a method 1000 for detecting a peak voltage of an input signal by using peak detectors 700 and 800 in the present invention. The method includes: in the peak detectors 700 and 800, the peak detectors 700 and 800 include a plurality of amplitude detection circuits 702 and 802 coupled in parallel to a first signal input 701N and 812N and a second signal input 701P and 812P, each of the plurality of amplitude detection circuits 702 and 802 includes an output 706 and 806, an averaging circuit 704 and 804, and a peak detector output 716 and 822, the averaging circuit 704 and 804 is coupled to the output 706 and 806 of each of the plurality of amplitude detection circuits 702 and 802, and the peak detector output 716 and 822 generates a peak voltage V at the output 706 and 806 of each of the plurality of amplitude detection circuits 702 and 802 PK , peak voltage V PK Indicates the input signal V received on the first signal input 701N, 812N and the second signal input 701P, 812P IN A peak voltage V is generated at the output 706, 806 of each of the amplitude detection circuits 702, 802. PK The method may include sequentially coupling each of the plurality of amplitude detection circuits 702, 802 one at a time to the first signal input 701N, 812N and the second signal input 701P, 812P (block 1004). The method includes generating an average voltage V at the peak detector output 716, 822. AVG , the average voltage V AVG The peak voltage V at the outputs 706, 806 of the plurality of amplitude detection circuits 702, 802 is included. PK The method may further include coupling the outputs 706, 806 of the plurality of amplitude detection circuits 702, 802 to a peak detector output (block 1008).

[0070] Fig.111 is a block diagram of an exemplary processor-based system 1100 including a processor 1102 (e.g., a microprocessor), the processor 1102 including an instruction processing circuit 1104. The processor-based system 1100 may be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing board, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 1100 includes a processor 1102. The processor 1102 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc. More specifically, the processor 1102 may be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming, which is used to transmit the generated value generated by the execution of the producer instruction. The processor 1102 is configured to execute the processing logic in the instruction for performing the operations and steps discussed herein. In this example, the processor 1102 includes an instruction cache 1106 for temporary fast access memory storage of instructions accessible by the instruction processing circuit 1104. Instructions fetched or pre-fetched from a memory (such as main memory 1108) via the system bus 1110 are stored in the instruction cache 1106. Data may be stored in a cache memory 1112 coupled to the system bus 1110 for low latency access by the processor 1102. The instruction processing circuit 1104 is configured to process instructions fetched into the instruction cache 1106 and process the instructions for execution.

[0071] The processor 1102 and the main memory 1108 are coupled to the system bus 1110 and may be coupled to peripheral devices included in the processor-based system 1100. As is well known, the processor 1102 communicates with these other devices by exchanging address, control, and data information on the system bus 1110. For example, the processor 1102 may transmit bus transaction requests to the memory controller 1114 in the main memory 1108 as an example of a slave device. Although not shown in FIG. Fig.11 1 , but multiple system buses 1110 may be provided; wherein each system bus 1110 constitutes a different structure. In this example, a memory controller 1114 is configured to provide memory access requests to a memory array 1116 in the main memory 1108. The memory array 1116 includes an array of storage bit cells for storing data. As non-limiting examples, the main memory 1108 may be a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) such as a synchronous DRAM (SDRAM), and / or a static memory (e.g., a flash memory, an SRAM, etc.).

[0072] Other devices may be connected to the system bus 1110. Fig.11 As shown, as examples, these devices may include a main memory 1108, one or more input devices 1118, one or more output devices 1120, a modem 1122, and one or more display controllers 1124. Input devices 1118 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1120 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 1122 may be any device configured to allow data to be exchanged with network 1126. Network 1126 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH networks, and the like. TM The modem 1122 may be configured to support any type of desired communication protocol. The processor 1102 may also be configured to access a display controller 1124 via the system bus 1110 to control information sent to one or more displays 1128. The display 1128 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0073] Fig.11 The processor-based system 1100 in the embodiment of the present invention may include a set of instructions 1130 to be executed by the processor 1102 for any application required according to the instructions. The instructions 1130 may be stored in the main memory 1108, the processor 1102, and / or the instruction cache 1106 as an example of a non-transitory computer-readable medium 1132. The instructions 1130 may also reside completely or at least partially within the main memory 1108 and / or within the processor 1102 during its execution. The instructions 1130 may also be sent or received over the network 1126 via the modem 1122 so that the network 1126 includes the computer-readable medium 1132.

[0074] like Figure 7 and 8 As shown, any circuit in the processor-based system 1100, particularly the modem 1122 and the output device 1120, may include a peak detector 700, 800 including multiple amplitude detection circuits coupled in parallel to generate an average voltage with a lower standard deviation. Any circuit in the processor-based system 1100, such as the modem 1122, may include a phase-locked loop (PLL) including a voltage-controlled oscillator having the peak detectors 700, 800.

[0075] Although the computer-readable medium 1132 is shown as a single medium in the exemplary embodiment, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and cause the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0076] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein can be formed by hardware components, or can be implemented with machine executable instructions, which can be used to make a general or special processor programmed with instructions to perform the steps. Alternatively, these steps can be performed by a combination of hardware and software.

[0077] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., a ROM, a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory device, etc.); etc.

[0078] Unless otherwise specifically noted, and as is apparent from the foregoing discussion, it should be understood that throughout this specification, discussions utilizing terms such as "processing," "computing," "determining," "displaying," and the like refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the computer system's registers and memory and transforms it into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage, transmission, or display devices.

[0079] The algorithms and displays provided herein do not inherently relate to any particular computer or other device. According to the teachings herein, various systems can be used together with the program, or it may prove convenient to construct a more specialized device to perform the required method steps. The structures required for various of these systems will emerge from the above description. In addition, the embodiments described herein are not described with reference to any particular programming language. It should be understood that various programming languages ​​may be used to implement the teachings of the embodiments described herein.

[0080] It will be further appreciated by those skilled in the art that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The components of the system described herein may be used in, for example, any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of required information. In order to clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps are generally described above in terms of their functions. How to implement this functionality depends on the specific application, design choice, and / or design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be interpreted as resulting in a departure from the scope of the embodiments of the present invention.

[0081] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the controller may be a processor. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0082] The embodiments disclosed herein may be implemented in hardware and in instructions stored in hardware and may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integrated with the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0083] It should also be noted that the operational steps described in any exemplary embodiment of this article are described as providing examples and discussions. The described operations can be performed in many different orders different from the illustrated order. In addition, the operations described in a single operational step can actually be performed in a plurality of different steps. In addition, one or more operational steps discussed in the exemplary embodiment can be combined. It will also be understood by those skilled in the art that any of a variety of techniques and methods can be used to represent information and signals. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that can be cited throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields, light fields, or particles, or any combination thereof.

[0084] Unless otherwise expressly stated, it is not intended that any method described herein be construed as requiring that its steps be performed in a specific order. Therefore, in the event that a method claim does not actually recite the order in which its steps are to be followed, or in the absence of other specific statements in the claims or description that the steps are limited to a specific order, no specific order is intended to be inferred.

[0085] It is obvious to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments that combine the spirit and essence of the present invention can be imagined by those skilled in the art, the present invention should be interpreted as including all contents within the scope of the attached claims and their equivalents.

Claims

1. A peak detector, comprising: a plurality of amplitude detection circuits coupled in parallel to the first signal input and the second signal input, each amplitude detection circuit of the plurality of amplitude detection circuits being configured to generate a peak voltage at an output, the peak voltage being indicative of an amplitude of an input signal received at the first signal input and the second signal input; as well as An averaging circuit is coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit being configured to generate an average voltage at a peak detector output, the average voltage comprising an average of the peak voltages at the outputs of the plurality of amplitude detection circuits.

2. The peak detector of claim 1 , each of the plurality of amplitude detection circuits comprising: a first sensing circuit configured to generate the peak voltage at the output based on the input signal received at the first input signal; as well as A second sensing circuit is configured to generate the peak voltage at the output based on the input signal received at the second input signal.

3. The peak detector according to claim 2, wherein The first sensing circuit includes a first transistor, and the first transistor includes: a gate coupled to the first signal input; a first source / drain coupled to a supply voltage source; as well as a second source / drain coupled to the output; The second sensing circuit includes a second transistor, and the second transistor includes: a gate coupled to the second signal input; a first source / drain coupled to the supply voltage source; and a second source / drain coupled to the output; and Each of the plurality of amplitude detection circuits further comprises: a capacitor coupled to the output and a reference voltage source; and A current source is coupled to the output and the reference voltage source.

4. The peak detector of claim 1 , wherein each of the plurality of amplitude detection circuits further comprises: a first input switch coupled to the first signal input; a second input switch coupled to the second signal input; as well as An output switch is coupled to the output.

5. The peak detector of claim 4, further comprising a control circuit configured to close both the first input switch and the second input switch in each of the plurality of amplitude detection circuits one amplitude detection circuit at a time.

6. The peak detector of claim 4, wherein each of the plurality of amplitude detection circuits further comprises: a first resistor capacitor (RC) circuit coupled to the first signal input through the first input switch; as well as A second RC circuit is coupled to the second signal input through the second input switch.

7. The peak detector of claim 6, wherein the averaging circuit comprises: a plurality of capacitors, each capacitor coupled to an output of a corresponding one of the plurality of amplitude detection circuits; as well as a plurality of averaging switches, each averaging switch being coupled to outputs of two amplitude detection circuits of the plurality of amplitude detection circuits; Wherein the plurality of averaging switches are coupled in series to couple each of the outputs of each of the plurality of amplitude detection circuits to the peak detector output.

8. The peak detector of claim 7, further comprising a control circuit configured to close the plurality of averaging switches to couple the plurality of capacitors to the peak detector output.

9. The peak detector of claim 4, further comprising: a first resistor capacitor (RC) circuit coupled to the first signal input and to the first input switch of each of the plurality of amplitude detection circuits; as well as A second RC circuit is coupled to the second signal input and to the second input switch of each amplitude detection circuit of the plurality of amplitude detection circuits.

10. The peak detector of claim 4, wherein: The plurality of amplitude detection circuits include a plurality of odd-numbered amplitude detection circuits and a plurality of even-numbered amplitude detection circuits; and The averaging circuit comprises: Multiple capacitors, including: a first capacitor coupled to an output of a first even amplitude detection circuit among the plurality of even amplitude detection circuits; and a plurality of second capacitors, each second capacitor being coupled to an output of one of the plurality of odd amplitude detection circuits; and a plurality of averaging switches, each averaging switch being coupled to an output of a corresponding one of the plurality of odd amplitude detection circuits and a corresponding one of the plurality of even amplitude detection circuits; and An output of the first even amplitude detection circuit is coupled to the outputs of the plurality of odd amplitude detection circuits and to the peak detector output.

11. The peak detector of claim 10 , wherein the control circuit is configured to, for each odd amplitude detection circuit in the plurality of odd amplitude detection circuits, close the averaging switch in the plurality of averaging switches one at a time, the averaging switch coupling one of the plurality of second capacitors corresponding to the odd amplitude detection circuit to the first capacitor.

12. The peak detector of claim 11, the control circuit further configured to close the plurality of averaging switches to couple the capacitor of each of the plurality of even amplitude detection circuits to the peak detector output.

13. An integrated circuit (IC), comprising: a transmitter configured to generate a transmission signal; a PLL including a voltage controlled oscillator (VCO) configured to generate an output signal having an amplitude based on a control voltage, the PLL configured to control a frequency of the transmission signal; Peak detectors, including: a plurality of amplitude detection circuits coupled in parallel to the first signal input and the second signal input, each amplitude detection circuit of the plurality of amplitude detection circuits being configured to generate a voltage at an output indicative of a voltage difference between the first signal input and the second signal input; and an averaging circuit coupled to an output of each of the plurality of amplitude detection circuits, the averaging circuit configured to generate an average voltage at a peak detector output, the average voltage comprising an average of the voltages generated at the outputs of the plurality of amplitude detection circuits; and The distance sensor is configured as: determining whether the average voltage at the peak detector output is outside of a voltage range; and The control voltage is adjusted in response to determining that the average voltage at the peak detector output is outside of a voltage range.

14. The IC of claim 13, wherein each of the plurality of amplitude detection circuits of the peak detector further comprises: A source follower circuit is configured to generate the voltage on the output based on a higher voltage on one of the first input and the second signal input.

15. The IC of claim 13, wherein each of the plurality of amplitude detection circuits of the peak detector further comprises: a first input switch coupled to the first signal input; as well as A second input switch is coupled to the second signal input.

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