Display device

Abstract

The invention provides a display device. The display device comprises a substrate; the first metal layer is arranged on the substrate and comprises a plurality of common lines and connecting lines, the length direction of the common lines is parallel to the first direction, and the common lines are arranged in the second direction; a gate insulating layer disposed on the first metal layer and the substrate; a semiconductor layer disposed on the gate insulating layer; the second metal layer is arranged on the gate insulation layer and comprises a plurality of shared lines, the length direction of the shared lines is parallel to the second direction, and the shared lines are arranged in the first direction; the common lines are electrically connected on two sides in a first direction through two first connecting lines, and the shared lines are electrically connected in a second direction through a second connecting line; or the common line is electrically connected with the fifth connecting line of the second metal layer through the third through hole, and the shared line is electrically connected with the fourth connecting line of the first metal layer through the second through hole. According to the invention, the electrostatic breakdown risk of the display device in the first dry etching process can be effectively reduced, and the product yield is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] At present, in order to improve the viewing angle characteristics of LCD display panels, three thin film transistors (TFT1, TFT2 and TFT3) are usually set in each pixel unit, and a shared line (SCOM1, SCOM2) is introduced to divide the voltage of the sub-pixels. Figure 1 However, as the resolution of LCD display panels continues to increase, the size of pixel units is getting smaller and smaller, resulting in a smaller spacing between the shared lines (SCOM1, SCOM2) and the data lines (DL1, DL2).

[0003] In the manufacturing process of LCD display panels, when using the A-si process 4mask process to make a thin film transistor array substrate, it is usually necessary to dry etch the semiconductor layer twice. Among them, the first dry etching is to etch the non-channel area of ​​the semiconductor layer. During the first dry etching process, since the gas is ionized by high power to form plasma, a large amount of static electricity will accumulate in the thin film transistor array substrate.

[0004] However, during the first dry etching process, the accumulated static electricity is easily released between the data lines (DL1, DL2) and the shared lines (SCOM1, SCOM2) in the thin film transistor array substrate, causing static electricity breakdown. Figure 2 As shown, the shared lines (SCOM1, SCOM2) or data lines (DL1, DL2) are disconnected, thereby reducing the product yield. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a display device to reduce the risk of electrostatic breakdown during the first dry etching process and improve the product yield.

[0006] An embodiment of the present application provides a display device, the display device includes a display panel, the display panel includes a display area and a non-display area, the display panel also includes: a substrate; a first metal layer arranged on the substrate, the first metal layer includes a plurality of common lines and two first connecting lines, the length direction of the common lines is parallel to the first direction, the plurality of common lines are arranged along a second direction, the first direction is perpendicular to the second direction, two first connecting lines are respectively arranged in the non-display area on opposite sides of the display panel in the first direction, the length direction of the first connecting line is parallel to the second direction, and two ends of the plurality of common lines are respectively electrically connected to the two first connecting lines; a gate insulating layer arranged on the first metal layer and the substrate; a semiconductor layer arranged on the gate insulating layer; and a second metal layer arranged on the gate insulating layer, the second metal layer includes a plurality of shared lines and a second connecting line, the length direction of the shared lines is parallel to the second direction, the plurality of shared lines are arranged along the first direction, the second connecting line is arranged in the non-display area of ​​the display panel in the second direction, and one end of the plurality of shared lines is electrically connected to the second connecting line.

[0007] In the above-mentioned display device, the first metal layer also includes a third connecting line, and the third connecting line is arranged in the non-display area of ​​the display panel opposite to the second connecting line in the second direction. The length direction of the third connecting line is parallel to the first direction, and the third connecting line is electrically connected to the shared line through a first through hole penetrating the gate insulation layer.

[0008] In the above display device, a plurality of the first through holes are arranged at intervals along the first direction.

[0009] In the above display device, the width of the third connection line is greater than the width of the sharing line.

[0010] In the above display device, the width of the first connection line is greater than the width of the common line; and the width of the second connection line is greater than the width of the common line.

[0011] In the above display device, the first metal layer further includes lead lines, and the lead lines are arranged in the non-display area; the first connecting lines are electrically connected to the lead lines.

[0012] An embodiment of the present application further provides a display device, the display device comprising a display panel, the display panel comprising a display area and a non-display area, the display panel further comprising: a substrate; a first metal layer disposed on the substrate, the first metal layer comprising a plurality of common lines and two fourth connection lines, the length direction of the common lines being parallel to a first direction, the plurality of common lines being arranged along a second direction, the first direction being perpendicular to the second direction, the two fourth connection lines being respectively disposed in the non-display area on two opposite sides of the display panel in the second direction, the length direction of the fourth connection lines being parallel to the first direction; a gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer arranged on the gate insulating layer; and a second metal layer arranged on the gate insulating layer, the second metal layer comprising a plurality of shared lines and two fifth connecting lines, the length direction of the shared lines being parallel to the second direction, the plurality of shared lines being arranged along the first direction, the plurality of shared lines being electrically connected to the fourth connecting lines via second through holes penetrating the gate insulating layer, the two fifth connecting lines being respectively arranged in the non-display area on opposite sides of the display panel in the first direction, the length direction of the fifth connecting lines being parallel to the second direction; wherein the plurality of shared lines are electrically connected to the fifth connecting lines via third through holes penetrating the gate insulating layer.

[0013] In the above display device, the width of the fourth connection line is greater than the width of the shared line; and the width of the fifth connection line is greater than the width of the common line.

[0014] In the above display device, a plurality of the second through holes are arranged at intervals along the first direction; and a plurality of the third through holes are arranged at intervals along the second direction.

[0015] In the above display device, the first metal layer further includes a lead line, and the lead line is arranged in the non-display area; the fifth connection line is electrically connected to the lead line through a fourth through hole penetrating the gate insulating layer.

[0016] The display device provided in the embodiment of the present application effectively reduces the risk of electrostatic breakdown of the display device during the first dry etching process through two different wiring design schemes. Specifically, in the first wiring design, the common line of the first metal layer is electrically connected on both sides of the first direction through two first connecting lines, and the shared line of the second metal layer is electrically connected on one side of the second direction through a second connecting line. The common line and the shared line are respectively formed into a grid structure. During the first dry etching process, even if a large amount of static electricity is accumulated in the common line network of the first metal layer, the shared line of the second metal layer also forms a grid structure, and after the first dry etching, and before the second wet etching, all data lines of the display device and the shared line grid form a unified electrical network, so that there is no potential difference between the data lines and shared lines of different columns, thereby avoiding electrostatic breakdown. In the second wiring design, the common line of the first metal layer is electrically connected to the fifth connecting line of the second metal layer through the third through hole, and the shared line of the second metal layer is electrically connected to the fourth connecting line of the first metal layer through the second through hole. The common line and the shared line remain in a single state during the first dry etching process. Since the static electricity of the single common line coupled to the single shared line through capacitance is small, the potential difference between the shared line and the adjacent data line is small, thereby avoiding electrostatic breakdown. Through the above technical solution, the display device of the present application can effectively solve the problem of shared line or data line disconnection due to electrostatic breakdown in the prior art, and significantly improve the product yield. The technical solution of the present application is suitable for high-resolution display devices with a small spacing between the shared line and the data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a pixel unit of a traditional LCD display panel.

[0018] Figure 2 yes Figure 1 The schematic diagram shows the electrostatic breakdown phenomenon occurring in the pixel unit of the LCD display panel.

[0019] Figure 3 is a block diagram of a display device provided in an embodiment of the present application.

[0020] Figure 4 It is a schematic diagram of a display device provided in the first embodiment of the present application.

[0021] Figure 5 is a schematic diagram of a display device provided in the second embodiment of the present application.

[0022] Figure 6 It is a cross-sectional view of the thin film transistor array substrate of the display device provided by the embodiment of the present application when the first dry etching is completed. DETAILED DESCRIPTION

[0023] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0024] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0025] The embodiments of the present application may be combined with each other.

[0026] When manufacturing the thin film transistor array substrate of the liquid crystal display panel, the amorphous silicon four-mask process is generally used. This process requires two dry etchings of the thin film transistor array substrate. The first dry etching is to etch the semiconductor layer A-Si in the non-channel area of ​​the thin film transistor array substrate. During the first dry etching process, a large amount of static electricity will accumulate in the thin film transistor array substrate because the gas is ionized by high power to form plasma.

[0027] like Figure 1 As shown in FIG. 1 , in order to improve the viewing angle characteristics of the liquid crystal display panel, three thin film transistors (TFT1, TFT2 and TFT3) are arranged in each pixel unit, and a shared line SCOM is introduced to divide the voltage of the sub-pixels. However, as the resolution of the liquid crystal display panel continues to increase, the size of the pixel unit is getting smaller and smaller, and the spacing between the shared line SCOM and the data line is also getting smaller and smaller.

[0028] However, during the first dry etching process, if the wiring design of the common line ACOM and the shared line SCOM is improper, the accumulated static electricity is easily released between the data line and the shared line SCOM, causing static electricity breakdown, such as Figure 2 As shown, the shared line SCOM or the data line is disconnected, thereby reducing the product yield. Specifically, when the first dry etching is completed, since the channel area of ​​the thin film transistors (TFT1, TFT2 and TFT3) is still covered by the photoresist PR, each data line and the source, drain and shared line SCOM (all belonging to the second metal layer M2) of the thin film transistor of the corresponding pixel are connected together to form a column unit, as shown in FIG. Figure 2 As shown. At this time, the common line ACOM of the first metal layer M1 will accumulate a large amount of static electricity, and couple the static electricity to the column unit of the second metal layer M2 through capacitive coupling. Since the through-hole layer has not yet been made, the shared line SCOM has not formed a grid structure, resulting in the voltage of the data line of the first column of pixels being equal to the voltage of the shared line SCOM of the first column of pixels, but not equal to the voltage of the data line of the second column of pixels (equal to the voltage of the shared line SCOM of the second column of pixels). Since there may be a large potential difference between the shared line SCOM of the first column of pixels and the data line of the second column of pixels, electrostatic breakdown is prone to occur when the spacing between them is small.

[0029] In order to solve the above technical problems, this application proposes two solutions.

[0030] like Figure 4 and Figure 6 As shown, the first solution is: the common line ACOM of the first metal layer M1 forms a grid structure through two first connection lines CL1, and the shared line SCOM of the second metal layer M2 forms a grid structure through the second connection line CL2. Specifically, the first metal layer M1 includes a plurality of common lines ACOM and two first connection lines CL1, the common line ACOM is arranged in the display area of ​​the display panel, the length direction of the common line ACOM is parallel to the first direction, the plurality of common lines ACOM are arranged along the second direction, the first connection line CL1 is arranged in the non-display area of ​​the display panel on both sides opposite to each other in the first direction, the length direction of the first connection line CL1 is parallel to the second direction, and the two ends of the plurality of common lines ACOM are electrically connected to the two first connection lines CL1 respectively. The second metal layer M2 includes a plurality of shared lines SCOM and a second connection line CL2, the length direction of the shared line SCOM is parallel to the second direction, the plurality of shared lines SCOM are arranged along the first direction, the shared line SCOM is arranged in the display area of ​​the display panel, one end of the shared line SCOM is electrically connected to the second connection line CL2, and the second connection line CL2 is arranged in the non-display area of ​​the display panel in the second direction. The first metal layer M1 also includes a third connection line CL3, which is located in a non-display area of ​​the display panel opposite to the second connection line CL2 in the second direction. The length direction of the third connection line CL3 is parallel to the first direction. The third connection line CL3 is electrically connected to the shared line SCOM through a first through hole VH1 that penetrates the gate insulating layer GI.

[0031] The beneficial effect of the first solution is: although the first dry etching process will cause the grid-shaped common line ACOM of the first metal layer M1 to accumulate a large amount of static electricity, since the shared line SCOM of the second metal layer M2 also forms a grid structure, after the first dry etching and before the second wet etching, since the channel area of ​​the thin film transistor (TFT1, TFT2 and TFT3) is still covered by the photoresist PR, the source and drain of the thin film transistor (TFT1, TFT2 and TFT3) are directly connected. Therefore, all data lines form a unified electrical network through the grid-shaped shared line SCOM, and no potential difference will be generated between the data lines in different columns and the shared line SCOM, thereby avoiding electrostatic breakdown.

[0032] like Figure 5As shown, the second solution is: the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both set to a single-line structure, and then a grid structure is formed by connecting lines located in different layers. Specifically, the first metal layer M1 includes a plurality of common lines ACOM and two fourth connecting lines CL4, the common line ACOM is set in the display area of ​​the display panel, the length direction of the common line ACOM is parallel to the first direction, the plurality of common lines ACOM are arranged along the second direction, the two fourth connecting lines CL4 are respectively set in the non-display area of ​​the display panel on both sides opposite to each other in the second direction, and the length direction of the fourth connecting line CL4 is parallel to the first direction. The second metal layer M2 includes a plurality of shared lines SCOM and two fifth connecting lines CL5, the shared line SCOM is set in the display area of ​​the display panel, the length direction of the shared line SCOM is parallel to the second direction, the plurality of shared lines SCOM are arranged along the first direction, the two fifth connecting lines CL5 are respectively set in the non-display area of ​​the display panel on both sides opposite to each other in the first direction, and the length direction of the fifth connecting line CL5 is parallel to the second direction. The plurality of common lines ACOM are electrically connected to the fifth connection line CL5 through the third through holes VH3 penetrating the gate insulating layer GI, and the plurality of sharing lines SCOM are electrically connected to the fourth connection line CL4 through the second through holes VH2 penetrating the gate insulating layer GI.

[0033] The beneficial effect of the second solution is: during the first dry etching process, since the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both single-line structures, the amount of static electricity from the single common line ACOM coupled to the single shared line SCOM through capacitance is small, so the potential difference between the shared line SCOM and the adjacent data line is small, and electrostatic breakdown is not easy to occur.

[0034] Through the above two solutions, the present application can effectively reduce the risk of electrostatic breakdown of the display panel during the manufacturing process and improve the product yield.

[0035] like Figure 3 As shown, the display device provided in the embodiment of the present application includes a display panel, a timing controller TCON, a source driving circuit DD and a power management chip (not shown in the figure, the power management chip can be integrated with the timing controller TCON into the same chip). The display panel can be, for example, a liquid crystal display panel.

[0036] The display panel includes a display area and a non-display area. The display area is provided with m×n pixel units P arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange the drive circuit and various signal lines. The display panel also includes a plurality of scan lines (GL1~GLn), a plurality of data lines (DL1~DLm) and a gate drive circuit GOA. The plurality of scan lines (GL1~GLn) extend along a first direction and are arranged along a second direction, and the plurality of data lines (DL1~DLm) extend along a second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit GOA is arranged in the non-display area and is electrically connected to the plurality of scan lines (GL1~GLn). The source drive circuit DD is electrically connected to the plurality of data lines (DL1~DLm) through a flexible circuit board. The timing controller TCON is electrically connected to the gate drive circuit GOA and the source drive circuit DD respectively.

[0037] The display panel includes a thin film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The thin film transistor array substrate includes a glass substrate, a first metal layer M1 disposed on the glass substrate, a gate insulating layer GI disposed on the first metal layer M1, a semiconductor layer A-Si disposed on the gate insulating layer GI, a second metal layer M2 disposed on the semiconductor layer A-Si, a passivation layer disposed on the second metal layer M2, and a pixel electrode disposed on the passivation layer. The first metal layer M1 includes scan lines (GL1~GLn), a gate electrode, etc. The second metal layer M2 includes data lines (DL1~DLm), a source electrode, a drain electrode, etc. The opposing substrate includes a glass substrate, a black matrix disposed on the glass substrate, a color filter layer disposed on the black matrix, and a common electrode disposed on the color filter layer.

[0038] Each pixel unit P includes at least one thin film transistor TFT and a pixel electrode. The gate of the thin film transistor TFT is electrically connected to the corresponding scan line, the source is electrically connected to the corresponding data line, and the drain is electrically connected to the corresponding pixel electrode. When the scan line outputs a high-level scan signal, the thin film transistor TFT is turned on, and the data signal on the data line is transmitted to the pixel electrode through the thin film transistor TFT; when the scan line outputs a low-level scan signal, the thin film transistor TFT is turned off, and the pixel electrode maintains the voltage corresponding to the data signal.

[0039] The gate drive circuit GOA includes n-stage cascaded gate drive units, and each stage of the gate drive unit is electrically connected to a scan line. Under the control of the timing controller TCON, the gate drive unit sequentially outputs scan signals to scan each row of pixel units in the display area line by line. Under the control of the timing controller TCON, the source drive circuit DD generates and outputs data signals according to the image data. The timing controller TCON is used to receive and process externally input image data and timing signals, generate control signals, and transmit image data to the source drive circuit DD. The power management chip is used to provide operating voltages for various parts of the liquid crystal display device, including providing common voltages for common electrodes, gate drive voltages for the gate drive circuit GOA, and gamma voltages for the source drive circuit DD.

[0040] like Figure 4 As shown, the first embodiment of the present application provides a display device, which includes a display panel, the display panel includes a display area and a non-display area, and the display panel also includes a thin film transistor array substrate, an opposing substrate, and a liquid crystal layer arranged between the thin film transistor array substrate and the opposing substrate.

[0041] The thin film transistor array substrate includes a substrate SBT, a first metal layer M1 arranged on the substrate SBT, a gate insulating layer GI arranged on the first metal layer M1 and the substrate SBT, a semiconductor layer A-Si arranged on the gate insulating layer GI, and a second metal layer M2 arranged on the gate insulating layer GI.

[0042] The first metal layer M1 includes a plurality of common lines ACOM and two first connecting lines CL1. The length direction of the common lines ACOM is parallel to the first direction. The plurality of common lines ACOM are arranged along a second direction. The first direction is perpendicular to the second direction. The two first connecting lines CL1 are respectively arranged in the non-display area on two opposite sides of the display panel in the first direction. The length direction of the first connecting lines CL1 is parallel to the second direction. Both ends of the plurality of common lines ACOM are respectively electrically connected to the two first connecting lines CL1.

[0043] The second metal layer M2 includes multiple shared lines SCOM and a second connecting line CL2. The length direction of the shared line SCOM is parallel to the second direction. The multiple shared lines SCOM are arranged along the first direction. The second connecting line CL2 is set in the non-display area of ​​the display panel in the second direction. The length direction of the second connecting line CL2 is parallel to the first direction. One end of the multiple shared lines SCOM is electrically connected to the second connecting line CL2.

[0044] The first metal layer M1 further includes a plurality of gate lines, and the length directions of the gate lines are parallel to the first direction.

[0045] The second metal layer M2 further includes a plurality of data lines, the length direction of the data lines is parallel to the second direction, and there is a preset distance between the data lines and the adjacent shared lines SCOM, and the preset distance is less than 10 micrometers.

[0046] In this embodiment, the substrate SBT is a glass substrate or a quartz substrate. The first metal layer M1 is a single metal layer or a multi-layer metal layer. The gate insulating layer GI can be made of insulating materials such as silicon nitride, silicon oxide or aluminum oxide. The semiconductor layer A-Si can be made of amorphous silicon material. The second metal layer M2 is made of the same material as the first metal layer M1.

[0047] A black matrix and a color filter layer are provided on the counter substrate. The black matrix is ​​used to block the light in the non-display area and is made of metal chromium or resin material. The color filter layer includes a red filter unit, a green filter unit and a blue filter unit, which are used to achieve color display. A common electrode is provided on the counter substrate, and the material of the common electrode is a transparent conductive material.

[0048] The display panel also includes a plurality of pixel units, each pixel unit includes a main pixel electrode, a sub-pixel electrode, a first thin film transistor TFT1, a second thin film transistor TFT2 and a third thin film transistor TFT3; wherein the gates of the first thin film transistor TFT1, the second thin film transistor TFT2 and the third thin film transistor TFT3 are all electrically connected to the gate line, the source of the first thin film transistor TFT1 and the source of the second thin film transistor TFT2 are electrically connected to the data line, the drain of the first thin film transistor TFT1 and the drain of the second thin film transistor TFT2 are electrically connected to the main pixel electrode and the sub-pixel electrode respectively, the drain of the second thin film transistor TFT2 is also electrically connected to the source of the third thin film transistor TFT3, and the drain of the third thin film transistor TFT3 is electrically connected to the shared line SCOM. The material of the main pixel electrode and the sub-pixel electrode is a transparent conductive material, such as indium tin oxide. The main pixel electrode and the sub-pixel electrode are electrically connected to the drain of the corresponding thin film transistor through a via located in the passivation layer. The passivation layer is an organic material or an inorganic material.

[0049] The semiconductor layer A-Si includes a non-channel portion and a channel portion, and the channel portion connects the source and drain of the first thin film transistor TFT1 , the second thin film transistor TFT2 , and the third thin film transistor TFT3 .

[0050] The gate line is arranged in parallel with the common line ACOM, and the data line is arranged in parallel with the sharing line SCOM.

[0051] In the display area, gate lines and common lines ACOM are alternately arranged in the first direction, that is, a common line ACOM is arranged between every two adjacent gate lines. Data lines and shared lines SCOM are alternately arranged in the first direction, that is, a shared line SCOM is arranged between every two adjacent data lines.

[0052] The first connection line CL1 may be provided with a plurality of connection parts in the connection area with the common line ACOM, and the width of each connection part may be 1.5 to 2 times the width of the common line ACOM. The second connection line CL2 may also be provided with a plurality of connection parts in the connection area with the shared line SCOM, and the width of each connection part may be 1.5 to 2 times the width of the shared line SCOM.

[0053] In this embodiment, the edges of the first connection line CL1 and the second connection line CL2 may be configured to be serrated, and the serrated edges are conducive to releasing stress and preventing the first connection line CL1 and the second connection line CL2 from cracking.

[0054] The first metal layer M1 also includes a third connection line CL3, which is arranged in a non-display area of ​​the display panel opposite to the second connection line CL2 in the second direction. The length direction of the third connection line CL3 is parallel to the first direction. The third connection line CL3 is electrically connected to the shared line SCOM through a first through hole VH1 that penetrates the gate insulating layer GI.

[0055] A plurality of first through holes VH1 are arranged at intervals along the first direction.

[0056] The width of the third connection line CL3 is greater than the width of the sharing line SCOM. For example, the width of the third connection line CL3 may be 1.2 to 2 times the width of the sharing line SCOM.

[0057] The width of the first connection line CL1 is greater than the width of the common line ACOM; the width of the second connection line CL2 is greater than the width of the shared line SCOM. Specifically, the width of the first connection line CL1 may be 1.2 to 2 times the width of the common line ACOM, and the width of the second connection line CL2 may be 1.2 to 2 times the width of the shared line SCOM. By increasing the width of the connection line, the conductivity of the connection line can be improved, which is beneficial to the conduction and dispersion of static electricity.

[0058] The first metal layer M1 further includes a lead line LW, which is disposed in the non-display area; the first connection line CL1 is electrically connected to the lead line LW, and the lead line LW is used to provide a common voltage of the power management chip to the common line ACOM.

[0059] In this embodiment, the lead wire LW may include a plurality of parallel sub-lead wires LW, and the width of each sub-lead wire LW may be 1.5 to 3 times the width of the common line ACOM. By providing a plurality of parallel sub-lead wires LW, the resistance of the lead wire LW may be reduced and the stability of the power supply may be improved.

[0060] The lead wire LW gradually widens as it extends outward from the end connected to the first connection wire CL1. For example, the width of the lead wire LW at the connection with the first connection wire CL1 may be 1 to 1.2 times the width of the first connection wire CL1, and the width of the lead wire LW at the outer end may be 2 to 3 times the width of the first connection wire CL1. This gradual width design is conducive to reducing stress concentration.

[0061] In this embodiment, the third connection line CL3 includes a plurality of fold line segments, and the angle between adjacent fold line segments is an obtuse angle, which can reduce the stress concentration of the third connection line CL3 at the corner. The fold line structure of the third connection line CL3 can provide a longer routing distance in a limited non-display area space. During the use of the display panel, due to changes in ambient temperature, the substrate SBT will undergo thermal expansion or contraction, causing the third connection line CL3 to be subjected to tensile or compressive stress. The third connection line CL3 with a fold line structure can buffer these stresses through deformation between the fold line segments, thereby avoiding stress concentration causing the third connection line CL3 to break.

[0062] The first through holes VH1 are arranged in a staggered manner, that is, two adjacent rows of through holes are arranged in a staggered manner in the first direction, or in a group arrangement manner, that is, a plurality of small through holes are arranged at each intersection of the third connection line CL3 and the shared line SCOM, and these small through holes are concentrated together to form a through hole. Since a large current needs to be transmitted at the intersection of the third connection line CL3 and the shared line SCOM, a large through hole structure composed of a plurality of small through holes can increase the conductive cross-sectional area and reduce the contact resistance.

[0063] The profile of each through hole is set to be an octagon to reduce stress concentration at the edge of the through hole. The side wall of the through hole is a slope, which is conducive to improving the coverage of the metal layer in the through hole.

[0064] The third connection line CL3 is provided with a structural reinforcement part at a position corresponding to the through hole, and the width of the structural reinforcement part is greater than the width of other parts of the third connection line CL3. The structural reinforcement part is arranged in a ring shape around the through hole, and the outer edge of the structural reinforcement part is arranged in an arc shape. This design can enhance the mechanical strength of the through hole, improve the reliability of the electrical connection, and avoid stress concentration.

[0065] Through the above technical solution, the display device of this embodiment can effectively reduce the risk of electrostatic breakdown during the first dry etching process. Specifically, since the common line ACOM of the first metal layer M1 forms a grid structure through the two first connection lines CL1, and the shared line SCOM of the second metal layer M2 forms a grid structure through the second connection line CL2, after the first dry etching and before the second wet etching, all data lines form a unified electrical network through the grid-like shared line SCOM, and no potential difference is generated between the data lines and the shared line SCOM in different columns, thereby avoiding electrostatic breakdown.

[0066] like Figure 5 As shown, the second embodiment of the present application provides a display device, and the second embodiment is similar to the first embodiment, except that:

[0067] The display device includes a display panel, which includes a display area and a non-display area. The display panel also includes a substrate SBT, a first metal layer M1 arranged on the substrate SBT, a gate insulating layer GI arranged on the first metal layer M1 and the substrate SBT, a semiconductor layer A-Si arranged on the gate insulating layer GI, and a second metal layer M2 arranged on the gate insulating layer GI.

[0068] The first metal layer M1 includes a plurality of common lines ACOM and two fourth connection lines CL4, the length direction of the common lines ACOM is parallel to the first direction, the plurality of common lines ACOM are arranged along the second direction, the first direction is perpendicular to the second direction, the two fourth connection lines CL4 are respectively arranged in the non-display area on both sides of the display panel opposite to each other in the second direction, and the length direction of the fourth connection lines CL4 is parallel to the first direction.

[0069] The second metal layer M2 includes multiple shared lines SCOM and two fifth connection lines CL5. The length direction of the shared lines SCOM is parallel to the second direction. The multiple shared lines SCOM are arranged along the first direction. The multiple shared lines SCOM are electrically connected to the fourth connection line CL4 through the second through hole VH2 that penetrates the gate insulation layer GI. The two fifth connection lines CL5 are respectively arranged in the non-display area on both sides of the display panel opposite to each other in the first direction, and the length direction of the fifth connection line CL5 is parallel to the second direction.

[0070] The plurality of common lines ACOM are electrically connected to the fifth connection line CL5 through the third through hole VH3 penetrating the gate insulating layer GI.

[0071] The width of the fourth connection line CL4 is greater than the width of the sharing line SCOM; the width of the fifth connection line CL5 is greater than the width of the common line ACOM.

[0072] A plurality of second through holes VH2 are arranged at intervals along the first direction; and a plurality of third through holes VH3 are arranged at intervals along the second direction.

[0073] The first metal layer M1 further includes lead lines LW, and the lead lines LW are disposed in the non-display area.

[0074] The fifth connection line CL5 is electrically connected to the lead line LW through a fourth through hole penetrating the gate insulating layer GI.

[0075] In this embodiment, the fourth connection line CL4 and the fifth connection line CL5 include a plurality of fold line segments, and the angle between adjacent fold line segments is an obtuse angle, which can reduce the stress concentration of the fourth connection line CL4 and the fifth connection line CL5 at the corner. The fold line structure of the fourth connection line CL4 and the fifth connection line CL5 can provide a longer routing distance in a limited non-display area space. During the use of the display panel, due to changes in ambient temperature, the substrate SBT will undergo thermal expansion or contraction, causing the fourth connection line CL4 and the fifth connection line CL5 to be subjected to tensile or compressive stress. The fourth connection line CL4 and the fifth connection line CL5 using a fold line structure can buffer these stresses through the deformation between the fold line segments, thereby avoiding stress concentration causing the fourth connection line CL4 and the fifth connection line CL5 to break.

[0076] The first through holes VH1 are arranged in a staggered manner, that is, two adjacent rows of through holes are arranged in a staggered manner in the first direction, or in a group arrangement manner, that is, a plurality of small through holes are arranged at each intersection of the fourth connection line CL4, the fifth connection line CL5 and the shared line SCOM, and these small through holes are concentrated together to form a through hole. Since a large current needs to be transmitted at the intersection of the fourth connection line CL4, the fifth connection line CL5 and the shared line SCOM, a large through hole structure composed of a plurality of small through holes can increase the conductive cross-sectional area and reduce the contact resistance.

[0077] The profile of each through hole is set to be an octagon to reduce stress concentration at the edge of the through hole. The side wall of the through hole is a slope, which is conducive to improving the coverage of the metal layer in the through hole.

[0078] The fourth connection line CL4 and the fifth connection line CL5 are provided with a structural reinforcement part at the position corresponding to the through hole, and the width of the structural reinforcement part is greater than the width of other parts of the fourth connection line CL4 and the fifth connection line CL5. The structural reinforcement part is arranged in a ring shape around the through hole, and the outer edge of the structural reinforcement part is arranged in an arc shape. This design can enhance the mechanical strength of the through hole, improve the reliability of the electrical connection, and avoid stress concentration.

[0079] Through the above technical solution, the display device of this embodiment can effectively reduce the risk of electrostatic breakdown during the first dry etching process. Specifically, during the first dry etching process, since the common line ACOM of the first metal layer M1 and the shared line SCOM of the second metal layer M2 are both single-line structures, the amount of static electricity of the single common line ACOM coupled to the single shared line SCOM through capacitance is small, so the potential difference between the shared line SCOM and the adjacent data line is small, and electrostatic breakdown is not easy to occur. After completing the first dry etching, the common line ACOM is electrically connected to the fifth connection line CL5 through the third through hole VH3 to form a grid structure, and the shared line SCOM is electrically connected to the fourth connection line CL4 through the second through hole VH2 to form a grid structure. This subsequently formed grid structure will not affect the electrostatic protection effect during the first dry etching process.

[0080] The display panel provided in the present application is manufactured through the following steps.

[0081] A thin film transistor array substrate and an opposing substrate are formed.

[0082] A liquid crystal layer is disposed on the thin film transistor array substrate.

[0083] An opposing substrate is disposed on the thin film transistor array substrate.

[0084] The step of forming a thin film transistor array substrate includes:

[0085] A first metal film is deposited on the substrate SBT.

[0086] The first metal film is etched to form a plurality of gate lines and a common line ACOM (first metal layer M1). In the first embodiment of the present application, two first connecting lines CL1 are also formed in the first metal layer M1. In the second embodiment of the present application, two fourth connecting lines CL4 are also formed in the first metal layer M1.

[0087] The step of etching the first metal film to form a plurality of gate lines and a common line ACOM includes: coating a photoresist on the first metal film; exposing and developing the photoresist to form a mask including a common line ACOM, a first connection line CL1 and a gate line pattern; etching the first metal film by a wet etching method; removing the photoresist to obtain a first metal layer M1. The material of the first metal layer M1 can be chromium, molybdenum, aluminum or an alloy thereof.

[0088] A gate insulating layer GI is formed on the first metal layer M1 and the substrate SBT.

[0089] A semiconductor layer A-Si is formed on the gate insulating layer GI.

[0090] A second metal thin film is deposited on the semiconductor layer A-Si and the gate insulating layer GI.

[0091] The second metal film is wet-etched for the first time to form a plurality of electrically connected data lines and shared lines SCOM, wherein the step of wet-etching the second metal film for the first time to form a plurality of electrically connected data lines and shared lines SCOM includes: coating a photoresist PR on the second metal film; exposing and developing the photoresist PR to form a mask including shared lines SCOM, second connection lines CL2 and data line patterns; etching the second metal film by a wet etching method. After the first wet etching, the second metal film exposes the non-channel region of the semiconductor layer A-Si, at which time, the source and drain of the three thin film transistors (the first thin film transistor TFT1, the second thin film transistor TFT2, and the third thin film transistor TFT3) are not separated, that is, the data line and the shared line SCOM are a whole, in the first embodiment of the present application, a second connection line CL2 is also formed in the second metal film, and in the second embodiment of the present application, two fifth connection lines CL5 are also formed in the second metal film;

[0092] The non-channel region of the semiconductor layer A-Si is first dry-etched.

[0093] The second metal film is wet-etched for the second time to remove the photoresist PR to form a data line and a shared line SCOM (a second metal layer M2). At this time, the source and drain of the three thin film transistors (a first thin film transistor TFT1, a second thin film transistor TFT2, and a third thin film transistor TFT3) are separated, that is, the data line and the shared line SCOM (a second metal layer M2) are formed. The material of the second metal layer M2 can be chromium, molybdenum, aluminum, or an alloy thereof.

[0094] The channel region of the semiconductor layer A-Si is dry-etched for the second time.

[0095] The embodiments of the present application are described in detail above, and the contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: The display device includes a display panel, the display panel includes a display area and a non-display area, and the display panel further includes: substrate; A first metal layer is provided on the substrate, the first metal layer comprises a plurality of common lines and two first connecting lines, the length direction of the common lines is parallel to the first direction, the plurality of common lines are arranged along a second direction, the first direction is perpendicular to the second direction, the two first connecting lines are respectively provided in the non-display area on two opposite sides of the display panel in the first direction, the length direction of the first connecting lines is parallel to the second direction, and two ends of the plurality of common lines are respectively electrically connected to the two first connecting lines; a gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer disposed on the gate insulating layer; and A second metal layer is arranged on the gate insulating layer, the second metal layer includes a plurality of shared lines and a second connecting line, the length direction of the shared lines is parallel to the second direction, the plurality of shared lines are arranged along the first direction, the second connecting line is arranged in the non-display area of ​​the display panel in the second direction, and one end of the plurality of shared lines is electrically connected to the second connecting line.

2. The display device according to claim 1, characterized in that The first metal layer also includes a third connecting line, which is arranged in the non-display area of ​​the display panel opposite to the second connecting line in the second direction. The length direction of the third connecting line is parallel to the first direction, and the third connecting line is electrically connected to the shared line through a first through hole penetrating the gate insulation layer.

3. The display device according to claim 2, characterized in that A plurality of the first through holes are arranged at intervals along the first direction.

4. The display device according to claim 2, characterized in that: The width of the third connection line is greater than the width of the sharing line.

5. The display device according to claim 1, characterized in that The width of the first connection line is greater than the width of the common line; The width of the second connection line is greater than the width of the sharing line.

6. The display device according to claim 1, characterized in that: The first metal layer further includes a lead-out line, and the lead-out line is arranged in the non-display area; The first connecting wire is electrically connected to the lead wire.

7. A display device, characterized in that: The display device includes a display panel, the display panel includes a display area and a non-display area, and the display panel further includes: substrate; A first metal layer is provided on the substrate, the first metal layer comprises a plurality of common lines and two fourth connecting lines, the length direction of the common lines is parallel to the first direction, the plurality of common lines are arranged along a second direction, the first direction is perpendicular to the second direction, the two fourth connecting lines are respectively provided in the non-display area on two sides of the display panel opposite to each other in the second direction, and the length direction of the fourth connecting lines is parallel to the first direction; a gate insulating layer disposed on the first metal layer and the substrate; A semiconductor layer disposed on the gate insulating layer; and a second metal layer disposed on the gate insulating layer, the second metal layer comprising a plurality of shared lines and two fifth connecting lines, the length direction of the shared lines being parallel to the second direction, the plurality of shared lines being arranged along the first direction, the plurality of shared lines being electrically connected to the fourth connecting lines via second through holes penetrating the gate insulating layer, the two fifth connecting lines being respectively disposed in the non-display area on two opposite sides of the display panel in the first direction, and the length direction of the fifth connecting lines being parallel to the second direction; The plurality of common lines are electrically connected to the fifth connection line through a third through hole penetrating the gate insulating layer.

8. The display device according to claim 7, characterized in that: The width of the fourth connection line is greater than the width of the shared line; The width of the fifth connection line is greater than the width of the common line.

9. The display device according to claim 7, characterized in that: A plurality of the second through holes are arranged at intervals along the first direction; The plurality of third through holes are arranged at intervals along the second direction.

10. The display device according to claim 7, characterized in that: The first metal layer further includes a lead-out line, and the lead-out line is arranged in the non-display area; The fifth connection line is electrically connected to the lead line through a fourth through hole penetrating the gate insulating layer.

Images