Timer processing method and device, equipment and storage medium

Abstract

The invention provides a timer processing method and device, equipment and a storage medium, and relates to the technical field of computers, in particular to the technical field of cloud services. The method comprises the steps of determining whether a virtual machine runs on a CPU core or not and whether the virtual machine uses a transparent transmission timer or not under the condition that the CPU core detects timing interruption, and obtaining a virtual machine determination result; wherein the virtual machine uses an unvarnished transmission timer for representing that the virtual machine directly accesses a first type of physical timer through an unvarnished transmission timer technology; processing the timing interruption according to the virtual machine determination result and the clock source of the timing interruption; wherein the clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast timing interruption to each CPU core in the host machine.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of cloud service technology, and specifically to a timer processing method, device, equipment and storage medium. Background Art

[0002] Many computer activities rely on the perception of time, such as counting the running time of a process for scheduling the process, and the file system needs to obtain the current date and time to record the creation time of a file. Among them, the timer focuses on how much time has passed, and the system's internal timing or delay mechanism relies on this.

[0003] In cloud computing scenarios, cloud service providers use virtualization technology to divide a single physical server (i.e., host machine) into multiple virtual machines for users to use. In this virtualization scenario, virtual machines still have a need for timers, but unlike the host machine, which can directly use the timer hardware resources, the timer of the virtual machine is simulated by the VMM (virtual machine monitor) on the host machine. Every time the virtual machine needs to set a timer, the control of the CPU will be handed over to the VMM in the host machine, and the VMM will simulate the timer function required by the virtual machine through software or hardware. The additional overhead caused by the CPU switching between the operating modes of the host machine and the virtual machine is huge, often hundreds or even thousands of CPU clock cycles.

[0004] Therefore, it is very important to reduce the timing overhead of virtual machines. Summary of the invention

[0005] The present disclosure provides a timer processing method, apparatus, device and storage medium.

[0006] According to one aspect of the present disclosure, a timer processing method is provided, including:

[0007] In the case where the CPU core detects a timing interrupt, determining whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to characterize that the virtual machine directly accesses a first type of physical timer through a transparent transmission timer technology;

[0008] Processing the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt;

[0009] The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

[0010] According to one aspect of the present disclosure, a timer processing device is provided, comprising:

[0011] A virtual machine result determination module is used to determine whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer when the CPU core detects a timing interrupt, and obtain a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to indicate that the virtual machine directly accesses the first type of physical timer through the transparent transmission timer technology;

[0012] A timer interrupt processing module, used for processing the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt;

[0013] The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

[0014] According to another aspect of the present disclosure, there is provided an electronic device, the electronic device comprising:

[0015] at least one processor; and

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method provided by any embodiment of the present disclosure.

[0018] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the method provided by any embodiment of the present disclosure.

[0019] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the method provided according to any embodiment of the present disclosure is implemented.

[0020] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flow chart of a timer processing method provided according to an embodiment of the present disclosure;

[0022] Figure 2 is a flowchart of another timer processing method provided according to an embodiment of the present disclosure;

[0023] Figure 3is a flowchart of another timer processing method provided according to an embodiment of the present disclosure;

[0024] Figure 4 is a flowchart of another timer processing method provided according to an embodiment of the present disclosure;

[0025] Figure 5 is a structural schematic diagram of a timer processing device provided according to an embodiment of the present disclosure;

[0026] Figure 6 The block diagram is a block diagram of an electronic device for implementing the timer processing method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Figure 1 1 is a flowchart of a timer processing method provided according to an embodiment of the present disclosure. The method is applicable to the case where the first type of physical timer is transparently transmitted to a virtual machine for use. The method can be executed by a timer processing device, which can be implemented in software and / or hardware and can be integrated into an electronic device. Figure 1 As shown, the timer processing method of this embodiment may include:

[0028] S101, when a CPU core detects a timing interrupt, determining whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to indicate that the virtual machine directly accesses a first type of physical timer through a transparent transmission timer technology;

[0029] S102, processing the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt;

[0030] The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

[0031] In the disclosed embodiment, the CPU in the host machine is multi-core, and multiple virtual machines can run on the host machine. Each physical CPU core (i.e., CPU core) can have a first-class physical timer; each CPU core can reuse a second-class physical timer, that is, the host machine has only a unique second-class physical timer, and the second-class physical timer can be configured to broadcast its own timing interrupt to each CPU core.

[0032] The pass-through timer technology is a technology implemented in a virtualized environment, which allows a virtual machine to directly access and operate the registers of the underlying hardware timer. Through the pass-through timer technology, the virtual machine can bypass the intervention of the virtualization layer and directly control the behavior of the physical timer, such as setting timing data, reading count values, etc. In the embodiment of the present disclosure, a virtual machine (Virtual Machine, VM) may be running on the CPU core, or a virtual machine may not be running; when a virtual machine is running on the CPU core, the first type of physical timer on the CPU core can be passed to the virtual machine for use through the pass-through timer technology. If the first type of physical timer is passed to the virtual machine for use through the pass-through timer technology, the virtual machine can directly access the first type of physical timer, and the timing data of the virtual machine can be directly written into the first type of physical timer when the virtual machine has a timing requirement. Therefore, in the process of writing timing data by the virtual machine, there is no need for the virtual machine to exit (VM-exit), that is, the CPU control mode can be maintained in the non-root mode without switching to the root mode. Among them, the root mode can be called the host mode, and the non-root mode can be called the virtual machine mode. The behavior of changing the CPU operation mode from host mode to virtual machine mode is called virtual machine entry (VM-enter), and vice versa, changing from virtual machine mode to host mode is called virtual machine exit (VM-exit). By transparently transmitting the first type of physical timer to the virtual machine for use, virtual machine exits can be reduced, thereby reducing virtual machine overhead. It should be noted that if the virtual machine does not support timer transparent transmission, software is still used to simulate the timer for the virtual machine, such as using HRtimer (High Resolution Timer) simulation.

[0033] However, when the CPU core detects a timer interrupt, the clock source of the timer interrupt may be the first type of physical timer or the second type of physical timer, and the timer interrupt may belong to the CPU core's timed task or the virtual machine's timed task. Therefore, in the transparent timer technology, how to handle the virtual machine's timer interrupt is very important.

[0034] In the disclosed embodiment, when the CPU core detects a timer interrupt, it is determined whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent timer to obtain a virtual machine determination result; and it is also determined whether the clock source of the timer interrupt is a first-class physical timer or a second-class physical timer. Combining the virtual machine determination result and the clock source of the timer interrupt can determine and distinguish whether the timer interrupt belongs to a timed task of the CPU core or a timed task of the virtual machine, and the corresponding timed task is processed in combination with the determination result of the virtual machine. By combining the virtual machine determination result and the clock source of the timer interrupt to process the timer interrupt, it is possible to distinguish whether the timer interrupt belongs to a timed task of the CPU core or a timed task of the virtual machine, thereby ensuring that the timer interrupt processing of the virtual machine is accurate.

[0035] The technical solution provided by the embodiment of the present disclosure can reduce virtual machine exits and thus virtual machine overhead by transparently transmitting the first type of physical timer to the virtual machine for use; and can ensure accurate timing interrupt processing of the virtual machine by combining the virtual machine determination result and the clock source of the timing interrupt to process the timing interrupt.

[0036] In an optional implementation, the first type of physical timer is an Advanced Programmable Interrupt Controller (APIC), and the second type of physical timer is a High Precision Event Timer (HPET).

[0037] Figure 2 is a flowchart of another timer processing method provided according to an embodiment of the present disclosure. Figure 2 Based on the above embodiment, the processing of the timer interrupt is further limited. The timer processing method of this embodiment may include:

[0038] S201, when the CPU core detects a timing interrupt, determining whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to indicate that the virtual machine directly accesses a first type of physical timer through a transparent transmission timer technology;

[0039] S202: If the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, determine whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer;

[0040] S203, if the clock source is the first type of physical timer, the virtual machine times out and injects an interrupt into the virtual machine control structure of the virtual machine through the kernel virtual machine module;

[0041] S204, processing the scheduled task of the virtual machine in response to the scheduled interrupt information of the virtual machine control structure by the virtual machine;

[0042] The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

[0043] When the CPU core detects a timer interrupt, it determines whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent timer; if a virtual machine is running on the CPU core and the virtual machine uses a transparent timer, it determines whether the clock source of the timer interrupt is a first-class physical timer or a second-class physical timer; if the clock source is a first-class physical timer, it determines that the timer interrupt belongs to the timed task of the virtual machine. In this case, the virtual machine times out and injects an interrupt into the virtual machine control structure of the virtual machine through the kernel virtual machine module (KVM). After the interrupt is injected, the virtual machine enters, detects the timer interrupt information transmitted by the virtual machine control structure, and processes the timed task of the virtual machine. If Intel virtualization technology is used, the virtual machine control structure is VMCS (Virtual Machine Control Structure); if AMD virtualization technology is used, the virtual machine control structure is VMCB (Virtual Machine Control Block). When the CPU core detects a timer interrupt, if the first-class physical timer on the CPU core is transparently transmitted to the virtual machine for use, and the clock source of the timer interrupt is a first-class physical timer, it is determined that the timer interrupt belongs to the timed task of the virtual machine, and the timed task of the virtual machine is processed, thereby improving the accuracy of virtual machine timer interrupt processing.

[0044] In an optional implementation, after determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer, it also includes: if the clock source is the second type of physical timer, judging whether the CPU core has timed out according to a preset physical timing variable; if the CPU core has timed out, processing the timing task of the CPU core.

[0045] Among them, the preset physical timing variable is used to record the timeout time of the CPU core timer when the virtual machine uses the transparent timer, and the physical timing variable can be per_cpu. When the CPU core detects a timing interrupt, it is determined whether a virtual machine is running on the CPU core and whether the virtual machine uses the transparent timer; if a virtual machine is running on the CPU core and the virtual machine uses the transparent timer, it is determined whether the clock source of the timing interrupt is a first-class physical timer or a second-class physical timer; if the clock source is a second-class physical timer, it is determined that the timing interrupt belongs to the timing task of the CPU core. In this case, the timing data of the CPU core is read from the physical timing variable, and combined with the timing data of the CPU core, it is determined whether the CPU core has timed out; if the CPU core has timed out, the timing task of the CPU core is processed; if the CPU core has not timed out, the interrupt processing can be exited.

[0046] When the CPU core detects a timed interrupt, if the first type of physical timer on the CPU core is transparently transmitted to the virtual machine for use, and the clock source of the timed interrupt is the second type of physical timer, it is determined that the timed interrupt belongs to the timed task of the CPU core. Combined with the physical timing variable, it is determined whether the CPU core has timed out. The CPU core's timed task is processed only when the CPU core has timed out. This can improve the accuracy of the CPU core timed interrupt processing, thereby avoiding abnormal deadlock of the host machine when the host machine has a timed task and improving the stability of the host machine.

[0047] The technical solution provided by the embodiment of the present disclosure is that when the CPU core detects a timer interrupt, if the first type of physical timer on the CPU core is transparently transmitted to the virtual machine for use, by judging whether the clock source of the timer interrupt is the first type of physical timer or the second type of physical timer, it is distinguished whether the timer interrupt belongs to the timed task of the virtual machine or the timed task of the CPU core, and the timed interrupt processing method is adjusted accordingly, which can improve the accuracy of the virtual machine's timed interrupt processing and, when the host machine has a timed task, can also improve the stability of the host machine.

[0048] In an optional implementation, the timing interrupt is processed according to the determination result of the virtual machine and the clock source of the timing interrupt, including: if the virtual machine is not running on the CPU core, determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer; if the clock source is the first type of physical timer, the CPU core times out and processes the timing task of the CPU core.

[0049] When the CPU core detects a timer interrupt, it determines whether a virtual machine is running on the CPU core. If no virtual machine is running on the CPU core, it determines whether the clock source of the timer interrupt is a first-class physical timer or a second-class physical timer. If the clock source is a first-class physical timer, it determines that the CPU core has timed out, that is, the timer interrupt belongs to the CPU core's timed task, and processes the CPU core's timed task. When the CPU core detects a timer interrupt, if there is no virtual machine on the CPU core and the clock source of the timer interrupt is a first-class physical timer, it determines that the CPU core has timed out and processes the CPU core's timed task, further improving the accuracy of the CPU core's timer interrupt processing.

[0050] In an optional implementation, after determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer, the method further includes: if the clock source is the second type of physical timer, exiting interrupt processing.

[0051] When the CPU core detects a timer interrupt, it determines whether a virtual machine is running on the CPU core. If no virtual machine is running on the CPU core, it determines whether the clock source of the timer interrupt is a first-class physical timer or a second-class physical timer. If the clock source is a second-class physical timer, the timer interrupt may belong to other CPU cores and does not need to be processed. The CPU core can exit the interrupt processing. The above processing can further reduce the abnormality of the CPU core's timer interrupt processing.

[0052] It should be noted that when the CPU core detects a timer interrupt, if a virtual machine is running on the CPU core, but the virtual machine does not use the transparent timer, that is, the CPU core uses its own first-class physical timer, and the virtual machine uses software simulation timing. In this case, it is determined whether the clock source of the timer interrupt is the first-class physical timer or the second-class physical timer; if the clock source is the first-class physical timer, the CPU core times out and the CPU core's timed task is processed; if the clock source is the second-class physical timer, no processing is required and the interrupt processing can be exited.

[0053] Figure 3 is a flowchart of another timer processing method provided according to an embodiment of the present disclosure. Figure 3 Based on the above embodiment, the writing of timing data is further limited. The timer processing method of this embodiment may include:

[0054] S301, when the virtual machine has a timing requirement, determining whether the virtual machine uses a transparent transmission timer;

[0055] S302, if the virtual machine uses a transparent timer, writing its own timing data into the first type of physical timer through the virtual machine;

[0056] S303, when the CPU core detects a timing interrupt, determining whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to indicate that the virtual machine directly accesses the first type of physical timer through the transparent transmission timer technology;

[0057] S304, processing the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt;

[0058] Among them, the relevant bits of the model-specific registers in the control domain of the virtual machine control structure are configured as follows: when the virtual machine reads and writes the register corresponding to the first type of physical timer in non-root mode, the non-root mode is maintained; the clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

[0059] When the virtual machine has a timing requirement on the CPU core, the KVM module determines whether the virtual machine uses the transparent timer, that is, whether the virtual machine uses the first type of physical timer on the CPU core; if the virtual machine uses the transparent timer, the virtual machine does not need to exit, and the virtual machine writes its own timing data to the first type of physical timer. By using the transparent timer, the virtual machine can write its own timing data to the first type of physical timer without the virtual machine exiting, reducing the number of virtual machine exits and thus reducing the overhead of the virtual machine.

[0060] In the disclosed embodiment, the relevant bits of the MSR (Model Specific Register) in the control domain of the virtual machine control structure can be set in advance so that when the virtual machine writes the timing data to the first type of physical timer, the virtual machine does not need to exit. Among them, the relevant bits of the MSR are used to set the access rights to the MSR, for example, it can be specified which MSRs can be read or written by the virtual machine, and which MSR accesses will cause the virtual machine to exit. In the case where the first type of physical timer is an APIC timer, the relevant bits of the MSR can be set so that the virtual machine does not need to exit when writing or reading the TMCCT (initial count register) and TMICT (current count register) registers of the APIC. If Intel virtualization technology is used, the virtual machine control structure is VMCS (Virtual Machine Control Structure); if AMD virtualization technology is used, the virtual machine control structure is VMCB (Virtual Machine Control Block).

[0061] The technical solution provided by the embodiment of the present disclosure is that when the virtual machine has a timing requirement, the virtual machine can write its own timing data into the first type of physical timer by using a transparent timer without the virtual machine exiting, thereby reducing the number of virtual machine exits and thus reducing the overhead of the virtual machine.

[0062] In an optional implementation, the above-mentioned timer processing method also includes: when the CPU core has a timing requirement, determining whether the virtual machine is running on the CPU core and whether the virtual machine uses a transparent timer to obtain a virtual machine determination result; if the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, the timing data of the CPU core is written into a preset physical timing variable.

[0063] When the CPU core has a timing requirement, determine whether a virtual machine is running on the CPU core. If a virtual machine is running, continue to determine whether the virtual machine uses a transparent transmission timer. If the virtual machine uses a timing transparent transmission timer, write the timing data of the CPU core into the preset physical timing variable. If there is no virtual machine on the CPU core, or the virtual machine does not use a transparent transmission timer, the CPU core writes its own timing data into the first type of physical timer. When the CPU core transparently transmits the first type of physical timer to the virtual machine for use, the CPU core can still take into account the timing tasks of the CPU core by writing its own timing data into the physical timing variable.

[0064] Figure 4 is a flowchart of another timer processing method provided according to an embodiment of the present disclosure. Figure 4Based on the above embodiment, the timer transparent transmission mode is further limited. The timer processing method of this embodiment may include:

[0065] S401, during the startup of the virtual machine, determining whether the virtual machine meets the transparent transmission condition of the timer transparent transmission mode;

[0066] S402, if the transparent transmission condition is met, controlling the virtual machine to use a transparent transmission timer through a kernel virtual machine module;

[0067] S403, when the CPU core detects a timing interrupt, determining whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to indicate that the virtual machine directly accesses the first type of physical timer through the transparent transmission timer technology;

[0068] S404, processing the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt;

[0069] The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

[0070] During the virtual machine startup process, it is determined whether the virtual machine meets the transparent transmission conditions of the timer transparent transmission mode. If the transparent transmission conditions are met, the virtual machine is controlled to use the transparent transmission timer through the kernel virtual machine module (KVM); otherwise, the virtual machine does not support timer transparent transmission and uses software simulation timing. During the virtual machine startup process, by determining whether the virtual machine meets the transparent transmission conditions, only virtual machines that meet the transparent transmission conditions can use the transparent transmission timer, that is, the transparent transmission timer is restricted accordingly, which can avoid timer anomalies or other potential problems caused by virtual machines that do not meet the transparent transmission conditions when trying to transparently access the timer.

[0071] In an optional embodiment, during the startup of the virtual machine, determining whether the virtual machine satisfies the transparent transmission conditions of the timer transparent transmission mode includes: during the startup of the virtual machine, determining whether the virtual machine working mode of the first type of physical timer corresponding to the virtual machine is the same as the host working mode of the first type of physical timer corresponding to the host machine; if the virtual machine working mode is the same as the host working mode, determining whether the virtual machine self-decrement frequency of the first type of physical timer corresponding to the virtual machine is the same as the host self-decrement frequency of the first type of physical timer corresponding to the host machine; if the virtual machine self-decrement frequency is the same as the host self-decrement frequency, determining that the virtual machine satisfies the transparent transmission conditions of the timer transparent transmission mode.

[0072] Among them, the decrement frequency is used to describe the speed or rate at which the internal counter of the timer decrements; the virtual machine decrement frequency refers to the count decrement rate set for the virtual machine, and the host decrement frequency refers to the count decrement rate set for the host. In the pre-host startup process, the host can specify the host working mode and host decrement frequency of its own first-class physical timer. During the virtual machine startup process, the set virtual machine working mode can be obtained, and it can be determined whether the virtual machine working mode is the same as the host working mode; if the working modes are different, the virtual machine does not meet the transparent transmission condition; if the working modes are the same, the set virtual machine decrement frequency can be obtained, and it can be determined whether the virtual machine decrement frequency is the same as the host decrement frequency; if the decrement frequencies are different, the virtual machine still does not meet the transparent transmission condition; if the decrement frequencies are the same, it is determined that the virtual machine meets the transparent transmission condition. By combining the virtual machine working mode, the host working mode, the virtual machine decrement frequency, and the host decrement frequency to determine whether the virtual machine meets the transparent transmission condition, the reliability of the timer transparent transmission is further improved.

[0073] In an optional implementation, the first type of physical timer is an advanced programmable interrupt controller, and the virtual machine operating mode is another operating mode except the timestamp cutoff mode.

[0074] When the first type of physical timer is an APIC timer, by shielding the timestamp deadline mode (TSCDeadline), the APIC timer is in a one-shot working mode or a periodic working mode, making the transparent timer technology applicable not only to Intel chips but also to AMD chips, further improving the scope of application of the transparent timer technology.

[0075] The technical solution provided by the embodiment of the present disclosure determines whether the virtual machine meets the transparent transmission conditions by combining the virtual machine working mode, the host working mode, the virtual machine self-decrease frequency, and the host self-decrease frequency during the virtual machine startup process. Only virtual machines that meet the transparent transmission conditions can use the transparent transmission timer, that is, the transparent transmission timer is restricted accordingly, which can avoid timer anomalies or other potential problems caused by virtual machines that do not meet the transparent transmission conditions when attempting to transparently access the timer.

[0076] In an optional implementation, during the startup of the virtual machine, determining whether the virtual machine working mode of the first type of physical timer corresponding to the virtual machine is the same as the host working mode of the first type of physical timer corresponding to the host machine, includes: during the startup of the virtual machine, executing a CPU identification instruction through the virtual machine; capturing the CPU identification instruction through the kernel virtual machine module, generating the return content of the CPU identification instruction, and masking the timestamp expiration mode from the return content; setting the virtual machine working mode of the first type of physical timer through the virtual machine, and the virtual machine exiting; detecting whether the virtual machine working mode is the same as the host working mode through the kernel virtual machine module; determining whether the virtual machine self-decrement frequency of the first type of physical timer corresponding to the virtual machine is the same as the host self-decrement frequency of the first type of physical timer corresponding to the host machine, includes: setting the virtual machine self-decrement frequency of the first type of physical timer through the virtual machine, and the virtual machine exiting; detecting whether the virtual machine self-decrement frequency is the same as the host self-decrement frequency through the kernel virtual machine module.

[0077] Exemplarily, during the virtual machine startup process, the virtual machine can execute the CPUID instruction (i.e., the CPU identification instruction) to obtain the timing register supported by the virtual machine system, triggering the virtual machine to exit, and the CPU control mode is switched to the host mode. The KVM module captures the CPUID instruction, generates the return content of the CPUID instruction, and shields the TSC Deadline mode from the return content, so that the virtual machine will not be in the TSC Deadline mode later, triggering the virtual machine to enter. After the virtual machine enters, the virtual machine can set the corresponding virtual machine working mode by setting the APIC_LVT register to trigger the virtual machine to exit. The KVM module determines whether the virtual machine working mode is consistent with the host working mode set in advance during the host startup process. If not, the virtual machine does not support timer transparent transmission; if consistent, the virtual machine supports timer transparent transmission. The virtual machine can set the virtual machine self-decrement frequency by setting the APIC_TDCR register to trigger the virtual machine to exit. The KVM module determines whether the virtual machine self-decrement frequency value is consistent with the pre-set host self-decrement frequency value. If not, the virtual machine does not support timer transparent transmission; if also consistent, the virtual machine supports timer transparent transmission. Through the above processing, it is possible to accurately determine whether the virtual machine meets the transparent transmission conditions.

[0078] It should be noted that in order to meet the transparent transmission conditions, if the host working mode is one-time mode, the KVM module only needs to shield the TSC Deadline mode from the return content of the CPUID instruction and set the virtual machine working mode to one-time mode. If the host working mode is periodic working mode, the KVM module shields both the TSC Deadline mode and the one-time mode from the return content of the CPUID instruction and sets the virtual machine working mode to periodic mode.

[0079] In an optional embodiment, controlling the virtual machine to use a transparent timer through a kernel virtual machine module includes: reading the initial count value and the current count value of the virtual machine through the kernel virtual machine module, and determining the remaining timing time of the virtual machine based on the read initial count value and the current count value, and writing the remaining timing time of the virtual machine into the first type of physical timer.

[0080] When the virtual machine meets the transparent transmission conditions, the KVM module can obtain the initial count value and current count value of the virtual machine from the variables of APIC_tmcct and APIC_tmict of the virtual machine, combine the two to calculate the remaining time of the virtual machine's timing, and write the remaining data of the virtual machine's timing into the TMCCT and TMICT registers of the APIC timer. By determining the remaining time of the virtual machine's timing and writing the remaining time of the virtual machine's timing into the first type of physical timer, the transparent transmission mechanism of the timer is realized.

[0081] In an optional embodiment, the method also includes: determining whether there are other virtual machines on the CPU core using the transparent timer; if no other virtual machines use the transparent timer, reading the values ​​of the initial count register and the current count register of the first type of physical timer through the kernel virtual machine module, and determining the remaining timing time of the CPU core based on the read initial count value and the current count value, and writing the remaining timing time of the CPU core into a preset physical timing variable; if other virtual machines use the transparent timer, the other virtual machines exit, and read the values ​​of the initial count register and the current count register of the first type of physical timer through the kernel virtual machine module, and determining the remaining timing time of the other virtual machines based on the read initial count value and the current count value, and simulating other timers based on the remaining timing time of the other virtual machines.

[0082] When the virtual machine meets the transparent transmission conditions, controlling the virtual machine to use the transparent transmission timer through the kernel virtual machine module also includes: the KVM module determines whether there are other virtual machines running on the CPU core, that is, whether the first type of physical timer on the CPU core has been transparently transmitted to other virtual machines for use. If it has not been transparently transmitted to other virtual machines for use, the KVM module also reads the values ​​of the initial count register (TMICT) and the current count register (TMCCT) of the first type of physical timer to obtain the initial count value and the current count value, determines the remaining time of the CPU core timing according to the read initial count value and the current count value, and writes the remaining time of the CPU core timing into the pre-set physical timing variable per_cpu. If it has been transparently transmitted to other virtual machines for use, then before the remaining time of the virtual machine's timing is written into the first type of physical timer, the other virtual machines need to give up the first type of physical timer, that is, trigger the other virtual machines to exit; accordingly, the values ​​of the initial count register (TMICT) and the current count register (TMCCT) of the first type of physical timer are read through the KVM module to obtain the initial count value and the current count value, and the remaining time of the timing of the other virtual machines is determined according to the read initial count value and the current count value, and other timers are simulated according to the remaining time of the timing of the other virtual machines, for example, using the kernel HRtimer to simulate other virtual machine timers. Through the above processing, while the first type of physical timer on the CPU core is transparently transmitted to the first virtual machine, it can also support the timing processing of the CPU core and the second virtual machine, thereby avoiding various deadlock exceptions of the host machine and further improving the stability of the host machine.

[0083] It should be noted that after the APIC timer is transparently transmitted to the first virtual machine for use, if other interrupts occur on the CPUS core, or the first virtual machine is preempted by other tasks, causing the first virtual machine to exit, the KVM module reads the values ​​of the initial count register (TMICT) and the current count register (TMCCT) of the APIC timer, determines the remaining timing time of the first virtual machine based on the read initial count value and the current count value, and simulates the timer of the first virtual machine based on the remaining timing time of the first virtual machine, for example, starting HRtimer to simulate the timer of the first virtual machine; and, reads the timer time of the CPU core from the physical timing variable per-cpu variable, and writes it into the TMICT and TMCCT registers of the APIC timer.

[0084] In summary, the problem to be solved by the embodiments of the present disclosure is that the overhead of setting a timer for a virtual machine in a virtualized scenario is too high. By using timer transparent transmission, the virtual machine exit triggered by writing registers during the timer setting process can be significantly reduced, and the virtualization overhead caused by the virtual machine exit caused by writing registers can be reduced, which can significantly improve the performance of the virtual machine. In addition, we use the Redis performance test tool and the network performance test tool based on the socket API (Application Programming Interface) to test the solution without and with the solution, and the test results are as follows:

[0085] 1. Redis performance test:

[0086] First results Second result average Do not use this solution 9.43s 9.48s 9.46s Use this solution 8.42s 8.44s 8.43s

[0087] 2. Message transmission test:

[0088] Run time Send a message Receiving Messages Average latency Do not use this solution 1s 104322 104321 4.746 Use this solution 1s 153136 153135 3.252

[0089] The above test results show that the use of this technical solution improves Redis performance by about 12.21%, and reduces Socket message delay by about 31.48%. Therefore, this technical solution can significantly improve the performance of machine processing related tasks.

[0090] Figure 5 1 is a schematic diagram of a timer processing device according to an embodiment of the present disclosure. The device is suitable for transparently transmitting the first type of physical timer to a virtual machine for use. The device can be implemented in software and / or hardware and can be integrated into an electronic device. Figure 5 As shown, the timer processing device 500 of this embodiment may include:

[0091] The virtual machine result determination module 510 is used to determine whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer when the CPU core detects a timing interrupt, and obtain a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to indicate that the virtual machine directly accesses the first type of physical timer through the transparent transmission timer technology;

[0092] A timer interrupt processing module 520, configured to process the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt;

[0093] The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

[0094] In an optional implementation, the timer interrupt processing module 520 includes a first timer interrupt submodule, and the first timer interrupt submodule is specifically used to:

[0095] If the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer;

[0096] If the clock source is the first type of physical timer, the virtual machine times out and an interrupt is injected into the virtual machine control structure of the virtual machine through the kernel virtual machine module;

[0097] The virtual machine processes the timed tasks of the virtual machine in response to the timed interrupt information of the virtual machine control structure.

[0098] In an optional implementation manner, the first timing interrupt submodule is further used for:

[0099] If the clock source is the second type of physical timer, determining whether the CPU core has timed out according to a preset physical timing variable;

[0100] If the CPU core times out, the scheduled task of the CPU core is processed.

[0101] In an optional implementation, the timer interrupt processing module 520 includes a second timer interrupt submodule, and the second timer interrupt submodule is specifically used to:

[0102] If the virtual machine is not running on the CPU core, determining whether the clock source of the timer interrupt is the first type of physical timer or the second type of physical timer;

[0103] If the clock source is the first type of physical timer, the CPU core times out and processes the timing task of the CPU core.

[0104] In an optional implementation manner, the second timing interrupt submodule is further used for:

[0105] If the clock source is the second-type physical timer, then exit the interrupt processing.

[0106] In an optional implementation, the timer processing device 500 further includes a virtual timing writing module, and the virtual timing writing module is specifically used to:

[0107] In the case where the virtual machine has a timing requirement, determining whether the virtual machine uses a transparent transmission timer;

[0108] If the virtual machine uses a transparent timer, the virtual machine writes its own timing data into the first type of physical timer;

[0109] The configuration of the relevant bits of the model-specific register in the control field of the virtual machine control structure is: when the virtual machine reads and writes the register corresponding to the first type of physical timer in the non-root mode, the non-root mode is maintained.

[0110] In an optional implementation manner, the timer processing device 500 further includes a core timing writing module, and the core timing writing module is specifically used to:

[0111] In the case where the CPU core has a timing requirement, determining whether the virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result;

[0112] If the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, the timing data of the CPU core is written into a preset physical timing variable.

[0113] In an optional implementation, the timer processing device 500 further includes a virtual machine startup module, and the virtual machine startup module includes:

[0114] A transparent transmission condition determination submodule, used to determine whether the virtual machine meets the transparent transmission condition of the timer transparent transmission mode during the startup of the virtual machine;

[0115] The virtual transparent transmission submodule is used to control the virtual machine to use the transparent transmission timer through the kernel virtual machine module if the transparent transmission condition is met.

[0116] In an optional implementation, the transparent transmission condition determination submodule includes:

[0117] A working mode determining unit, used to determine, during the startup of the virtual machine, whether the virtual machine working mode of the first type of physical timer corresponding to the virtual machine is the same as the host working mode of the first type of physical timer corresponding to the host machine;

[0118] A self-decrement frequency determination unit, configured to determine whether the virtual machine self-decrement frequency of the first type of physical timer corresponding to the virtual machine is the same as the host self-decrement frequency of the first type of physical timer corresponding to the host machine if the virtual machine working mode is the same as the host working mode;

[0119] The transparent transmission condition determination unit is used to determine that the virtual machine meets the transparent transmission condition of the timer transparent transmission mode if the virtual machine self-decrease frequency is the same as the host self-decrease frequency.

[0120] In an optional implementation manner, the working mode determination unit is specifically configured to:

[0121] During the startup of the virtual machine, executing a CPU identification instruction through the virtual machine;

[0122] The CPU identification instruction is captured by a kernel virtual machine module, a return content of the CPU identification instruction is generated, and a timestamp cutoff mode is masked from the return content;

[0123] Setting the virtual machine working mode of the first type of physical timer through the virtual machine, and the virtual machine exits;

[0124] Detecting whether the virtual machine working mode is the same as the host working mode through the kernel virtual machine module;

[0125] The transparent transmission condition determination unit is specifically used for:

[0126] Setting the virtual machine self-decrement frequency of the first type of physical timer by the virtual machine, and the virtual machine exits;

[0127] The kernel virtual machine module is used to detect whether the virtual machine self-decrement frequency is the same as the host self-decrement frequency.

[0128] In an optional implementation, the first type of physical timer is an advanced programmable interrupt controller, and the virtual machine operating mode is another operating mode except the timestamp cutoff mode.

[0129] In an optional implementation manner, the virtual transparent transmission submodule is specifically used for:

[0130] The initial count value and the current count value of the virtual machine are read through the kernel virtual machine module, and the remaining time of the timing of the virtual machine is determined according to the read initial count value and the current count value, and the remaining time of the timing of the virtual machine is written into the first type of physical timer.

[0131] In an optional implementation manner, the virtual transparent transmission submodule is further used for:

[0132] Determine whether there are other virtual machines on the CPU core that use a transparent transmission timer;

[0133] If no other virtual machine uses the transparent timer, the values ​​of the initial count register and the current count register of the first type of physical timer are read through the kernel virtual machine module, and the remaining time of the timing of the CPU core is determined according to the read initial count value and the current count value, and the remaining time of the timing of the CPU core is written into the preset physical timing variable;

[0134] If other virtual machines use the transparent timer, the other virtual machines exit, and the values ​​of the initial count register and the current count register of the first type of physical timer are read through the kernel virtual machine module, and the remaining timing time of the other virtual machines is determined based on the read initial count value and current count value, and other timers are simulated based on the remaining timing time of the other virtual machines.

[0135] In an optional implementation, the second type of physical timer is a high-precision event timer.

[0136] The timer processing device provided in the embodiment of the present invention can execute the timer processing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0137] In the technical solution disclosed herein, the acquisition, storage and application of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0138] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0139] Figure 6 The block diagram is a block diagram of an electronic device for implementing the timer processing method according to an embodiment of the present disclosure. Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0140] like Figure 6 As shown, the electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 can also be stored. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0141] Multiple components in the electronic device 600 are connected to the I / O interface 605, including: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a disk, an optical disk, etc.; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the electronic device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0142] The computing unit 601 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), an image processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 601 performs the various methods and processes described above, such as a timer processing method. For example, in some embodiments, the timer processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the timer processing method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the timer processing method in any other appropriate manner (e.g., by means of firmware).

[0143] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0144] like Figure 6As shown, the electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 can also be stored. The computing unit 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0145] Multiple components in the electronic device 600 are connected to the I / O interface 605, including: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a disk, an optical disk, etc.; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the electronic device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0146] The computing unit 601 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), an image processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 601 performs the various methods and processes described above, such as a timer processing method. For example, in some embodiments, the timer processing method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the timer processing method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the timer processing method in any other appropriate manner (e.g., by means of firmware).

[0147] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0148] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0149] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0150] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, audio input, or tactile input).

[0151] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web player through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0152] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0153] Artificial intelligence is a discipline that studies how to use computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, planning, etc.). It includes both hardware-level and software-level technologies. Artificial intelligence hardware technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, and big data processing; artificial intelligence software technologies mainly include computer vision technology, audio recognition technology, natural language processing technology, machine learning / deep learning technology, big data processing technology, knowledge graph technology, and other major directions.

[0154] Cloud computing refers to a technology system that uses network access to elastically scalable shared physical or virtual resource pools. Resources can include servers, operating systems, networks, software, applications, and storage devices, and can be deployed and managed on demand and in a self-service manner. Cloud computing technology can provide efficient and powerful data processing capabilities for technical applications such as artificial intelligence and blockchain, as well as model training.

[0155] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0156] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A timer processing method, comprising: In the case where the CPU core detects a timing interrupt, determining whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to characterize that the virtual machine directly accesses a first type of physical timer through a transparent transmission timer technology; Processing the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt; The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

2. The method according to claim 1, wherein: The processing of the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt includes: If the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer; If the clock source is the first type of physical timer, the virtual machine times out and an interrupt is injected into the virtual machine control structure of the virtual machine through the kernel virtual machine module; The virtual machine processes the timed tasks of the virtual machine in response to the timed interrupt information of the virtual machine control structure.

3. The method according to claim 2, after determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer, further comprises: If the clock source is the second type of physical timer, determining whether the CPU core has timed out according to a preset physical timing variable; If the CPU core times out, the scheduled task of the CPU core is processed.

4. The method according to claim 1, wherein: The processing of the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt includes: If the virtual machine is not running on the CPU core, determining whether the clock source of the timer interrupt is the first type of physical timer or the second type of physical timer; If the clock source is the first type of physical timer, the CPU core times out and processes the timing task of the CPU core.

5. The method according to claim 4, after determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer, further comprises: If the clock source is the second-type physical timer, then exit the interrupt processing.

6. The method according to claim 1, further comprising: In the case where the virtual machine has a timing requirement, determining whether the virtual machine uses a transparent transmission timer; If the virtual machine uses a transparent timer, the virtual machine writes its own timing data into the first type of physical timer; The configuration of the relevant bits of the model-specific register in the control field of the virtual machine control structure is: when the virtual machine reads and writes the register corresponding to the first type of physical timer in the non-root mode, the non-root mode is maintained.

7. The method according to claim 1, further comprising: In the case where the CPU core has a timing requirement, determining whether the virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; If the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, the timing data of the CPU core is written into a preset physical timing variable.

8. The method according to any one of claims 1 to 7, further comprising: During the startup of the virtual machine, determining whether the virtual machine meets the transparent transmission condition of the timer transparent transmission mode; If the transparent transmission condition is met, the virtual machine is controlled to use the transparent transmission timer through the kernel virtual machine module.

9. The method according to claim 8, wherein: The step of determining whether the virtual machine satisfies a transparent transmission condition of a timer transparent transmission mode during the startup of the virtual machine includes: During the startup of the virtual machine, determining whether the virtual machine working mode of the first type of physical timer corresponding to the virtual machine is the same as the host working mode of the first type of physical timer corresponding to the host machine; If the virtual machine working mode is the same as the host working mode, determining whether the virtual machine self-decrement frequency of the first type of physical timer corresponding to the virtual machine is the same as the host self-decrement frequency of the first type of physical timer corresponding to the host machine; If the virtual machine self-decrement frequency is the same as the host self-decrement frequency, it is determined that the virtual machine meets the transparent transmission condition of the timer transparent transmission mode.

10. The method according to claim 9, wherein: The determining, during the startup of the virtual machine, whether the virtual machine working mode of the first type of physical timer corresponding to the virtual machine is the same as the host working mode of the first type of physical timer corresponding to the host machine comprises: During the startup of the virtual machine, executing a CPU identification instruction through the virtual machine; The CPU identification instruction is captured by a kernel virtual machine module, a return content of the CPU identification instruction is generated, and a timestamp cutoff mode is masked from the return content; Setting the virtual machine working mode of the first type of physical timer through the virtual machine, and the virtual machine exits; Detecting whether the virtual machine working mode is the same as the host working mode through the kernel virtual machine module; The determining whether the virtual machine self-decrement frequency of the first type of physical timer corresponding to the virtual machine is the same as the host self-decrement frequency of the first type of physical timer corresponding to the host machine includes: Setting the virtual machine self-decrement frequency of the first type of physical timer by the virtual machine, and the virtual machine exits; The kernel virtual machine module is used to detect whether the virtual machine self-decrement frequency is the same as the host self-decrement frequency.

11. The method according to claim 9, wherein: The first type of physical timer is an advanced programmable interrupt controller, and the virtual machine working mode is other working modes except the timestamp cut-off mode.

12. The method according to claim 8, wherein: The controlling the virtual machine to use a transparent transmission timer through a kernel virtual machine module includes: The initial count value and the current count value of the virtual machine are read through the kernel virtual machine module, and the remaining time of the timing of the virtual machine is determined according to the read initial count value and the current count value, and the remaining time of the timing of the virtual machine is written into the first type of physical timer.

13. The method according to claim 12, further comprising: Determine whether there are other virtual machines on the CPU core that use a transparent transmission timer; If no other virtual machine uses the transparent timer, the values ​​of the initial count register and the current count register of the first type of physical timer are read through the kernel virtual machine module, and the remaining time of the timing of the CPU core is determined according to the read initial count value and the current count value, and the remaining time of the timing of the CPU core is written into the preset physical timing variable; If other virtual machines use the transparent timer, the other virtual machines exit, and the values ​​of the initial count register and the current count register of the first type of physical timer are read through the kernel virtual machine module, and the remaining timing time of the other virtual machines is determined based on the read initial count value and current count value, and other timers are simulated based on the remaining timing time of the other virtual machines.

14. The method according to claim 1, wherein: The second type of physical timer is a high-precision event timer.

15. A timer processing device, comprising: A virtual machine result determination module is used to determine whether a virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer when the CPU core detects a timing interrupt, and obtain a virtual machine determination result; wherein the virtual machine uses a transparent transmission timer to indicate that the virtual machine directly accesses the first type of physical timer through the transparent transmission timer technology; A timer interrupt processing module, used for processing the timer interrupt according to the virtual machine determination result and the clock source of the timer interrupt; The clock source is the first type of physical timer or the second type of physical timer, and the second type of physical timer is configured to broadcast a timing interrupt to each CPU core in the host machine.

16. The device according to claim 15, wherein: The timer interrupt processing module includes a first timer interrupt submodule, and the first timer interrupt submodule is specifically used for: If the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, determining whether the clock source of the timing interrupt is the first type of physical timer or the second type of physical timer; If the clock source is the first type of physical timer, the virtual machine times out and an interrupt is injected into the virtual machine control structure of the virtual machine through the kernel virtual machine module; The virtual machine processes the timed tasks of the virtual machine in response to the timed interrupt information of the virtual machine control structure.

17. The device according to claim 16, wherein the first timing interruption submodule is further configured to: If the clock source is the second type of physical timer, determining whether the CPU core has timed out according to a preset physical timing variable; If the CPU core times out, the scheduled task of the CPU core is processed.

18. The device according to claim 15, wherein: The timer interrupt processing module includes a second timer interrupt submodule, and the second timer interrupt submodule is specifically used for: If the virtual machine is not running on the CPU core, determining whether the clock source of the timer interrupt is the first type of physical timer or the second type of physical timer; If the clock source is the first type of physical timer, the CPU core times out and processes the timing task of the CPU core.

19. The device according to claim 18, wherein the second timing interruption submodule is further configured to: If the clock source is the second-type physical timer, then exit the interrupt processing.

20. The device according to claim 15, further comprising a virtual timing writing module, wherein the virtual timing writing module is specifically configured to: In the case where the virtual machine has a timing requirement, determining whether the virtual machine uses a transparent transmission timer; If the virtual machine uses a transparent timer, the virtual machine writes its own timing data into the first type of physical timer; in, The configuration of the relevant bits of the model specific register in the control field of the virtual machine control structure is: when the virtual machine reads and writes the register corresponding to the first type of physical timer in the non-root mode, the non-root mode is maintained.

21. The device according to claim 15, further comprising a core timing writing module, wherein the core timing writing module is specifically configured to: In the case where the CPU core has a timing requirement, determining whether the virtual machine is running on the CPU core and whether the virtual machine uses a transparent transmission timer, and obtaining a virtual machine determination result; If the virtual machine is running on the CPU core and the virtual machine uses a transparent timer, the timing data of the CPU core is written into a preset physical timing variable.

22. The device according to any one of claims 15 to 21, further comprising a virtual machine startup module, wherein the virtual machine startup module comprises: A transparent transmission condition determination submodule, used to determine whether the virtual machine meets the transparent transmission condition of the timer transparent transmission mode during the startup of the virtual machine; The virtual transparent transmission submodule is used to control the virtual machine to use the transparent transmission timer through the kernel virtual machine module if the transparent transmission condition is met.

23. The device according to claim 22, wherein: The transparent transmission condition determination submodule includes: A working mode determining unit, used to determine, during the startup of the virtual machine, whether the virtual machine working mode of the first type of physical timer corresponding to the virtual machine is the same as the host working mode of the first type of physical timer corresponding to the host machine; A self-decrement frequency determination unit, configured to determine whether the virtual machine self-decrement frequency of the first type of physical timer corresponding to the virtual machine is the same as the host self-decrement frequency of the first type of physical timer corresponding to the host machine if the virtual machine working mode is the same as the host working mode; The transparent transmission condition determination unit is used to determine that the virtual machine meets the transparent transmission condition of the timer transparent transmission mode if the virtual machine self-decrease frequency is the same as the host self-decrease frequency.

24. The device according to claim 23, wherein: The working mode determination unit is specifically used for: During the startup of the virtual machine, executing a CPU identification instruction through the virtual machine; The CPU identification instruction is captured by a kernel virtual machine module, a return content of the CPU identification instruction is generated, and a timestamp cutoff mode is masked from the return content; Setting the virtual machine working mode of the first type of physical timer through the virtual machine, and the virtual machine exits; Detecting whether the virtual machine working mode is the same as the host working mode through the kernel virtual machine module; The transparent transmission condition determination unit is specifically used for: Setting the virtual machine self-decrement frequency of the first type of physical timer by the virtual machine, and the virtual machine exits; The kernel virtual machine module is used to detect whether the virtual machine self-decrement frequency is the same as the host self-decrement frequency.

25. The device according to claim 23, wherein The first type of physical timer is an advanced programmable interrupt controller, and the virtual machine working mode is other working modes except the timestamp cut-off mode.

26. The device according to claim 22, wherein: The virtual transparent transmission submodule is specifically used for: The initial count value and the current count value of the virtual machine are read through the kernel virtual machine module, and the remaining time of the timing of the virtual machine is determined according to the read initial count value and the current count value, and the remaining time of the timing of the virtual machine is written into the first type of physical timer.

27. The device according to claim 26, wherein the virtual transparent transmission submodule is further used for: Determine whether there are other virtual machines on the CPU core that use a transparent transmission timer; If no other virtual machine uses the transparent timer, the values ​​of the initial count register and the current count register of the first type of physical timer are read through the kernel virtual machine module, and the remaining time of the timing of the CPU core is determined according to the read initial count value and the current count value, and the remaining time of the timing of the CPU core is written into the preset physical timing variable; If other virtual machines use the transparent timer, the other virtual machines exit, and the values ​​of the initial count register and the current count register of the first type of physical timer are read through the kernel virtual machine module, and the remaining timing time of the other virtual machines is determined based on the read initial count value and current count value, and other timers are simulated based on the remaining timing time of the other virtual machines.

28. The device according to claim 15, wherein: The second type of physical timer is a high-precision event timer.

29. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 14.

30. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to make a computer execute the method according to any one of claims 1-14.

31. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 14.

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