Heterogeneous redundant firmware starting circuit and method

Abstract

The invention discloses a heterogeneous redundant firmware starting circuit which comprises a single-chip microcomputer MCU, a CPU, a FLASH memory, an SD card memory, a single-chip microcomputer MCU power supply and a CPU power supply. An IO [2: 0] interface of the single-chip microcomputer MCU is connected with an SECFG [2: 0] interface of the CPU, the single-chip microcomputer MCU is connected with the CPU power supply, the CPU power supply is connected with the CPU, the CPU is connected with the FLASH memory through a QSPI interface, the CPU is connected with the SD card memory through an SDIO interface, and the CPU power supply is connected with the single-chip microcomputer MCU. The invention further discloses a heterogeneous redundant firmware starting method. The problem that the CPU board card cannot be started due to the fault of a single firmware circuit or the common fault of a redundant firmware circuit is solved.

Description

Technical Field

[0001] The invention relates to a heterogeneous redundant firmware startup circuit and method. Background Art

[0002] The CPU (central processing unit) board cannot load firmware after power-on, which will cause the entire system to not work properly.

[0003] In the existing technical solutions, the two patents CN115562904A and CN115934427A are both based on the SPI interface FLASH redundant firmware startup circuit, which has a certain reliability. However, in some scenarios that require high reliability operation, the invention cannot avoid common cause failures of the SPI interface circuit or FLASH.

[0004] The redundant firmware switching method with patent number CN112732486A is aimed at the redundancy of a software processing flow at the firmware level, and cannot solve the problem of a single firmware circuit failure that prevents startup.

[0005] Therefore, a heterogeneous redundant firmware startup circuit and method are provided. Summary of the invention

[0006] The purpose of the present invention is to overcome the existing defects and provide a heterogeneous redundant firmware startup circuit and method, which solves the problem that the CPU board cannot be started due to a single firmware circuit failure or a common cause failure of the redundant firmware circuit.

[0007] The technical solution to achieve the above purpose is:

[0008] A heterogeneous redundant firmware startup circuit, comprising: a single-chip microcomputer MCU, a CPU, a FLASH memory, an SD card memory, a single-chip microcomputer MCU power supply and a CPU power supply;

[0009] The IO[2:0] interface of the single-chip microcomputer MCU is interconnected with the SE_CFG[2:0] interface of the CPU, the single-chip microcomputer MCU is connected to the CPU power supply, the CPU power supply is connected to the CPU, the CPU is connected to the FLASH memory through a QSPI (short for Quad SPI, indicating 6-wire spi) interface, the CPU is connected to the SD card memory through an SDIO (secure digital input and output) interface, and the CPU power supply is connected to the single-chip microcomputer MCU.

[0010] Preferably, the configuration of the SE_CFG[2:0] interface includes: “000”, “001”, “010”, “011”, “100”, “101”, “110” and “111”.

[0011] Preferably, the single-chip microcomputer MCU is interconnected with the SE_CFG[2:0] interface of the CPU via the IO[2:0] interface, and the SE_CFG[2:0] interface is configured, and the initial configuration defaults to "001", that is, the CPU reads the firmware of the FLASH memory via the QSPI interface to start by default.

[0012] Preferably, if the CPU initially defaults to reading the firmware of the FLASH memory through the QSPI interface for startup and the startup fails, the SE_CFG[2:0] interface is reconfigured to "100", that is, the CPU reads the firmware of the SD card memory through the SDIO interface for startup.

[0013] Preferably, the single-chip microcomputer MCU controls the CPU power supply to power on and start the CPU.

[0014] Preferably, the single-chip microcomputer MCU power supply is used to provide power to the single-chip microcomputer MCU.

[0015] A second method for starting heterogeneous redundant firmware includes:

[0016] Step S1, the IO[2:0] interface of the single-chip microcomputer MCU is interconnected with the SE_CFG[2:0] interface of the CPU, and the SE_CFG[2:0] interface is configured, and the initial configuration defaults to "001";

[0017] Step S2, the single-chip microcomputer MCU controls the CPU power supply through the power control signal to power on the CPU;

[0018] Step S3, the CPU reads the firmware of the FLASH memory through the QSPI interface to start;

[0019] Step S4, if the CPU is successfully started, the CPU sends a feedback signal to the single-chip microcomputer MCU;

[0020] Step S5, if the CPU fails to start and the single-chip microcomputer MCU does not receive a feedback signal within a certain preset time, the single-chip microcomputer MCU controls the CPU power supply to cut off the power of the CPU;

[0021] Step S6, after power off, reconfigure the SE_CFG[2:0] interface to "100";

[0022] Step S7, the single-chip microcomputer MCU controls the CPU power supply through a power control signal to power on and start the CPU;

[0023] Step S8: The CPU reads the firmware of the SD card memory through the SDIO interface to start.

[0024] The beneficial effects of the present invention are as follows: based on the firmware startup configuration pins of the domestic Feiteng CPU, the present invention designs two sets of independent heterogeneous firmware startup circuits; the firmware startup circuit is configured with hardware-level redundancy to improve availability; the firmware startup circuit has an independent physical interface and conforms to the differentiated design, effectively avoiding the risks brought by common cause failures and improving reliability; the problem that the FLASH firmware startup circuit of the traditional SPI interface cannot be reliably started due to failure is solved, the robustness of the system is enhanced, and the reliability of the operation of the entire system is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a module diagram of a heterogeneous redundant firmware startup circuit of the present invention;

[0026] Figure 2 The present invention is a flowchart of a heterogeneous redundant firmware startup method.

[0027] In the figure: 1. MCU; 2. CPU; 3. FLASH memory; 4. SD card memory; 5. MCU power supply; 6. CPU power supply. DETAILED DESCRIPTION

[0028] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0029] The present invention will be further described below in conjunction with the accompanying drawings.

[0030] The present invention makes full use of the diversity of the startup configuration interface of the domestic Feiteng CPU to provide a redundant heterogeneous firmware startup circuit, and the circuit is implemented as follows:

[0031] like Figure 1As shown, a heterogeneous redundant firmware startup circuit includes: a single-chip microcomputer MCU 1, a CPU 2, a FLASH memory 3, an SD card memory 4, a single-chip microcomputer MCU power supply 5 and a CPU power supply 6; the IO[2:0] interface of the single-chip microcomputer MCU 1 is interconnected with the SE_CFG[2:0] interface of the CPU 2, the single-chip microcomputer MCU 1 is connected to the CPU power supply 6, the CPU power supply 6 is connected to the CPU 2, the CPU 2 is connected to the FLASH memory 3 through the QSPI interface, the CPU 2 is connected to the SD card memory 4 through the SDIO interface, and the CPU power supply 6 is connected to the single-chip microcomputer MCU1.

[0032] In an embodiment, the configuration of the SE_CFG[2:0] interface includes: “000”, “001”, “010”, “011”, “100”, “101”, “110” and “111”.

[0033] Among them, 000: reserved by the CPU design manufacturer, not open to users for the time being; 001: initial configuration; 010: LocalBus (bus principle), a universal computer communication parallel bus, which can connect devices with this bus interface; 011: non-volatile storage device with NAND (flash memory) technology; 100: the first SD card interface of the CPU, connected to the SD card storage device; 101: similar to 100, the second SD card interface of the CPU, connected to the SD card storage device; 110: the first SD interface of the CPU, connected to the eMMC (embedded multimedia card) storage device; 111: the same as "000"; the configuration description is shown in Table 1 below:

[0034]

[0035]

[0036] Table 1

[0037] In the embodiment, the single-chip microcomputer MCU 1 is interconnected with the SE_CFG[2:0] interface of the CPU 2 through the IO[2:0] interface, and the SE_CFG[2:0] interface is configured. The initial configuration defaults to "001", that is, the default CPU 2 reads the firmware of the FLASH memory 3 through the QSPI interface to start.

[0038] In the embodiment, if the initial default CPU 2 reads the firmware of the FLASH memory 3 through the QSPI interface to start up, and the startup fails, the SE_CFG[2:0] interface is reconfigured to "100", that is, the CPU 2 reads the firmware of the SD card memory 4 through the SDIO interface to start up.

[0039] In the embodiment, the single chip microcomputer MCU 1 controls the CPU power supply 6 to power on the CPU 2 and start it.

[0040] In the embodiment, the single-chip microcomputer MCU power supply 5 is used to provide power to the single-chip microcomputer MCU 1 .

[0041] like Figure 2 As shown, a heterogeneous redundant firmware startup method includes:

[0042] Step S1, the IO[2:0] interface of the microcontroller MCU 1 is interconnected with the SE_CFG[2:0] interface of the CPU 2, and the SE_CFG[2:0] interface is configured, and the initial configuration defaults to "001";

[0043] Step S2, the single chip microcomputer MCU 1 controls the CPU power supply 6 through the power control signal to power on the CPU 2;

[0044] Step S3, CPU 2 reads the firmware of FLASH memory 3 through QSPI interface to start;

[0045] Step S4, if the CPU 2 is successfully started, the CPU 2 sends a feedback signal to the microcontroller MCU 1;

[0046] Step S5, if the CPU 2 fails to start and the single-chip microcomputer MCU 1 does not receive a feedback signal within a certain preset time, the single-chip microcomputer MCU 1 controls the CPU power supply 6 to power off the CPU 2;

[0047] Step S6, after power off, reconfigure the SE_CFG[2:0] interface to "100";

[0048] Step S7, the single chip microcomputer MCU 1 controls the CPU power supply 6 through the power control signal to power on the CPU 2;

[0049] Step S8, the CPU 2 reads the firmware of the SD card memory 4 through the SDIO interface to start.

[0050] The firmware startup circuit has an independent physical interface and conforms to the differentiated design, which effectively avoids the risks brought by common cause failures and improves reliability; it solves the problem that the FLASH firmware startup circuit of the traditional SPI interface cannot be reliably started due to failure.

[0051] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments may still be modified, or some or all of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A heterogeneous redundant firmware startup circuit, characterized in that: include: Single-chip microcomputer MCU (1), CPU (2), FLASH memory (3), SD card memory (4), single-chip microcomputer MCU power supply (5) and CPU power supply (6); The IO[2:0] interface of the single-chip microcomputer MCU (1) is interconnected with the SE_CFG[2:0] interface of the CPU (2); the single-chip microcomputer MCU (1) is connected to the CPU power supply (6); the CPU power supply (6) is connected to the CPU (2); the CPU (2) is connected to the FLASH memory (3) via a QSPI interface; the CPU (2) is connected to the SD card memory (4) via an SDIO interface; and the CPU power supply (6) is connected to the single-chip microcomputer MCU (1).

2. A heterogeneous redundant firmware startup circuit according to claim 1, characterized in that: The configurations of the SE_CFG[2:0] interface include: "000", "001", "010", "011", "100", "101", "110" and "111".

3. A heterogeneous redundant firmware startup circuit according to claim 2, characterized in that: The single-chip microcomputer MCU (1) is interconnected with the SE_CFG[2:0] interface of the CPU (2) via the IO[2:0] interface, and the SE_CFG[2:0] interface is configured. The initial configuration defaults to "001", that is, the CPU (2) defaults to reading the firmware of the FLASH memory (3) via the QSPI interface for startup.

4. A heterogeneous redundant firmware startup circuit according to claim 3, characterized in that: If the CPU (2) is initially defaulted to read the firmware of the FLASH memory (3) through the QSPI interface for startup, and the startup fails, the SE_CFG[2:0] interface is reconfigured to "100", that is, the CPU (2) reads the firmware of the SD card memory (4) through the SDIO interface for startup.

5. The heterogeneous redundant firmware startup circuit according to claim 1, characterized in that: The single chip computer MCU (1) controls the CPU power supply (6) to power on and start the CPU (2).

6. The heterogeneous redundant firmware startup circuit according to claim 1, characterized in that: The single-chip microcomputer MCU power supply (5) is used to provide power to the single-chip microcomputer MCU (1).

7. A method for starting heterogeneous redundant firmware, characterized in that: include: Step S1, interconnecting the IO[2:0] interface of the single-chip microcomputer MCU (1) with the SE_CFG[2:0] interface of the CPU (2), configuring the SE_CFG[2:0] interface, with the initial configuration defaulting to "001"; Step S2, the single chip microcomputer MCU (1) controls the CPU power supply (6) through a power supply control signal to power on the CPU (2); Step S3, the CPU (2) reads the firmware of the FLASH memory (3) through the QSPI interface to start; Step S4, if the CPU (2) is successfully started, the CPU (2) sends a feedback signal to the single-chip microcomputer MCU (1); Step S5, if the CPU (2) fails to start and the single-chip microcomputer MCU (1) does not receive a feedback signal within a certain preset time, the single-chip microcomputer MCU (1) controls the CPU power supply (6) to cut off the power of the CPU (2); Step S6, after power off, reconfigure the SE_CFG[2:0] interface to "100"; Step S7, the single chip computer MCU (1) controls the CPU power supply (6) through a power control signal to power on and start the CPU (2); Step S8, the CPU (2) reads the firmware of the SD card memory (4) through the SDIO interface to start.

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