Automatic testing method and system based on artificial intelligence

Abstract

The invention relates to the technical field of automatic testing, in particular to an automatic testing method and system based on artificial intelligence, and the method comprises the steps: collecting to-be-tested data of a to-be-tested system connected with a plurality of to-be-tested interfaces; through the signal conditioning module and the filtering gating module, performance indexes such as the signal-to-noise ratio, the spurious-free dynamic range and the common-mode rejection ratio of signals to be detected are improved, high-precision collection is achieved, and multi-channel parallel sampling is achieved through the ADC collection module. Input signal gating and power supply on-off control of tested equipment are realized through the gating switch control module, so that tested data can safely and quickly enter a monitoring state and are uploaded to the FPGA core control module, real-time data uploading and acquisition are completed, control and data storage of multiple pieces of test data are realized, and the data are combined and sent to the automatic test module. And automatic testing is carried out. Automatic test control of artificial intelligence is realized, and the efficiency of automatic test is improved.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence automated testing technology, and in particular to an artificial intelligence-based automated testing method and system. Background Art

[0002] With the rapid development of computer technology, the speed of system update is also accelerating. When a system modifies some functions or develops new functions, it is necessary to test the system to determine whether it affects other functions of the system.

[0003] As the digitalization process develops, the importance of data systems in enterprise operations is increasing day by day. Before the data system goes online, it is necessary to test the data system, which is of great significance for evaluating the stability of the data system.

[0004] The existing testing method is usually for testers to manually test the data system built on the physical computer, and the test results depend on the technical level of the testers, resulting in low testing efficiency. The existing testing method is to test the system by manually constructing a large amount of data and requires frequent data maintenance, which is not only costly, but also has low automated testing efficiency. Summary of the invention

[0005] The purpose of the present invention is to provide an artificial intelligence-based automated testing method and system to address the technical problem of how to improve the testing efficiency of data systems in view of the defects and shortcomings of the prior art.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] An automated test system based on artificial intelligence, comprising a multi-channel interface module to be tested, a front-end data acquisition module, a data front-end preprocessing module, a strobe switch control module, an FPGA core control module, a DMB receiving module, a data transmission module, an automated test module, an external command input module, a real-time data display module, a clock module, a data storage module and a power supply module, wherein the multi-channel interface module to be tested comprises a USB transmission module, a serial port module, a data processing center, a USB interface, a Gigabit network interface and an HDMI interface;

[0008] The output end of the multi-channel interface module to be tested is connected to the input end of the front-end data acquisition module, the output end of the front-end data acquisition module is connected to the input end of the data front-end preprocessing module, the output end of the data front-end preprocessing module is connected to the input end of the selection switch control module, the output end of the selection switch control module is connected to the input end of the FPGA core control module, the command input module, the real-time data display module, the DMB receiving module, the data transmission module and the power supply module are respectively connected to the FPGA core control module, the FPGA core control module is connected to the automatic test module, the FPGA core control module is connected to the data processing center via the USB transmission module and the serial port module, and the USB interface, the Gigabit network interface and the HDMI interface are respectively connected to the data processing center.

[0009] As a further preferred solution of an artificial intelligence-based automated testing system of the present invention, the data front-end preprocessing module includes a signal conditioning module, a filter gating module, and an ADC acquisition module. The front-end data acquisition module is connected to the FPGA core control module through the signal conditioning module, the filter gating module, and the ADC acquisition module in sequence.

[0010] As a further preferred solution of an artificial intelligence-based automated testing system of the present invention, the gating switch control module includes a TTL level conversion unit, a coaxial switch switching unit and an analog signal switching unit, which are used to realize input signal gating and power on / off control of the device under test, so that the data under test can enter the monitoring state safely and quickly.

[0011] As a further preferred solution of an artificial intelligence-based automated testing system of the present invention, the FPGA core control module includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command deframing unit, a FIFO data cache unit, a Flash data storage control unit, and a data reading unit. The AD acquisition control unit, the port control unit, the synchronous clock control unit, the command deframing unit, the FIFO data cache unit, the Flash data storage control unit, and the data reading unit are respectively connected to the data processing and RAM read-write module unit.

[0012] As a further preferred embodiment of an automated test system based on artificial intelligence of the present invention, the DMB receiving module comprises a tuning module, an ADC module, a channel decoding and demultiplexing module, a data stream module, a decoding module, a text data stream module, a controller module and a data interface module; the RF tuning module is connected to the channel decoding and demultiplexing module through the ADC module, the channel decoding and demultiplexing module is connected to the audio decoding module through the data stream module, the audio decoding module is connected to the power amplifier module through the DAC module, the channel decoding and demultiplexing module is connected to the controller module through the text data stream module, and the controller module is connected to the FPGA core control module.

[0013] As a further preferred embodiment of an automated testing system based on artificial intelligence of the present invention, the signal conditioning module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier, wherein the signal input -IN terminal is connected to one end of the first resistor, the other end of the first resistor is respectively connected to one end of the first capacitor, one end of the third resistor and the negative power supply pin of the first operational amplifier, the other end of the first capacitor is respectively connected to the other end of the third resistor and the output pin of the first operational amplifier, the signal input +IN terminal is connected to one end of the second resistor, and the other end of the second resistor is respectively connected to the first operational amplifier. The positive power pin of the amplifier, one end of the fourth resistor, and one end of the second capacitor, the other end of the second capacitor is connected to the other end of the fourth resistor and grounded, the output pin of the first operational amplifier is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the positive power pin of the second operational amplifier, the negative power pin of the second operational amplifier is connected to the negative power pin of the third operational amplifier, the positive power pin of the third operational amplifier is respectively connected to one end of the eighth resistor and one end of the ninth resistor, the other end of the ninth resistor is grounded, the other end of the eighth resistor is respectively connected to one end of the seventh resistor and the output pin of the second operational amplifier, the other end of the seventh resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded.

[0014] As a further preferred solution of an artificial intelligence-based automated testing system of the present invention, the filtering and gating module comprises an anti-aliasing filtering unit and a signal gating unit connected in sequence, and the signal conditioning module is connected to the ADC acquisition module in sequence through the anti-aliasing filtering unit and the signal gating unit; wherein the chip model of the anti-aliasing filtering unit is OPA2277, and the chip model of the signal gating unit is ADG1634BCPZ.

[0015] As a further preferred solution of an artificial intelligence-based automated testing system of the present invention, the data storage module adopts ST's S25FL128P Flash memory for real-time storage. The chip has a storage capacity of 128Mbit and establishes communication with an external controller through an SPI interface. The maximum clock frequency of the interface can reach 104MHz.

[0016] As a further preferred embodiment of an automated test system based on artificial intelligence of the present invention, the power module 1 comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a second inductor L2, a first diode D1, a second diode D2, a third diode D3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first electrolytic capacitor E1, a second electrolytic capacitor E2, a third electrolytic capacitor E3, a fourth electrolytic capacitor E4, a fifth electrolytic capacitor E5, a first switching power supply chip U1, a second switching power supply chip U2, a voltage stabilizing chip U3, a voltage input terminal, a first voltage output terminal, a second voltage output terminal, and a third voltage output terminal;

[0017] The voltage input terminal is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is respectively connected to one end of the third capacitor C3, the positive electrode of the first electrolytic capacitor E1, one end of the first resistor R1, and the pin 6 of the first switching power supply U1;

[0018] The other end of the first resistor R1 is respectively connected to the pin 7 of the first switch power chip U1, the pin 8 of the first switch power chip U1 and the pin 1 of the first switch power chip U1;

[0019] Pin 2 of the first switch power chip U1 is connected to the cathode of the second diode D2 and one end of the first inductor L1 respectively;

[0020] The other end of the first inductor L1 is respectively connected to the positive electrode of the first electrolytic capacitor E1, one end of the first capacitor C1 and the first voltage output end;

[0021] The other end of the first capacitor C1 is respectively connected to the cathode of the first electrolytic capacitor E1, the anode of the second diode D2, one end of the fourth capacitor C4, the pin 4 of the first switching power chip U1, one end of the fifth resistor R5, the cathode of the third electrolytic capacitor E3 and the other end of the third capacitor C3;

[0022] The other end of the fourth capacitor C4 is connected to the pin 3 of the first switch power chip U1;

[0023] The other end of the fifth resistor R5 is respectively connected to the pin 5 of the first switch power chip U1 and one end of the third resistor R3;

[0024] The other end of the third resistor R3 is connected to the first voltage output end;

[0025] The other end of the third capacitor C3 is also connected to one end of the fifth capacitor C5, the positive electrode of the fourth electrolytic capacitor E4, one end of the second resistor R2, and the pin 6 of the second switch power chip U2;

[0026] The other end of the second resistor R2 is respectively connected to the pin 7 of the second switch power chip U2, the pin 8 of the second switch power chip U2 and the pin 1 of the second switch power chip U2;

[0027] Pin 2 of the second switch power chip U2 is connected to the cathode of the second diode D3 and one end of the second inductor L2 respectively;

[0028] The other end of the second inductor L2 is respectively connected to the positive electrode of the second electrolytic capacitor E2, one end of the second capacitor C2, the second voltage output end and the pin 3 of the voltage stabilizing chip U3;

[0029] The other end of the second capacitor C2 is respectively connected to the pin 1 of the voltage stabilizing chip U3, the negative electrode of the fifth capacitor E5, one end of the seventh capacitor C7, the negative electrode of the second electrolytic capacitor E2, the positive electrode of the third diode D3, one end of the sixth capacitor C6, the pin 4 of the second switching power chip U2, one end of the sixth resistor R6, the negative electrode of the fourth electrolytic capacitor E4 and the other end of the fifth capacitor C5;

[0030] The other end of the sixth capacitor C6 is connected to the pin 3 of the second switch power chip U2, the other end of the sixth resistor R6 is respectively connected to the pin 5 of the second switch power chip U2 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the second voltage output terminal;

[0031] The other end of the seventh capacitor C7 is respectively connected to the positive electrode of the electrolytic capacitor E5, the pin 2 of the voltage stabilizing chip U3, the pin 4 of the voltage stabilizing chip U3 and the third voltage output terminal.

[0032] A testing method for an automated testing system based on artificial intelligence specifically comprises the following steps;

[0033] Step 1: access the test data of the system under test through multiple test interfaces and generate control instructions;

[0034] Step 2, collecting the test data of the system under test accessed by multiple test interfaces;

[0035] Step 3: Through the signal conditioning module and the filtering and gating module, the signal-to-noise ratio, spurious-free dynamic range, common mode rejection ratio and other performance indicators of the measured signal are improved to achieve high-precision acquisition, and multi-channel parallel sampling is achieved through the ADC acquisition module;

[0036] Step 4, through the gating switch control module, the input signal gating and power on / off control of the device under test are realized, so that the measured data can safely and quickly enter the monitoring state, upload to the FPGA core control module, complete the real-time uploading of collected data, realize the control and data storage of multiple test data, and send the combined data to the automated test module for automated testing.

[0037] After adopting the above structure, the beneficial effects of the present invention are:

[0038] (1) The present invention provides an automated testing method and system based on artificial intelligence, comprising a multi-channel test interface module, a front-end data acquisition module, a data front-end preprocessing module, a gating switch control module, an FPGA core control module, a DMB receiving module, a data transmission module, an automated testing module, an external command input module, a data real-time display module, a clock module, a data storage module and a power supply module, wherein the test data of the test system is accessed through the multi-channel test interface, and a control instruction is generated; the test data of the test system accessed by the multi-channel test interface is collected; the signal conditioning module and the filtering gating module are used to improve the performance indicators such as the signal-to-noise ratio, the spurious-free dynamic range, and the common mode rejection ratio of the test signal to achieve high-precision acquisition, and the ADC acquisition module is used to achieve multi-channel parallel sampling; the gating switch control module is used to achieve the input signal gating and power on / off control of the device under test, so that the test data can enter the monitoring state safely and quickly, upload to the FPGA core control module, complete the real-time uploading of the collected data, realize the control and data storage of multiple test data, and send the combined data to the automated testing module for automated testing. The automated testing control of artificial intelligence is realized, and the efficiency of automated testing is improved.

[0039] (2) The present invention uses Xilinx's Spartan6 series FPGA as the core control device, realizing functions such as data acquisition control, data caching, data processing, data storage, data transmission and synchronous clock control, and has the characteristics of high precision, fast speed, good reliability, strong real-time performance and low cost. The 16-channel real-time, high-speed and high-precision synchronous data acquisition system with FPGA as the main processor has a sampling frequency of 200kHz in the actual monitoring project. FPGA is used to reasonably control and coordinate the transmission of data streams between various modules, thereby realizing the real-time, synchronous and high-speed acquisition functions required by the system.

[0040] (3) The data front-end preprocessing module of the present invention includes a signal conditioning module, a filtering and gating module, and an ADC acquisition module. Through two-stage programmable amplification, optional low-pass filtering, multi-channel AD acquisition, real-time data transmission and other functions, it provides a low-cost and easy-to-implement solution for application scenarios in the acquisition field that have high requirements on volume, energy consumption, acquisition accuracy, and anti-interference ability; it has functions such as programmable gain amplification and low-pass filtering, and can perform high-speed parallel acquisition of multiple AC and DC signals. In environments with large interference such as high-speed rotation, it still has good performance indicators such as amplitude accuracy higher than 0.1% and SFDR greater than 60dBc; it adopts a portable design, the system has a small volume and space, is easy to carry and install, and is based on FPGA modular design, has strong scalability, stable performance, and is easy to maintain, and has good application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application, but do not constitute an improper limitation of the present invention. In the drawings:

[0042] Figure 1 This is a structural principle diagram of an automatic testing system based on artificial intelligence of the present invention;

[0043] Figure 2 This is a structural principle diagram of the data front-end preprocessing module of the present invention;

[0044] Figure 3 This is a structural principle diagram of the gating switch control module of the present invention;

[0045] Figure 4 It is a structural principle diagram of the FPGA core control module of the present invention;

[0046] Figure 5 The structural principle diagram of the DMB receiving module of the present invention;

[0047] Figure 6 is a circuit diagram of the signal conditioning module of the present invention;

[0048] Figure 7 is a circuit diagram of a power module of the present invention;

[0049] Figure 8 The present invention discloses a test flow chart of a test method of an automatic test system based on artificial intelligence. DETAILED DESCRIPTION

[0050] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein the illustrative embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention:

[0052] An automated testing system based on artificial intelligence, such as Figure 1 As shown, it includes a multi-channel interface module to be tested, a front-end data acquisition module, a data front-end preprocessing module, a strobe switch control module, an FPGA core control module, a DMB receiving module, a data transmission module, an automated testing module, an external command input module, a data real-time display module, a clock module, a data storage module and a power supply module. The multi-channel interface module to be tested includes a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface; the output end of the multi-channel interface module to be tested is connected to the input end of the front-end data acquisition module, the output end of the front-end data acquisition module is connected to the input end of the data front-end preprocessing module, the output end of the data front-end preprocessing module is connected to the input end of the strobe switch control module, the output end of the strobe switch control module is connected to the input end of the FPGA core control module, the external command input module, the data real-time display module, the DMB receiving module, the data transmission module and the power supply module are respectively connected to the FPGA core control module, the FPGA core control module is connected to the automated testing module, the FPGA core control module is connected to the data processing center through the USB transmission module and the serial port module, and the USB interface, the gigabit network interface and the HDMI interface are respectively connected to the data processing center.

[0053] The present invention accesses the test data of the system under test through multiple test interfaces and generates control instructions; collects the test data of the system under test accessed by the multiple test interfaces; improves the performance indicators such as the signal-to-noise ratio, the spurious-free dynamic range, the common mode rejection ratio and the like of the test signal through a signal conditioning module and a filtering gating module, realizes high-precision collection, and realizes multi-channel parallel sampling through an ADC acquisition module; realizes input signal gating and power on / off control of the device under test through a gating switch control module, so that the test data can safely and quickly enter the monitoring state, be uploaded to the FPGA core control module, complete the real-time uploading of the collected data, realize the control and data storage of multiple test data, and send the combined data to the automatic test module for automatic testing.

[0054] like Figure 2As shown, the data front-end preprocessing module includes a signal conditioning module, a filter gating module, and an ADC acquisition module. The front-end data acquisition module is connected to the FPGA core control module through the signal conditioning module, the filter gating module, and the ADC acquisition module in sequence. Figure 3 As shown, the gating switch control module includes a TTL level conversion unit, a coaxial switch switching unit and an analog signal switching unit, which are used to realize input signal gating and power on / off control of the device under test, so that the measured data can enter the monitoring state safely and quickly.

[0055] The data front-end preprocessing module of the present invention comprises a signal conditioning module, a filtering and gating module, and an ADC acquisition module. Through two-stage program-controlled amplification, optional low-pass filtering, multi-channel AD acquisition, real-time data transmission and other functions, it provides a low-cost and easy-to-implement solution for application scenarios in the acquisition field that have high requirements on volume, energy consumption, acquisition accuracy, and anti-interference ability; it has functions such as program-controlled gain amplification and low-pass filtering, and can perform high-speed parallel acquisition of multi-channel AC and DC signals. In an environment with large interference such as high-speed rotation, it still has good performance indicators such as amplitude accuracy higher than 0.1% and SFDR greater than 60dBc; it adopts a portable design, the system has a small volume and space, is easy to carry and install, and is based on FPGA modular design, has strong scalability, stable performance, and is easy to maintain, and has good application value;

[0056] like Figure 4 As shown, the FPGA core control module includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command de-framing unit, a FIFO data cache unit, a Flash data storage control unit, and a data reading unit. The AD acquisition control unit, the port control unit, the synchronous clock control unit, the command de-framing unit, the FIFO data cache unit, the Flash data storage control unit, and the data reading unit are connected to the data processing and RAM read-write module unit. After the system is powered on, wait for the FPGA to be initialized and enter the waiting connection state. When the relevant command parameters are input externally, the FPGA receives and parses the command. First, the internal selection switch of the system is controlled to work, and the selected device signal is connected to the acquisition system. Then, control information is sent to the device under test, and the acquisition system monitors the power supply of the device under test in real time. Subsequently, the collected data is cached in the random access memory (Random Access Memory, RAM) inside the FPGA for processing. Finally, the collected data is transmitted back to the external monitor through the first-in-first-out queue (First Input First Output, FIFO) on the FPGA chip for real-time display, and judged and stored according to the corresponding rules to form a test data report.

[0057] The present invention adopts Xilinx's Spartan6 series FPGA as the core control device, realizes the functions of data acquisition control, data caching, data processing, data storage, data transmission and synchronous clock control, and has the characteristics of high precision, fast speed, good reliability, strong real-time performance and low cost. The 16-channel real-time, high-speed and high-precision synchronous data acquisition system with FPGA as the main processor has a sampling frequency of 200kHz in the actual monitoring project, and uses FPGA to reasonably control and coordinate the transmission of data streams between various modules, thereby realizing the real-time, synchronous and high-speed acquisition functions required by the system.

[0058] like Figure 5 As shown, the DMB receiving module includes a tuning module, an ADC module, a channel decoding and demultiplexing module, a data stream module, a decoding module, a text data stream module, a controller module and a data interface module; the RF tuning module is connected to the channel decoding and demultiplexing module through the ADC module, the channel decoding and demultiplexing module is connected to the audio decoding module through the data stream module, the audio decoding module is connected to the power amplifier module through the DAC module, the channel decoding and demultiplexing module is connected to the controller module through the text data stream module, and the controller module is connected to the FPGA core control module.

[0059] Among them, the BF tuning module of the DMB receiving module retrieves the DMB signal from it and reduces it from a high-frequency signal to an intermediate-frequency signal. The intermediate-frequency signal is converted into an 8-bit digital signal after ADC conversion. The digital signal is sent to the DMB baseband decoding chip, and after channel decoding and demultiplexing, a data stream and a text data stream are obtained. The data stream is decoded by the decoder in the DMB baseband decoding chip, and then converted by the DAC chip and restored to a signal. After the signal is amplified by the power amplifier, the text data stream passes through the data interface of the DMB baseband decoding and is output to the single-chip microcomputer in the DMB receiving module for analysis. After obtaining the standard time information and instruction information, the module converts the text data into pixel information.

[0060] like Figure 6As shown, the signal conditioning module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier, wherein the signal input -IN terminal is connected to one end of the first resistor, the other end of the first resistor is respectively connected to one end of the first capacitor, one end of the third resistor and the negative power pin of the first operational amplifier, the other end of the first capacitor is respectively connected to the other end of the third resistor and the output pin of the first operational amplifier, the signal input +IN terminal is connected to one end of the second resistor, the other end of the second resistor is respectively connected to the positive power pin of the first operational amplifier, one end of the fourth resistor The output pin of the first operational amplifier is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the positive power pin of the second operational amplifier, the negative power pin of the second operational amplifier is connected to the negative power pin of the third operational amplifier, the positive power pin of the third operational amplifier is respectively connected to one end of the eighth resistor and one end of the ninth resistor, the other end of the ninth resistor is grounded, the other end of the eighth resistor is respectively connected to one end of the seventh resistor and the output pin of the second operational amplifier, the other end of the seventh resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded.

[0061] The signal conditioning module amplifies and filters the data and then inputs it into the signal conversion circuit, which greatly reduces the signal noise and signal loss in the measurement. The amplification circuit part is composed of an OPA277 operational amplifier and a resistor and capacitor. This circuit is a typical differential amplifier circuit. At the same time, C3 and R6, C4 and R7 form a low-pass filter, and two OPA277 operational amplifiers form a dual op amp bandpass filter. The bandpass filter Q value and center frequency are adjustable. Adjusting R9 can adjust the resonant frequency of the circuit, and adjusting R8 can adjust the Q value of the circuit. It is worth noting that after the signal is collected, the multiplexed analog switch selects the output to the signal processing circuit and then inputs it into the AD7794 for digital-to-analog conversion, converting the analog signal into a digital signal, which is conducive to the long-distance wireless transmission of the signal. It is worth noting that the noise of the 24-bit Σ-Δ analog-to-digital converter AD7794 is only 40nV, and the power consumption current is only 400μA, which is particularly suitable for applications requiring low power consumption and high-precision measurement.

[0062] The filter gating module comprises an anti-aliasing filter unit and a signal gating unit connected in sequence, and the signal conditioning module is connected to the ADC acquisition module in sequence through the anti-aliasing filter unit and the signal gating unit; wherein the chip model of the anti-aliasing filter unit is OPA2277, and the chip model of the signal gating unit is ADG1634BCPZ.

[0063] The data storage module uses ST's S25FL128P Flash memory for real-time storage. The chip has a storage capacity of 128Mbit and communicates with an external controller via an SPI interface. The maximum clock frequency of the interface can reach 104MHz.

[0064] like Figure 7 As shown, the power module 1 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a second inductor L2, a first diode D1, a second diode D2, a third diode D3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first electrolytic capacitor E1, a second electrolytic capacitor E2, a third electrolytic capacitor E3, a fourth electrolytic capacitor E4, a fifth electrolytic capacitor E5, a first switching power supply chip U1, a second switching power supply chip U2, a voltage stabilizing chip U3, a voltage input terminal, a first voltage output terminal, a second voltage output terminal, and a third voltage output terminal;

[0065] The voltage input terminal is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is respectively connected to one end of the third capacitor C3, the positive electrode of the first electrolytic capacitor E1, one end of the first resistor R1, and the pin 6 of the first switching power supply U1;

[0066] The other end of the first resistor R1 is respectively connected to the pin 7 of the first switch power chip U1, the pin 8 of the first switch power chip U1 and the pin 1 of the first switch power chip U1;

[0067] Pin 2 of the first switch power chip U1 is connected to the cathode of the second diode D2 and one end of the first inductor L1 respectively;

[0068] The other end of the first inductor L1 is respectively connected to the positive electrode of the first electrolytic capacitor E1, one end of the first capacitor C1 and the first voltage output end;

[0069] The other end of the first capacitor C1 is respectively connected to the cathode of the first electrolytic capacitor E1, the anode of the second diode D2, one end of the fourth capacitor C4, the pin 4 of the first switching power chip U1, one end of the fifth resistor R5, the cathode of the third electrolytic capacitor E3 and the other end of the third capacitor C3;

[0070] The other end of the fourth capacitor C4 is connected to the pin 3 of the first switch power chip U1;

[0071] The other end of the fifth resistor R5 is respectively connected to the pin 5 of the first switch power chip U1 and one end of the third resistor R3;

[0072] The other end of the third resistor R3 is connected to the first voltage output end;

[0073] The other end of the third capacitor C3 is also connected to one end of the fifth capacitor C5, the positive electrode of the fourth electrolytic capacitor E4, one end of the second resistor R2, and the pin 6 of the second switch power chip U2;

[0074] The other end of the second resistor R2 is respectively connected to the pin 7 of the second switch power chip U2, the pin 8 of the second switch power chip U2 and the pin 1 of the second switch power chip U2;

[0075] Pin 2 of the second switch power chip U2 is connected to the cathode of the second diode D3 and one end of the second inductor L2 respectively;

[0076] The other end of the second inductor L2 is respectively connected to the positive electrode of the second electrolytic capacitor E2, one end of the second capacitor C2, the second voltage output end and the pin 3 of the voltage stabilizing chip U3;

[0077] The other end of the second capacitor C2 is respectively connected to the pin 1 of the voltage stabilizing chip U3, the negative electrode of the fifth capacitor E5, one end of the seventh capacitor C7, the negative electrode of the second electrolytic capacitor E2, the positive electrode of the third diode D3, one end of the sixth capacitor C6, the pin 4 of the second switching power chip U2, one end of the sixth resistor R6, the negative electrode of the fourth electrolytic capacitor E4 and the other end of the fifth capacitor C5;

[0078] The other end of the sixth capacitor C6 is connected to the pin 3 of the second switch power chip U2, the other end of the sixth resistor R6 is respectively connected to the pin 5 of the second switch power chip U2 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the second voltage output terminal;

[0079] The other end of the seventh capacitor C7 is respectively connected to the positive electrode of the electrolytic capacitor E5, the pin 2 of the voltage stabilizing chip U3, the pin 4 of the voltage stabilizing chip U3 and the third voltage output terminal.

[0080] This circuit is not only small in size, high in efficiency, precise in voltage regulation and low in interference, but can also convert the input voltage into +12V, +5V and +3.3V DC power through the first switching power supply, the second switching power supply and the voltage regulator chip, providing +12V, +5V and +3.3V DC voltages, and can provide power supply for multiple chips and circuits at the same time.

[0081] The chip models of the first switching power supply chip U1 and the second switching power supply are both MC33063.

[0082] MC33063 Chinese data pin function application circuit

[0083] MC34063A (MC33063) integrated circuit chip device introduction: The device itself contains the main functions required by the DC / DC converter monolithic control circuit and is inexpensive.

[0084] MC34063A (MC33063) Integrated Circuit Chip Device Introduction This device contains the main functions of the DC / DC converter in a single-chip control circuit and is inexpensive. It consists of a reference voltage generator with automatic temperature compensation function, a comparator, an oscillator with controllable duty cycle, an R-S trigger, and a high-current output switch circuit. This device can be used as the control core of a boost converter, a buck converter, and an inverter. The DC / DC converter formed by it uses only a small number of external components. It is mainly used in systems based on microprocessors (MPUs) or single-chip microcomputers (MCUs).

[0085] Main features of MC34063 integrated circuit: Input voltage range: 2.5~40V Output voltage adjustable range: 1.25~40V Output current up to: 1.5A Operating frequency: up to 100kHz Low quiescent current Short-circuit current limit Can realize step-up or step-down power converter.

[0086] The chip model of the voltage stabilizing chip U3 is ASM1117.

[0087] ASM1117 is a voltage regulator chip suitable for high-efficiency linear voltage regulators, switching power supply regulators, battery chargers, active small computer system interface terminals, notebook computer power management, and battery-powered instruments. Chip is a general term for semiconductor component products, or microcircuit, microchip, wafer, integrated circuit. In electronics, it is a way to miniaturize circuits (mainly semiconductor devices, but also passive components, etc.), and is often manufactured on the surface of semiconductor wafers.

[0088] The third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are all voltage-dividing resistors, and the resistance of the third resistor R3 is 4.3 kilo-ohms, the resistance of the fourth resistor R4 is 3.6 kilo-ohms, and the resistance of the fifth resistor R5 is 5.1 kilo-ohms.

[0089] The resistance value of the first resistor R1 is 0.2 ohms, the resistance value of the fourth resistor R4 is 3.6 kilo-ohms, and the resistance value of the sixth resistor R6 is 1.2 kilo-ohms.

[0090] like Figure 8 As shown, a testing method for an automated testing system based on artificial intelligence specifically comprises the following steps;

[0091] Step 1: access the test data of the system under test through multiple test interfaces and generate control instructions;

[0092] Step 2, collecting the test data of the system under test accessed by multiple test interfaces;

[0093] Step 3: Through the signal conditioning module and the filtering and gating module, the signal-to-noise ratio, spurious-free dynamic range, common mode rejection ratio and other performance indicators of the measured signal are improved to achieve high-precision acquisition, and multi-channel parallel sampling is achieved through the ADC acquisition module;

[0094] Step 4, through the gating switch control module, the input signal gating and power on / off control of the device under test are realized, so that the measured data can safely and quickly enter the monitoring state, upload to the FPGA core control module, complete the real-time uploading of collected data, realize the control and data storage of multiple test data, and send the combined data to the automated test module for automated testing.

[0095] The above description is only a preferred embodiment of the present invention, so all equivalent changes or modifications made according to the structure, characteristics and principles described in the scope of the patent application of the present invention are included in the scope of the patent application of the present invention.

[0096] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0097] The above embodiments are only for explaining the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention shall fall within the protection scope of the present invention. The above embodiments of the present invention are described in detail, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in the field without departing from the purpose of the present invention.

Claims

1. An automated testing system based on artificial intelligence, characterized in that: It comprises a multi-channel interface module to be tested, a front-end data acquisition module, a data front-end preprocessing module, a strobe switch control module, an FPGA core control module, a DMB receiving module, a data transmission module, an automated test module, an external command input module, a data real-time display module, a clock module, a data storage module and a power supply module, wherein the multi-channel interface module to be tested comprises a USB transmission module, a serial port module, a data processing center, a USB interface, a Gigabit network interface and an HDMI interface; The output end of the multi-channel interface module to be tested is connected to the input end of the front-end data acquisition module, the output end of the front-end data acquisition module is connected to the input end of the data front-end preprocessing module, the output end of the data front-end preprocessing module is connected to the input end of the selection switch control module, the output end of the selection switch control module is connected to the input end of the FPGA core control module, the command input module, the real-time data display module, the DMB receiving module, the data transmission module and the power supply module are respectively connected to the FPGA core control module, the FPGA core control module is connected to the automatic test module, the FPGA core control module is connected to the data processing center via the USB transmission module and the serial port module, and the USB interface, the Gigabit network interface and the HDMI interface are respectively connected to the data processing center.

2. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The data front-end preprocessing module includes a signal conditioning module, a filter gating module, and an ADC acquisition module. The front-end data acquisition module is connected to the FPGA core control module through the signal conditioning module, the filter gating module, and the ADC acquisition module in sequence.

3. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The gating switch control module includes a TTL level conversion unit, a coaxial switch switching unit and an analog signal switching unit, which are used to realize input signal gating and power on / off control of the device under test, so that the measured data can enter the monitoring state safely and quickly.

4. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The FPGA core control module includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command deframing unit, a FIFO data cache unit, a Flash data storage control unit, and a data reading unit. The AD acquisition control unit, the port control unit, the synchronous clock control unit, the command deframing unit, the FIFO data cache unit, the Flash data storage control unit, and the data reading unit are respectively connected to the data processing and RAM read-write module unit.

5. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The DMB receiving module comprises a tuning module, an ADC module, a channel decoding and demultiplexing module, a data stream module, a decoding module, a text data stream module, a controller module and a data interface module; the RF tuning module is connected to the channel decoding and demultiplexing module through the ADC module, the channel decoding and demultiplexing module is connected to the audio decoding module through the data stream module, the audio decoding module is connected to the power amplifier module through the DAC module, the channel decoding and demultiplexing module is connected to the controller module through the text data stream module, and the controller module is connected to the FPGA core control module.

6. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The signal conditioning module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first operational amplifier, a second operational amplifier, and a third operational amplifier, wherein a signal input -IN terminal is connected to one end of the first resistor, the other end of the first resistor is respectively connected to one end of the first capacitor, one end of the third resistor and a negative power supply pin of the first operational amplifier, the other end of the first capacitor is respectively connected to the other end of the third resistor and an output pin of the first operational amplifier, and a signal input +IN terminal is connected to one end of the second resistor, the other end of the second resistor is respectively connected to the positive power supply pin of the first operational amplifier, one end of the fourth resistor The output pin of the first operational amplifier is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to the positive power pin of the second operational amplifier, the negative power pin of the second operational amplifier is connected to the negative power pin of the third operational amplifier, the positive power pin of the third operational amplifier is respectively connected to one end of the eighth resistor and one end of the ninth resistor, the other end of the ninth resistor is grounded, the other end of the eighth resistor is respectively connected to one end of the seventh resistor and the output pin of the second operational amplifier, the other end of the seventh resistor is connected to one end of the fourth capacitor, the other end of the fourth capacitor is respectively connected to one end of the ninth resistor, the other end of the ninth resistor is connected to one end of the third capacitor, and the other end of the third capacitor is grounded.

7. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The filter gating module comprises an anti-aliasing filter unit and a signal gating unit connected in sequence, and the signal conditioning module is connected to the ADC acquisition module in sequence through the anti-aliasing filter unit and the signal gating unit; wherein the chip model of the anti-aliasing filter unit is OPA2277, and the chip model of the signal gating unit is ADG1634BCPZ.

8. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The data storage module uses S25FL128P Flash memory for real-time storage. The chip has a storage capacity of 128Mbit and communicates with an external controller via an SPI interface. The maximum clock frequency of the interface can reach 104MHz.

9. The artificial intelligence-based automated testing system according to claim 1, characterized in that: The power module includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first inductor L1, a second inductor L2, a first diode D1, a second diode D2, a third diode D3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a first electrolytic capacitor E1, a second electrolytic capacitor E2, a third electrolytic capacitor E3, a fourth electrolytic capacitor E4, a fifth electrolytic capacitor E5, a first switching power chip U1, a second switching power chip U2, a voltage stabilizing chip U3, a voltage input terminal, a first voltage output terminal, a second voltage output terminal, and a third voltage output terminal; The voltage input terminal is connected to the positive electrode of the diode D1, and the negative electrode of the diode D1 is respectively connected to one end of the third capacitor C3, the positive electrode of the first electrolytic capacitor E1, one end of the first resistor R1, and the pin 6 of the first switching power supply U1; The other end of the first resistor R1 is respectively connected to the pin 7 of the first switch power chip U1, the pin 8 of the first switch power chip U1 and the pin 1 of the first switch power chip U1; Pin 2 of the first switch power chip U1 is connected to the cathode of the second diode D2 and one end of the first inductor L1 respectively; The other end of the first inductor L1 is respectively connected to the positive electrode of the first electrolytic capacitor E1, one end of the first capacitor C1 and the first voltage output end; The other end of the first capacitor C1 is respectively connected to the cathode of the first electrolytic capacitor E1, the anode of the second diode D2, one end of the fourth capacitor C4, the pin 4 of the first switching power chip U1, one end of the fifth resistor R5, the cathode of the third electrolytic capacitor E3 and the other end of the third capacitor C3; The other end of the fourth capacitor C4 is connected to the pin 3 of the first switch power chip U1; The other end of the fifth resistor R5 is respectively connected to the pin 5 of the first switch power chip U1 and one end of the third resistor R3; The other end of the third resistor R3 is connected to the first voltage output end; The other end of the third capacitor C3 is also connected to one end of the fifth capacitor C5, the positive electrode of the fourth electrolytic capacitor E4, one end of the second resistor R2, and the pin 6 of the second switch power chip U2; The other end of the second resistor R2 is respectively connected to the pin 7 of the second switch power chip U2, the pin 8 of the second switch power chip U2 and the pin 1 of the second switch power chip U2; Pin 2 of the second switch power chip U2 is connected to the cathode of the second diode D3 and one end of the second inductor L2 respectively; The other end of the second inductor L2 is respectively connected to the positive electrode of the second electrolytic capacitor E2, one end of the second capacitor C2, the second voltage output end and the pin 3 of the voltage stabilizing chip U3; The other end of the second capacitor C2 is respectively connected to the pin 1 of the voltage stabilizing chip U3, the negative electrode of the fifth capacitor E5, one end of the seventh capacitor C7, the negative electrode of the second electrolytic capacitor E2, the positive electrode of the third diode D3, one end of the sixth capacitor C6, the pin 4 of the second switching power chip U2, one end of the sixth resistor R6, the negative electrode of the fourth electrolytic capacitor E4 and the other end of the fifth capacitor C5; The other end of the sixth capacitor C6 is connected to the pin 3 of the second switch power chip U2, the other end of the sixth resistor R6 is respectively connected to the pin 5 of the second switch power chip U2 and one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the second voltage output terminal; The other end of the seventh capacitor C7 is respectively connected to the positive electrode of the electrolytic capacitor E5, the pin 2 of the voltage stabilizing chip U3, the pin 4 of the voltage stabilizing chip U3 and the third voltage output terminal.

10. A testing method for an artificial intelligence-based automated testing system according to any one of claims 1 to 9, characterized in that: The specific steps include: Step 1: access the test data of the system under test through multiple test interfaces and generate control instructions; Step 2, collecting the test data of the system under test accessed by multiple test interfaces; Step 3: Through the signal conditioning module and the filtering and gating module, the signal-to-noise ratio, spurious-free dynamic range, common mode rejection ratio and other performance indicators of the measured signal are improved to achieve high-precision acquisition, and multi-channel parallel sampling is achieved through the ADC acquisition module; Step 4, through the gating switch control module, the input signal gating and power on / off control of the device under test are realized, so that the measured data can safely and quickly enter the monitoring state, upload to the FPGA core control module, complete the real-time uploading of collected data, realize the control and data storage of multiple test data, and send the combined data to the automated test module for automated testing.

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