Multi-chip bare chip system and chip starting method

Abstract

The invention provides a multi-chip bare chip system and a chip starting method. The system comprises a first chip bare chip and at least one second chip bare chip, a corresponding low-speed communication interface is arranged between the first bare chip and the at least one second bare chip; the first bare chip is connected with an off-chip memory, and the second bare chip is provided with an on-chip memory; after the first bare chip loads and starts a first chip bootstrap program from the off-chip memory, reading a second chip bootstrap program from the off-chip memory, and pushing the second chip bootstrap program to the on-chip memory of the at least one second bare chip through the low-speed communication interface; and the at least one second bare chip loads the second chip bootstrap program from the on-chip memory and starts the second chip bootstrap program. According to the method disclosed by the invention, the bootloader is pushed among the multiple dies without depending on a D2D (Device-to-Device) interface.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a multi-chip bare die system and a chip startup method. Background Art

[0002] With the increasing complexity of chip design and the cost of advanced manufacturing processes, multi-chip die architecture has become an effective solution to the difficulty of large chip design. The startup process of multi-chip die is a complex process, which involves the collaborative work and initialization between multiple chip dies. Summary of the invention

[0003] The purpose of the present application is to provide a multi-chip bare die system and a chip startup method, aiming to solve the problem that the startup of the chip bare die in the multi-chip bare die system depends on the establishment of a high-speed communication interface D2D (Die to Die, chip bare die to chip bare die) link.

[0004] According to a first aspect of the present application, there is provided a multi-chip die system, comprising: a first chip die and at least one second chip die;

[0005] A corresponding low-speed communication interface is provided between the first chip die and the at least one second chip die;

[0006] The first chip die is connected to an off-chip memory, and the second chip die is provided with an on-chip memory;

[0007] After the first chip bare die loads and starts the first chip boot program from the off-chip memory, the second chip boot program is read from the off-chip memory and pushed to the on-chip memory of the at least one second chip bare die through the low-speed communication interface;

[0008] The at least one second chip die loads and starts the second chip boot program from the on-chip memory.

[0009] In an optional embodiment, after the at least one second chip die starts the second chip boot program, the first chip die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip die through the low-speed communication interface;

[0010] The at least one second chip die loads and starts the second operating system from the on-chip memory;

[0011] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0012] In an optional embodiment, the first chip die and the at least one second chip die are further provided with corresponding high-speed communication interfaces;

[0013] After the first chip die pushes the second chip boot program, initializing the high-speed communication interface of the first chip die;

[0014] After the at least one second chip bare die starts the second chip boot program, initializing the high-speed communication interface of the at least one second chip bare die;

[0015] The first chip die and the at least one second chip die establish a communication link between the high-speed communication interface.

[0016] In an optional embodiment, after the at least one second chip die starts the second chip boot program, the first chip die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip die through the high-speed communication interface;

[0017] The at least one second chip die loads and starts the second operating system from the on-chip memory;

[0018] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0019] In an optional embodiment, the at least one second chip die is provided with a command register and a status register; the first chip die writes a command to the command register through the low-speed communication interface, and the at least one second chip die reads the command written by the first chip die from the command register;

[0020] The at least one second chip die writes a status to the status register, and the first chip die reads the status written by the at least one second chip die from the status register through the low-speed communication interface.

[0021] In an optional implementation manner, the first chip bare die reads the status written in the status register, and after determining that the at least one second chip bare die has completed loading and running the chip startup code, writes a command to start pushing the second chip boot program to the command register, and after pushing the second chip boot program, writes a command to complete pushing the second chip boot program to the command register;

[0022] The first chip bare die also reads the status written in the status register, and after determining that the at least one second chip bare die has completed the startup of the second chip boot program, writes a command to start pushing the second operating system to the command register, and after pushing the second operating system, writes a command to complete pushing the second operating system to the command register.

[0023] In an optional implementation manner, after the second chip bare die loads and starts the chip startup code, the second chip bare die writes the status of completing the startup of the chip startup code to the status register;

[0024] The at least one second chip bare die reads the command written in the command register, and after determining that the first chip bare die starts to push the second chip boot program and completes the pushing of the second chip boot program, loads and starts the second chip boot program from the on-chip memory, and also writes a status of completing the startup of the second chip boot program to the status register;

[0025] The at least one second chip bare die reads the command written in the command register, and after determining that the first chip bare die starts to push the second operating system and completes the pushing of the second operating system, loads and starts the second operating system from the on-chip memory, and also writes the status of completing the startup of the second operating system to the status register.

[0026] According to a second aspect of the present application, a chip startup method is provided, the method being performed in the multi-chip bare die system according to the first aspect, the method comprising:

[0027] The first chip bare die loads the first chip boot program from the off-chip memory and starts;

[0028] The first chip bare die reads the second chip boot program from the off-chip memory and pushes it to the on-chip memory of at least one second chip bare die through the low-speed communication interface;

[0029] The at least one second chip die loads and starts the second chip boot program from the on-chip memory.

[0030] In an optional embodiment, the method further comprises:

[0031] After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the low-speed communication interface;

[0032] The at least one second chip die loads and starts the second operating system from the on-chip memory;

[0033] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0034] In an optional embodiment, the method further comprises:

[0035] After the first chip die pushes the second chip boot program, initializing the high-speed communication interface of the first chip die;

[0036] After the at least one second chip bare die starts the second chip boot program, initializing the high-speed communication interface of the at least one second chip bare die;

[0037] The first chip die and the at least one second chip die establish a communication link between the high-speed communication interface.

[0038] In an optional embodiment, the method further comprises:

[0039] After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the high-speed communication interface;

[0040] The at least one second chip die loads and starts the second operating system from the on-chip memory;

[0041] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0042] In an optional implementation, the first chip bare die reads the second chip boot program from the off-chip memory and pushes it to the on-chip memory of at least one second chip bare die through the low-speed communication interface, including:

[0043] The first chip die reads the status of the status register set in the second chip die, and after determining that the at least one second chip die has completed the loading and running of the chip startup code, writes a command to start pushing the second chip boot program to the command register set in the second chip die, and after pushing the second chip boot program, writes a command to complete pushing the second chip boot program to the command register.

[0044] In an optional implementation, after the at least one second chip die starts the second chip boot program, the first chip die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip die through the low-speed communication interface, including:

[0045] The first chip bare die reads the status of the status register set in the second chip bare die, and after determining that the at least one second chip bare die has completed the startup of the second chip boot program, writes a command to start pushing the second operating system to the command register set in the second chip bare die, and after pushing the second operating system, writes a command to complete pushing the second operating system to the command register.

[0046] In an optional embodiment, the method further comprises:

[0047] After the second chip bare die loads and starts the chip startup code, the status of completing the startup of the chip startup code is written to the status register set in the second chip bare die;

[0048] The at least one second chip bare die loads and starts the second chip boot program from the on-chip memory, comprising:

[0049] The at least one second chip bare die reads the command written in the command register set in the second chip bare die, and after determining that the first chip bare die starts to push the second chip boot program and completes the pushing of the second chip boot program, loads and starts the second chip boot program from the on-chip memory, and also writes the status of completing the startup of the second chip boot program to the status register.

[0050] In an optional implementation, the at least one second chip die loads and starts the second operating system from the on-chip memory, comprising:

[0051] The at least one second chip die reads a command register set in the second chip die, and after determining that the first chip die starts to push the second operating system and completes the pushing of the second operating system, loads and starts the second operating system from the on-chip memory, and also writes the status of completing the startup of the second operating system to a status register set in the second chip die.

[0052] Compared with the related art, the technical solution of this application has the following advantages:

[0053] 1. Pushing bootloader between multiple Dies does not depend on the D2D interface.

[0054] 2. Low-speed communication interfaces such as Uart have relatively low rates, good signal quality, and high reliability in Die data transmission.

[0055] 3. The program for initializing the D2D interface is merged into the Bootloader, and the Bootloader is burned into the Flash. The Bootloader can be updated at any time, which increases the flexibility of the D2D interface initialization.

[0056] 4. When pushing OS through multiple Dies, you can select low-speed communication interfaces such as Uart or D2D interfaces as needed.

[0057] 5. The push protocol and process effectively ensure the reliability of the pushed data.

[0058] 6. In addition to Uart interface, I2C and other low-speed communication interfaces can be used as similar applications to save the sideband signal of the D2D interface.

[0059] 7. The Die of the Uart master device can manage other Dies through the Uart interface, such as obtaining the status of other Dies, and can directly issue a reset command to restart other Dies.

[0060] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0062] Figure 1 It is a structural diagram of a multi-die chip system.

[0063] Figure 2 It is a schematic diagram of the structure of a multi-die chip system according to an exemplary embodiment of the present application.

[0064] Figure 3 It is another structural schematic diagram of a multi-die chip system according to an exemplary embodiment of the present application.

[0065] Figure 4 2 is a schematic diagram of the startup process of two Die chips according to an exemplary embodiment of the present application.

[0066] Figure 5 is another schematic diagram of a startup process of two Die chips according to an exemplary embodiment of the present application.

[0067] Figure 6 1 is a schematic diagram of the push handshake protocol flow of two Die chips according to an exemplary embodiment of the present application.

[0068] Figure 7It is a structural schematic diagram of a three-Die chip system according to an exemplary embodiment of the present application.

[0069] Figure 8 It is a flowchart of a chip startup method according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0071] In the relevant multi-chip bare die, each chip bare die is usually an independent SoC chip. The software code supporting the SoC chip usually has three parts: Bootcode (chip startup code), Bootloader (chip boot program) and OS (operating system). Bootcode is the initial startup code of the chip, which is solidified in the ROM inside the chip. It completes the initial startup and configures and initializes the chip clock, reset, and basic peripheral interfaces. Bootloader and OS are stored in the chip's external media Flash. After the Bootcode runs, the Bootloader and OS are loaded into the chip's internal cache and run in turn.

[0072] There is only one Flash outside the multi-chip die, and this Flash can only be linked to one of the chip dies. After the Bootcode runs, when each chip die needs to load the Bootloader and OS from the external Flash, only this one chip die can directly read the Flash, and other chip dies can only read the Flash through the cross-chip die method to complete the entire chip startup process.

[0073] See also Figure 1 As shown, the internal interconnection structure of the multi-chip die structure 101 including two chip dies is as follows:

[0074] Two Dies 102 are interconnected through a D2D (Die to Die) interface 105. When the chip runs the Bootcode to start up, Die0 and Die1 read the Bootcode from their respective on-chip ROMs to start the chip. After the Bootcode runs, Die0 directly loads the Bootloader from Flash 103, and after the Bootloader runs, it directly loads the OS from Flash. After the Bootcode runs, Die1 first configures and initializes the link establishment of the D2D interface with Die0. Usually, the two Dies (chip dies) synchronize the status of the D2D interface when establishing the link through the sideband signal 104. This requires that the Bootcode of Die0 and Die1 must contain the code for initializing the D2D interface. After the D2D interface is established, Die0 can read the Flash through the Diel data path through the D2D interface to load the Bootloader and OS.

[0075] The above multi-chip bare die startup process has the following problems:

[0076] 1. Die0 must rely on the D2D interface to obtain the complete Bootloader and OS.

[0077] 2. The D2D interface is usually a high-speed interface. The code for initializing the D2D interface must be integrated into the Bootcode and solidified in the on-chip ROM. After the chip is manufactured, the Bootcode cannot be modified, which makes the D2D initialization code lack flexibility.

[0078] 3. For multi-chip bare chips that implement switching functions, such as Ethernet, PCIe, IB and other protocol switching chips, the D2D interface is the data path for protocol switching. Usually, the D2D interface is not used as a path for the on-chip MCU (Microcontroller Unit) to access external Flash. If it is used to access external Flash, the system implementation complexity will be greatly increased and the protocol data processing bandwidth will be occupied.

[0079] Based on the above analysis, this application interconnects Die and Die through a low-speed communication interface, as well as a custom reliable transmission protocol between Dies, so that each Die in a multi-chip die can be started correctly and reliably without relying on a D2D interface, thereby completing the startup process of the multi-chip die.

[0080] See also Figure 2 As shown, the present application exemplarily provides a multi-chip die system, which includes: a first chip die and at least one second chip die;

[0081] A corresponding low-speed communication interface is provided between the first chip die and at least one second chip die;

[0082] The first chip die is connected to an off-chip memory, and the second chip die is provided with an on-chip memory;

[0083] After the first chip bare die loads and starts the first chip boot program from the off-chip memory, the second chip boot program is read from the off-chip memory and pushed to the on-chip memory of at least one second chip bare die through the low-speed communication interface;

[0084] At least one second chip die loads and starts a second chip boot program from the on-chip memory.

[0085] The multi-chip bare die system proposed in the present application is described below by taking a second chip bare die as an example.

[0086] For example, see Figure 2 As shown, in the two-chip bare die system 201, low-speed communication interfaces are added to both Dies 202. Figure 2What is shown is a low-speed communication interface Uart (Universal Asynchronous Receiver / Transmitter). It is understandable that, in addition to the Uart interface, other low-speed communication interfaces are also applicable to the present application. A Uart functional module is added to two Die202 (where Die1 is the first chip bare die and Die0 is the second chip bare die) to serve as a link between Diel and Die0. In Die1 is a Uart master device (Uart_M), in Die0 is a Uart slave device (Uart_S), and the Uart slave device in Die0 has a Die intra-bus access interface, which can directly access the on-chip memory in the Die, that is, the cache SRAM shown in the figure. It is understandable that the on-chip memory can also be other memories such as ROM. Die10 and Die1 are each internally provided with a ROM, which can be used to store the chip boot code (Bootcode). After power-on, the chip boot code is started, and then Die1 reads the first chip boot program Bootloader from the off-chip memory, that is, Flash203 shown in the figure and starts, and reads the second chip boot program Bootloader and the second operating system OS of Die0 from the off-chip memory. Die1 can push the second chip boot program Bootloader and the second operating system OS to the cache SRAM in Die0 through the Uart interface 204. Die0 can directly run the second chip boot program Bootloader and the second operating system OS from the cache SRAM in Die to complete the startup process. Die1 directly reads the first chip boot program Bootloader and the first operating system OS of Die1 from Flash203 to complete the startup process. After Die0 and Die1 complete the startup process, the D2D interface is initialized and the link is successfully established. The entire multi-chip bare die system completes the startup process and can start normal operation. It can be seen that in this startup process, the push of Bootloader and operating system OS relies on the low-speed communication interface between Dies, such as Uart interface, instead of D2D interface. Since the rate of low-speed communication interface such as Uart interface is relatively low and the signal quality is good, the reliability of transmitting Bootloader and operating system OS data between Dies is high. For example, see Figure 3 As shown, the multi-chip bare die system 301 includes two Dies 302, Die0 and Die1, where Die1 is externally connected to Flash 303. Die0 and Die1 are interconnected by two groups of interfaces, one group of interfaces is a low-speed communication interface UART 304, which is mainly used for data push, including firmware push; the other group is a D2D interface 305, which serves as a data path between the two Dies. Figure 3 COM_REG 306 is a data push protocol register, which is mainly used for handshake between two Dies during the data push process.

[0087] In some optional implementations, after the at least one second chip die starts the second chip boot program, the first chip die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip die through the low-speed communication interface;

[0088] at least one second chip die loads and starts a second operating system from the on-chip memory;

[0089] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0090] Exemplarily, after the second chip die starts the second chip boot program, the first chip die also reads the second operating system from the off-chip memory and pushes it to the second chip die through the low-speed communication interface. After the second chip die receives the second operating system, it starts the second operating system. The first chip die also reads the first operating system from the off-chip memory and starts the first operating system. It is understandable that the first chip die can also read the first operating system from the off-chip memory and start it after the first chip boot program is started, and then push the second chip boot program and the second operating system to the second chip die.

[0091] The following still takes two chip dies as an example to describe the startup process of the chip dies in the multi-chip die system.

[0092] For example, see Figure 4 As shown, the startup process of the chip die includes:

[0093] 401: After the power-on reset is released, the respective MCUs of Die0 and Die1 read their respective chip boot codes (Bootcode) from the ROM in the chip die to start up.

[0094] 402: After the Bootcode of Die1 is started, Die1 reads the first chip boot program Bootloader of Die1 from Flash.

[0095] 403: The MCU of Die1 runs the first chip bootloader, and the first chip bootloader is started up.

[0096] 404: Die1 reads the second chip bootloader Bootloader of Die0 from Flash, and pushes it to the on-chip cache SRAM (ie, on-chip memory) of Die0 through Uart. Die0 will be notified after the push starts and is completed.

[0097] 405: Die0 waits for the second chip bootloader to be pushed to completion.

[0098] 406: The MCU of Die0 runs the second chip boot program Bootloader, the second chip boot program Bootloader starts successfully, and notifies Die1 of the successful startup status.

[0099] 407: Die1 reads the second operating system (OS) of Die0 from Flash, and pushes it to the on-chip cache SRAM of Die0 through Uart. Die0 will be notified after the push starts and is completed.

[0100] 408: Die0 waits for the second operating system OS to be pushed to completion.

[0101] 409: The MCU of Die0 runs the second operating system OS, the second operating system OS starts successfully, and notifies Die1 of the successful startup status.

[0102] 410: Die1 reads the first operating system OS of Die1 from Flash, and starts the first operating system OS.

[0103] It should be noted that after the power-on reset is removed, the Uart interconnected between the two Dies can be used, and data can be transmitted through Uart. In addition, in the chip startup process, the second chip bootloader Bootloader and the second operating system OS of Die0 are pushed by Die1 through Uart, which is suitable for chips that do not require high startup time. Since the Uart interface is a low-speed communication interface, the OS is usually large and takes a long time to push.

[0104] In some optional implementations, the first chip die and at least one second chip die are further provided with corresponding high-speed communication interfaces;

[0105] After the first chip die pushes the second chip boot program, the high-speed communication interface of the first chip die is initialized;

[0106] Initializing the high-speed communication interface of at least one second chip bare die after the at least one second chip bare die starts the second chip boot program;

[0107] The first chip die and at least one second chip die establish a communication link between the high-speed communication interface.

[0108] Exemplarily, there may be two groups of interfaces for interconnecting the first chip die and the second chip die, one group of interfaces is a low-speed communication interface, which is mainly used for data push, including firmware push; the other group is a D2D interface, which serves as a data path between the two Dies. Since the second operating system is relatively large, it will be relatively slow to push it using a low-speed communication interface. Therefore, after the second chip boot program is started, a communication link of the D2D interface can be established between the first chip die and the second chip die, so as to push the second operating system through the D2D interface. In this exemplary embodiment, since the D2D interface can be initialized after the Bootloader is started, the initialization program for the D2D interface can be incorporated into the Bootloader. Since the Bootloader is burned into the external memory Flash, it can be updated at any time, thereby increasing the flexibility of the D2D interface initialization.

[0109] In some optional implementations, after the at least one second chip die starts the second chip boot program, the first chip die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip die through the high-speed communication interface;

[0110] at least one second chip die loads and starts a second operating system from the on-chip memory;

[0111] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0112] The following still takes two chip dies as an example to describe the startup process of the chip dies in the multi-chip die system.

[0113] For example, Figure 5 As shown, the startup process of the two-chip bare die includes the following steps:

[0114] 501: After the power-on reset is released, the respective MCUs of Die0 and Die1 read their respective Bootcodes from the ROM in the Die to start up.

[0115] 502: After the chip boot code Bootcode of Die1 is started, Die1 reads the first chip boot program Bootloader of Die1 from Flash.

[0116] 503: The MCU of Die1 runs the first chip bootloader, and the first chip bootloader starts.

[0117] 504: Die1 reads the second chip bootloader Bootloader of Die0 from Flash, pushes it to the on-chip cache SRAM of Die0 through Uart, and notifies Die0 after the push starts and is completed.

[0118] 505: Die0 waits for the second chip boot program Bootloader to be pushed to completion.

[0119] 506: The MCU of Die0 runs the second chip boot program Bootloader, the second chip boot program Bootloader starts successfully, and notifies Die1 of the successful startup status.

[0120] 507: The second chip bootloader Bootloader of Die0 and the first chip bootloader Bootloader of Die1 simultaneously perform the initialization configuration in the Die, including the initialization of the D2D interface, and start the D2D interface negotiation and link establishment.

[0121] 508: The D2D interface link between Die0 and Die1 is established successfully.

[0122] 509: Die1 reads the second operating system OS of Die0 from Flash, pushes it to the on-chip cache SRAM of Die0 through the D2D interface, and notifies Die0 after the push starts and is completed.

[0123] 510: Die0 waits for the second operating system OS to be pushed to complete.

[0124] 511: The MCU of Die0 runs the second operating system OS, the second operating system OS starts successfully, and notifies Die1 of the successful startup status.

[0125] 512: Die1 reads the first operating system OS of Die1 from Flash, and starts the first operating system OS.

[0126] It should be noted that in the above chip startup process, the second chip bootloader Bootloader of Die0 is pushed through Uart, and the second operating system OS of Die0 is pushed by Die1 through the D2D interface, which is suitable for chips with high requirements for startup time. The D2D interface is a high-speed interface, and the OS is usually relatively large. Pushing the OS through the D2D interface can be completed in a very short time, shortening the chip startup time. Based on this exemplary embodiment and the aforementioned exemplary embodiment, the push of the operating system OS can select a low-speed communication interface such as Uart or a D2D interface as needed.

[0127] In some optional implementations, at least one second chip die is provided with a command register and a status register; the first chip die writes a command to the command register through a low-speed communication interface, and at least one second chip die reads the command written by the first chip die from the command register;

[0128] At least one second chip die writes a status to the status register, and the first chip die reads the status written by the at least one second chip die from the status register through the low-speed communication interface.

[0129] For example, the present application has at least the following three improvements compared to the related art:

[0130] First, add a low-speed communication interface such as Uart between Dies. In addition to the Uart interface, you can also use low-speed communication interfaces such as I2C, I3C, USB, etc., so as to save the sideband signal of the D2D interface. Taking Uart as an example, in the two Dies, the Uart interface needs to match the hardware function, such as Figure 3 In the example, Die1 is the Uart master device (Uart_M), and Die0 is the Uart slave device (Uart_S). The Uart slave device has bus access rights in Die0, and the read and write command operations received by the Uart slave device can directly access the cache SRAM and protocol register group COM_REG in Die0.

[0131] Secondly, the handshake protocol when Die0 pushes data to Die1 is used to ensure the reliability of data push.

[0132] Finally, Die1 pushes the second chip bootloader Bootloader and the second operating system OS to Die0, without Die0 having to read them.

[0133] In some optional implementations, the first chip die reads the status written in the status register, and after determining that at least one second chip die has completed loading and running the chip startup code, writes a command to start pushing the second chip boot program to the command register, and after pushing the second chip boot program, writes a command to complete pushing the second chip boot program to the command register;

[0134] The first chip bare die also reads the status written in the status register, and after determining that at least one second chip bare die has completed the startup of the second chip boot program, writes a command to start pushing the second operating system to the command register, and after pushing the second operating system, writes a command to complete pushing the second operating system to the command register.

[0135] As described above, the second chip die of the present application writes its own status to the status register, the first chip die reads the status of the second chip die from the status register, and decides whether to push the second chip boot program and / or the second operating system to the second chip die according to the status. At the same time, the first chip die also writes commands to the command register, including commands for starting and completing the push of the second chip boot program and / or the second operating system, and the second chip die can determine the start and completion of the push of the second chip boot program and / or the second operating system by reading the command register.

[0136] In some optional implementations, after the second chip die loads and starts the chip startup code, the status of completing the startup of the chip startup code is written to the status register;

[0137] At least one second chip bare die reads the command written in the command register, and after determining that the first chip bare die starts to push the second chip boot program and completes the pushing of the second chip boot program, loads and starts the second chip boot program from the on-chip memory, and also writes the status of completing the startup of the second chip boot program to the status register;

[0138] At least one second chip bare die reads the command written in the command register, and after determining that the first chip bare die starts pushing the second operating system and completes the pushing of the second operating system, loads and starts the second operating system from the on-chip memory, and also writes the status of completing the startup of the second operating system to the status register.

[0139] The following still takes the two-chip bare die system as an example to describe the process of using the status register and the command register to complete the handshake protocol during the bare die startup process.

[0140] Exemplarily, the following Table 1 shows the status or command written in the status register and the command register and the corresponding meaning.

[0141] Table 1

[0142]

[0143] This application uses a custom push handshake protocol to ensure reliable push completion. In this custom handshake protocol, Figure 3The COM_REG 306 register group of Die0 can be understood as a handshake register. The COM_REG register group includes the CMD command register group and the STATUS status register group. The bit width of the two registers can be defined as needed, such as 32 bits. In this application, the definitions of the CMD and STATUS register groups are shown in Table 1 above, and the handshake meaning of the register group can be defined according to the push handshake protocol. The CMD register is written by Die1 and read by Die0. This register group is used by Die1 to issue commands to Die0; the STATUS register is written by Die0 and read by Die1. This register group is used by Die0 to feedback status to Die1.

[0144] The COM_REG register group is combined with the firmware push process. The complete firmware push protocol process is as follows: Figure 6 As shown:

[0145] 601: Die1 starts the chip boot code Bootcode; Die0 starts the chip boot code Bootcode, the default value of the CMD register in Die0 is CMD_IDLE, indicating that there is no valid command, and the default value of the STATUS register is STATUS_IDLE, indicating the initial state.

[0146] 602: After the chip boot code Bootcode of Die1 is started, the first chip boot program Bootloader code of Die1 is read from Flash and started to run.

[0147] 603: After the chip boot code Bootcode of DieO is successfully started, the value of the STATUS register group is updated to STATUS_CODE_OK, indicating that the Bootcode is successfully started, and waits for the push of the second chip boot program Bootloader.

[0148] The first chip bootloader Bootloader running on Die1 reads the STATUS status of Die0 through Uart to determine whether the Bootcode of Die0 is successfully started. If the Bootcode of Die0 is successfully started, proceed to step 604; if the STATUS of Die0 stays in the STATUS_IDLE state, Die1 waits for a while and reads the STATUS status again. If the STATUS of Die0 stays in STATUS_IDLE for a long time, it means that Die0 fails to start the Bootcode. Die1 can write the CMD register of Die0 to CMD_RST_DIE through Uart to issue a command to reset Die0, reset Die1, and restart Die1.

[0149] It should be noted that Die1 in the following steps means "Bootloader running on Die1" and Die0 means "Bootcode running on Die0".

[0150] 604: Die1 writes CMD register of Die0 to CMD_LOAD_START through Uart, indicating that the second chip bootloader Bootloader of Die0 starts to be pushed.

[0151] When Die0 reads the CMD register as CMD_LOAD_START, it starts to receive the push of the second chip bootloader Bootloader.

[0152] 605: Die1 reads the second chip bootloader Bootloader of Die0 from Flash, and pushes it to the cache of Die0 through Uart until the push is completed.

[0153] The cache in Die0 receives the writing of the bootloader of the second chip.

[0154] 606: After Die1 completes pushing the second chip boot program Bootloader, Die1 writes the CMD register of Die0 to CMD_LOAD_OVER through Uart, indicating that the second chip boot program Bootloader has been pushed successfully.

[0155] When Die0 reads the CMD register as CMD_LOAD_OVER, it is learned that the cache has completed receiving the second chip boot program Bootloader.

[0156] 607: Die0 verifies the second chip bootloader Bootloader. If the verification succeeds, the STATUS register is updated to STATUS_LOAD_OK, and the second chip bootloader Bootloader is successfully started. If the verification fails, the STATUS register is updated to STATUS_LOAD_FAIL.

[0157] Die1 reads the STATUS register of Die0 through the Uart interface to determine whether the second chip bootloader of Die0 is successfully started. If the second chip bootloader of Die0 is successfully started, proceed to step 608; if the second chip bootloader of Die0 fails to verify and start, Die1 re-initiates the push of the second chip bootloader.

[0158] 608: The first chip bootloader Bootloader running in Die1 writes CMD register of Die0 to CMD_OS_START through Uart, indicating that the second operating system OS starts to be pushed.

[0159] When the second chip bootloader Bootloader running in Die0 reads the CMD register as CMD_OS_START, it starts to receive push notifications from the second operating system OS.

[0160] It should be noted that Die1 in the following steps means "Bootloader running on Die1" and Die0 means "Bootloader running on Die0".

[0161] 609: Die1 reads the second operating system OS of Die0 from Flash and pushes it to the cache of Die0 through Uart until the push is completed.

[0162] The cache in Die0 receives the write of the second operating system OS.

[0163] 610: After Die1 completes pushing the second operating system OS, Die1 writes the CMD register of Die0 to CMD_OS_OVER through Uart, indicating that the pushing of the second operating system OS is completed.

[0164] Die0 waits until the CMD register is CMD_OS_OVER, and then learns that the cache has completed receiving the second operating system OS.

[0165] 611: Die0 verifies the second operating system OS. If the verification succeeds, the STATUS register is updated to STATUS_OS_OK, and the second operating system OS is successfully started. If the verification fails, the STATUS register is updated to STATUS_OS_FAIL.

[0166] Die1 reads the STATUS register of Die0 through the Uart interface to determine whether the second operating system OS of Die0 is successfully started. If the second operating system OS of Die0 is successfully started, proceed to step 612; if the OS verification of Die0 fails, the startup fails, and Die1 re-initiates the push of the second operating system OS.

[0167] 612: Die1 loads the first operating system OS of Die1 from F1ash, and starts the first operating system OS.

[0168] It should be noted that for steps 608 to 611, the D2D interface can also be used for OS push. The CMD and STATUS register groups of Die0 can also be accessed through the D2D interface Die1. The push protocol process is the same. Only the D2D interface link is established before pushing, and the Uart interface is replaced by the D2D interface.

[0169] In the above exemplary embodiments, the reliable transmission protocol and corresponding process between multiple Dies are implemented by using the status register, command register and the corresponding defined status and command, thereby ensuring the reliability of the pushed data. In addition, the Die of the Uart master device can also manage other Dies through the Uart interface, such as obtaining the status of other Dies through the status register, and using the command register to directly issue a reset command, restart other Dies, etc.

[0170] The above-mentioned multi-chip bare die system proposed in this application is also applicable to the interconnection and chip startup of three or more Dies, that is, the second chip bare die may include one or more. If multiple second chip bare die are included, each second chip bare die has a corresponding low-speed communication interface with the first chip bare die. The push protocol in the above-mentioned two-chip bare die system is still applicable to systems with more than two.

[0171] For example, Figure 7 A multi-chip bare die system with three dies is shown, where 701 identifies the multi-chip bare die, 702 identifies three dies: Die0, Die1 and Die2, 703 identifies the off-chip Flash, that is, the off-chip memory, 704 identifies the Uart interconnection interface, 705 identifies the D2D interface between dies, and 706 identifies the CMD and STATUS registers used for the push protocol within the die.

[0172] Accordingly, see Figure 8 As shown, the present application exemplarily provides a chip startup method, which is performed in the above-mentioned multi-chip bare die system, and the method includes:

[0173] In step 801, a first chip bare die loads a first chip boot program from an off-chip memory and starts up;

[0174] In step 802, the first chip bare die reads the second chip boot program from the off-chip memory and pushes it to the on-chip memory of at least one second chip bare die through the low-speed communication interface;

[0175] In step 803, at least one second chip die loads and starts a second chip boot program from an on-chip memory.

[0176] In some optional implementations, the method further includes:

[0177] After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the low-speed communication interface;

[0178] at least one second chip die loads and starts a second operating system from the on-chip memory;

[0179] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0180] In some optional implementations, the method further includes:

[0181] After the first chip die pushes the second chip boot program, the high-speed communication interface of the first chip die is initialized;

[0182] Initializing the high-speed communication interface of at least one second chip bare die after the at least one second chip bare die starts the second chip boot program;

[0183] The first chip die and at least one second chip die establish a communication link between the high-speed communication interface.

[0184] In some optional implementations, the method further includes:

[0185] After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the high-speed communication interface;

[0186] at least one second chip die loads and starts a second operating system from the on-chip memory;

[0187] After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

[0188] In some optional implementations, the first chip bare die reads the second chip boot program from the off-chip memory and pushes it to the on-chip memory of at least one second chip bare die through the low-speed communication interface, including:

[0189] The first chip die reads the status of the status register set in the second chip die, and after determining that at least one second chip die has completed the loading and running of the chip startup code, writes a command to start pushing the second chip boot program to the command register set in the second chip die, and after pushing the second chip boot program, writes a command to complete pushing the second chip boot program to the command register.

[0190] In some optional implementations, after the at least one second chip die starts the second chip boot program, the first chip die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip die through the low-speed communication interface, including:

[0191] The first chip bare die reads the status of the status register set in the second chip bare die, and after determining that at least one second chip bare die has completed the startup of the second chip boot program, writes a command to start pushing the second operating system to the command register set in the second chip bare die, and after pushing the second operating system, writes a command to complete pushing the second operating system to the command register.

[0192] In some optional implementations, the method further includes:

[0193] After the second chip bare die loads and starts the completion chip startup code, the status of the completion startup chip startup code is written to the status register set in the second chip bare die;

[0194] At least one second chip bare die loads and starts a second chip boot program from an on-chip memory, including:

[0195] At least one second chip bare die reads the command written in the command register set in the second chip bare die, and after determining that the first chip bare die starts to push the second chip boot program and completes the pushing of the second chip boot program, loads and starts the second chip boot program from the on-chip memory, and also writes the status of completing the startup of the second chip boot program to the status register.

[0196] In some optional implementations, at least one second chip die loads and starts a second operating system from an on-chip memory, including:

[0197] At least one second chip bare die reads a command register set in the second chip bare die, and after determining that the first chip bare die starts to push the second operating system and completes the push of the second operating system, loads and starts the second operating system from the on-chip memory, and also writes the status of completing the startup of the second operating system to the status register set in the second chip bare die.

[0198] The above method can be implemented in the multi-chip bare die system provided in the above embodiment. The specific implementation method can refer to the description of the multi-chip bare die system in the above embodiment, which will not be repeated here.

[0199] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.

[0200] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A multi-chip bare die system, characterized in that: include: a first chip die and at least one second chip die; A corresponding low-speed communication interface is provided between the first chip die and the at least one second chip die; The first chip die is connected to an off-chip memory, and the second chip die is provided with an on-chip memory; After the first chip bare die loads and starts the first chip boot program from the off-chip memory, the second chip boot program is read from the off-chip memory and pushed to the on-chip memory of the at least one second chip bare die through the low-speed communication interface; The at least one second chip die loads and starts the second chip boot program from the on-chip memory.

2. The multi-chip bare die system according to claim 1, characterized in that: After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the low-speed communication interface; The at least one second chip die loads and starts the second operating system from the on-chip memory; After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

3. The multi-chip bare die system according to claim 1, characterized in that: The first chip die and the at least one second chip die are also provided with corresponding high-speed communication interfaces; After the first chip die pushes the second chip boot program, initializing the high-speed communication interface of the first chip die; After the at least one second chip bare die starts the second chip boot program, initializing the high-speed communication interface of the at least one second chip bare die; The first chip die and the at least one second chip die establish a communication link between the high-speed communication interface.

4. The multi-chip bare die system according to claim 3, characterized in that: After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the high-speed communication interface; The at least one second chip die loads and starts the second operating system from the on-chip memory; After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

5. The multi-chip bare die system according to any one of claims 1 to 4, characterized in that: The at least one second chip die is provided with a command register and a status register; the first chip die writes a command to the command register through the low-speed communication interface, and the at least one second chip die reads the command written by the first chip die from the command register; The at least one second chip die writes a status to the status register, and the first chip die reads the status written by the at least one second chip die from the status register through the low-speed communication interface.

6. The multi-chip bare die system according to claim 5, characterized in that: The first chip bare die reads the status written in the status register, and after determining that the at least one second chip bare die has completed loading and running the chip startup code, writes a command to start pushing the second chip boot program to the command register, and after pushing the second chip boot program, writes a command to complete pushing the second chip boot program to the command register; The first chip bare die also reads the status written in the status register, and after determining that the at least one second chip bare die has completed the startup of the second chip boot program, writes a command to start pushing the second operating system to the command register, and after pushing the second operating system, writes a command to complete pushing the second operating system to the command register.

7. The multi-chip bare die system according to claim 5, characterized in that: After the second chip bare die loads and starts the chip startup code, the second chip bare die writes the status of completing the startup of the chip startup code to the status register; The at least one second chip bare die reads the command written in the command register, and after determining that the first chip bare die starts to push the second chip boot program and completes the pushing of the second chip boot program, loads and starts the second chip boot program from the on-chip memory, and also writes a status of completing the startup of the second chip boot program to the status register; The at least one second chip bare die reads the command written in the command register, and after determining that the first chip bare die starts to push the second operating system and completes the pushing of the second operating system, loads and starts the second operating system from the on-chip memory, and also writes the status of completing the startup of the second operating system to the status register.

8. A chip startup method, characterized in that: The method is performed in a multi-chip bare die system according to any one of claims 1 to 7, and the method comprises: The first chip bare die loads the first chip boot program from the off-chip memory and starts; The first chip bare die reads the second chip boot program from the off-chip memory and pushes it to the on-chip memory of at least one second chip bare die through the low-speed communication interface; The at least one second chip die loads and starts the second chip boot program from the on-chip memory.

9. The chip startup method according to claim 8, characterized in that: The method further comprises: After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the low-speed communication interface; The at least one second chip die loads and starts the second operating system from the on-chip memory; After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

10. The chip startup method according to claim 8, characterized in that: The method further comprises: After the first chip die pushes the second chip boot program, the high-speed communication interface of the first chip die is initialized: After the at least one second chip bare die starts the second chip boot program, initializing the high-speed communication interface of the at least one second chip bare die; The first chip die and the at least one second chip die establish a communication link between the high-speed communication interface.

11. The chip startup method according to claim 10, characterized in that: The method further comprises: After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the high-speed communication interface; The at least one second chip die loads and starts the second operating system from the on-chip memory; After the first chip die pushes the second operating system, the first operating system is loaded and started from the off-chip memory.

12. The chip startup method according to claim 8, characterized in that: The first chip bare die reads the second chip boot program from the off-chip memory and pushes it to the on-chip memory of at least one second chip bare die through the low-speed communication interface, including: The first chip die reads the status of the status register set in the second chip die, and after determining that the at least one second chip die has completed the loading and running of the chip startup code, writes a command to start pushing the second chip boot program to the command register set in the second chip die, and after pushing the second chip boot program, writes a command to complete pushing the second chip boot program to the command register.

13. The chip startup method according to claim 9, characterized in that: After the at least one second chip bare die starts the second chip boot program, the first chip bare die reads the second operating system from the off-chip memory and pushes it to the on-chip memory of the at least one second chip bare die through the low-speed communication interface, including: The first chip bare die reads the status of the status register set in the second chip bare die, and after determining that the at least one second chip bare die has completed the startup of the second chip boot program, writes a command to start pushing the second operating system to the command register set in the second chip bare die, and after pushing the second operating system, writes a command to complete pushing the second operating system to the command register.

14. The chip startup method according to claim 8, characterized in that: The method further comprises: After the second chip bare die loads and starts the chip startup code, the status of completing the startup of the chip startup code is written to the status register set in the second chip bare die; The at least one second chip bare die loads and starts the second chip boot program from the on-chip memory, comprising: The at least one second chip bare die reads the command written in the command register set in the second chip bare die, and after determining that the first chip bare die starts to push the second chip boot program and completes the pushing of the second chip boot program, loads and starts the second chip boot program from the on-chip memory, and also writes the status of completing the startup of the second chip boot program to the status register.

15. The chip startup method according to claim 9, characterized in that: The at least one second chip die loads and starts the second operating system from the on-chip memory, comprising: The at least one second chip die reads a command register set in the second chip die, and after determining that the first chip die starts to push the second operating system and completes the pushing of the second operating system, loads and starts the second operating system from the on-chip memory, and also writes the status of completing the startup of the second operating system to a status register set in the second chip die.

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