Driving circuit

Abstract

The invention relates to a driving circuit, the driving circuit comprises a control module, a first output module and a second output module, and the second output module comprises a first output sub-module and a first control sub-module; the control module is connected with the first output module and the first output sub-module, and is also connected with the first control sub-module, and the first control sub-module is also connected with the first output sub-module; the control module is used for controlling the first output module to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used for controlling the second output module to output a second signal with the first control sub-module under the control of the first input signal, the clock signal, the first control signal and a second control signal; the first signal and the second signal are different in frequency. The driving circuit provided by the invention can output two signals with different frequencies at the same time without adding extra signals, so that the size of a frame is increased.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a driving circuit. Background Art

[0002] OLEDs (Organic Light Emitting Diodes) can reduce the power consumption of the display screen at low display frequencies. During OLED display, the display module is typically divided into a write frame and a hold frame. The write frame is used for writing and storing data, while the hold frame does not write data and controls light emission using stored signals. Therefore, during the hold frame, part of the signal is converted from an AC clock signal to a DC clock signal.

[0003] In order to ensure normal display of the display screen, it is necessary to add additional control signals or clock signals. In traditional technology, additional signal generating circuits are usually added to generate additional control signals or clock signals, which results in an increase in the size of the display panel frame. Summary of the Invention

[0004] Based on this, it is necessary to provide a driving circuit to address the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a driving circuit, comprising: a control module, a first output module, and a second output module, wherein the second output module comprises a first output submodule and a first control submodule; the control module is connected to both the first output module and the first output submodule, and is also connected to the first control submodule, and the first control submodule is also connected to the first output submodule;

[0006] A control module is used to control the first output module to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used to control the second output module to output a second signal under the control of the first input signal, the clock signal, the first control signal and the second control signal together with the first control submodule; the frequencies of the first signal and the second signal are different.

[0007] In a second aspect, an embodiment of the present application provides a driving circuit, including a control module, a first output module, and a second output module, wherein the second output module includes a fifth output unit and a sixth output unit; the control module is connected to both the first output module and the fifth output unit, the first output module is connected to the sixth output unit, and the fifth output unit is connected to the sixth output unit;

[0008] The control module is used to control the first output module to output a first signal and the second output module to output a second signal under the control of the first input signal, the second input signal, the first control signal and the clock signal, and the frequencies of the first signal and the second signal are different.

[0009] In a third aspect, an embodiment of the present application provides a driving circuit, comprising: a control module, a first output module, and a second output module, wherein the second output module comprises a second output submodule and a third control submodule; the control module is connected to both the first output module and the second output submodule, and the second output submodule is further connected to both the first output module and the third control submodule;

[0010] A control module is used to control the first output module to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used together with a third control submodule to control the second output module to output a second signal under the control of the first input signal, the first control signal and the clock signal; the frequencies of the first signal and the second signal are different.

[0011] In a fourth aspect, an embodiment of the present application provides a scanning driving circuit, comprising a plurality of cascaded driving circuits such as those provided in the first aspect, the driving circuits provided in the second aspect, and any one of the driving circuits provided in the third aspect; the output signal of the first output module of the previous driving circuit among the multiple driving circuits is the input signal of the next driving circuit.

[0012] The embodiment of the present application provides a driving circuit, which includes a control module, a first output module and a second output module, the second output module includes a first output submodule and a first control submodule; the control module is connected to both the first output module and the first output submodule, and is also connected to the first control submodule, and the first control submodule is also connected to the first output submodule; the control module is used to control the first output module to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used to control the second output module to output a second signal under the control of a first input signal, a clock signal, a first control signal and a second control signal with the first subcontrol module; the frequencies of the first signal and the second signal are different. The driving circuit provided in this embodiment includes two output modules (a first output module and a second output module), and the control module is controlled by a first input signal, a clock signal, a first control signal and a second control signal to control the two output modules to output a first signal and a second signal with different frequencies, respectively, so that the transistor source potential in the low-frequency pixel circuit can be reset without adding an additional signal generating circuit to generate an additional control signal or clock signal, thereby improving the low-frequency display effect. Moreover, the size of the display panel frame will not be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of a display circuit provided by one embodiment;

[0014] Figure 2 A schematic diagram of output current provided for one embodiment;

[0015] Figure 3 A schematic diagram of a display circuit provided for another embodiment;

[0016] Figure 4 A schematic diagram of output current provided for another embodiment;

[0017] Figure 5 A schematic structural diagram of a driving circuit provided in one embodiment;

[0018] Figure 6 A schematic structural diagram of a driving circuit provided in another embodiment;

[0019] Figure 7 A schematic structural diagram of a driving circuit provided in another embodiment;

[0020] Figure 8 A timing diagram of a driving circuit provided in one embodiment;

[0021] Figure 9 A schematic diagram of a waveform of an output signal of a driving circuit provided in one embodiment;

[0022] Figure 10 A schematic structural diagram of a driving circuit provided in another embodiment;

[0023] Figure 11 A timing diagram of a driving circuit provided in another embodiment;

[0024] Figure 12 A schematic structural diagram of a driving circuit provided in another embodiment;

[0025] Figure 13 A timing diagram of a driving circuit provided in another embodiment;

[0026] Figure 14 A schematic diagram of a waveform of an output signal of a driving circuit provided in another embodiment;

[0027] Figure 15 A schematic diagram of a scan driving circuit provided by an embodiment;

[0028] Figure 16 A schematic diagram of a scan driving circuit provided in another embodiment;

[0029] Figure 17 A schematic diagram of a pixel circuit provided by one embodiment;

[0030] Figure 18 A timing diagram of a pixel circuit provided by one embodiment;

[0031] Figure 19A schematic diagram of the layout of a driving circuit provided in one embodiment;

[0032] Figure 20 A schematic diagram of a layout of a driving circuit provided in another embodiment;

[0033] Figure 21 A timing diagram of a driving circuit provided in another embodiment;

[0034] Figure 22 A schematic structural diagram of a driving circuit provided in another embodiment;

[0035] Figure 23 A timing diagram of a driving circuit provided in another embodiment;

[0036] Figure 24 A schematic diagram of a scan driving circuit provided in another embodiment.

[0037] Description of reference numerals:

[0038] 10. Drive circuit; 20. Drive circuit; 30. Drive circuit; 100. Control module; 200. First output module; 300. Second output module; 310. First output submodule; 320. First control submodule; 311. First output unit; 312. Second output unit; 210. Third output unit; 220. Fourth output unit; 110. Input submodule; 120. Second control submodule; 330. Fifth output unit; 340. Sixth output unit; 350. Second output submodule; 360. Third control submodule. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0040] The serial numbers assigned to the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning.

[0041] First of all, before introducing the technical solutions of the embodiments disclosed in the present application in detail, the background technology or technology evolution context on which the embodiments of the present application are based is introduced. In the OLED (Organic Light Emitting Diode) display industry, the pursuit of picture quality has never stopped, and the refresh frequency of the screen has repeatedly broken new highs. In addition, the reduction of screen power consumption is also continuing, low-frequency display continues to break through, and screen logic power consumption continues to decrease. In the OLED display process, the display module is usually divided into a writing frame (Data writing frame) and a keeping frame (Data keeping frame). The writing frame is used for writing and storing data. Data is not written in the keeping frame, and the stored signal controls the pixel unit to emit light. Therefore, in the keeping frame, part of the signal is converted from an AC clock signal to a DC signal, and the power consumption of the control chip (IC) and the screen body is reduced. Conventional such as Figure 1 In the 7T1C display circuit shown in the figure, when the output transistor is under the action of the voltage difference pressure for a long time, the output current of the write frame and the hold frame will differ, causing the brightness to change, that is, the screen flicker, as shown in the figure. Figure 2 As shown. Low frequency display circuit 8T1C is as follows Figure 3 As shown, or other circuits with transistor source reset function, have better display effect at low frequency, by constantly resetting the potential of the output transistor source, the output current of the write frame and the hold frame are kept consistent, such as Figure 4 As shown. Since the low-frequency pixel circuit timing is divided into a writing frame and a holding frame, it is necessary to add an additional control signal or clock signal to reset the source voltage of the transistor to prevent the current output of the writing frame and the holding frame from being different under the low-frequency long-term stress state, resulting in brightness differences between different frames. However, the working states of the control signals and clock signals of the writing frame and the holding frame are inconsistent. For example: when writing the frame, all the clock signals of the pixel circuit are AC signals; when holding the frame, the clock signal for controlling the writing of data by the pixel circuit is changed to output a continuous high-voltage DC signal. The added additional clock signal needs to still output an AC signal to reset the stress state of the transistor, which results in the added additional control signal clock signal being unable to be shared with the original signal. In the traditional technology, an additional driving circuit is added to output the newly added clock signal or control signal. However, this will increase the frame size of the display panel, which is not conducive to the trend of narrow frame, resulting in insufficient space or compressing smaller line width and line spacing to increase impedance and power consumption. In this regard, the present application provides a driving circuit.

[0042] The technical solution of the present application and how the technical solution of the present application solves the technical problem are described in detail below with specific embodiments.

[0043] In one embodiment, Figure 5As shown, a driving circuit 10 is provided, including a control module 100, a first output module 200 and a second output module 300; the second output module 300 includes a first output submodule 310 and a first control submodule 320; the control module 100 is connected to both the first output module 200 and the first output submodule 310, and is also connected to the first control submodule 320, and the first control submodule 320 is also connected to the first output submodule 310.

[0044] The control module 100 is used to control the first output module 200 to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used to control the second output module 300 to output a second signal under the control of the first input signal, the clock signal, the first control signal and the second control signal together with the first control submodule 320; the frequencies of the first signal and the second signal are different.

[0045] The control module 100 includes a first terminal, a second terminal, and a third terminal. The first output submodule 310 includes two control terminals. The first control submodule 320 includes a first terminal and a second terminal. The first terminal of the control module 100 is connected to the first output module 200, the second terminal of the control module 100 is connected to one control terminal of the first output submodule 310, and the third terminal of the control module 100 is connected to the first terminal of the first control submodule 320. The other control terminal of the first output submodule 310 is connected to the second terminal of the first control submodule 320.

[0046] The first input signal, the clock signal, the first control signal, and the second control signal can all be periodic pulse signals. The input to the control module 100 can include multiple clock signals. After the first input signal, the clock signal, and the first control signal are input to the control module 100, the control module 100 controls the first output module 200 to output the first signal (out1), and simultaneously inputs the second control signal to the first control submodule 320, so that the control module 100 and the first control submodule 320 simultaneously control the second output module 300 to output the second signal (out2). In other words, the drive circuit 10 includes two output terminals, which respectively output the first signal and the second signal. Through the control of the control module 100 and the first control submodule 320, the frequencies of the output first signal and the second signal are different. This embodiment does not limit the specific structure of the control module 100, the first output module 200, the first output submodule 310, and the first control submodule 320, as long as their functions can be achieved.

[0047] In other words, when writing a frame, the control module 100 controls the first output module 200 to input a first signal to the pixel circuit using the input first input signal, clock signal, and first control signal. When holding a frame, the control module 100 and the first control submodule 320 control the second output module 300 to input a second signal to the pixel circuit using the input first input signal, clock signal, first control signal, and second control signal, so that the writing frame and the holding frame output signals of different frequencies, respectively.

[0048] The driving circuit 10 provided in the embodiment of the present application includes a control module 100, a first output module 200 and a second output module 300, and the second output module 300 includes a first output sub-module 310 and a first control sub-module 320; the control module 100 is connected to both the first output module 200 and the first output sub-module 310, and is also connected to the first control sub-module 320, and the first control sub-module 320 is also connected to the first output sub-module 310; the control module 100 is used to control the first output module 200 to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used to control the second output module 300 to output a second signal under the control of the first input signal, the clock signal, the first control signal and the second control signal together with the first control sub-module 320; the frequencies of the first signal and the second signal are different. The driving circuit 10 provided in this embodiment includes two output modules (a first output module 200 and a second output module 300). Under the control of a first input signal, a clock signal, a first control signal, and a second control signal, the control module 100 can control the two output modules to respectively output a first signal and a second signal having different frequencies. This allows the transistor source potential in a low-frequency pixel circuit to be reset, thereby improving low-frequency display effects, without adding an additional signal generating circuit to generate an additional control signal or clock signal. Furthermore, the display panel frame size will not be increased.

[0049] In one embodiment, Figure 6 As shown, the first output submodule 310 includes a first output unit 311 and a second output unit 312; the first end of the first output unit 311 is connected to the control module 100, the second end of the first output unit 311 is used to input a high potential, the first end of the second output unit 312 is connected to the first control submodule 320, the second end of the second output unit 312 is used to input a first clock signal, and the third end of the first output unit 311 is connected to the third end of the second output unit 312.

[0050] The first output unit 311 includes a first terminal, a second terminal, and a third terminal. The second output unit 312 also includes a first terminal, a second terminal, and a third terminal. The first terminal of the first output unit 311 is connected to the control module 100 as a control terminal of the first output submodule 310. The second terminal of the first output unit 311 is used to input the high voltage VGH. The third terminal of the first output unit 311 is connected to the third terminal of the second output unit 312. The first terminal of the second output unit 312 is connected to the first control submodule 320 as another control terminal of the first output submodule 310. The second terminal of the second output unit 312 is used to input the first clock signal.

[0051] Under the control of the first input signal, the first clock signal, the first control signal, and the second control signal, the control module 100 and the first control submodule 320 control the first output unit 311 and the second output unit 312 to jointly output the second signal. This embodiment does not limit the specific structures of the first output unit 311 and the second output unit 312, as long as their functions can be achieved.

[0052] In this embodiment, the first output submodule 310 includes a first output unit 311 and a second output unit 312 . Such a first output submodule 310 has a simple structure.

[0053] Please continue to see Figure 6 In one embodiment, the first output unit 311 includes a first transistor T1, and the second output unit 312 includes a first capacitor C1 and a second transistor T2.

[0054] The first end of the first transistor T1 is connected to the control module 100 , the second end of the first transistor T1 is used to input the high potential VGH, and the third end of the first transistor T1 is connected to the third end of the second output unit 312 ;

[0055] The first end of the first capacitor C1 is connected to the first control submodule 320, the second end of the first capacitor C1 is connected to the third end of the second output unit 312, the first end of the second transistor T2 is connected to the first end of the first capacitor C1, the second end of the second transistor T2 is used to input the first clock signal SCK1, and the third end of the second transistor T2 is connected to the second end of the first capacitor C1.

[0056] The first end (control end) of the first transistor T1 is connected to the control module 100 as the first end of the first output unit 311, the second end of the first transistor T1 is used to input the high potential VGH, and the third end of the first transistor T1 is connected to the third end of the second output unit 312 as the third end of the first output unit 311.

[0057] The first end of the first capacitor C1 is connected to the first control submodule 320 as the first end of the second output unit 312. The second end of the first capacitor C1 is connected to the third end of the second output unit 312, that is, it is also connected to the third end of the first output unit 311. The first end of the second transistor T2 is connected to the first end of the first capacitor C1, that is, it is also connected to the first control submodule 320. The second end of the second transistor T2 is used to input the first clock signal SCK1. The third end of the second transistor T2 is connected to the second end of the first capacitor C1, that is, it is also connected to the third end of the first output unit 311. The first capacitor C1 is used to store a signal and discharges to provide a signal to the second transistor T2 when the first control submodule 320 is disconnected.

[0058] In this embodiment, the first output unit 311 includes a first transistor T1, and the second output unit 312 includes a first capacitor C2 and a second transistor T1. The structures of the first output unit 311 and the second output unit 312 are simple, and the capacitors and transistors are readily available at low cost, thereby improving the practicality of the driving circuit 10.

[0059] Please continue to see Figure 6 In one embodiment, the first control submodule 320 includes: a third transistor T3; a first end of the third transistor T3 is used to input the second control signal SW2, a second end of the third transistor T3 is connected to the control module 100, and a third end of the third transistor T3 is connected to the first output submodule 310.

[0060] The second end of the third transistor T3 is connected to the control module 100 as the first end of the first control submodule 320, and the third end of the third transistor T3 is connected to the first output submodule 310 as the second end of the first control submodule 320. The third transistor T3 is turned on or off under the control of the second control signal SW2, and works together with the control module 100 to control the first output submodule 310 to output the second signal.

[0061] In this embodiment, the first control submodule 320 includes a third transistor T3. The first control submodule 320 has a simple structure, and the third transistor T3 is easy to obtain and has low cost, so that the driving circuit 10 has higher practicality.

[0062] Please continue to see Figure 6In one embodiment, the first output module 200 includes a third output unit 210 and a fourth output unit 220; a first end of the third output unit 210 is connected to the control module 100, and a second end of the third output unit 210 is used to input a high potential VGH; a first end of the fourth output unit 220 is connected to the control module 100, and a second end of the fourth output unit 220 is used to input a first clock signal SCK1; a third end of the fourth output unit 220 is connected to a third end of the third output unit 210.

[0063] The first end of the third output unit 210 and the first end of the fourth output unit 220 are both connected to the control module 100 and are configured to receive control signals transmitted by the control module 100. The second end of the third output unit 210 is configured to input a high voltage VGH, and the second end of the fourth output unit 220 is configured to input a first clock signal. The third end of the third output unit 210 is connected to the third end of the fourth output unit 220. In other words, the third end of the third output unit 210 and the third end of the fourth output unit 220 serve as output ends of the first output module 200, outputting the first signal. This embodiment does not limit the specific structures of the third output unit 210 and the fourth output unit 220, as long as they can achieve their intended functions.

[0064] In this embodiment, the first output module 200 includes a third output unit 210 and a fourth output unit 220. The first output module 200 has a simple structure and is easy to implement.

[0065] Please continue to see Figure 6 The third output unit 210 includes a second capacitor C2 and a fourth transistor T4, and the fourth output unit 220 includes a third capacitor C3 and a fifth transistor T5.

[0066] Wherein, a first end of the second capacitor C2 is connected to the control module 100, a second end of the second capacitor C2 is used to input a high potential VGH, a first end of the fourth transistor T4 is connected to the first end of the second capacitor C2, a second end of the fourth transistor T4 is used to input a high potential VGH, and a third end of the fourth transistor T4 is connected to a third end of the fourth output unit 220;

[0067] A first end of the third capacitor C3 is connected to the control module 100, a second end of the third capacitor C3 is connected to a third end of the third output unit 210, a first end of the fifth transistor T5 is connected to the first end of the third capacitor C3, a second end of the fifth transistor T5 is used to input the first clock signal SCK1, and a third end of the fifth transistor T5 is connected to the second end of the third capacitor C3.

[0068] The first end of the second capacitor C2 is connected to the control module 100 as the first end of the third output unit 210, and the second end of the second capacitor C2 is used to input the high potential VGH as the second end of the third output unit 210, and is connected to the second end of the fourth transistor T4, that is, the second end of the fourth transistor T4 is also used to input the high potential VGH. The first end (control end) of the fourth transistor T4 is connected to the first end of the second capacitor C2, that is, connected to the control module 100. The control signal input by the control module 100 to the fourth transistor T4 can control the on and off of the fourth transistor T4. The third end of the fourth transistor T4 is connected to the third end of the fourth output unit 220 as the third end of the third output unit 210. The second capacitor C2 is used to store a signal to discharge and provide a signal to the fourth transistor T4 when the control module 100 does not input a control signal to the fourth transistor T4.

[0069] The first end of the third capacitor C3 is connected to the control module 100 as the first end of the fourth output unit 220, and the second end of the third capacitor C3 is connected to the third end of the third output unit 210 as the third end of the fourth output unit 220. The first end (control end) of the fifth transistor T5 is connected to the first end of the third capacitor C3, that is, also connected to the control module 100. The control signal input by the control module 100 to the fifth transistor T5 can control the on and off of the fifth transistor T5. The second end of the fifth transistor T5 is used to input the first clock signal SCK1. When the fifth transistor T5 is turned on, the first clock signal SCK1 can be output by the fifth transistor T5. The third end of the fifth transistor T5 is connected to the second end of the third capacitor C3, that is, also connected to the third end of the third output unit 210. The third capacitor C3 is used to store a signal to discharge and provide a signal to the fifth transistor T5 when the control module 100 does not input a control signal to the fifth transistor T5.

[0070] In this embodiment, the third output unit 210 includes a second capacitor C2 and a fourth transistor T2, and the fourth output unit 220 includes a third capacitor C3 and a fifth transistor T5. The third output unit 210 and the fourth output unit 220 have simple structures, and the capacitors and transistors are readily available at low cost, thereby improving the practicality of the driving circuit 10.

[0071] In one embodiment, Figure 7 As shown, the control module 100 includes an input submodule 110 and a second control submodule 120, the first end of the input submodule 110 is used to input the second clock signal SCK2, the second end of the input submodule 110 is used to input the first input signal SIN1, and the third end of the input submodule 110 is connected to the input end of the second control submodule 120.

[0072] The control end of the second control submodule 120 is used to input the first clock signal SCK1, the second clock signal SCK2, the first control signal SW1 and the high potential VGH. The output end of the second control submodule 120 is connected to the first output module 200, the first output submodule 310 and the first control submodule 320.

[0073] The input submodule 110 includes a first terminal, a second terminal, and a third terminal, while the second control submodule 120 includes an input terminal, a control terminal, and an output terminal. The first terminal of the input submodule 110 is used to input the second clock signal SCK2, the second terminal of the input submodule 110 is used to input the first input signal SIN1, and the third terminal of the input submodule 110 is connected to the input terminal of the second control submodule 120. The control terminal of the second control submodule 120 is respectively used to input the first clock signal SCK1, the second clock signal SCK2, the first control signal SW1, and the high voltage VGH required for control. The output terminal of the second control submodule 120 is connected to the first output module 200, the first output submodule 310, and the first control submodule 320.

[0074] The second control submodule 120 is configured to, under the control of the first clock signal SCK1, the second clock signal SCK2, the first control signal SW1, the second control signal SW2, the high voltage VGH, and the first input signal SIN1 input via the input submodule 110, work with the first control submodule 320 to control the first output module 200 to output the first signal and the second output module 300 to output the second signal. This embodiment does not impose any limitation on the specific structures of the input submodule 110 and the second control submodule 120, as long as their functions can be achieved.

[0075] In this embodiment, the control module 100 includes an input submodule 110 and a second control submodule 120. That is, the first output module 200 and the second output module 300 respectively output a first signal and a second signal through the joint control of the input submodule 110 and the second control submodule 120. Such a control module 100 has a simple structure and is easy to implement, making the drive circuit 10 highly practical.

[0076] Please continue to see Figure 7 In one embodiment, the input submodule 110 includes at least one sixth transistor T6, a first end of the sixth transistor T6 is used to input the second clock signal SCK2, a second end of the sixth transistor T6 is used to input the first input signal SIN1, and a third end of the sixth transistor T6 is connected to the first end of the second control submodule 120.

[0077] The input submodule 110 may include one sixth transistor T6, or may include multiple sixth transistors T6. When the input submodule 110 includes one sixth transistor T6, a first end of the sixth transistor T6 serves as the first end of the input submodule 110 for inputting the second clock signal SCK2, a second end of the sixth transistor T6 serves as the second end of the input submodule 110 for inputting the first input signal SIN1, and a third end of the sixth transistor T6 serves as the third end of the input submodule 110 for inputting the first input signal SIN1.

[0078] In the case where the input submodule 110 includes multiple sixth transistors T6, the first ends of the multiple sixth transistors T6 are all used to input the second clock signal SCK2, and the multiple sixth transistors T6 are cascaded, that is, the second end of the first sixth transistor T6 is used to input the first input signal SIN1, the third end of the first sixth transistor T6 is connected to the second end of the second sixth transistor T6, the third end of the second sixth transistor T6 is connected to the second end of the third sixth transistor T6, and so on. The third end of the last sixth transistor T6 serves as the third end of the input submodule 110 and is connected to the first end of the second control submodule 120.

[0079] In this embodiment, the input submodule 110 includes at least one sixth transistor T6. The input submodule 110 has a simple structure, and transistors are easily available and low in cost, so that the driving circuit 10 has higher practicality.

[0080] Please continue to see Figure 7 The second control submodule 120 includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; a first end of the seventh transistor T7 is connected to the third end of the input submodule 110, a second end of the seventh transistor T7 is used to input the first clock signal SCK1, and a third end of the seventh transistor T7 is connected to the first end of the eighth transistor T8;

[0081] The second end of the eighth transistor T8 is used to input the high potential VGH, the third end of the eighth transistor T8 is connected to the first end of the ninth transistor T9, the second end of the ninth transistor T9 is used to input the second clock signal SCK2, and the third end of the ninth transistor T9 is connected to the first end of the tenth transistor T10; the second end of the tenth transistor T10 is used to input the first control signal SW1, and the third end of the tenth transistor T10 is connected to the first output module 200;

[0082] A first end of the eleventh transistor T11 is connected to the third end of the eighth transistor T8 , a second end of the eleventh transistor T11 is used to input the second clock signal SCK2 , and a third end of the eleventh transistor T11 is used to input the low potential VGL.

[0083] The second control submodule 120 includes a plurality of transistors, namely a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11. The second control submodule 120 controls the on and off of each transistor using the first input signal, the first clock signal, the second clock signal, and the first control signal, so that each transistor inputs a control signal to the first output module 200 and the second output module 300, causing the first output module 200 and the second output module 300 to output the first signal and the second signal, respectively.

[0084] In this embodiment, the second control submodule 120 includes a plurality of transistors, which has a simple structure. Transistors are easy to obtain and have low cost, thereby improving the practicality of the driving circuit 10 .

[0085] In one embodiment, a driving method applied to the driving circuit 10 is provided, the method comprising:

[0086] Under the control of the first input signal, the first clock signal, the second clock signal, the first control signal and the second control signal, the first output module is controlled to output the first signal and the second output module is controlled to output the second signal; the frequencies of the first signal and the second signal are different.

[0087] Among them, the low-level pulse signal in each cycle of the first input signal corresponds to the low-level pulse signal in the second clock signal, and the low-level pulse signal in each cycle of the first input signal corresponds to the high-level pulse signal in the first clock signal; the first control signal is a low-level signal, and the second control signal changes from a low level to a high level when triggering a low-level pulse signal in the second cycle of the first input signal.

[0088] The timing diagram of the first input signal, the first clock signal, the second clock signal, the first control signal and the second control signal, and the first signal output by the first output module and the second signal output by the second output module is as shown in FIG. Figure 8 shown. Figure 8, which shows the pulse waveforms of the first clock signal, the second clock signal, the first control signal, and the second control signal in two cycles of the first input signal. In the first cycle of the first input signal (i.e., the write frame of the display module), the first control signal and the second control signal are both low-level pulse signals, and the low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal, and the high-level pulse signal corresponding to the first clock signal. In the second cycle of the first input signal (i.e., the hold frame of the display module), the first control signal is a low-level pulse signal, and the second control signal changes from a low level to a high level and remains at a high level when the first input signal triggers a low-level pulse signal; the low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal, and the high-level pulse signal corresponding to the first clock signal.

[0089] In such Figure 8 As shown in the timing diagram, Figure 7 The working process of the driving circuit 10 shown is as follows:

[0090] In phase ①, the first input signal is at a low level, the second clock signal is at a low level, the first clock signal is at a high level, and both the first control signal and the second control signal are at a low level. At this point, the sixth transistor T6 is on, the seventh transistor T7 is off, the eighth transistor T8 is on, the ninth transistor T9 is on, the tenth transistor T10 is on, the eleventh transistor T11 is on, the fourth transistor T4 is on, and the fifth transistor T5 is on. The first output module outputs a first signal, which is VGH and the first clock signal SCK1. In the second output module, the first transistor T1 is on, the second transistor T2 is on, and the third transistor T3 is on. The second output module outputs a second signal, which is VGH and the first clock signal SCK1.

[0091] In stage ②, the first input signal is high, the second clock signal is high, the first clock signal is low, and both the first control signal and the second control signal are low. At this point, the sixth transistor T6 is off, the seventh transistor T7 is on, the eighth transistor T8 is on, the ninth transistor T9 is off, the tenth transistor T10 is on, the eleventh transistor T11 is off, the fourth transistor T4 is off, and the first transistor T1 is off. In the first output module, the capacitor C3 maintains its potential, turning on the fifth transistor T5. The first output module outputs the first signal, which is the first clock signal. In the second output module, the capacitor C1 maintains its potential, turning on the second transistor T2. The second output module outputs the second signal, which is the first clock signal.

[0092] In phase ③, the first input signal is low, the second clock signal is low, the first clock signal is high, the first control signal is low, and the second control signal is high. At this point, the sixth transistor T6 is on, the seventh transistor T7 is off, the eighth transistor T8 is on, the ninth transistor T9 is on, the tenth transistor T10 is on, the eleventh transistor T11 is on, and both the fourth transistor T4 and the fifth transistor T5 are on. The first output module outputs the first signal, which is VGH and the first clock signal SCK1. The first transistor T1 in the second output module is on, the potential of capacitor C1 is maintained, the second transistor T2 is on, and the second output module outputs the second signal, which is VGH and the first clock signal SCK1.

[0093] In stage ④, the first input signal is high, the second clock signal is high, the first clock signal is low, the first control signal is low, and the second control signal is high. At this point, the sixth transistor T6 is off, the seventh transistor T7 is on, the eighth transistor T8 is on, the ninth transistor T9 is off, the tenth transistor T10 is on, the eleventh transistor T11 is off, and the fourth transistor T4 and the first transistor T1 are off. In the first output module, the potential of capacitor C3 is maintained, turning on the fifth transistor T5. The first output module outputs the first signal, which is the first clock signal. The second output module outputs the second signal, which is low.

[0094] The driving method provided in this embodiment is applied to the driving circuit 10 provided in the above embodiment. The driving method has all the beneficial effects of the driving circuit 10 and will not be described in detail here.

[0095] In an optional embodiment, the waveform of the signal output by the driving circuit 10 in the write frame and the hold frame is as follows: Figure 9 shown. Figure 9 The first four waveforms are waveforms of the first signal output by the first output module, and the last four waveforms are waveforms of the second signal output by the second output module.

[0096] In one embodiment, Figure 10 As shown, a driving circuit 20 is provided, including a control module 100, a first output module 200 and a second output module 300, the second output module 300 including a fifth output unit 330 and a sixth output unit 340; the control module 100 is connected to both the first output module 200 and the fifth output unit 330, the first output module 200 is connected to the sixth output unit 340, and the fifth output unit 330 is connected to the sixth output unit 340.

[0097] The control module 100 is used to control the first output module 200 to output a first signal and the second output module 300 to output a second signal under the control of a first input signal, a second input signal, a first control signal and a clock signal. The frequencies of the first signal and the second signal are different.

[0098] For the description of the control module 100 and the first output module 200 , reference may be made to the specific description in the above embodiments, which will not be repeated here.

[0099] The second output module 300 includes two output units: a fifth output unit 330 and a sixth output unit 340. The fifth output unit 330 includes a first terminal, a second terminal, and a third terminal. The sixth output unit 340 also includes a first terminal, a second terminal, and a third terminal. The first terminal (control terminal) of the fifth output unit 330 is connected to the control module 100. The second terminal of the fifth output unit 330 is used to input a high voltage. The third terminal of the fifth output unit 330 is connected to the third terminal of the sixth output unit 340. The first terminal of the sixth output unit 340 is used to input the second input signal. The second terminal of the sixth output unit 340 is connected to the first output module 200.

[0100] The first input signal, the second input signal, the first control signal, and the clock signal can all be periodic pulse signals. The inputs to the control module 100 may include multiple clock signals. When the first input signal, the clock signal, and the first control signal are input to the control module 100, and the second output signal is input to the sixth output unit 340, the control module 100 controls the first output module 200 to output the first signal and the second output module 300 to output the second signal. The first signal and the second signal have different frequencies. This embodiment does not limit the specific structure of the fifth output unit 330 and the sixth output unit 340, as long as their functions can be achieved.

[0101] In other words, the control module 100 can control the first output module 200 and the second output module 300 to output signals of different frequencies, so that different clock signals or control signals can be provided to the pixel circuit in the writing frame and the holding frame respectively.

[0102] The driving circuit 20 provided in the embodiment of the present application includes a control module 100, a first output module 200 and a second output module 300, the second output module 300 includes a fifth output unit 330 and a sixth output unit 340; the control module 100 is connected to both the first output module 200 and the fifth output unit 330, the first output module 200 is connected to both the fifth output unit 330 and the sixth output unit 340; the fifth output unit 330 is connected to the sixth output unit 340; the control module 100 is used to control the first output module 200 to output a first signal and control the second output module 300 to output a second signal under the control of a first input signal, a second input signal, a first control signal and a clock signal, and the frequencies of the first signal and the second signal are different. The driving circuit 20 provided in this embodiment includes two output modules, namely a first output module 200 and a second output module 300. Under the control of a first input signal, a second input signal, a clock signal, and a first control signal, the control module 100 can control the two output modules to respectively output a first signal and a second signal having different frequencies. This allows the transistor source potential in low-frequency pixel circuits to be reset, thereby improving low-frequency display effects, without adding an additional signal generating circuit to generate an additional control signal or clock signal. Furthermore, this does not increase the size of the display panel frame.

[0103] Please continue to see Figure 10 In one embodiment, the fifth output unit 330 includes a twelfth transistor T12, and the sixth output unit 340 includes a thirteenth transistor T13.

[0104] A first end of the twelfth transistor T12 is used to input a high potential, a second end of the twelfth transistor T12 is connected to the control module 100, and a third end of the twelfth transistor T12 is connected to a first end of the thirteenth transistor T13;

[0105] The second end of the thirteenth transistor T13 is used to input the second input signal SIN2 , and the third end of the thirteenth transistor T13 is connected to the first output module 200 .

[0106] The fifth output unit 330 includes a twelfth transistor T12, the first end of the twelfth transistor T12 serves as the second end of the fifth output unit 330 for inputting a high potential, the second end of the twelfth transistor T12 serves as the first end of the fifth output unit 330 and is connected to the control module 100, and the third end of the twelfth transistor T12 serves as the third end of the fifth output unit 330 and is connected to the third end of the sixth output unit 340.

[0107] The sixth output unit 340 includes a thirteenth transistor T13, the first end of the thirteenth transistor T13 is connected to the fifth output unit 330 as the third end of the sixth output unit 340, the second end of the thirteenth transistor T13 is used to input the second input signal SIN2 as the first end of the sixth output unit 340, and the third end of the thirteenth transistor T13 is connected to the first output module 200 as the second end of the sixth output unit 340.

[0108] In this embodiment, the fifth output unit 330 includes a twelfth transistor T12, and the sixth output unit 340 includes a thirteenth transistor T13. Such a fifth output unit 330 and sixth output unit 340 have simple structures, and transistors are easily available and low in cost, making the driving circuit 20 more practical.

[0109] In one embodiment, a driving method applied to the driving circuit 20 is provided, the method comprising:

[0110] Under the control of the first input signal, the second input signal, the first control signal, the first clock signal and the second clock signal, the first output module is controlled to output the first signal and the second output module is controlled to output the second signal; the frequencies of the first signal and the second signal are different;

[0111] Among them, the low-level pulse signal in each cycle of the first input signal corresponds to the low-level pulse signal in the second clock signal, the low-level pulse signal in each cycle of the first input signal corresponds to the high-level pulse signal of the first clock signal, and the high-level pulse signal in the second input signal corresponds to the second cycle of the first input signal.

[0112] The timing diagram of the first input signal, the second input signal, the first clock signal and the second clock signal is as follows: Figure 11 As shown (the first control signal is always a pulse signal of low level, not shown in the figure). Figure 11 The figure shows the pulse waveforms of the first clock signal, the second clock signal, and the second input signal in two cycles of the first input signal. In the first cycle of the first input signal (i.e., the write frame of the display module), the second input signal is at a low level; the low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal, and corresponds to the high-level pulse signal of the first clock signal. In the second cycle of the first input signal (i.e., the hold frame of the display module), the second input signal becomes a high level, the low-level pulse signal of the first input signal corresponds to the low-level pulse signal of the second clock signal, and corresponds to the high-level pulse signal of the first clock signal.

[0113] In such Figure 11 As shown in the timing diagram, Figure 10The working process of the driving circuit 20 shown is as follows:

[0114] In the first stage, the first input signal is at a low level, the second clock signal SCK2 is at a low level, the first clock signal SCK1 is at a high level, the second input signal SIN2 is at a low level, and the first control signal SW1 is at a low level; at this time, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the ninth transistor T9 is turned on, the eighth transistor T8 is turned on, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the twelfth transistor T12 and the thirteenth transistor T3 are also turned on, then the first output module outputs the first signal, the first signal is VGH and the first clock signal SCK1, and the second output module outputs the second signal, the second signal is VGH and the first clock signal SCK1.

[0115] In the second stage, the first input signal is high, the second clock signal SCK2 is high, the first clock signal SCK1 is high, the second input signal SIN2 is low, and the first control signal SW1 is low; at this time, the potentials of the capacitors C3 and C2 are maintained, the fourth transistor T4 and the fifth transistor T5 are turned on, the first output module outputs the first signal, the first signal is VGH and the first clock signal SCK1, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the second output module outputs the second signal, the second signal is 2 VGH and the first clock signal SCK1.

[0116] In stage ③, the first input signal is high, the second clock signal SCK2 is high, the first clock signal SCK1 is low, the second input signal SIN2 is low, and SW1 is low; at this time, the sixth transistor T6 is turned off, the seventh transistor T7 is turned on, the eighth transistor T8 is turned on, the ninth transistor T9 is turned off, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned off, the fourth transistor T4 and the fifth transistor T5 are turned off, the first output module outputs the first signal, the first signal is low, the twelfth transistor T12 and the thirteenth transistor are turned off, and the second output module outputs the second signal, the second signal is low.

[0117] In the fourth stage, the first input signal is at a low level, the second clock signal SCK2 is at a low level, the first clock signal SCK1 is at a high level, the second input signal SIN2 is at a high level, and the first control signal SW1 is at a low level; at this time, the sixth transistor T6 is turned on, the seventh transistor T7 is turned off, the ninth transistor T9 is turned on, the eighth transistor T8 is turned on, the tenth transistor T10 is turned on, the eleventh transistor T11 is turned on, the fourth transistor T4 and the fifth transistor T5 are both turned on, and the twelfth transistor T12 and the thirteenth transistor T3 are also turned on, then the first output module outputs the first signal, the first signal is VGH and the first clock signal SCK1, and the second output module outputs the second signal, the second signal is VGH.

[0118] In the fifth stage, the first input signal is high, the second clock signal SCK2 is high, the first clock signal SCK1 is high, the second input signal SIN2 is high, and the first control signal SW1 is low; at this time, the potentials of the capacitors C3 and C2 are maintained, the fourth transistor T4 and the fifth transistor T5 are turned on, the first output module outputs the first signal, the first signal is VGH and the first clock signal SCK1, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the second output module outputs the second signal, the second signal is 2 VGH.

[0119] The driving method provided in this embodiment is applied to the driving circuit provided in the above embodiment. The driving method has all the beneficial effects of the driving circuit, which will not be described in detail here.

[0120] In one embodiment, Figure 12 As shown, a driving circuit 30 is provided, including: a control module 100, a first output module 200 and a second output module 300, the second output module 300 including a second output submodule 350 and a third control submodule 360; the control module 100 is connected to both the first output module 200 and the second output submodule 350, and the second output submodule 350 is also connected to both the first output module 200 and the third control submodule 360;

[0121] The control module 100 is used to control the first output module 200 to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used together with the third control submodule 360 ​​to control the second output module 300 to output a second signal under the control of the first input signal, the clock signal and the first control signal; the frequencies of the first signal and the second signal are different.

[0122] For the description of the control module 100 and the first output module 200 , reference may be made to the specific description in the above embodiments, which will not be repeated here.

[0123] The second output module 300 includes a second output submodule 350 and a third control submodule 360. The second output submodule 350 includes a first terminal, a second terminal, and a third terminal, while the third control submodule 360 ​​includes a first terminal, a second terminal, and a third terminal. The first terminal of the second output submodule 350 is connected to the control module 100, the second terminal of the second output submodule 350 is connected to the first output module 200, and the third terminal of the second output submodule 350 is connected to the third terminal of the third control submodule 360. The first terminal of the third control submodule 360 ​​is connected to a low voltage, and the second terminal of the third control submodule 360 ​​is used to input a clock signal.

[0124] The first input signal, the clock signal, and the first control signal can all be periodic pulse signals. The first input signal, the clock signal, and the first control signal are input to the control module 100, and the clock signal is input to the third control submodule 360, so that the control module 100 controls the first output module 200 to output the first signal, and the control module 100 and the third control submodule 360 ​​control the second output submodule 350 to output the second signal. In other words, the control module 100 and the third control submodule 360 ​​can control the first output module 200 and the second output module 300 to output signals of different frequencies, so that different clock signals or control signals can be provided to the pixel circuit in the write frame and the hold frame, respectively.

[0125] The driving circuit 30 provided in the embodiment of the present application includes a control module 100, a first output module 200 and a second output module 300, and the second output module 300 includes a second output sub-module 350 and a third control sub-module 360; the control module 100 is connected to both the first output module 200 and the second output sub-module 350, and the second output sub-module 350 is also connected to both the first output module 200 and the third control sub-module 360; the control module 100 is used to control the first output module 200 to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used to control the second output module 300 to output a second signal under the control of the first input signal, the first control signal and the clock signal together with the third control sub-module 360; the frequencies of the first signal and the second signal are different. The driving circuit 30 provided in this embodiment includes two output modules, namely a first output module 200 and a second output module 300. Under the control of a first input signal, a clock signal, and a first control signal, the control module 100 can control the two output modules to respectively output a first signal and a second signal of different frequencies. This allows the transistor source potential in a low-frequency pixel circuit to be reset, thereby improving low-frequency display effects, without adding an additional signal generating circuit to generate an additional control signal or clock signal. Furthermore, the size of the display panel frame is not increased.

[0126] Please continue to see Figure 12In one embodiment, the third control submodule 360 ​​includes: a fourteenth transistor T14 and a fifteenth transistor T15, wherein a first end of the fourteenth transistor T14 is used to input the first clock signal SCK1, a second end of the fourteenth transistor T14 is used to input a low potential, and a third end of the fourteenth transistor T14 is connected to a first end of the fifteenth transistor T15;

[0127] A second end of the fifteenth transistor T15 is used to input the third clock signal SCK3 , and a third end of the fifteenth transistor T15 is connected to the second output submodule 350 .

[0128] The first end of the fourteenth transistor T14 serves as the second end of the third control submodule 360 ​​for inputting the first clock signal, the second end of the fourteenth transistor T14 serves as the first end of the third control submodule 360 ​​for inputting a low potential, and the third end of the fourteenth transistor T14 is connected to the first end of the fifteenth transistor T15.

[0129] The second end of the fifteenth transistor T15 serves as the second end of the third control submodule 360 ​​for inputting the third clock signal SCK3 , and the third end of the fifteenth transistor T15 serves as the third end of the third control submodule 360 ​​connected to the second output submodule 350 .

[0130] In this embodiment, the third control submodule 360 ​​includes a fourteenth transistor T14 and a fifteenth transistor T15. Such a third control submodule 360 ​​has a simple structure, and transistors are easily available and low in cost, so that the driving circuit 30 has higher practicality.

[0131] Please continue to see Figure 12 In one embodiment, the second output submodule 350 includes a sixteenth transistor T16 and a seventeenth transistor T17; a first end of the sixteenth transistor T16 is connected to the first output module 200, a second end of the sixteenth transistor T16 is connected to the control module 100, and a third end of the sixteenth transistor T16 is connected to a first end of the seventeenth transistor T17;

[0132] A second end of the seventeenth transistor T17 is connected to the control module 100 , and a third end of the seventeenth transistor T17 is connected to the third control submodule 360 ​​.

[0133] The first end of the sixteenth transistor T16 is connected to the first output module 200 as the second end of the second output submodule 350. The second end of the sixteenth transistor T16 is connected to the control module 100 as the first end of the second output submodule 350. The third end of the sixteenth transistor T16 is connected to the first end of the seventeenth transistor T17. The second end of the seventeenth transistor T17 is connected to the control module 100 as the second end of the second output submodule 350. The third end of the seventeenth transistor T17 is connected to the third control submodule 360 ​​as the third end of the second output submodule 350.

[0134] In this embodiment, the second output submodule 350 includes a sixteenth transistor T16 and a seventeenth transistor T17. Such a second output submodule 350 has a simple structure, and transistors are easily available and low in cost, so that the driving circuit 30 has higher practicality.

[0135] In one embodiment, a driving method applied to the driving circuit 30 provided in the above embodiment is provided, and the driving method includes:

[0136] Under the control of the input signal, the first clock signal, the second clock signal, the third clock signal and the first control signal, the first output module is controlled to output the first signal and the second output module is controlled to output the second signal; the frequencies of the first signal and the second signal are different;

[0137] Wherein, the low-level pulse signal in the first cycle of the first input signal corresponds to the high-level pulse signal in the second clock signal, the low-level pulse signal in each cycle of the first input signal corresponds to the low-level pulse signal of the first clock signal, and the low level in each cycle of the first input signal corresponds to the low-level pulse signal of the third clock signal;

[0138] The high-level pulse signal in the third clock signal corresponds to the second cycle of the first input signal.

[0139] The timing diagram of the first input signal, the first clock signal, the second clock signal, and the third clock signal is as follows: Figure 13 As shown (the first control signal is always a pulse signal of low level, not shown in the figure). Figure 13: Figure 2 shows a schematic diagram of the pulse waveforms of the first clock signal, the second clock signal, and the third clock signal in two cycles of the first input signal. In the first cycle of the first input signal (i.e., the write frame of the display module), the low-level pulse signal of the first input signal corresponds to the high-level pulse signal of the second clock signal, and the low-level pulse signal of the first clock signal, and the low-level pulse signal of the third clock signal. In the second cycle of the first input signal (i.e., the hold frame of the display module), the low-level pulse signal of the first input signal corresponds to the high-level pulse signal of the second clock signal, and corresponds to the low-level pulse signal of the first clock signal, and the third clock signal is a continuous high-level pulse signal.

[0140] In an optional embodiment, the waveform of the signal output by the driving circuit 10 in the write frame and the hold frame is as follows: Figure 14 shown. Figure 14 The first four waveforms are waveforms of the first signal output by the first output module, and the last four waveforms are waveforms of the second signal output by the second output module.

[0141] An embodiment of the present application provides a scan driving circuit, comprising a plurality of cascaded Figure 5 、 Figure 6 and Figure 7 The driving circuit 10 shown, as described above Figure 9 The driving circuit 20 shown and the above Figure 11 Any one of the driving circuits 30 shown; the output signal of the first output module of the previous driving circuit in the plurality of driving circuits is the input signal of the next driving circuit.

[0142] In the case where the scan driving circuit includes the driving circuit 10 or the driving circuit 20 provided in the above embodiment, the schematic diagram of the scan driving circuit is as follows: Figure 15 As shown, the scan driving circuit includes multiple driving circuits 10 or driving circuits 20, and the output signal of the first output module of the previous driving circuit is used as the input signal of the next driving circuit. Pixel represents pixel circuit, and EM represents driving circuit.

[0143] In the case where the scan driving circuit includes the driving circuit 30 provided in the above embodiment, the schematic diagram of the scan driving circuit is as follows: Figure 16 As shown, the scan driving circuit includes a plurality of cascaded driving circuits 30 .

[0144] The scanning driving circuit provided in this embodiment includes any one of the driving circuit 10, driving circuit 20 and driving circuit 30 provided in the above embodiments. The scanning driving circuit has all the beneficial effects of the above driving circuit 10, driving circuit 20 or driving circuit 30, which will not be repeated here.

[0145] An embodiment of the present application provides a display device, which includes the scan driving circuit provided in the above embodiment.

[0146] The display device further includes a pixel circuit, and the output signal of the scanning driving circuit serves as a control signal or a clock signal of the pixel circuit. Figure 17 As shown. S1, S2 and S3 are the input terminals of the pixel circuit. S1 and S2 input high frequency signals, and S3 input low frequency signals. The waveform diagram of the pixel circuit is shown in Figure 18 shown.

[0147] The display device provided in the embodiment of the present application includes a scan driving circuit, and the display device has all the beneficial effects of the scan driving circuit, which will not be described in detail here.

[0148] In conventional technology, different frequencies can be provided to the entire area of ​​a display device through a scan driver circuit and an emission (EM) driver circuit. In an optional embodiment, the scan driver circuit provided by this embodiment can be used to connect pixel circuits in different areas of a display device, so that different areas of the display device have different frequencies. The layout of the scan driver circuit and the EM driver circuit in the display device can be as follows: Figure 19 As shown, Figure 19 The black rectangle in the figure is the setting position of the EM drive circuit, and the gray rectangle is the setting position of the Scan drive circuit. Figure 19 It can be seen that the Scan driving circuit can be set at the display frame of the display device or in the middle of the display device. The Scan driving circuit can provide signals of different frequencies to the pixel circuits of the two areas connected to it, so that the display frequencies of the two areas are different. Figure 20 As shown, the left and right areas of the Scan driving circuit can display different frequencies. At the same time, the upper and lower areas on the left side of the Scan driving circuit can also display different frequencies. The three areas on the right side of the Scan driving circuit can also display different frequencies. If the upper and lower areas on the left side of the Scan driving circuit display different frequencies, the timing diagram of the driving circuit 10 is as follows Figure 21 shown.

[0149] In one embodiment, a Figure 22 The driving circuit shown in FIG. Figure 23 The scanning drive circuit includes multiple cascaded Figure 22In the driving circuit shown in FIG. 1 , the waveform of the clock signal input to one end of the nineteenth transistor T19 of the first driving circuit is SCK3, and the waveform of the clock signal input to one end of the nineteenth transistor T19 of the second driving circuit is SCK4, that is, the clock signals SCK3 and SCK4 are connected alternately, and so on. The schematic diagram of the scanning driving circuit is shown in FIG. Figure 24 shown.

[0150] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0151] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A driving circuit, characterized in that: include: A control module, a first output module and a second output module, wherein the second output module includes a first output submodule and a first control submodule; the control module is connected to both the first output module and the first output submodule, and is also connected to the first control submodule, and the first control submodule is also connected to the first output submodule; The control module is used to control the first output module to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used to control the second output module to output a second signal under the control of the first input signal, the clock signal, the first control signal and the second control signal together with the first control submodule; the frequencies of the first signal and the second signal are different.

2. The driving circuit according to claim 1, characterized in that: The first output submodule includes: a first output unit and a second output unit; the first end of the first output unit is connected to the control module, the second end of the first output unit is used to input a high potential, the first end of the second output unit is connected to the first control submodule, the second end of the second output unit is used to input a first clock signal, and the third end of the first output unit is connected to the third end of the second output unit.

3. The driving circuit according to claim 2, characterized in that: The first output unit includes a first transistor, and the second output unit includes: a first capacitor and a second transistor; Wherein, the first end of the first transistor is connected to the control module, the second end of the first transistor is used to input the high potential, and the third end of the first transistor is connected to the third end of the second output unit; The first end of the first capacitor is connected to the first control submodule, the second end of the first capacitor is connected to the third end of the second output unit, the first end of the second transistor is connected to the first end of the first capacitor, the second end of the second transistor is used to input a first clock signal, and the third end of the second transistor is connected to the second end of the first capacitor.

4. The driving circuit according to claim 1, characterized in that: The first control submodule includes: a third transistor; a first end of the third transistor is used to input the second control signal, a second end of the third transistor is connected to the control module, and a third end of the third transistor is connected to the first output submodule.

5. The driving circuit according to claim 1, characterized in that: The first output module includes a third output unit and a fourth output unit; the first end of the third output unit is connected to the control module, the second end of the third output unit is used to input a high potential, the first end of the fourth output unit is connected to the control module, the second end of the fourth output unit is used to input a first clock signal, and the third end of the fourth output unit is connected to the third end of the third output unit.

6. The driving circuit according to claim 5, characterized in that: The third output unit includes a second capacitor and a fourth transistor, and the fourth output unit includes a third capacitor and a fifth transistor; Wherein, the first end of the second capacitor is connected to the control module, the second end of the second capacitor is used to input the high potential, the first end of the fourth transistor is connected to the first end of the second capacitor, the second end of the fourth transistor is used to input the high potential, and the third end of the fourth transistor is connected to the third end of the fourth output unit; The first end of the third capacitor is connected to the control module, the second end of the third capacitor is connected to the third end of the third output unit, the first end of the fifth transistor is connected to the first end of the third capacitor, the second end of the fifth transistor is used to input the first clock signal, and the third end of the fifth transistor is connected to the second end of the third capacitor.

7. The driving circuit according to any one of claims 1 to 6, characterized in that: The control module comprises an input submodule and a second control submodule, the first end of the input submodule is used to input the second clock signal, the second end of the input submodule is used to input the first input signal, and the third end of the input submodule is connected to the input end of the second control submodule; The control end of the second control submodule is used to input a first clock signal, a second clock signal, the first control signal and a high potential, and the output end of the second control submodule is connected to the first output module, the first output submodule and the first control submodule.

8. The driving circuit according to claim 7, characterized in that: The input submodule includes: at least one sixth transistor, the first end of the sixth transistor is used to input the second clock signal, the second end of the sixth transistor is used to input the first input signal, and the third end of the sixth transistor is connected to the first end of the second control submodule.

9. The driving circuit according to claim 7, characterized in that: The second control submodule comprises: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor; a first end of the seventh transistor is connected to a third end of the input submodule, a second end of the seventh transistor is used to input the first clock signal, and a third end of the seventh transistor is connected to a first end of the eighth transistor; The second end of the eighth transistor is used to input the high potential, the third end of the eighth transistor is connected to the first end of the ninth transistor, the second end of the ninth transistor is used to input the second clock signal, and the third end of the ninth transistor is connected to the first end of the tenth transistor; the second end of the tenth transistor is used to input the first control signal, and the third end of the tenth transistor is connected to the first output module; The first end of the eleventh transistor is connected to the third end of the eighth transistor, the second end of the eleventh transistor is used to input a second clock signal, and the third end of the eleventh transistor is used to input a low potential.

10. A driving circuit, characterized in that: It includes a control module, a first output module and a second output module, wherein the second output module includes a fifth output unit and a sixth output unit; the control module is connected to both the first output module and the fifth output unit, the first output module is connected to the sixth output unit, and the fifth output unit is connected to the sixth output unit; The control module is used to control the first output module to output a first signal and control the second output module to output a second signal under the control of a first input signal, a second input signal, a first control signal and a clock signal, and the frequencies of the first signal and the second signal are different.

11. The driving circuit according to claim 10, characterized in that: The fifth output unit includes a twelfth transistor, and the sixth output unit includes a thirteenth transistor; The first end of the twelfth transistor is used to input a high potential, the second end of the twelfth transistor is connected to the control module, and the third end of the twelfth transistor is connected to the first end of the thirteenth transistor; The second end of the thirteenth transistor is used to input a second input signal, and the third end of the thirteenth transistor is connected to the first output module.

12. A driving circuit, characterized in that: include: A control module, a first output module and a second output module, wherein the second output module includes a second output submodule and a third control submodule; the control module is connected to both the first output module and the second output submodule, and the second output submodule is also connected to both the first output module and the third control submodule; The control module is used to control the first output module to output a first signal under the control of a first input signal, a clock signal and a first control signal, and is used together with the third control submodule to control the second output module to output a second signal under the control of the first input signal, the first control signal and the clock signal; the frequencies of the first signal and the second signal are different.

13. The driving circuit according to claim 12, characterized in that: The third control submodule comprises: a fourteenth transistor and a fifteenth transistor, wherein a first end of the fourteenth transistor is used to input a first clock signal, a second end of the fourteenth transistor is used to input a low potential, and a third end of the fourteenth transistor is connected to the first end of the fifteenth transistor; The second end of the fifteenth transistor is used to input a third clock signal, and the third end of the fifteenth transistor is connected to the second output submodule.

14. The driving circuit according to claim 12, characterized in that: The second output submodule includes a sixteenth transistor and a seventeenth transistor; the first end of the sixteenth transistor is connected to the first output module, the second end of the sixteenth transistor is connected to the control module, and the third end of the sixteenth transistor is connected to the first end of the seventeenth transistor; The second end of the seventeenth transistor is connected to the control module, and the third end of the seventeenth transistor is connected to the third control submodule.

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