Class AB operational amplifier

Abstract

The class AB operational amplifier comprises a first-stage operational amplification module; a second-stage operational amplification module; the first-stage operational amplifier module is connected with the second-stage operational amplifier module, the second-stage operational amplifier module is connected with the output module, and the second-stage operational amplifier module is provided with a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; the first transmission gate, the first transistor and the second transistor are connected in series to form a first circuit, the first transmission gate, the third transistor and the fourth transistor are connected in series to form a second circuit, and the output module is provided with a sixth transistor; the drain electrode of the sixth transistor is connected with the voltage output end, when the AB-type operational amplifier is in a low-power-consumption mode, the first transmission gate is opened, the first circuit and the second circuit are connected in parallel, and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor form a linear transconductance ring.

Description

Technical Field

[0001] The present invention relates to a class AB operational amplifier for a DRAM system. Background Art

[0002] In the DRAM system, one end of the storage cell of a transistor plus a capacitor structure (abbreviated as 1T1C structure) is connected to the bit line, and the other end usually needs to be biased to a voltage of vdd / 2. If the cell state is "1", the end of the storage cell that sees the bit line will be charged to vdd. If the storage state is "0", the end of the storage cell that sees the bit line will be pulled to 0. Therefore, in order to absorb the current of charging and discharging of the storage cell, a class AB operational amplifier is usually used to provide bias for the other end of the storage cell. There are three common output stage circuits in operational amplifiers: CLASS-A, CLASS-B, and CLASS-AB (push-pull output stage). When the operational amplifier needs to drive large capacitors and small resistors, the op amp output stage circuit usually uses a CLASS-AB structure. The working state of the CLASS-AB output stage op amp is between CLASS-A and CLASS-B, making the two transistors work in push-pull mode, which makes up for the shortcomings of the CLASS-A output stage op amp's high static power consumption and the CLASS-B output stage op amp's distortion. Therefore, the CLASS-AB output stage op amp has the advantages of low static power consumption, low distortion, and high efficiency.

[0003] The control of the quiescent current of a class-AB operational amplifier often consists of two parts: 1. The quiescent current of the transconductance amplifier (OTA) and the bias circuit is usually controlled by the bias current generated by the bias circuit; 2. The quiescent current of the class-AB output stage is controlled by adjusting the linear transconductance loop (translinear loop). In other words, in a CLASS-AB output stage operational amplifier, a translinear loop is often used to bias the two transistors of the output stage to set the quiescent current of the op amp output stage. Summary of the invention

[0004] Technical problem to be solved by the invention

[0005] In low-power DRAM design, it is hoped that the static current is as small as possible. However, in traditional designs, the static power consumption of class AB operational amplifiers is rarely controlled. Therefore, due to the large static current, the static power consumption of class AB operational amplifiers is large, which often leads to an increase in the overall static power consumption of the chip.

[0006] Purpose of the Invention

[0007] The present invention is completed to solve the above-mentioned problem, and its purpose is to provide a class AB operational amplifier that can further reduce static power consumption.

[0008] Technical solutions to technical problems

[0009] A first aspect of the present invention provides a class AB operational amplifier, comprising:

[0010] A first stage operational amplifier module; a second stage operational amplifier module; and an output module,

[0011] The first-stage operational amplifier module is connected to one end of the second-stage operational amplifier module, and the other end of the second-stage operational amplifier module is connected to the output module.

[0012] The second-stage operational amplifier module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first transmission gate,

[0013] The first transistor and the second transistor are connected in series to form a first circuit, and the first transmission gate, the third transistor, and the fourth transistor are connected in series to form a second circuit.

[0014] The output module comprises a sixth transistor; and a voltage output terminal, the drain of the sixth transistor being connected to the voltage output terminal,

[0015] When the class AB operational amplifier is to be placed in a low power consumption mode, the first transmission gate is opened, the first circuit is connected in parallel with the second circuit, and a linear transconductance loop is formed by the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor.

[0016] When the class AB operational amplifier is to be placed in the normal mode, the first transmission gate is closed.

[0017] In the class AB operational amplifier of the second aspect of the present invention,

[0018] The second-stage operational amplifier module also includes a first current source; a voltage source,

[0019] One end of the first current source is connected to the voltage source, and the other end is respectively connected to the drain and gate of the first transistor, one end of the first transmission gate, and the gate of the fifth transistor.

[0020] The source of the first transistor is connected to the drain and the gate of the second transistor respectively,

[0021] The other end of the first transmission gate is connected to the drain and gate of the third transistor respectively.

[0022] The source of the third transistor is connected to the drain and the gate of the fourth transistor respectively,

[0023] A source of the second transistor and a source of the fourth transistor are grounded.

[0024] In the class AB operational amplifier of the third aspect of the present invention,

[0025] The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors.

[0026] In the class AB operational amplifier of the fourth aspect of the present invention,

[0027] The second stage operational amplifier module comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a second transmission gate,

[0028] The output module comprises a twelfth transistor, the drain of the twelfth transistor is connected to the voltage output terminal,

[0029] The seventh transistor and the eighth transistor are connected in series to form a third circuit, and the second transmission gate, the ninth transistor and the tenth transistor are connected in series to form a fourth circuit.

[0030] When the class AB operational amplifier is to be placed in a low power consumption mode, the second transmission gate is opened, the third circuit is connected in parallel with the fourth circuit, and the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor form a linear transconductance loop.

[0031] When the class AB operational amplifier is to be placed in the normal mode, the second transmission gate is closed.

[0032] In the class AB operational amplifier of the fifth aspect of the present invention,

[0033] The second-stage operational amplifier module also includes a second current source;

[0034] The source of the seventh transistor is connected to the voltage source,

[0035] The gate and drain of the seventh transistor are connected to the source of the eighth transistor respectively.

[0036] The gate and drain of the eighth transistor are respectively connected to one end of the second current source,

[0037] The other end of the second current source is grounded.

[0038] The source of the ninth transistor is connected to the voltage source,

[0039] The gate and drain of the ninth transistor are connected to the source of the tenth transistor respectively.

[0040] The gate and drain of the tenth transistor are respectively connected to one end of the second transmission gate,

[0041] The other end of the second transmission gate is connected to the gate of the eleventh transistor and one end of the second current source respectively.

[0042] A source of the eleventh transistor is connected to a gate of the twelfth transistor.

[0043] In the class AB operational amplifier according to the sixth aspect of the present invention,

[0044] The seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are PMOS transistors.

[0045] In the class AB operational amplifier according to the seventh aspect of the present invention,

[0046] The second stage operational amplifier module also includes a third current source and a fourth current source.

[0047] One end of the third current source is connected to the source of the fifth transistor, the drain of the eleventh transistor, and the gate of the sixth transistor respectively.

[0048] The other end of the third current source is grounded,

[0049] One end of the fourth current source is connected to the voltage source,

[0050] The other end of the fourth current source is respectively connected to the drain of the fifth transistor, the source of the eleventh transistor, and the gate of the twelfth transistor.

[0051] In the class AB operational amplifier of the eighth aspect of the present invention,

[0052] The first-stage operational amplifier module comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a fifth current source.

[0053] The source of the thirteenth transistor, the source of the fifteenth transistor, the source of the seventeenth transistor, and the source of the eighteenth transistor are connected to the voltage source respectively,

[0054] The gate and drain of the thirteenth transistor are connected to the gate of the seventeenth transistor and the drain of the fourteenth transistor.

[0055] The gate and drain of the fifteenth transistor are connected to the gate of the eighteenth transistor and the drain of the sixteenth transistor,

[0056] The source of the fourteenth transistor and the source of the sixteenth transistor are respectively connected to one end of the fifth current source,

[0057] The other end of the fifth current source is grounded,

[0058] The drain of the seventeenth transistor is connected to the gate and drain of the nineteenth transistor,

[0059] The drain of the eighteenth transistor is connected to the drain of the twentieth transistor and the gate of the sixth transistor respectively.

[0060] The gate of the nineteenth transistor is connected to the gate of the twentieth transistor,

[0061] The source of the nineteenth transistor and the source of the twentieth transistor are grounded,

[0062] A first input signal is received at the gate of the fourteenth transistor, a second input signal is received at the gate of the sixteenth transistor, and the class AB operational amplifier operates according to the first input signal and the second input signal.

[0063] In the class AB operational amplifier of the ninth aspect of the present invention,

[0064] The thirteenth transistor, the fifteenth transistor, the seventeenth transistor, and the eighteenth transistor are PMOS transistors,

[0065] The fourteenth transistor, the sixteenth transistor, the nineteenth transistor, and the twentieth transistor are NMOS transistors.

[0066] In the class AB operational amplifier according to the tenth aspect of the present invention,

[0067] The second-stage operational amplifier module comprises a twenty-third transistor, a twenty-fourth transistor, and a third transmission gate, wherein the third transmission gate, the twenty-third transistor, and the twenty-fourth transistor are connected in series to form a fifth circuit.

[0068] When the class AB operational amplifier is to be placed in a low power consumption mode, the first transmission gate and the third transmission gate are opened, the first circuit, the second circuit, and the fifth circuit are connected in parallel, and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the twenty-third transistor, and the twenty-fourth transistor form a linear transconductance loop.

[0069] When the class AB operational amplifier is to be placed in a normal mode, the first transmission gate and the third transmission gate are closed.

[0070] Effects of the Invention

[0071] According to the class AB operational amplifier of the present invention, the quiescent current of the class AB operational amplifier can be reduced, thereby further reducing the power consumption of the class AB operational amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figure 1 A block diagram of a class AB operational amplifier according to an embodiment of the present invention is shown.

[0073] Figure 2 A circuit diagram showing an example of a class AB operational amplifier according to an embodiment of the present invention.

[0074] Figure 3 A circuit diagram showing another example of the class AB operational amplifier according to the embodiment of the present invention.

[0075] Description of symbols

[0076] 1. First-stage operational amplifier module

[0077] 2 Second stage operational amplifier module

[0078] 3 Output Module

[0079] VDD voltage source

[0080] Vout voltage output terminal

[0081] MN4 first transistor

[0082] MN5 Second transistor

[0083] MN7 Third transistor

[0084] MN6 Fourth transistor

[0085] MN9 Fifth transistor

[0086] MN8 Sixth transistor

[0087] MP5 Seventh Transistor

[0088] MP4 Eighth Transistor

[0089] MP6 Ninth Transistor

[0090] MP7 Tenth transistor

[0091] MP9 11th transistor

[0092] MP8 12th transistor

[0093] MP0 13th transistor

[0094] MN0 Fourteenth transistor

[0095] MP1 15th transistor

[0096] MN1 Sixteenth transistor

[0097] MP2 Seventeenth transistor

[0098] MP3 18th Transistor

[0099] MN2 19th transistor

[0100] MN3 20th transistor

[0101] MN10 23rd transistor

[0102] MN11 24th transistor

[0103] MP10 25th transistor

[0104] MP11 26th transistor

[0105] PG0 First transmission gate

[0106] PG1 Second transmission gate

[0107] PG2 third transmission gate

[0108] PG3 Fourth transmission gate

[0109] I0 First current source

[0110] I1 Second current source

[0111] I2 The third current source

[0112] I3 Fourth current source

[0113] I4 fifth current source. DETAILED DESCRIPTION

[0114] <Structure of the Class AB Operational Amplifier of the Present Invention>

[0115] Reference Figures 1 to 3 , the class AB operational amplifier of the present invention is described. Figure 1 A block diagram of a class AB operational amplifier of the present invention is shown.

[0116] Example 1

[0117] Figure 1 A block diagram of a class AB operational amplifier according to an embodiment of the present invention is shown.

[0118] Figure 2 A circuit diagram showing an example of a class AB operational amplifier according to an embodiment of the present invention.

[0119] like Figure 1 As shown, the class AB operational amplifier includes: a first-stage operational amplifier module 1 (ie, a first-stage OTA); a second-stage operational amplifier module 2 (ie, a floating current source); and an output module 3 (ie, a class AB output stage).

[0120] The first-stage operational amplifier module 1 is connected to one end of the second-stage operational amplifier module 2 , and the other end of the second-stage operational amplifier module 2 is connected to the output module 3 .

[0121] like Figure 2 As shown, the first-stage operational amplifier module 1 has a thirteenth transistor MP0, a fourteenth transistor MN0, a fifteenth transistor MP1, a sixteenth transistor MN1, a seventeenth transistor MP2, an eighteenth transistor MP3, a nineteenth transistor MN2, a twentieth transistor MN3, and a fifth current source (micro current Itail) I4.

[0122] The second-stage operational amplifier module 2 has a first transistor MN4, a second transistor MN5, a third transistor MN7, a fourth transistor MN6, a fifth transistor MN9, a seventh transistor MP5, an eighth transistor MP4, a ninth transistor MP6, a tenth transistor MP7, an eleventh transistor MP9, a first transmission gate PG0, a second transmission gate PG1, a first current source I0, a second current source I1, a third current source I2, a fourth current source I3, and a voltage source VDD. The current values ​​of the first current source I0, the second current source I1, the third current source I2, and the fourth current source I3 satisfy the following relationship: 2×I0=2×I1=I2=I3.

[0123] The transmission gate in the present invention is composed of a PMOS transistor and an NMOS transistor connected in parallel. The gate of the PMOS is connected to the ACT signal, and the gate of the NMOS is connected to the ACTb signal, and the ACT signal and the ACTb signal are of opposite levels. In this way, when ACT is at a low level, ACTb is at a high level, the transmission gate is opened, and the signal is allowed to pass. Conversely, when ACT is at a high level, ACTb is at a low level, the transmission gate is closed, and the signal is prevented from passing.

[0124] The output module 3 has a sixth transistor MN8, a twelfth transistor MP8, and a voltage output terminal Vout. The sixth transistor MN8 and the twelfth transistor MP8 form an output stage, driving a load and providing an output signal to the voltage output terminal Vout.

[0125] In the first stage operational amplifier module 1,

[0126] A source of the thirteenth transistor MP0 , a source of the fifteenth transistor MP1 , a source of the seventeenth transistor MP2 , and a source of the eighteenth transistor MP3 are respectively connected to the voltage source VDD.

[0127] The gate and drain of the thirteenth transistor MP0 are connected to the gate of the seventeenth transistor MP2 and the drain of the fourteenth transistor MN0 , respectively.

[0128] The gate and drain of the fifteenth transistor MP1 are connected to the gate of the eighteenth transistor MP3 and the drain of the sixteenth transistor MN1 , respectively.

[0129] A source of the fourteenth transistor MN0 and a source of the sixteenth transistor MN1 are respectively connected to one end of the fifth current source I4 , and the other end of the fifth current source I4 is grounded.

[0130] The drain of the seventeenth transistor MP2 is connected to the gate and drain of the nineteenth transistor MN2.

[0131] The drain of the eighteenth transistor MP3, the drain of the twentieth transistor MN3, and the gate of the sixth transistor MN8 are connected.

[0132] The gate of the nineteenth transistor MN2 is connected to the gate of the twentieth transistor MN3.

[0133] A source of the nineteenth transistor MN2 and a source of the twentieth transistor MN3 are grounded.

[0134] The gate of the fourteenth transistor MN0 receives the input signal INP. The gate of the sixteenth transistor MN1 receives the input signal INN. The class AB operational amplifier operates according to the input signal INN and the input signal INP.

[0135] In the second stage operational amplifier module 2,

[0136] One end of the first current source I0 is connected to the voltage source VDD, and the other end is respectively connected to the drain and gate of the first transistor MN4 , one end of the first transmission gate PG0 , and the gate of the fifth transistor MN9 .

[0137] The source of the first transistor MN4 is connected to the drain and the gate of the second transistor MN5 , respectively.

[0138] The other end of the first transmission gate PG0 is connected to the drain and the gate of the third transistor MN7 , respectively.

[0139] The source of the third transistor MN7 is connected to the drain and the gate of the fourth transistor MN6 , respectively.

[0140] A source of the second transistor MN5 and a source of the fourth transistor MN6 are grounded.

[0141] The first transistor MN4 and the second transistor MN5 are connected in series to form a first circuit. The first transmission gate PG0, the third transistor MN7, and the fourth transistor MN6 are connected in series to form a second circuit.

[0142] A source of the seventh transistor MP5 is connected to the voltage source VDD.

[0143] The gate and drain of the seventh transistor MP5 are connected to the source of the eighth transistor MP4 , respectively.

[0144] The gate and drain of the eighth transistor MP4 are respectively connected to one end of the second current source I1. The other end of the second current source I1 is grounded.

[0145] A source of the ninth transistor MP6 is connected to the voltage source VDD.

[0146] The gate and drain of the ninth transistor MP6 are respectively connected to the source of the tenth transistor MP7 .

[0147] A gate and a drain of the tenth transistor MP7 are respectively connected to one end of the second transmission gate PG1 .

[0148] The other end of the second transmission gate PG1 is connected to the gate of the eleventh transistor MP9 and one end of the second current source I1 respectively.

[0149] The source of the eleventh transistor MP9 is connected to the gate of the twelfth transistor MP8 .

[0150] The seventh transistor MP5 and the eighth transistor MP4 are connected in series to form a third circuit. The second transmission gate PG1, the ninth transistor MP6, and the tenth transistor MP7 are connected in series to form a fourth circuit.

[0151] One end of the third current source I2 is connected to the source of the fifth transistor MN9, the drain of the eleventh transistor MP9, and the gate of the sixth transistor MN8, respectively. The other end of the third current source I2 is grounded.

[0152] One end of the fourth current source I3 is connected to the voltage source VDD, and the other end of the fourth current source I3 is connected to the drain of the fifth transistor MN9, the source of the eleventh transistor MP9, and the gate of the twelfth transistor MP8, respectively.

[0153] In the output module 3, the source of the sixth transistor MN8 is connected to the ground, the drain of the sixth transistor MN8 is connected to the voltage output terminal Vout, the source of the twelfth transistor MP8 is connected to the voltage source VDD, and the drain of the twelfth transistor MP8 is connected to the voltage output terminal Vout.

[0154] When the class AB operational amplifier is to be placed in normal mode (Active mode), the first transmission gate PG0 is closed by a high-level ACT signal, and the first transistor MN4, the second transistor MN5, the fifth transistor MN9, and the sixth transistor MN8 form a first linear transconductance loop (NMOS linear transconductance loop).

[0155] In addition, when the class AB operational amplifier is to be placed in normal mode (Active mode), the second transmission gate PG1 is closed by a high-level ACT signal, and the seventh transistor MP5, the eighth transistor MP4, the eleventh transistor MP9, and the twelfth transistor MP8 form a third linear transconductance loop (PMOS linear transconductance loop).

[0156] When the class AB operational amplifier is to be put into low power consumption mode, the first transmission gate PG0 is opened by a low-level ACT signal, the first circuit is connected in parallel with the second circuit, and the first transistor MN4, the second transistor MN5, the third transistor MN7, the fourth transistor MN6, the fifth transistor MN9, and the sixth transistor MN8 form a second linear transconductance loop (NMOS linear transconductance loop).

[0157] And when the class AB operational amplifier is to be placed in low power consumption mode, the second transmission gate PG1 is opened by a low-level ACT signal, and the third circuit is connected in parallel with the fourth circuit to form a fourth linear transconductance loop (PMOS linear transconductance loop) consisting of a seventh transistor MP5, an eighth transistor MP4, a ninth transistor MP6, a tenth transistor MP7, an eleventh transistor MP9, and a twelfth transistor MP8.

[0158] The first transistor MN4 , the second transistor MN5 , the third transistor MN7 , the fourth transistor MN6 , the fifth transistor MN9 , the sixth transistor MN8 , the fourteenth transistor MN0 , the sixteenth transistor MN1 , the nineteenth transistor MN2 , and the twentieth transistor MN3 are NMOS transistors.

[0159] The seventh transistor MP5 , the eighth transistor MP4 , the ninth transistor MP6 , the tenth transistor MP7 , the eleventh transistor MP9 , the twelfth transistor MP8 , the thirteenth transistor MP0 , the fifteenth transistor MP1 , the seventeenth transistor MP2 , and the eighteenth transistor MP3 are PMOS transistors.

[0160] The present invention realizes the switching of power consumption modes by controlling a linear transconductance loop, thereby controlling the static power consumption of a class AB output stage.

[0161] Principle of the present invention:

[0162] like Figure 1 As shown, first, in the working (Active) mode, the ACT signal input to the first transmission gate (PASS GATE) PG0 and the second transmission gate (PASS GATE) PG1 is set to a high level. At this time, the first transmission gate PG0 and the second transmission gate PG1 are closed. There are a first linear transconductance loop and a third linear transconductance loop in the second-stage operational amplifier module 2, that is, the first linear transconductance loop (NMOS linear transconductance loop) is composed of the first transistor MN4, the second transistor MN5, the fifth transistor MN9, and the sixth transistor MN8, and the third linear transconductance loop (PMOS linear transconductance loop) is composed of the eighth transistor MP4, the seventh transistor MP5, the eleventh transistor MP9, and the twelfth transistor MP8.

[0163] And the gate-source voltage V of the first transistor MN4 is GSMN4 , the gate-source voltage V GSMN5 , the gate-source voltage V GSMN9 , the gate-source voltage V GSMN8 The following relationship is satisfied:

[0164] V GSMN4 +V GSMN5 =V GSMN8 +V GSMN9 (Formula 1).

[0165] Similarly, the gate-source voltage V GSMP4 , the gate-source voltage V GSMP5 , the gate-source voltage V GSMP9, the gate-source voltage V GSMP8 The following relationship is satisfied:

[0166] V GSMP4 +V GSMP5 =V GSMP8 +V GSMP9 (Formula 2).

[0167] Usually, transistors MN4, MN5, MN9, MN8, MP4, MP5, MP9, and MP8 are composed of MOS tubes with the same finger width but different numbers of fingers, so the following equation can be obtained:

[0168] (MOS tube saturation current formula) (Formula 3)

[0169] V GS : Gate to source voltage.

[0170] V TH : Threshold voltage, which is the minimum gate-source voltage required to turn on the MOSFET.

[0171] I D : Drain current is the current flowing from the drain to the source.

[0172] μn: Electron mobility, which indicates the speed at which electrons move in a semiconductor.

[0173] Cox: Gate oxide capacitance, which represents the capacitance per unit area.

[0174] W: Width of MOSFET.

[0175] L: length of MOSFET.

[0176] Substitute equation 3 into equation 1 above and rearrange it to get the following equation:

[0177]

[0178] The width-to-length ratios of the first transistor MN4, the second transistor MN5, the fifth transistor MN9, and the sixth transistor MN8 are set to:

[0179] (W / L) MN4 =(W / L) MN5 (Formula 5),

[0180] (W / L) MN9 =2(W / L) MN5 (Formula 6),

[0181] (W / L) MN8 =N(W / L)MN5 (Formula 7).

[0182] according to Figure 2 It can be seen that I DSMN4 =I DSNP5 =I DSMN9 =I0 (Formula 8)

[0183] Substituting equation 5, equation 6, equation 7, and equation 8 into equation 4, we get:

[0184]

[0185] Next, in the standby low power consumption mode, the ACT signal is changed to a low level. By inputting the low level ACT signal into the first transmission gate PG0, the first transmission gate PG0 is opened, so that the first circuit formed by the first transistor MN4 and the second transistor MN5 connected in series is connected in parallel with the second circuit formed by the first transmission gate PG0, the third transistor MN7, and the fourth transistor MN6 connected in series.

[0186] The first transistor MN4 , the second transistor MN5 , the third transistor MN7 , and the fourth transistor MN6 are all the same transistors.

[0187] Therefore, it can be considered that the circuit composed of the first transistor MN4, the second transistor MN5, the third transistor MN7, and the fourth transistor MN6 is equivalent to a circuit composed of the transistor MN4' and the transistor MN5' connected in series, and the width-to-length ratios of the transistor MN4' and the transistor MN5' are respectively twice that of the second transistor MN5. The following formula is obtained:

[0188]

[0189] (W / L) MN4′ =2(W / L) Mm5 (Formula 11)

[0190] (W / L) MN5′ =2(W / L) MN5 (Formula 12)

[0191] I DSMN4′ =I DSMN5′ =I DSMN9′ =I DSMN4 +I DsMN7 =I0(Formula 13).

[0192] I DSMN4′ ,I DSMN5′ ,I DSMN9′ ,I DSMN8′They respectively represent the currents flowing through the transistor MN4 ′, the transistor MN5 ′, the transistor MN9 , and the transistor MN8 when the first transmission gate PG0 is turned on.

[0193] Substituting equations 6, 7, 11, 12, and 13 into equation 10, we get the following equations:

[0194]

[0195] I DSMN8 FIG. 4 shows the current flowing through the sixth transistor MN8 when the conventional class AB operational amplifier is in the low power consumption mode.

[0196] I DSMN8 ' represents the current flowing through the sixth transistor MN8 when the class AB operational amplifier of the present invention is in the low power consumption mode.

[0197] Dividing equation 14 by equation 9, we get

[0198] In addition, the current derivation formulas of the eighth transistor MP4, the seventh transistor MP5, the eleventh transistor MP9, the twelfth transistor MP8, the tenth transistor MP7, and the ninth transistor MP6 are the same as the current derivation formulas of the first transistor MN4, the second transistor MN5, the fifth transistor MN9, the sixth transistor MN8, the third transistor MN7, and the fourth transistor MN6.

[0199] Substitute equation 3 into equation 2 above and rearrange it to get the following equation:

[0200]

[0201] The width-to-length ratios of the eighth transistor MP4, the seventh transistor MP5, the eleventh transistor MP9, and the twelfth transistor MP8 are set to:

[0202] (W / L) MP4 =(W / L) MP5 (Formula 16)

[0203] (W / L) MP9 =2(W / L) MP5 (Formula 17)

[0204] (W / L) MP8 =N(W / L) MP5 (Formula 18)

[0205] I DSMP9 =I DSMP4 =I DSMP5 =I0 (Formula 19)

[0206] Substituting equations 16, 17, 18, and 19 into equation 15, we obtain:

[0207]

[0208] Next, when the class AB operational amplifier is to be placed in a standby low power consumption mode, the ACT signal is changed to a low level. By inputting the low level ACT signal into the second transmission gate PG1, the second transmission gate PG1 is opened, so that the third circuit formed by the eighth transistor MP4 and the seventh transistor MP5 connected in series is connected in parallel with the fourth circuit formed by the second transmission gate PG1, the tenth transistor MP7, and the ninth transistor MP6 connected in series.

[0209] The eighth transistor MP4 , the seventh transistor MP5 , the tenth transistor MP7 , and the ninth transistor MP6 are the same transistors.

[0210] Therefore, it can be considered that the circuit formed by the eighth transistor MP4, the seventh transistor MP5, the tenth transistor MP7, and the ninth transistor MP6 is equivalent to a circuit formed by connecting transistors MP4' and MP5' in series, whose width-to-length ratios of MOS transistors are twice that of the seventh transistor MP5. The following formula is obtained:

[0211]

[0212] (W / L) MP4′ =2(W / L) MP5 (Formula 23)

[0213] (W / L) MP5′ =2(W / L) MP5 (Formula 24)

[0214] I DSMP4′ =I DSMP5′ =I DSMP9′ =I DSMP4 +I DSMP7 =I0 (Formula 25).

[0215] I DSMP4′ ,I DSMP5′ ,I DSMP9′ ,I DSMP8′ It represents the current flowing through the transistor MP4', the transistor MP5', the eleventh transistor MP9 and the twelfth transistor MP8 when the second transmission gate PG1 is turned on.

[0216] Substituting equation 23, equation 24, equation 25, equation 17, and equation 18 into equation 22, we get the following equation:

[0217] Dividing equation 26 by equation 20, we get

[0218] I DSMP8 FIG. 4 shows the current flowing through the twelfth transistor MP8 when the conventional class AB operational amplifier is in the low power consumption mode.

[0219] I DSMP8 ' represents the current flowing through the twelfth transistor MP8 when the class AB operational amplifier of the present invention is in the low power consumption mode.

[0220] In the conventional class AB operational amplifier in the normal power consumption (active) mode, the current flowing through the transistor switches MN8 and MP8 is about 200uA, while in the class AB operational amplifier of the present invention, after entering the low power consumption mode, the current flowing through MN8 and MP8 is about 60uA.

[0221] Therefore, it can be seen that the static current (I DSMN8 ') is reduced to the quiescent current (I DSMN8 ) is less than 1 / 3 (0.299). This enables mode switching and power consumption control.

[0222] By opening the first transmission gate PG0 and the second transmission gate PG1 when the class AB operational amplifier is in low power consumption mode, the current flowing through the sixth transistor MN8 and the twelfth transistor MP8 is reduced, thereby reducing the static current of the class AB operational amplifier, thereby further reducing the power consumption of the class AB operational amplifier.

[0223] Example 2

[0224] Figure 3 FIG. 2 is a circuit diagram showing another example of a class AB operational amplifier according to an embodiment of the present invention. Figure 3 As shown, the difference between Embodiment 2 and Embodiment 1 is that the second-stage operational amplifier module 2 further has a third transmission gate PG2, a fourth transmission gate PG3, a twenty-third transistor MN10, a twenty-fourth transistor MN11, a twenty-fifth transistor MP10, and a twenty-sixth transistor MP11.

[0225] One end of the third transmission gate PG2 is connected to the other end of the first current source I0, the drain and gate of the first transistor MN4, one end of the first transmission gate PG0, and the gate of the fifth transistor MN9, and the other end of the third transmission gate PG2 is connected to the gate and drain of the twenty-third transistor MN10. The source of the twenty-third transistor MN10 is connected to the gate and drain of the twenty-fourth transistor MN11. The source of the twenty-fourth transistor MN11 is grounded.

[0226] The third transmission gate PG2 , the twenty-third transistor MN10 , and the twenty-fourth transistor MN11 are connected in series to form a fifth circuit.

[0227] When the class AB operational amplifier is to be placed in a standby low power consumption mode, the ACT signal is changed to a low level. By inputting the low level ACT signal into the first transmission gate PG0 and the third transmission gate PG2, the first transmission gate PG0 and the third transmission gate PG2 are opened, so that the first circuit, the second circuit, and the fifth circuit are connected in parallel, and the first transistor MN4, the second transistor MN5, the third transistor MN7, the fourth transistor MN6, the fifth transistor MN9, the sixth transistor MN8, the twenty-third transistor MN10, and the twenty-fourth transistor MN11 form a fifth linear transconductance loop (NMOS linear transconductance loop).

[0228] The first transistor MN4 , the second transistor MN5 , the third transistor MN7 , the fourth transistor MN6 , the twenty-third transistor MN10 , and the twenty-fourth transistor MN11 are the same transistors.

[0229] Therefore, it can be considered that the circuit composed of the first transistor MN4, the second transistor MN5, the third transistor MN7, the fourth transistor MN6, the twenty-third transistor MN10, and the twenty-fourth transistor MN11 is equivalent to a circuit formed by connecting the transistor MN4" and the transistor MN5" in series, and the width-to-length ratios of the transistor MN4" and the transistor MN5' are respectively 3 times that of the second transistor MN5.

[0230] Substituting equation (3) into equation (1), we get the following equation:

[0231]

[0232] (W / L) MN4″ =3(W / L) MN5 (Formula 28)

[0233] (W / L) MN5″ =3(W / L) MN5 (Formula 29)

[0234] I DSMN4″ =I DSMN5″ =IDSMN9″ =I DSMN4 +I DSMN7 +I DSMN11 =I0 (Formula 30)

[0235] I DSMN4″ ,I DSMN5″ ,I DSMN8″ ,I DSMN9″ It represents the current flowing through the transistor MN4", the transistor MN5", the sixth transistor MN8 and the fifth transistor MN9 when the first transmission gate PG0 and the third transmission gate PG2 are turned on.

[0236] Substituting equation 6, equation 7, equation 28, equation 29, and equation 30 into equation 27, we obtain the following equations:

[0237]

[0238] Dividing equation 31 by equation 9, we get

[0239] I DSMN8 FIG. 4 shows the current flowing through the sixth transistor MN8 when the conventional class AB operational amplifier is in the low power consumption mode.

[0240] I DSMN8 ” represents the current flowing through the sixth transistor MN8 when the class AB operational amplifier of the present invention is in the low power consumption mode.

[0241] The second-stage operational amplifier module 2 further includes a twenty-fifth transistor MP10 , a twenty-sixth transistor MP11 , and a fourth transmission gate PG3 .

[0242] A source of the twenty-fifth transistor MP10 is connected to the voltage source VDD, and a gate and a drain of the twenty-fifth transistor MP10 are connected to a source of the twenty-sixth transistor MP11 .

[0243] The drain and gate of the twenty-sixth transistor MP11 are connected to one end of the fourth transmission gate PG3, and the other end of the fourth transmission gate PG3 is connected to one end of the second current source I1, the other end of the second transmission gate PG1, the gate of the eleventh transistor MP9, and the gate and drain of the eighth transistor MP4.

[0244] The fourth transmission gate PG3 , the twenty-fifth transistor MP10 , and the twenty-sixth transistor MP11 are connected in series to form a sixth circuit.

[0245] When the class AB operational amplifier is to be placed in a standby low power mode, i.e., a low power mode, the ACT signal becomes a low level. By inputting the low level ACT signal into the second transmission gate PG1 and the fourth transmission gate PG3, the second transmission gate PG1 and the fourth transmission gate PG3 are opened, so that the third circuit, the fourth circuit, and the sixth circuit are connected in parallel, and the eighth transistor MP4, the seventh transistor MP5, the tenth transistor MP7, the ninth transistor MP6, the eleventh transistor MP9, the twelfth transistor MP8, the twenty-fifth transistor MP10, and the twenty-sixth transistor MP11 form a sixth linear transconductance loop (PMOS linear transconductance loop).

[0246] When the class AB operational amplifier is to be placed in the normal mode, the ACT signal becomes high level, so that the second transmission gate PG1 and the fourth transmission gate PG3 are closed.

[0247] The current derivation formulas of the eighth transistor MP4, the seventh transistor MP5, the eleventh transistor MP9, the twelfth transistor MP8, the tenth transistor MP7, the ninth transistor MP6, the twenty-fifth transistor MP10, and the twenty-sixth transistor MP11 are similar to the current derivation formulas of the first transistor MN4, the second transistor MN5, the fifth transistor MN9, the sixth transistor MN8, the third transistor MN7, the fourth transistor MN6, the twenty-third transistor MN10, and the twenty-fourth transistor MN11.

[0248] The eighth transistor MP4 , the seventh transistor MP5 , the tenth transistor MP7 , the ninth transistor MP6 , the twenty-fifth transistor MP10 , and the twenty-sixth transistor MP11 are the same transistors.

[0249] Therefore, it can be considered that the circuit formed by the eighth transistor MP4, the seventh transistor MP5 and the tenth transistor MP7, the ninth transistor MP6, the twenty-fifth transistor MP10, and the twenty-sixth transistor MP11 is equivalent to a circuit formed by connecting transistors MP4″ and MP5″ in series, and the width-to-length ratios of the transistors MP4″ and MP5″ are respectively 3 times that of the second transistor MN5.

[0250] Substituting equation (3) into equation 2, we get the following equation:

[0251]

[0252] (W / L) MP4″ =3(W / L) MP5 (Formula 33)

[0253] (W / L) MP5″ =3(W / L) MP5 (Formula 34)

[0254] I DSMP4″ =I DSMP5″ =I DSMP9″ =I DSMP4 +I DsMP7 +I DSMP11 =I0 (Formula 35)

[0255] I DSMP4″ ,I DSMP5″ ,I DSMP9″ ,I DSMP8″ It represents the current flowing through the transistor MP4 ″, the transistor MP5 ″, the eleventh transistor MP9 , and the twelfth transistor MP8 when the second transmission gate PG1 and the fourth transmission gate PG3 are turned on.

[0256] Substituting equation 33, equation 34, equation 35, equation 17, and equation 18 into equation 32, we get the following equation:

[0257] Dividing equation 36 by equation 20, we get

[0258] I DSMP8 FIG. 4 shows the current flowing through the twelfth transistor MP8 when the conventional class AB operational amplifier is in the low power consumption mode.

[0259] I DSMP8 ” represents the current flowing through the twelfth transistor MP8 when the class AB operational amplifier of the present invention is in the low power consumption mode.

[0260] After the class AB operational amplifier of Example 2 enters the low power consumption mode, the current of MN8 and MP8 is about 24uA.

[0261] Therefore, it can be seen that the static current (I ) of the class AB output stage can be reduced by reducing the area and logic cost (adding the first transmission gate PG0, the third transmission gate PG2, the second transmission gate PG1, the fourth transmission gate PG3, the third transistor MN7, the fourth transistor MN6, the twenty-third transistor MN10, the twenty-fourth transistor MN11, the tenth transistor MP7, the ninth transistor MP6, the twenty-fifth transistor MP10, and the twenty-sixth transistor MP11). DSMN8 ”) is reduced to the quiescent current (I DSMN8 ) is less than 1 / 8 (0.119). This enables mode switching and power consumption control.

[0262] When the class AB operational amplifier is to be put into low power consumption mode, the first transmission gate PG0, the third transmission gate PG2, the second transmission gate PG1, and the fourth transmission gate PG3 are opened, and the current flowing through the sixth transistor MN8 and the twelfth transistor MP8 is reduced, thereby reducing the quiescent current of the class AB operational amplifier, thereby further reducing the power consumption of the class AB operational amplifier.

[0263] In addition, when more transistor circuits are connected in parallel with the first transistor MN4 and the second transistor MN5, or with the seventh transistor MP5 and the eighth transistor MP4, the static current (the sixth transistor MN8 and the twelfth transistor MP8) can be further reduced, thereby further reducing the power consumption of the class AB operational amplifier.

[0264] So far, a class AB operational amplifier according to an embodiment of the present disclosure has been described. The market has increasingly higher requirements for the power consumption of class AB operational amplifiers. The present disclosure provides a class AB operational amplifier to reduce the quiescent current of the class AB operational amplifier, thereby further reducing the power consumption of the class AB operational amplifier.

[0265] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present disclosure, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present disclosure. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present disclosure, the various embodiments are not meant to be restrictive, but exemplary embodiments. In reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. A class AB operational amplifier, characterized in that: include: The first stage operational amplifier module; the second stage operational amplifier module; and output modules, The first-stage operational amplifier module is connected to one end of the second-stage operational amplifier module, and the other end of the second-stage operational amplifier module is connected to the output module. The second-stage operational amplifier module comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first transmission gate, The first transistor and the second transistor are connected in series to form a first circuit, and the first transmission gate, the third transistor, and the fourth transistor are connected in series to form a second circuit. The output module has a sixth transistor; and a voltage output terminal, the drain of the sixth transistor being connected to the voltage output terminal, When the class AB operational amplifier is to be placed in a low power consumption mode, the first transmission gate is opened, the first circuit is connected in parallel with the second circuit, and a linear transconductance loop is formed by the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor. When the class AB operational amplifier is to be placed in the normal mode, the first transmission gate is closed.

2. The class AB operational amplifier according to claim 1, wherein: The second-stage operational amplifier module also includes a first current source; a voltage source, One end of the first current source is connected to the voltage source, and the other end is respectively connected to the drain and gate of the first transistor, one end of the first transmission gate, and the gate of the fifth transistor. The source of the first transistor is connected to the drain and the gate of the second transistor respectively, The other end of the first transmission gate is connected to the drain and gate of the third transistor respectively. The source of the third transistor is connected to the drain and the gate of the fourth transistor respectively, A source of the second transistor and a source of the fourth transistor are grounded.

3. The class AB operational amplifier according to claim 2, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS transistors.

4. The class AB operational amplifier according to claim 2, wherein: The second stage operational amplifier module comprises a seventh transistor; an eighth transistor; a ninth transistor; a tenth transistor; and an eleventh transistor; The second transmission gate, The output module comprises a twelfth transistor, the drain of the twelfth transistor is connected to the voltage output terminal, The seventh transistor and the eighth transistor are connected in series to form a third circuit, and the second transmission gate, the ninth transistor and the tenth transistor are connected in series to form a fourth circuit. When the class AB operational amplifier is in a low power consumption mode, the second transmission gate is opened, the third circuit is connected in parallel with the fourth circuit, and the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor form a linear transconductance loop, When the class AB operational amplifier is in a normal mode, the second transmission gate is closed.

5. The class AB operational amplifier according to claim 4, wherein: The second-stage operational amplifier module also includes a second current source; The source of the seventh transistor is connected to the voltage source, The gate and drain of the seventh transistor are connected to the source of the eighth transistor respectively. The gate and drain of the eighth transistor are respectively connected to one end of the second current source, The other end of the second current source is grounded. The source of the ninth transistor is connected to the voltage source, The gate and drain of the ninth transistor are connected to the source of the tenth transistor respectively. The gate and drain of the tenth transistor are respectively connected to one end of the second transmission gate, The other end of the second transmission gate is connected to the gate of the eleventh transistor and one end of the second current source respectively. A source of the eleventh transistor is connected to a gate of the twelfth transistor.

6. The class AB operational amplifier according to claim 5, wherein: The seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are PMOS transistors.

7. The class AB operational amplifier according to claim 5, wherein: The second stage operational amplifier module also includes a third current source and a fourth current source. One end of the third current source is connected to the source of the fifth transistor, the drain of the eleventh transistor, and the gate of the sixth transistor respectively. The other end of the third current source is grounded, One end of the fourth current source is connected to the voltage source, The other end of the fourth current source is respectively connected to the drain of the fifth transistor, the source of the eleventh transistor, and the gate of the twelfth transistor.

8. The class AB operational amplifier according to claim 2, wherein: The first-stage operational amplifier module comprises a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a fifth current source. The source of the thirteenth transistor, the source of the fifteenth transistor, the source of the seventeenth transistor, and the source of the eighteenth transistor are connected to the voltage source respectively, The gate and drain of the thirteenth transistor are connected to the gate of the seventeenth transistor and the drain of the fourteenth transistor. The gate and drain of the fifteenth transistor are connected to the gate of the eighteenth transistor and the drain of the sixteenth transistor, The source of the fourteenth transistor and the source of the sixteenth transistor are respectively connected to one end of the fifth current source, The other end of the fifth current source is grounded, The drain of the seventeenth transistor is connected to the gate and drain of the nineteenth transistor, The drain of the eighteenth transistor is connected to the drain of the twentieth transistor and the gate of the sixth transistor respectively. The gate of the nineteenth transistor is connected to the gate of the twentieth transistor, The source of the nineteenth transistor and the source of the twentieth transistor are grounded, A first input signal is received at the gate of the fourteenth transistor, a second input signal is received at the gate of the sixteenth transistor, and the class AB operational amplifier operates according to the first input signal and the second input signal.

9. The class AB operational amplifier according to claim 8, wherein: The thirteenth transistor, the fifteenth transistor, the seventeenth transistor, and the eighteenth transistor are PMOS transistors, The fourteenth transistor, the sixteenth transistor, the nineteenth transistor, and the twentieth transistor are NMOS transistors.

10. The class AB operational amplifier according to claim 1, wherein: The second-stage operational amplifier module comprises a twenty-third transistor, a twenty-fourth transistor, and a third transmission gate, wherein the third transmission gate, the twenty-third transistor, and the twenty-fourth transistor are connected in series to form a fifth circuit. When the class AB operational amplifier is to be placed in a low power consumption mode, the first transmission gate and the third transmission gate are opened, the first circuit, the second circuit, and the fifth circuit are connected in parallel, and the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the twenty-third transistor, and the twenty-fourth transistor form a linear transconductance loop. When the class AB operational amplifier is to be placed in a normal mode, the first transmission gate and the third transmission gate are closed.

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