Reconfigurable tri-state content addressable storage unit and matched entry searching method thereof

Abstract

The invention provides a reconfigurable tri-state content addressable storage unit and a matched entry searching method thereof, and relates to the technical field of nonvolatile memory circuit design. The reconfigurable tri-state content addressable storage unit comprises a data storage module, a write-in control module, a first comparison module and a second comparison module, and the matching entry searching method realized based on the reconfigurable tri-state content addressable storage unit can realize two different searching modes according to an external control instruction. The first search mode can realize a tri-state data matching search function of the TCAM, and the second search mode can realize search of accurate matching entries on the basis of the first search mode. According to the method, a reconstruction multiplexing mode is adopted, the same circuit structure is adopted, the basic matching searching function of the TCAM is achieved, accurate matching items can be directly searched, and hardware resources are saved.

Description

Technical Field

[0001] The present invention relates to the technical field of non-volatile memory circuit design, and in particular to a reconfigurable three-state content addressable storage unit and a matching entry search method thereof. Background Art

[0002] TCAM (ternary content addressable memory) is widely used in applications with high-speed data search requirements due to its high-speed and fully parallel data search characteristics. However, as the feature size of CMOS (complementary metal oxide semiconductor) continues to shrink, the leakage current in traditional CMOS-based TCAM continues to increase, resulting in high standby power consumption. TCAM based on non-volatile device MTJ (magnetic tunnel junction) has begun to attract attention and research.

[0003] Writing based on the STT (spin transfer torque) effect is currently a widely used MTJ writing mechanism. However, in pursuit of faster writing speeds, a relatively large STT write current is used, which accelerates the aging of the MTJ barrier layer and results in poor write tolerance of the MTJ. The SOT (spin-orbit transfer torque) effect overcomes the defects of STT writing. SOT writing directly overcomes the magnetic anisotropy field to flip the magnetization direction of the MTJ free layer and achieve high-speed switching. In addition, the write current passes directly through the heavy metal layer instead of the MTJ, avoiding the destruction of the barrier layer. However, in order to achieve deterministic switching of the perpendicular magnetic anisotropy MTJ, an additional magnetic field is required on the basis of SOT, which increases the complexity of writing. In order to solve the above problems, an STT-assisted SOT MTJ writing method has emerged. It uses the interaction between the STT effect and the SOT effect to achieve effective switching of the MTJ under field-free conditions, and shortens the write pulse width, which is conducive to improving the switching speed, energy efficiency and write tolerance.

[0004] The third state 'X' (don't care bit) of TCAM can match any search data among '0', '1' and 'X' as a wildcard, so TCAM usually needs PE (priority encoder) to select the highest priority matching entry to solve the multiple matching problem caused by the third state 'X'. However, PE can only select the entry with the highest matching degree among multiple matching results, and the 'X' state may still be stored in the entry, so TCAM cannot meet some application scenarios that require precise matching like BCAM (two-state content addressable memory). Summary of the invention

[0005] Purpose of the invention: To propose a reconfigurable ternary content addressable storage unit based on STT-assisted SOT writing, and further propose a matching entry search method based on the TCAM storage unit to solve the above problems raised by the prior art.

[0006] In order to achieve the above technical objectives, the technical solutions adopted by the present invention are as follows: A reconfigurable three-state content addressable storage unit comprises four components: a data storage module, a write control module, a first comparison module and a second comparison module.

[0007] The data storage module consists of a four-port device formed by two perpendicular magnetic anisotropy MTJs (magnetic tunnel junctions) and a heavy metal layer, including the first fixed layer, the first barrier layer, the first free layer, the heavy metal layer of the magnetic tunnel junction M0 and the second free layer, the second barrier layer, and the second fixed layer of the magnetic tunnel junction M1, which are stacked in sequence.

[0008] The write control module is composed of a P-type transistor P0 and N-type transistors N0, N1, and N2. The gate of transistor P0 is connected to the first control signal V0, the drain is connected to one end of the heavy metal layer, and the source is connected to the first bit line BL0. The gate of transistor N0 is connected to the word line WL, the drain is connected to the other end of the heavy metal layer, and the source is connected to the second bit line BLB0. The gate of transistor N1 is connected to the first source line SL, the drain is connected to the first fixed layer of M0, and the source is connected to the third bit line BL1. The gate of transistor N2 is connected to the second source line SLB, the drain is connected to the second fixed layer of M1, and the source is connected to the fourth bit line BLB1.

[0009] The first comparison module is composed of an inverter INV0 and an N-type transistor N3, wherein the input end of the inverter is connected to the drain of the transistor P0, and the output end is connected to the gate of the transistor N3. The drain of the transistor N3 is connected to the first matching line ML0, and the source is grounded.

[0010] The second comparison module is composed of P-type transistors P1, P2 and N-type transistor N4. The gate of transistor P1 is connected to the second control signal V1, the drain is connected to the first fixed layer of the magnetic tunnel junction M0, and the source is connected to the power supply voltage VDD. The gate of transistor P2 is connected to the first fixed layer of the magnetic tunnel junction M0, the drain is connected to the drain of transistor N4, and the source is connected to the second matching line ML1. The gate of transistor N4 is connected to the second search mode enable signal SENX, and the source is grounded.

[0011] The present invention uses STT to assist SOT to flip the magnetization direction of the free layer of the magnetic tunnel junction M0 and M1 under field-free conditions, so as to efficiently realize data writing of the storage unit. When writing data, first, transistors P0 and N0 are turned on in response to the word line signal WL and the first control signal V0, and the first bit line BL0 and the second bit line BLB0 are connected to the control voltage to control the conduction of a set direction current pulse in the heavy metal layer. Then transistor N1 or N2 is turned on in response to the first source line SL or the second source line SLB, and at the same time, the third bit line BL1 or the fourth bit line BLB1 is connected to the control voltage so that a set direction current flows through the magnetic tunnel junction M0 or M1. When transistor N1 is turned on, the third bit line BL1 is connected to the control voltage, so that a set direction current flows through the magnetic tunnel junction M0 to change the relative magnetization direction of the magnetic tunnel junction M0. When transistor N2 is turned on, the fourth bit line BLB1 is connected to the control voltage, so that a set direction current flows through the magnetic tunnel junction M1 to change the relative magnetization direction of the magnetic tunnel junction M1.

[0012] The present invention also proposes a matching entry search method implemented by using the reconfigurable ternary content storage unit, which includes two sets of search modes to implement two matching search solutions with different purposes.

[0013] The first search mode completes the basic three-state matching search function of TCAM. When the stored data is in the third state 'X' or is consistent with the search data, it means that the stored data matches the search data. The second search mode implements the exact matching search function of TCAM based on the first search mode. Among all the matching entries after the first search mode ends, if and only if the stored data is consistent with the search data, it means that the stored data and the search data are exactly matched. If the stored data is in the third state 'X', it is not an exact match.

[0014] When the first search mode is adopted, transistor N1 or N2 is turned on in response to the first source line SL or the second source line SLB, the first bit line BL0 is connected to the power supply voltage VDD, and the third bit line BL1 and the fourth bit line BLB1 are grounded. The first control signal V0 is connected to the first control voltage V BIAS1 The control transistor P0 conducts a set current, which flows from the drain of the transistor P0 through one of the magnetic tunnel junctions of M0 and M1. The voltage of the node Q0 connected to the drain of the transistor P0 and one end of the heavy metal layer controls the switch of the transistor N3 after passing through the first inverter INV0 to control whether the first match line ML0 is grounded through the transistor N3. If and only if the data stored in the memory cell is consistent with the search data or is in the 'X' state, ML0 will not be grounded through the transistor N3.

[0015] When the second search mode is adopted, the fourth bit line BLB1 is grounded, and the transistor N2 is turned on in response to the second source line SLB. The second control signal V1 is connected to the second control voltage V BIAS2To control the transistor P1 to conduct a set current, the set current will flow from the drain of the transistor P1 through the magnetic tunnel junctions M0 and M1. The voltage of the node Q1 connected to the drain of the transistor P1 and the drain of the transistor N1 will be determined by the series resistance of the magnetic tunnel junctions M0 and M1. The voltage of the node Q1 controls the switch of the transistor P2 to control whether the second match line ML1 is connected to the drain of the transistor P2. The transistor N4 is turned on in response to the second search mode enable signal SENX, so that the drain of the transistor P2 is grounded through the transistor N4. When and only when the storage data is stored in the 'X' state, the node Q1 is a high voltage, the transistor P2 will not be turned on, and ML1 will not be grounded through the transistor P2 and the transistor N4.

[0016] Beneficial effects: The present invention proposes a reconfigurable three-state content addressable storage unit and a matching entry search method thereof. The three-state content addressable storage unit can realize two different search modes according to external control instructions. The first search mode can realize the three-state data matching search function of TCAM, and the second search mode can realize the search of accurate matching entries based on the first search mode. The present invention adopts a reconfiguration multiplexing method. With the same circuit structure, in addition to realizing the basic matching search function of TCAM, it can also directly search for accurate matching entries, saving hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 4 is a schematic diagram of the circuit structure of TCAM in an embodiment of the present invention.

[0018] Figure 2 Schematic diagram of the timing of related signals when writing data to TCAM in an embodiment of the present invention.

[0019] Figure 3 Schematic diagram of the circuit structure and related signal timing of TCAM in the first search mode.

[0020] Figure 4 Schematic diagram of the circuit structure and related signal timing of TCAM in the second search mode. DETAILED DESCRIPTION

[0021] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described.

[0022] See also Figure 1 The embodiment of the present invention provides a reconfigurable three-state content addressable storage unit based on STT-assisted SOT, and its circuit structure includes: The data storage module is composed of a non-volatile four-port device formed by two MTJs (magnetic tunnel junctions) and a heavy metal layer. It includes a first fixed layer 1, a first barrier layer 2, a first free layer 3, a heavy metal layer 4, and a second free layer 5, a second barrier layer 6, and a second fixed layer 7 of a magnetic tunnel junction M0 stacked in sequence, wherein the first free layer 3 of M0 and the second free layer 5 of M1 are respectively connected to the upper and lower surfaces of the heavy metal layer 4. In a specific embodiment, the magnetic tunnel junctions M0 and M1 are both non-volatile devices, that is, in the case of power failure, the data stored in the magnetic tunnel junction will not be lost. The magnetic tunnel junctions M0 and M1 are both perpendicular magnetic anisotropy MTJs, and the magnetic tunnel junction is effectively reversibly converted between a high resistance state and a low resistance state by means of STT current assisting SOT current to store 1 bit of information.

[0023] The write control module is composed of a P-type transistor P0 and N-type transistors N0, N1, and N2. The gate of transistor P0 is connected to the first control signal V0, the drain is connected to one end of the heavy metal layer 4, and the source is connected to the first bit line BL0. The gate of transistor N0 is connected to the word line WL, the drain is connected to the other end of the heavy metal layer 4, and the source is connected to the second bit line BLB0. The gate of transistor N1 is connected to the first source line SL, the drain is connected to the first fixed layer 1 of M0, and the source is connected to the third bit line BL1. The gate of transistor N2 is connected to the second source line SLB, the drain is connected to the second fixed layer 7 of M1, and the source is connected to the fourth bit line BLB1; The first comparison module is composed of an inverter INV0 and an N-type transistor N3, wherein the input end of the inverter is connected to the drain of the transistor P0, and the output end is connected to the gate of the transistor N3. The drain of the transistor N3 is connected to the first matching line ML0, and the source is grounded; The second comparison module is composed of P-type transistors P1 and P2 and an N-type transistor N4. The gate of transistor P1 is connected to the second control signal V1, the drain is connected to the first fixed layer 1 of the magnetic tunnel junction M0, and the source is connected to the power supply voltage VDD. The gate of transistor P2 is connected to the first fixed layer 1 of the magnetic tunnel junction M0, the drain is connected to the drain of transistor N4, and the source is connected to the second matching line ML1. The gate of transistor N4 is connected to the second search mode enable signal SENX, and the source is grounded.

[0024] When the storage unit is written, the storage data of the storage unit corresponds to the resistance state of the magnetic tunnel junctions M0 and M1 as follows: when the storage data is '1', the magnetic tunnel junction M0 is in the AP state and M1 is in the P state; when the storage data is '0', the magnetic tunnel junction M0 is in the P state and M1 is in the AP state; when the storage data is 'X', the magnetic tunnel junctions M0 and M1 are both in the AP state. AP represents that the relative magnetization direction of the magnetic tunnel junction is antiparallel, corresponding to the high resistance state, and P represents that the relative magnetization direction of the magnetic tunnel junction is parallel, corresponding to the low resistance state.

[0025] In the second search mode, when the stored data is '1' or '0', the resistance states of the magnetic tunnel junctions M0 and M1 are complementary, that is, one is in a high resistance state and the other is in a low resistance state, then the series resistance of M0 and M1 is small, the voltage division of node Q1 is small, transistor P2 is turned on, and the second match line ML1 will be discharged to GND; when the stored data is the third state 'X', the magnetic tunnel junctions M0 and M1 are both in a high resistance state, then the series resistance of M0 and M1 is large, the voltage division of node Q1 is large, transistor P2 is turned off, and the second match line ML1 will maintain VDD. Combined with the state of the first match line ML0 after the first search mode ends, and according to the state of the second match line ML1 after the second search mode ends, it can be known whether the stored data and the search data are accurately matched.

[0026] When writing data, the voltage of the second control signal V1 is VDD, and the voltage of the second search mode enable signal SENX is GND, then transistors P1 and N4 are turned off. The voltage of the first control signal V0 remains GND, and the voltage of the word line signal WL remains VDD. The first source line SL and the second source line SLB control the switches of transistors N1 and N2 when writing data to implement the magnetization direction reversal operation of the magnetic tunnel junctions M0 and M1 in two stages. The first stage performs a magnetization direction reversal operation on the magnetic tunnel junction M0, and the second stage performs a magnetization direction reversal operation on the magnetic tunnel junction M1. The voltages of the first bit line BL0, the second bit line BLB0, the third bit line BL1, the fourth bit line BLB1, the first source line SL, and the second source line SLB determine whether the magnetic tunnel junction is written as an AP state or a P state.

[0027] like Figure 2 As shown in (a), when the magnetic tunnel junction M0 or M1 needs to be written to the P state, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND. At this time, transistors P0 and N0 are both turned on. At the same time, the voltages of the first source line SL and the second source line SLB are both GND, and transistors N1 and N1 are both turned off. The voltage difference between the first bit line BL0 and the second bit line BLB0 will cause a set direction current I to be conducted in the heavy metal layer. SOT The current I in the heavy metal layer SOT After a short period of time, the voltage of the second bit line BLB0 will change from GND to VDD, and the transistor N0 will change from on to off. At the same time, the voltage of the first source line SL (or the second source line SLB) changes from GND to VDDa, the voltage of the third bit line BL1 (or the fourth bit line BLB1) is GND, and the transistor N1 (or N2) is turned on. The voltage difference between the first bit line BL0 and the third bit line BL1 (or the fourth bit line BLB1) will cause a set direction current I to be turned on in the magnetic tunnel junction M0 (or M1). STT, the current will flow from the drain of transistor P0 through the heavy metal layer, then flow into the free layer of M0 (or M1) and out of the fixed layer of M0 (or M1). Current I STT After a period of time, the magnetic tunnel junction will flip to the P state. It is worth noting that when using STT to assist SOT to change the state of the magnetic tunnel junction, the current I STT Only a small value is needed to achieve the state flipping of the magnetic tunnel junction, so a voltage VDDa slightly higher than VDD can make sufficient STT current flow through the transistor N1 or N2.

[0028] like Figure 2 As shown in (b), when the magnetic tunnel junction M0 or M1 needs to be written to the AP state, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND. At this time, transistors P0 and N0 are both turned on. At the same time, the voltages of the first source line SL and the second source line SLB are both GND, and transistors N1 and N1 are both turned off. Then the voltage difference between the first bit line BL0 and the second bit line BLB0 will cause a set direction current I to be conducted in the heavy metal layer. SOT The current I in the heavy metal layer SOT After a short period of time, the voltage of the first bit line BL0 will change from VDD to GND, and the transistor P0 will change from on to off. At the same time, the voltage of the first source line SL (or the second source line SLB) changes from GND to VDDa, the voltage of the third bit line BL1 (or the fourth bit line BLB1) is VDD, and the transistor N1 (or N2) is turned on. The voltage difference between the second bit line BLB0 and the third bit line BL1 (or the fourth bit line BLB1) will cause a set direction current I to be turned on in the magnetic tunnel junction M0 or M1. STT The current will flow from the drain of transistor N1 (or N2) into the fixed layer of M0 (or M1) and out of the free layer of M0 (or M1), and then flow to the drain of transistor N0 through the heavy metal layer. Current I STT After a period of time, the magnetic tunnel junction will flip to the AP state.

[0029] Specifically, if data '1' needs to be written to the storage cell, the magnetization direction reversal operation is performed on the magnetic tunnel junctions M0 and M1 respectively in two stages. In the first stage, the voltage of the second control signal V1 is VDD, the voltage of the second search mode enable signal SENX is GND, and the transistors P1 and N4 are turned off. The voltage of the first control signal V0 remains GND, and the voltage of the word line signal WL remains VDD. First, the voltage of the first source line SL and the second source line SLB is GND, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND, then the transistors N1 and N2 are turned off, and P0 and N0 are turned on. Due to the voltage difference between the first bit line BL0 and the second bit line BLB0, a set direction current I is conducted in the heavy metal layer. SOTThe current I in the heavy metal layer SOT After a short period of time, the voltage of the first bit line BL0 will change from VDD to GND, and the transistor P0 will change from on to off. At the same time, the voltage of the first source line SL changes from GND to VDDa, the voltage of the third bit line BL1 is VDD, and the transistor N1 is turned on. The voltage difference between the second bit line BLB0 and the third bit line BL1 will cause a set direction current I to be conducted in the magnetic tunnel junction M0. STT The current will flow from the drain of transistor N1 into the fixed layer of M0 and out of the free layer of M0, and then flow through the heavy metal layer to the drain of transistor N0. The current I STT After a period of time, the magnetic tunnel junction M0 will flip to the AP state.

[0030] In the second stage, the voltage of the second control signal V1 is VDD, the voltage of the second search mode enable signal SENX is GND, and the transistors P1 and N4 are turned off. The voltage of the first control signal V0 remains GND, and the voltage of the word line signal WL remains VDD. First, the voltage of the first source line and the second source line is GND, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND, then the transistors N1 and N2 are turned off, and P0 and N0 are turned on. Due to the voltage difference between the first bit line BL0 and the second bit line BLB0, a set direction current I is conducted in the heavy metal layer. SOT The current I in the heavy metal layer SOT After a short period of time, the voltage of the second bit line BLB0 will change from GND to VDD, and the transistor N0 will change from on to off. At the same time, the voltage of the second source line SLB changes from GND to VDDa, the voltage of the fourth bit line BLB1 is GND, and the transistor N2 is turned on. The voltage difference between the first bit line BL0 and the fourth bit line BLB1 will cause a set direction current I to be turned on in the magnetic tunnel junction M1. STT The current will flow from the drain of transistor P0 through the heavy metal layer, then into the free layer of M1 and out of the fixed layer of M1. STT After a period of time, the magnetic tunnel junction M1 will flip to the P state.

[0031] like Figure 3As shown, when the first search mode is performed, the first match line ML0 has been precharged to VDD through an external transistor in the initial state. The voltage of the word line signal WL is GND, the voltage of the second bit line BLB0 is GND, the voltage of the second control signal V1 is VDD, and the voltage of the second search mode enable signal SENX is GND, then transistors N0, P1, and N4 are all turned off. The voltages of the third bit line BL1 and the fourth bit line BLB1 are both GND, and the first source line SL and the second source line SLB are complementary signals at this time: when searching for '1', the voltage of the first source line SL is VDD, and the voltage of the second source line SLB is GND, then transistor N1 is turned on and N2 is turned off; when searching for '0', the voltage of the first source line SL is GND, and the voltage of the second source line SLB is VDD, then transistor N1 is turned off and N2 is turned on. The voltage of the first control signal V0 is V BIAS0 , so that a constant current I is conducted on transistor P0 READ1 , then when searching for '1', the constant current I READ1 It will flow from the drain of P0 to the heavy metal layer, through the free layer, barrier layer, fixed layer and transistor N1 of M0 and then to GND; when searching for '1', the constant current I READ1 It flows from the drain of P0 to the heavy metal layer, passes through the free layer, barrier layer, fixed layer and transistor N2 of M1, and then flows to GND. Depending on the difference between the stored data and the search data, the constant current I READ1 The resistance states of the magnetic tunnel junctions on the DC paths are different, so the node Q0 will generate different voltage divisions. The voltage of Q0 controls the switch of transistor N3 through the first inverter INV0 to determine whether the first match line ML0 that has been precharged to VDD is discharged. The final voltage of the first match line ML0 can be used to determine whether the stored data matches the search data.

[0032] If the stored data matches the search data, that is, the stored data is the third state 'X' or is the same as the search data, the constant current I READ1 The magnetic tunnel junction on the DC path is in high impedance state (AP), Q0 point is high voltage, then transistor N3 is turned off, and the result is that the first match line ML0 maintains VDD; if the stored data and the search data do not match, that is, the stored data and the search data are different, the constant current I READ1 The magnetic tunnel junction on the DC path is in a low resistance state (P), the Q0 point is at a low voltage, and the transistor N3 is turned on, resulting in the first matching line ML0 being discharged to GND through the transistor N3.

[0033] Take the search operation when the memory cell stores '1' as an example. When the stored data is '1', the magnetic tunnel junction M0 is in the AP state and the magnetic tunnel junction M1 is in the P state. When searching for '1', the voltage of the first source line SL is VDD and the voltage of the second source line SLB is GND, then the transistor N1 is turned on and N2 is turned off. The magnetic tunnel junction M0 will exist in the constant current I READ1 In the DC path, since the magnetic tunnel junction M0 is in a high impedance state, the voltage of the node Q0 is high, the transistor N3 is turned off, and the first match line ML0 will maintain VDD. When searching for '0', the voltage of the first source line SL is GND, and the voltage of the second source line SLB is VDD, then the transistor N1 is turned off and N2 is turned on. The magnetic tunnel junction M1 will exist in a constant current I READ1 In the DC path, since the magnetic tunnel junction M1 is in a low resistance state, the voltage of the node Q0 is low, the transistor N3 is turned on, and the first matching line ML0 is discharged to GND through N3.

[0034] The first search mode completes the basic three-state matching search function of TCAM, and the matching result is reflected in the voltage of the first match line ML0. When the stored data is the third state 'X' or consistent with the search data, it means that the stored data matches the search data, and ML0 is always VDD. When the stored data is different from the search data, it means that the stored data does not match the search data, and ML0 will discharge to GND.

[0035] After the first search mode ends, whether to perform the second search mode can be determined according to the second search mode enable signal SENX. Figure 4 As shown, when the second search mode is performed, the second match line ML1 has been precharged to VDD through an external transistor in the initial state. The voltage of the second search mode enable signal SENX is VDD, the voltage of the word line signal WL is GND, the voltage of the first control signal V0 is VDD, the voltages of the first bit line BL0, the second bit line BLB0, the third bit line BL1 and the fourth bit line BLB1 are all GND, the voltage of the first source line SL is GND, and the voltage of the second source line SLB is VDD, then transistors N2 and N4 are turned on, and P0, N0 and N1 are turned off. The voltage of the second control signal V1 is V BIAS1 , so that a constant current I is conducted on transistor P1 READ2. The current flows from the drain of transistor P1 to the fixed layer of the magnetic tunnel junction M0, passes through the barrier layer, free layer, heavy metal layer of M0, the free layer, barrier layer, fixed layer of M1 and transistor N2, and then flows to GND. Node Q1 will generate different voltage divisions according to the series resistance of the magnetic tunnel junctions M0 and M1. The voltage controls the switch of transistor P2 to determine whether the second match line ML1 that has been precharged to VDD is discharged. If the first match line ML0 maintains VDD in the first search mode, when the second match line ML1 is discharged to GND in the second search mode, it means that the stored data and the search data are accurately matched; when the second match line ML1 maintains VDD in the second search mode, it means that the stored data and the search data are not accurately matched.

[0036] Taking storing '1' and searching '1' as an example, since the stored data is the same as the search data, the first match line ML0 will maintain VDD after the first search mode ends. Since the magnetic tunnel junctions M0 and M1 are in AP state and P state respectively when storing '1', the series resistance is small, so the voltage of node Q1 is small when the second search mode is performed, the transistor P2 will be turned on, and the second match line ML1 will be discharged to GND, indicating that the stored data and the search data are accurately matched.

[0037] Taking storing 'X' and searching for '1' as an example, since the stored data is the third state 'X', the first match line ML0 will remain at VDD after the first search mode ends. Since the magnetic tunnel junctions M0 and M1 are both in the AP state when storing 'X', the series resistance is large, so the voltage of the node Q1 is large when the second search mode is performed, the transistor P2 is turned off, and the second match line ML1 will remain at VDD, indicating that the stored data and the search data are not an exact match, but a match achieved due to the storage of the third state 'X'.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A reconfigurable ternary content addressable storage unit, characterized in that: It includes a data storage module, a write control module, a first comparison module, and a second comparison module; The data storage module includes a first fixed layer, a first barrier layer, a first free layer, a heavy metal layer of a magnetic tunnel junction M0 and a second free layer, a second barrier layer, and a second fixed layer of a magnetic tunnel junction M1, which are stacked in sequence; The write control module includes a P-type transistor P0 and N-type transistors N0, N1, and N2; wherein the gate of the P-type transistor P0 is connected to the first control signal V0, the drain is connected to one end of the heavy metal layer, and the source is connected to the first bit line BL0; The gate of the N-type transistor N0 is connected to the word line WL, the drain is connected to the other end of the heavy metal layer, and the source is connected to the second bit line BLB0; The gate of the N-type transistor N1 is connected to the first source line SL, the drain is connected to the first fixed layer of the magnetic tunnel junction M0, and the source is connected to the third bit line BL1; The gate of the N-type transistor N2 is connected to the second source line SLB, the drain is connected to the second fixed layer of the magnetic tunnel junction M1, and the source is connected to the fourth bit line BLB1; The first comparison module includes an inverter INV0 and an N-type transistor N3; the input end of the inverter INV0 is connected to the drain of the P-type transistor P0, and the output end is connected to the gate of the N-type transistor N3; the drain of the N-type transistor N3 is connected to the first matching line ML0, and the source is grounded; The second comparison module includes P-type transistors P1 and P2 and an N-type transistor N4; the gate of the P-type transistor P1 is connected to the second control signal V1, the drain is connected to the first fixed layer of the magnetic tunnel junction M0, and the source is connected to the power supply voltage VDD; The gate of the P-type transistor P2 is connected to the first fixed layer of the magnetic tunnel junction M0, the drain is connected to the drain of the N-type transistor N4, and the source is connected to the second matching line ML1; The gate of the N-type transistor N4 is connected to the second search mode enable signal SENX, and the source is grounded.

2. The reconfigurable ternary content addressable storage unit according to claim 1, characterized in that: When writing data: The P-type transistor P0 and the N-type transistor N0 are turned on in response to the word line signal WL and the first control signal V0, and the first bit line BL0 and the second bit line BLB0 are connected to the control voltage to control the heavy metal layer to conduct a set direction current pulse; The N-type transistor N1 or N2 is turned on in response to the first source line SL or the second source line SLB.

3. The reconfigurable ternary content addressable storage unit according to claim 2, characterized in that: When the N-type transistor N1 is turned on, the third bit line BL1 is connected to the fixed layer of the magnetic tunnel junction M0. The third bit line BL1 is connected to a control voltage so that a set direction current flows through the magnetic tunnel junction M0 to change the relative magnetization direction of the magnetic tunnel junction M0.

4. The reconfigurable ternary content addressable memory cell according to claim 2, characterized in that: When the N-type transistor N2 is turned on, the fourth bit line BLB1 is connected to the fixed layer of the magnetic tunnel junction M1. The fourth bit line BLB1 is connected to a control voltage so that a set direction current flows through the magnetic tunnel junction M1 to change the relative magnetization direction of the magnetic tunnel junction M1.

5. The matching entry search method of the reconfigurable ternary content addressable storage unit according to claim 1, characterized in that: including a first search mode and a second search mode; The first search mode completes the three-state matching search function of the TCAM; The second search mode implements an exact match search function of the TCAM based on the first search mode; After the first search mode ends, whether to perform the second search mode is determined according to the state of the second search mode enable signal SENX.

6. The matching entry search method of the reconfigurable ternary content addressable storage unit according to claim 5, characterized in that: In the first search mode, when the stored data is in the third state or is consistent with the search data, it means that the stored data matches the search data; Among all the matching entries after the first search mode ends, if and only if the stored data is consistent with the search data, it means that the stored data and the search data are exactly matched. If the stored data is in the third state, it is an inexact match.

7. The matching entry search method of the reconfigurable ternary content addressable storage unit according to claim 5, characterized in that: When using the first search mode: The N-type transistor N1 or N2 is turned on in response to the first source line SL or the second source line SLB, the first bit line BL0 is connected to the power supply voltage VDD, and the third bit line BL1 and the fourth bit line BLB1 are grounded; The first control signal V0 is connected to the first control voltage V BIAS1 The control transistor P0 is used to conduct a set current, and the set current flows from the drain of the P-type transistor P0 through one of the magnetic tunnel junctions M0 or M1; The voltage of the node Q0 connected to the drain of the P-type transistor P0 and one end of the heavy metal layer controls the switch of the transistor N3 after passing through the first inverter INV0 to control whether the first matching line ML0 is grounded through the transistor N3; If and only if the data stored in the memory cell is consistent with the search data or is in the third state, the node Q0 is a high voltage, the output voltage of the inverter INV0 is a low voltage, the transistor N3 is turned off, and ML0 is not grounded through the transistor N3.

8. The matching entry search method of the reconfigurable ternary content addressable storage unit according to claim 5, characterized in that: When using the second search mode: The fourth bit line BLB1 is grounded, and the N-type transistor N2 is turned on in response to the second source line SLB; The second control signal V1 is connected to the second control voltage V BIAS2 To control the transistor P1 to conduct a set current, and the set current flows from the drain of the transistor P1 through the magnetic tunnel junctions M0 and M1; The voltage of the node Q1 connected between the drain of the P-type transistor P1 and the drain of the N-type transistor N1 will be determined by the series resistance of the magnetic tunnel junctions M0 and M1. The voltage of the node Q1 controls the switch of the P-type transistor P2 to control whether the second matching line ML1 is connected to the drain of the transistor P2. The N-type transistor N4 is turned on in response to the second search mode enable signal SENX, so that the drain of the transistor P2 is connected to the ground through the transistor N4; The switching state of transistor P2 determines whether the second match line ML1 is connected to the ground through transistors P2 and N4. When and only when the memory cell stores data in the third state 'X', node Q1 is at a high voltage, transistor P2 will not be turned on, and ML1 will not be grounded through transistors P2 and N4.

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