Method of operating a storage system, method of reading data from a memory, and storage system

Abstract

The present disclosure provides an operating method of a storage system, a data reading method of a memory and a storage system, relates to the storage field, and solves the problems of increased read retry rate and decreased read performance of a NAND flash memory due to threshold voltage offset of a storage unit. The specific scheme is as follows: an operating method of a storage system is provided, which comprises the following steps: firstly, determining an offset voltage value corresponding to a selected word line in N word lines according to the number N of the word lines and offset voltage information, the N word lines being word lines arranged adjacently in a storage block Block of the memory, and K storage units coupled with the N word lines storing data, K and N being positive integers, and the offset voltage information being used for indicating N corresponding offset voltage values. Then, a data reading command is sent to the memory, the data reading command being used for instructing the memory to generate a read voltage according to the offset voltage value and apply the read voltage to the selected word line.

Description

Technical Field

[0001] This disclosure relates to the field of storage, and more particularly to methods for operating a storage system, methods for reading data from a memory, and storage systems. Background Technology

[0002] 3D NAND flash memory consists of multiple blocks, each block contains multiple pages, and each page contains multiple memory cells. When some pages in a block are written to, the block is called an open block; when all pages in a block are written to, the block is called a closed block.

[0003] As the demand for 3D NAND flash memory storage capacity continues to increase, 3D NAND flash memory is constantly developing towards smaller device sizes and more stacked layers, which will lead to an increase in the read retry ratio of 3D NAND flash memory, a decrease in the read performance of 3D NAND flash memory, and a poor user experience. Summary of the Invention

[0004] The embodiments of this disclosure provide an operation method for a storage system, a data reading method for a memory, and a storage system, which solve the problem that the read retry rate of NAND flash memory increases and the read performance decreases due to the threshold voltage offset of the storage cell.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, a method for operating a storage system is provided. This method includes: First, determining the offset voltage value corresponding to a selected word line among the N word lines based on the number N word lines N and offset voltage information. The N word lines are adjacent word lines within a memory block, and K memory cells coupled to the N word lines store data. K and N are positive integers, and the offset voltage information indicates the offset voltage value corresponding to N. Then, a data read command is sent to the memory, instructing the memory to generate a read voltage based on the offset voltage value and apply the read voltage to the selected word line.

[0007] Optionally, the aforementioned offset voltage information may be in tabular form or in other forms, and this disclosure does not limit this.

[0008] Optionally, the selected character line can be one of N character lines, or it can be multiple of N character lines. This embodiment of the present disclosure does not limit this.

[0009] Optionally, the types of the aforementioned K storage units include at least one of single-level units, multi-level units, three-level units, and four-level units, and this disclosure does not limit this type.

[0010] The storage system operation method provided in this disclosure determines the offset voltage value corresponding to a selected word line among the N word lines based on the number N word lines N and offset voltage information. These N word lines are adjacent word lines in a storage block, and K storage cells coupled to the N word lines store data. It is understood that the offset voltage value determined in this disclosure takes into account the different offsets of the threshold voltage of the storage cells in the storage block when the number of data-written word lines differs. Therefore, the offset voltage value determined in this disclosure is more accurate, and the read voltage determined based on this offset voltage value is more accurate, thereby reducing the read retry rate of the memory and improving read performance.

[0011] In some embodiments, determining the offset voltage value corresponding to the selected word line among the N word lines based on the number N of N word lines and the offset voltage information includes: determining the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line, and the offset voltage information. The position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

[0012] The storage system operation method provided in this embodiment determines the corresponding bias voltage value based on the position information of the selected word line among N word lines, which can further improve the accuracy of the bias voltage value. The memory applies a read voltage to the selected word line based on the bias voltage value, thereby further reducing the read retry rate and improving read performance.

[0013] In some embodiments, the selected character line includes a first selected character line or a second selected character line. The first selected character line includes character lines 1 to (N-1)th, and the second selected character line includes the Nth character line. Determining the offset voltage value corresponding to the selected character line based on N, the position information of the selected character line, and the offset voltage information includes: determining a first offset voltage value corresponding to the first selected character line based on N, the position information of the first selected character line, and the offset voltage information. Alternatively, determining a second offset voltage value corresponding to the second selected character line based on N, the position information of the second selected character line, and the offset voltage information, wherein the first offset voltage value is less than the second offset voltage value.

[0014] Optionally, the first selected character line may include one of the first character line to the (N-1)th character line, or may include multiple of the first character line to the (N-1)th character line. This embodiment of the present disclosure does not limit this.

[0015] In some embodiments, among the K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states. The determination of the offset voltage value corresponding to the selected word line among the N word lines based on the number N of N word lines and the offset voltage information includes: determining the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line, the preset read voltage of the selected memory cell, and the offset voltage information. The selected memory cell is the memory cell coupled to the selected word line among the K memory cells. The preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell. The offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

[0016] Optionally, the selected storage unit can be a single storage unit coupled to the selected word line, or it can be multiple storage units coupled to the selected word line. This embodiment of the present disclosure does not limit this.

[0017] The storage system operation method provided in this embodiment determines the corresponding offset voltage value based on the preset read voltage corresponding to each programming state of the storage unit, which can further improve the accuracy of the offset voltage value. The memory applies a read voltage to the selected word line according to the offset voltage value, thereby further reducing the read retry rate and improving read performance.

[0018] In some embodiments, the memory block further includes M word lines arranged adjacent to the N word lines, and L memory cells coupled to the M word lines. The M word lines are arranged adjacent to each other, and no data is stored in the L memory cells. M is an integer greater than or equal to 0, and L is a positive integer. The offset voltage information is determined by comparing a first threshold voltage distribution when data is stored in the K memory cells with a second threshold voltage distribution when data is stored in the K memory cells and the L memory cells.

[0019] On the other hand, a data reading method for a memory is also provided. This method includes: first, receiving a data read command, which instructs the memory to generate a read voltage based on an offset voltage value and apply the read voltage to a selected word line among N word lines. The offset voltage value is determined based on the number N word lines N and offset voltage information. The N word lines are adjacent word lines in a memory block, and K memory cells coupled to the N word lines store data. K and N are positive integers, and the offset voltage information indicates the offset voltage value corresponding to N. Then, according to the data read command, a read voltage is generated and applied to the selected word line.

[0020] In some embodiments, the offset voltage value is determined based on N, the position information of the selected character line, and the offset voltage information. The position information of the selected character line is used to indicate the position of the selected character line among the N character lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected character line.

[0021] In some embodiments, the selected character line includes a first selected character line or a second selected character line. The first selected character line includes character lines 1 to (N-1)th, and the second selected character line includes character line N. The offset voltage value includes a first offset voltage value or a second offset voltage value. The first offset voltage value is determined based on N, the position information of the first selected character line, and the offset voltage information. The second offset voltage value is determined based on N, the position information of the second selected character line, and the offset voltage information. The first offset voltage value is less than the second offset voltage value.

[0022] In some embodiments, among the K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states; the offset voltage value is determined based on N, the position information of the selected word line, the preset read voltage of the selected memory cell, and the offset voltage information. The selected memory cell is the memory cell coupled to the selected word line among the K memory cells, the preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell, and the offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

[0023] In some embodiments, the memory block further includes M word lines arranged adjacent to the N word lines, and L memory cells coupled to the M word lines. The M word lines are arranged adjacent to each other, and no data is stored in the L memory cells. M is an integer greater than or equal to 0, and L is a positive integer. The offset voltage information is determined by comparing a first threshold voltage distribution when data is stored in the K memory cells with a second threshold voltage distribution when data is stored in the K and L memory cells.

[0024] In another aspect, a storage system is provided, comprising a controller and a memory coupled to the controller. The controller is configured to determine an offset voltage value corresponding to a selected word line among the N word lines based on the number N word lines N and offset voltage information. The N word lines are adjacent word lines in a memory block, and K memory cells coupled to the N word lines store data. K and N are positive integers, and the offset voltage information indicates the offset voltage value corresponding to N. The controller is also configured to send a data read command to the memory, which instructs the memory to generate a read voltage based on the offset voltage value and apply the read voltage to the selected word line. The memory is configured to receive the data read command and, based on the data read command, generate and apply the read voltage to the selected word line.

[0025] In some embodiments, the controller is further configured to determine the offset voltage value corresponding to the selected character line based on N, the position information of the selected character line, and the offset voltage information. The position information of the selected character line is used to indicate the position of the selected character line among the N character lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected character line.

[0026] In some embodiments, the selected character line includes a first selected character line or a second selected character line. The first selected character line includes character lines 1 to (N-1)th, and the second selected character line includes the Nth character line. The controller is further configured to determine a first offset voltage value corresponding to the first selected character line based on N, the position information of the first selected character line, and offset voltage information. Alternatively, the controller is further configured to determine a second offset voltage value corresponding to the second selected character line based on N, the position information of the second selected character line, and offset voltage information, wherein the first offset voltage value is less than the second offset voltage value.

[0027] In some embodiments, among the K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states. The controller is also configured to determine the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line, the preset read voltage of the selected memory cell, and offset voltage information. The selected memory cell is the memory cell coupled to the selected word line among the K memory cells. The preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell. The offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

[0028] In another aspect, a computer-readable storage medium is provided, which stores a computer program that, when executed on a processor, causes the processor to perform the operation method of the storage system provided in the preceding aspect, or to perform the data reading method of the memory provided in the preceding aspect.

[0029] It is understood that the beneficial effects of the data reading method, storage system and computer-readable storage medium of the memory provided in the above embodiments of this disclosure can be referred to the beneficial effects of the operation method of the storage system described above, and will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments;

[0032] Figure 2 This is a schematic diagram of the structure of a memory according to some embodiments;

[0033] Figure 3 This is a schematic diagram of the structure of a storage array according to some embodiments;

[0034] Figure 4 This is a schematic diagram of a threshold voltage distribution curve according to some embodiments;

[0035] Figure 5 This is a flowchart illustrating an operation method of a storage system according to some embodiments;

[0036] Figure 6 This is a schematic diagram of another threshold voltage distribution curve according to some embodiments. Detailed Implementation

[0037] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0038] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0039] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0040] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0041] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0042] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0043] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0044] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0045] Before introducing the embodiments of this disclosure, the technical terms and background technology involved in this disclosure will be introduced first.

[0046] The term "3D memory" refers to a semiconductor device formed by a series of memory cell transistors (referred to herein as "strings," such as NAND strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface). The string address is the address corresponding to the "string." The "selected word line (WL)" is the word line corresponding to the word line address in the read request instruction, and the "unselected word line" is any word line other than the word line corresponding to the word line address in the read request instruction.

[0047] Read retry ratio: This refers to the ratio of the number of successful data reads to the total number of data read attempts within a certain number of read attempts. It is one of the important indicators for measuring the read performance and stability of memory, and can reflect the reliability and performance of memory.

[0048] A word line for writing data refers to a memory cell coupled to which data is stored. For ease of description, this word line is referred to as a word line for writing data in this embodiment of the disclosure.

[0049] Unwritten word line: refers to a memory cell coupled to which no data is stored. For ease of description, this word line is referred to as an unwritten word line in this embodiment of the disclosure.

[0050] Dummy data: This type of data is typically used for testing, demonstration, or teaching purposes.

[0051] Single-level cell (SLC): Each storage unit has only one storage bit and can only store one data item.

[0052] Multi-level cell (MLC): Each storage cell has two storage bits and can store two data items.

[0053] Triple-level cell (TLC): Each storage unit has three storage bits and can store three data items simultaneously.

[0054] Quad-level cell (QLC): Each storage unit has four storage bits and can store four data items simultaneously.

[0055] like Figure 1As shown, a storage system 100 is typically provided in an electronic device 10. This storage system 100 includes a memory 200 and a controller 300. The controller 300 is coupled to the memory 200, and can read data from or write data to the memory 200.

[0056] It is understood that the storage system 100 may include a controller 300 and one or more memories 200. For example, in one embodiment, the controller 300 and a single memory 200 may be integrated into a memory card. The memory card may include PCMCIA (PC) cards, compact flash cards (CF cards), smart media cards (SM cards), memory sticks, multimedia cards (MMC), secure digital cards (SD cards), universal flash storage (UFS), etc. Multimedia cards can be further categorized into MMC, reduced-size MMC (RS-MMC), and mini MMC (MMCmicro), etc.; secure digital cards include SD, miniSD, microSD, and secure digital high capacity (SDHC), etc. Furthermore, the memory card may also include a memory card connector that couples the memory card to the host computer.

[0057] In another embodiment, the controller 300 and the plurality of memories 200 may be integrated into a solid-state disk (SSD). The SSD may also include an SSD connector that couples the SSD to the host. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card. Furthermore, the aforementioned electronic device may be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc., and this disclosure does not limit this to any particular type.

[0058] like Figure 2 As shown, the memory 200 typically includes a memory array 210 and peripheral circuitry. The peripheral circuitry includes terminal blocks 221, control logic circuitry 222, registers 223, a voltage generator 224, row drivers 225, column drivers 226, and page buffers 227, etc.

[0059] Terminal 221 is mainly used to receive read and write commands from controller 300 and to send read data to controller 300. Control logic circuit 222 is mainly used to control row driver 225 to connect voltage generator 224 to the corresponding word line and column driver 226 to connect voltage generator 224 to the corresponding bit line (BL) according to the received read command, thereby reading the corresponding data. Register 223 includes an address register and a status register. The address register stores the word line address and string address in the read request command. The status register stores the current state of the memory, including ready and busy states. When control logic circuit 222 is reading data from or writing data to memory array 210, the status register stores a "busy" state, and the next read or write operation cannot be performed. When memory array 210 completes the read or write process, the status register switches to a "ready" state, and the next read or write operation can be performed. Page cache 227 includes a first register and a second register, wherein the first register is used to cache data read from storage array 210 and the second register is used to cache data transferred out from the first register.

[0060] The memory array 210 in memory 200 may include multiple memory cells arranged at the intersection of word lines and bit lines. Based on structural differences in the memory array 210, the memory can be divided into two-dimensional memory and three-dimensional memory. For example... Figure 3 The diagram shows a schematic of a storage array 210 in a three-dimensional memory. The storage array 210 includes word lines WL1-WL3 and bit lines BL1-BL7. Multiple storage cells perpendicular to each bit line on each word line form a page 2111, and multiple storage cells perpendicular to each word line on each bit line form a storage cell string 2112. Each storage cell string 2112 has a top selective gate (TSG) at the top and a bottom selective gate (BSG) at the bottom. Multiple storage cell strings 2112 can be configured on each bit line, and each word line can be coupled to the storage cells in multiple storage cell strings 2112. The difference between a two-dimensional memory and a three-dimensional memory is that in a two-dimensional memory, there is only one storage cell in the storage cell string 2112 perpendicular to each bit line.

[0061] The smallest unit for programming in NAND flash memory is a page. Taking a memory cell within a page as an example, when data needs to be stored in this cell, turn-on voltages are applied to the top select transistor (TSG) and bottom select transistor (BSG) to turn them on. Then, a programming voltage is applied to the word line coupled to the cell, and a programming enable voltage is applied to the bit line coupled to the cell. This allows programming the threshold voltage (Vth) of the cell, enabling information storage. When data needs to be read from the cell, turn-on voltages are applied to the top select transistor and bottom select transistor to turn them on. Then, a read voltage is applied to the word line coupled to the cell, and a turn-on voltage is applied to the bit line coupled to the cell, enabling information retrieval.

[0062] As the demand for memory storage capacity continues to increase, memory technology is constantly evolving towards smaller device sizes. For example, in 3D NAND flash memory arrays, the thickness of each word line is becoming thinner, the spacing between word lines is decreasing, and the number of stacked layers is increasing. This leads to increasingly severe capacitive coupling and back pattern dependency (BPD) effects. Consequently, the threshold voltage distribution of memory cells in open blocks of 3D NAND flash memory deviates from the threshold voltage distribution of memory cells in completed blocks. This results in increased read retry rates, decreased read performance, and a poor user experience when reading data from open block memory cells.

[0063] For example, consider a storage cell within a memory block as a three-level cell (TLC). Figure 4 As shown in (a), when all word lines in the memory block are write lines, it can be understood that all pages in the memory block are written with data, and this memory block can be called a complete block. Because the capacitive coupling effect between the write lines in the complete block is strong, and the back bias effect is also strong, the charge changes between the memory cells in the complete block can cancel each other out. The threshold voltage distribution shift of the memory cells in the complete block is small, which can also be called a small initial threshold voltage shift (IVS). The threshold voltage distribution curve of the memory cells in the complete block is as follows: Figure 4 The completed block curve is shown in (b) of the diagram.

[0064] like Figure 4As shown in (a), when some word lines in a memory block are used for writing data and the rest are used for not writing data, it is understandable that some pages in the memory block are used for writing data, and this memory block can be called an open block. Because the capacitive coupling effect between the word lines used for writing data in this open block is weak, and the back bias effect is also weak, the charge changes between the memory cells in the open block cannot cancel each other out, resulting in a large shift in the threshold voltage distribution of the memory cells in the open block. The threshold voltage distribution curve of the memory cells in this open block is as follows: Figure 4 The open block curve is shown in (b) of the diagram.

[0065] in, Figure 4 In (b), "L6" and "L7" represent different programming states. Figure 4 (b) in the example illustrates the two programming states. Based on the completed block curve and the open block curve, it can be understood that, compared with the threshold voltage distribution of the storage cells in the completed block in each programming state, the threshold voltage distribution of the storage cells in the open block in each corresponding programming state has a certain offset. This will result in an increased read retry rate, reduced read performance, and a poor user experience when reading data from the storage cells in the open block.

[0066] To address this issue, when a memory block is open, dummy data can be written to memory cells coupled to unwritten data word lines, transforming the block into a completed block. This enhances the capacitive coupling and back bias effects between word lines within the block, allowing charge changes between cells to cancel each other out, reducing threshold voltage distribution offset, lowering read retry rates, and improving read performance. However, writing dummy data to open blocks results in higher memory power consumption.

[0067] Experimental testing revealed that the offset of the threshold voltage distribution of memory cells within a memory block is related to the number of write word lines in the memory block. To address this issue, this disclosure provides an operation method for a memory system and a data reading method for a memory. These two methods determine the offset voltage value corresponding to a selected word line in the memory block based on the number of write data word lines, and apply a read voltage to the selected word line based on this offset voltage value. This reduces the memory's read retry rate, improves read performance, and enhances the user experience. These two methods can be applied to the aforementioned memory system 100. This disclosure provides an illustrative example using the application of this method to the aforementioned memory system 100.

[0068] like Figure 5 The diagram shown is a flowchart illustrating an operation method of a storage system and a data reading method of a memory provided in an embodiment of this disclosure. The method includes steps S501-S504.

[0069] S501, the controller 300 determines the offset voltage value corresponding to the selected word line among the N word lines based on the number N of word lines N and the offset voltage information. Here, the N word lines are adjacent word lines arranged in the storage block of the memory 200, and K storage cells coupled to the N word lines store data. K and N are positive integers, and this embodiment does not limit the specific values ​​of N and K. It can be understood that the above-mentioned N word lines are write data word lines. The offset voltage information is used to indicate the offset voltage value corresponding to N.

[0070] Optionally, the aforementioned offset voltage information can be in tabular form or other forms. This disclosure does not limit this; the following embodiments use tabular form as an example for illustrative purposes.

[0071] For example, the offset voltage information can be shown in Table 1 below. According to Table 1, different numbers of N word lines correspond to different offset voltage values. For instance, when the N word lines include one word line, it corresponds to an offset voltage value of 0.2; when the N word lines include two word lines, it corresponds to an offset voltage value of 0.1. Therefore, based on the number N of N word lines N and Table 1, the offset voltage value corresponding to the selected word line among the N word lines can be determined.

[0072] Table 1

[0073] The number of N word lines Offset voltage value 1 0.2 2 0.1 …… ……

[0074] Optionally, the selected character line can be one of N character lines, or it can be multiple of N character lines. This embodiment of the present disclosure does not limit this.

[0075] For example, when there are N character lines including 10 character lines, the selected character line can be one of the 10 character lines, or it can be three of the 10 character lines.

[0076] Optionally, the types of the aforementioned K storage units include at least one of single-level units, multi-level units, three-level units, and four-level units, and this disclosure does not limit this type.

[0077] Experimental testing revealed that when the selected word line is located at different positions among the N word lines, the threshold voltage offset of the memory cell coupled to the selected word line is different. The controller 300 determines the corresponding bias voltage value based on the position information of the selected word line among the N word lines, which can further improve the accuracy of the offset voltage value. The memory 200 applies a read voltage to the selected word line based on the offset voltage value, thereby further reducing the read retry rate and improving read performance.

[0078] In one possible embodiment, the controller 300 determines the offset voltage value corresponding to the selected word line among the N word lines based on the number N of N word lines and the offset voltage information. This includes: the controller 300 determines the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line, and the offset voltage information. The position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

[0079] Specifically, the selected character line may include a first selected character line or a second selected character line. The first selected character line includes the 1st character line to the (N-1)th character line, and the second selected character line includes the Nth character line. The controller 300 determines the offset voltage value corresponding to the selected character line based on N, the position information of the selected character line, and the offset voltage information. This includes: the controller 300 determining a first offset voltage value corresponding to the first selected character line based on N, the position information of the first selected character line, and the offset voltage information; or, the controller 300 determining a second offset voltage value corresponding to the second selected character line based on N, the position information of the second selected character line, and the offset voltage information, wherein the first offset voltage value is less than the second offset voltage value.

[0080] For example, when the offset voltage information is also used to indicate the offset voltage value corresponding to the position information of N and the selected word line, the offset voltage information can be as shown in Table 2. According to Table 2, when the N word lines include different numbers of word lines, and the selected word line is located in different positions among the N word lines, the selected word line corresponds to different offset voltage values.

[0081] For example, combining Figure 6 In example (a), the storage block contains G word lines, where G is a positive integer greater than or equal to N.

[0082] When n out of the G word lines are the word lines for writing data, and n is a positive integer, the memory block can be called the first open block. The number of the above N word lines is n. The first selected word line includes the 1st word line WL0 to the (N-1)th word line WLn-1, and the second selected word line includes the Nth word line WLn. According to Table 2, the offset voltage value corresponding to the first selected word line is O1, and the offset voltage value corresponding to the second selected word line is O1'.

[0083] When n+m word lines out of G word lines are used for writing data, and m is a positive integer, the memory block can be called the second open block. The number of the aforementioned N word lines is n+m. The first selected word line includes word line 1 WL0 to word line N-1 WLn+m-1, and the second selected word line includes word line N WLn+m. According to Table 2, the offset voltage value corresponding to the first selected word line is O2, and the offset voltage value corresponding to the second selected word line is O2'.

[0084] When n+y word lines out of G word lines are used for writing data, and y is a positive integer greater than m, the memory block can be called the third open block. The number of the above N word lines is n+y. The first selected word line includes word line 1 WL0 to word line N-1 WLn+y-1, and the second selected word line includes WLn+y. According to Table 2, the offset voltage value corresponding to the first selected word line is O3, and the offset voltage value corresponding to the second selected word line is O3'.

[0085] When all the word lines in the G word lines are word lines for writing data, the memory block can be called a complete block. The number of the above N word lines is G. The first selected word line includes word line 1 WL0 to word line N-1 WLG-1, and the second selected word line includes WLG. According to Table 2, the offset voltage values ​​corresponding to the first selected word line and the second selected word line are both 0.

[0086] Table 2

[0087]

[0088]

[0089] Optionally, the first selected character line may include one of the first character line to the (N-1)th character line, or may include multiple of the first character line to the (N-1)th character line. This embodiment of the present disclosure does not limit this.

[0090] Experimental testing revealed that the threshold voltage offset of the memory cell coupled to the selected word line differs when programmed to different programming states. The controller 300 determines the corresponding offset voltage value based on the preset read voltage corresponding to each programming state of the memory cell, which can further improve the accuracy of the offset voltage value. The memory 200 applies a read voltage to the selected word line based on the offset voltage value, thereby further reducing the read retry rate and improving read performance.

[0091] In one possible embodiment, among the K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states. The controller 300 determines the offset voltage value corresponding to the selected word line among the N word lines based on the number N of the N word lines and the offset voltage information, including:

[0092] Based on N, the position information of the selected word line, the preset read voltage of the selected memory cell, and the offset voltage information, the offset voltage value corresponding to the selected word line is determined. The selected memory cell is the memory cell coupled to the selected word line among the K memory cells. The preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell. The offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

[0093] For example, when the offset voltage information is also used to indicate the position information of N, the selected word line, and the offset voltage value corresponding to the preset read voltage of the selected memory cell, the offset voltage information can be as shown in Table 3. According to Table 3, when the memory cell coupled to the selected word line is programmed to different programming states, corresponding to different preset read voltages, the selected word line corresponds to different offset voltage values.

[0094] For example, combining Figure 6 In (a), a memory block includes G word lines, and the memory cells coupled to the G word lines are three-level cells. The memory cells coupled to the G word lines can be programmed to 8 programming states. Except for the first programming state and the erase state, the preset read voltages corresponding to the second to eighth programming states are V1 to V7, respectively.

[0095] When n out of G word lines are word lines for writing data, the selected word line is the first selected word line, which includes word line 1 WL0 to word line (N-1) WLn-1. The selected memory cell is the memory cell coupled to the first selected word line and programmed to the second programming state. When the preset read voltage of the selected memory cell is V1, according to Table 3, the offset voltage value corresponding to the selected word line is O1-V1.

[0096] When n out of G word lines are word lines for writing data, the selected word line is the second selected word line, which includes the Nth word line WLn. The selected memory cell is a memory cell coupled to the second selected word line and programmed to the 5th programming state. When the preset read voltage of the selected memory cell is V4, according to Table 3, the offset voltage value corresponding to the selected word line is O1-U4.

[0097] It is understandable that when the number N of selected word lines is n+m, n+y or G, the selected word line is the first selected word line or the second selected word line, and the selected memory cell is the memory cell coupled to the selected word line and programmed to any programming state, the corresponding offset voltage value can be determined according to Table 3 when the selected memory cell corresponds to any preset read voltage. The embodiments of this disclosure will not be described in detail here.

[0098] Table 3

[0099]

[0100] Optionally, the selected storage unit can be a single storage unit coupled to the selected word line, or it can be multiple storage units coupled to the selected word line. This embodiment of the present disclosure does not limit this.

[0101] In one possible embodiment, the storage block further includes M word lines arranged adjacent to the N word lines, and L storage cells coupled to the M word lines. The M word lines are arranged adjacent to each other, and no data is stored in the L storage cells. M is an integer greater than or equal to 0, and L is a positive integer. This embodiment does not limit the specific values ​​of M and L.

[0102] For example, when M equals 0, the storage block includes N word lines, and all N word lines are word lines for writing data; this storage block can be called a completed block. When M is greater than 0, the storage block includes N+M word lines, where N word lines are word lines for writing data and M word lines are word lines for not writing data; this storage block can be called an open block.

[0103] The aforementioned offset voltage information is determined by comparing the first threshold voltage distribution when data is stored in K memory cells with the second threshold voltage distribution when data is stored in K memory cells and L memory cells. It can be understood that when M equals 0, the aforementioned offset voltage information is determined by comparing the first threshold voltage distribution when the memory block is a completed block with the second threshold voltage distribution when the memory block is a completed block. When M is greater than 0, the aforementioned offset voltage information is determined by comparing the first threshold voltage distribution when the memory block is an open block with the second threshold voltage distribution when the memory block is a completed block.

[0104] This disclosure uses the determination of the offset voltage information shown in Table 3 as an example for illustrative purposes. The process of determining other offset voltage information can be referred to the following description, and will not be repeated here.

[0105] For example, such as Figure 6 As shown in (a), taking a storage block that includes G word lines, G = N + M, M is greater than 0, the storage block is the first open block, the number of N is n, and the storage cell coupled with the G word lines is a three-level cell as an example.

[0106] The threshold voltage distribution curves of the memory cells coupled to word lines WL0 (1st word line) to WLn-1 (N-1th word line) are as follows: Figure 6 The open block curve shown in (b) is the threshold voltage distribution curve of the memory cell coupled to the Nth word line WLn, as shown in the figure. Figure 6 The open block curves shown in (c) are, understandably, curves corresponding to the first threshold voltage distribution when data is stored in K memory cells.

[0107] When all of the G word lines are write data word lines, the threshold voltage distribution curve of the memory cell coupled to these G word lines is as follows: Figure 6 The completed block curve shown in (b) is, or, as in Figure 6The completion block curve shown in (c) is an example. It can be understood that these two completion block curves represent the second threshold voltage distributions when data is stored in K and L memory cells, respectively.

[0108] Here, L0 to L7 represent different programming states, and V1 to V7 represent the preset read voltages corresponding to the memory units of each programming state.

[0109] according to Figure 6 (b) and Figure 6 As shown in (c), by comparing the completed block curve and the open block curve, the offset voltage value corresponding to the selected memory cell coupled to the selected word line and programmed to any programming state at different positions among the N word lines can be determined. For example, according to Figure 6 In step (b), it can be determined that when the selected word line is the first word line WL0 among the N word lines, the memory cell coupled to the first word line WL0 is programmed to the programming state L1. When the preset read voltage V1 is applied, the offset voltage value corresponding to the selected word line is O1-V1. The specific process of determining the above offset voltage information based on the curves corresponding to the first threshold voltage distribution and the second threshold voltage distribution can be referred to the above description, and will not be repeated here in the embodiments of this disclosure.

[0110] In one possible embodiment, the aforementioned offset voltage information may be stored in the controller 300.

[0111] S502, the controller 300 sends a data read command to the memory 200. The data read command is used to instruct the memory 200 to generate a read voltage according to the offset voltage value and apply the read voltage to the selected word line.

[0112] S503, memory 200 receives data read commands.

[0113] S504, memory 200 generates and applies a read voltage to the selected word line according to the data read command.

[0114] The storage system operation method and memory data reading method provided in this disclosure determine the offset voltage value corresponding to the selected word line among the N word lines based on the number N word lines N and offset voltage information. These N word lines are adjacent word lines arranged in a storage block of the memory 200, and K storage cells coupled to the N word lines store data. It is understood that the offset voltage value determined in this disclosure takes into account the different offsets of the threshold voltage of the storage cells in the storage block when the number of data word lines written in the storage block is different. Therefore, the offset voltage value determined in this disclosure is more accurate, and the read voltage determined based on this offset voltage value is more accurate, thereby reducing the read retry rate of the memory 200 and improving read performance. Simultaneously, compared with the scheme of writing virtual data in open blocks, the power consumption of the memory 200 can be reduced.

[0115] This disclosure also provides a storage system including a controller and a memory coupled to the controller. The storage system can be structured as follows: Figure 1 The structure of the storage system 100 shown is illustrated in this embodiment of the present disclosure, which uses the structure of the storage system 100 as an example for illustrative purposes.

[0116] The controller 300 is configured to determine the offset voltage value corresponding to a selected word line among the N word lines based on the number N word lines N and the offset voltage information. The N word lines are adjacent word lines in a memory block, and data is stored in K memory cells coupled to the N word lines. K and N are positive integers. This embodiment does not limit the specific values ​​of N and K. The offset voltage information is used to indicate the offset voltage value corresponding to N.

[0117] Optionally, the aforementioned offset voltage information may be in tabular form or in other forms, and this disclosure does not limit this.

[0118] Optionally, the selected character line can be one of N character lines, or it can be multiple of N character lines. This embodiment of the present disclosure does not limit this.

[0119] Optionally, the types of the aforementioned K storage units include at least one of single-level units, multi-level units, three-level units, and four-level units, and this disclosure does not limit this type.

[0120] The controller 300 is also configured to send a data read command to the memory 200, which instructs the memory 200 to generate a read voltage based on an offset voltage value and apply the read voltage to the selected word line.

[0121] The memory 200 is configured to receive a data read command and, based on the data read command, generate and apply a read voltage to the selected word line.

[0122] In one possible embodiment, the controller 300 is further configured to determine the offset voltage value corresponding to the selected character line based on N, the position information of the selected character line, and the offset voltage information. The position information of the selected character line is used to indicate the position of the selected character line among the N character lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected character line.

[0123] In one possible embodiment, the selected character line includes a first selected character line or a second selected character line, the first selected character line includes the first character line to the (N-1)th character line, and the second selected character line includes the Nth character line.

[0124] The controller 300 is also configured to determine the first offset voltage value corresponding to the first selected character line based on N, the position information of the first selected character line, and the offset voltage information.

[0125] Alternatively, the controller 300 is also configured to determine the second offset voltage value corresponding to the second selected character line based on N, the position information of the second selected character line, and the offset voltage information, wherein the first offset voltage value is less than the second offset voltage value.

[0126] Optionally, the first selected character line may include one of the first character line to the (N-1)th character line, or may include multiple of the first character line to the (N-1)th character line. This embodiment of the present disclosure does not limit this.

[0127] In one possible embodiment, among the K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states. The controller 300 is further configured to determine the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line, the preset read voltage of the selected memory cell, and offset voltage information. The selected memory cell is the memory cell coupled to the selected word line among the K memory cells. The preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell. The offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

[0128] Optionally, the selected storage unit can be a single storage unit coupled to the selected word line, or it can be multiple storage units coupled to the selected word line. This embodiment of the present disclosure does not limit this.

[0129] The storage system provided in this disclosure determines the offset voltage value corresponding to a selected word line among the N word lines based on the number N of N word lines and offset voltage information. These N word lines are adjacent word lines arranged in a storage block of the memory 200, and K storage cells coupled to the N word lines store data. It is understood that the offset voltage value determined in this disclosure takes into account the different offsets of the threshold voltage of the storage cells in the storage block when the number of data-written word lines is different. Therefore, the offset voltage value determined in this disclosure is more accurate, and the read voltage determined based on this offset voltage value is more accurate, thereby reducing the read retry rate of the memory 200 and improving read performance.

[0130] Based on this, embodiments of this disclosure also provide a computer-readable storage medium storing a computer program that, when executed on a processor, causes the processor to perform actions such as... Figure 5 The operation method of the storage system or the data reading method of the memory are shown.

[0131] The detailed description of the operation method of the storage system and the data reading method of the memory, as well as the analysis of the beneficial effects, described above can be applied to the storage system and the computer-readable storage medium, and will not be repeated here in the embodiments of this application.

[0132] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a storage system, characterized in that, The storage system includes a memory, and the memory's storage block includes G word lines; The method includes: Based on the number N of the G word lines and the corresponding offset voltage information table, the offset voltage value corresponding to the selected word line among the N word lines is determined; the N word lines are word lines arranged adjacently in the memory block, and data is stored in the K memory cells coupled to the N word lines, where K is a positive integer, N is a positive integer greater than or equal to 2, and G is a positive integer greater than or equal to N. The offset voltage information table is used to indicate the offset voltage value corresponding to N; A data read command is sent to the memory, the data read command being used to instruct the memory to generate a read voltage based on the offset voltage value and apply the read voltage to the selected word line.

2. The method according to claim 1, characterized in that, The step of determining the offset voltage value corresponding to the selected word line among the N word lines based on the number N of the G word lines and the corresponding offset voltage information table includes: Based on N, the position information of the selected character line, and the offset voltage information table, the offset voltage value corresponding to the selected character line is determined. The position information of the selected character line is used to indicate the position of the selected character line among the N character lines, and the offset voltage information table is also used to indicate the offset voltage value corresponding to N and the position information of the selected character line.

3. The method according to claim 2, characterized in that, The selected character line includes a first selected character line or a second selected character line. The first selected character line includes the 1st character line to the (N-1)th character line, and the second selected character line includes the Nth character line. The step of determining the offset voltage value corresponding to the selected character line based on N, the position information of the selected character line, and the offset voltage information table includes: Based on N, the position information of the first selected character line, and the offset voltage information table, determine the first offset voltage value corresponding to the first selected character line; or, Based on N, the position information of the second selected character line, and the offset voltage information table, the second offset voltage value corresponding to the second selected character line is determined, and the first offset voltage value is less than the second offset voltage value.

4. The method according to claim 1, characterized in that, Of the K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states. The step of determining the offset voltage value corresponding to the selected word line among the N word lines based on the number N of the N word lines in the G word lines and the corresponding offset voltage information table includes: Based on N, the position information of the selected word line, the preset read voltage of the selected memory cell, and the offset voltage information table, the offset voltage value corresponding to the selected word line is determined. The selected memory cell is the memory cell coupled to the selected word line among the K memory cells. The preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell. The offset voltage information table is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

5. The method according to any one of claims 1-4, characterized in that, The storage block further includes M word lines arranged adjacent to the N word lines, and L storage cells coupled to the M word lines. The M word lines are arranged adjacent to each other, and the L storage cells do not store data. M is an integer greater than or equal to 0, and L is a positive integer. The offset voltage information table is determined by comparing the first threshold voltage distribution when data is stored in the K storage cells with the second threshold voltage distribution when data is stored in the K storage cells and the L storage cells.

6. A method for reading data from a memory, characterized in that, The memory block includes G word lines; the method includes: A data read command is received, which instructs the memory to generate a read voltage based on an offset voltage value and apply the read voltage to a selected word line among N word lines. The offset voltage value is determined based on the number N word lines among the G word lines and the corresponding offset voltage information table. The N word lines are adjacent word lines in the memory's block, and data is stored in K memory cells coupled to the N word lines. K is a positive integer, N is a positive integer greater than or equal to 2, and G is a positive integer greater than or equal to N. The offset voltage information table is used to indicate the offset voltage value corresponding to N. According to the data read command, the read voltage is generated and applied to the selected word line.

7. The method according to claim 6, characterized in that, The offset voltage value is determined based on N, the position information of the selected character line, and the offset voltage information table. The position information of the selected character line is used to indicate the position of the selected character line among the N character lines, and the offset voltage information table is also used to indicate the offset voltage value corresponding to N and the position information of the selected character line.

8. The method according to claim 7, characterized in that, The selected character line includes a first selected character line or a second selected character line. The first selected character line includes the 1st character line to the (N-1)th character line, and the second selected character line includes the Nth character line. The offset voltage value includes a first offset voltage value or a second offset voltage value. The first offset voltage value is determined based on N, the position information of the first selected character line, and the offset voltage information table. The second offset voltage value is determined based on N, the position information of the second selected character line, and the offset voltage information table. The first offset voltage value is less than the second offset voltage value.

9. The method according to claim 6, characterized in that, Of the K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states; the offset voltage value is determined based on N, the position information of the selected word line, the preset read voltage of the selected memory cell, and the offset voltage information table. The selected memory cell is the memory cell coupled to the selected word line among the K memory cells. The preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell. The offset voltage information table is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

10. The method according to any one of claims 6-9, characterized in that, The storage block further includes M word lines arranged adjacent to the N word lines, and L storage cells coupled to the M word lines. The M word lines are arranged adjacent to each other, and the L storage cells do not store data. M is an integer greater than or equal to 0, and L is a positive integer. The offset voltage information table is determined by comparing the first threshold voltage distribution when data is stored in the K storage cells with the second threshold voltage distribution when data is stored in the K storage cells and the L storage cells.

11. A storage system, characterized in that, The storage system includes a controller and a memory coupled to the controller, wherein a storage block of the memory includes G word lines; The controller is configured to determine the offset voltage value corresponding to the selected word line among the N word lines based on the number N of N word lines in the G word lines and the corresponding offset voltage information table; The N word lines are adjacent word lines in the memory block, and data is stored in the K memory cells coupled to the N word lines. K is a positive integer, N is a positive integer greater than or equal to 2, and G is a positive integer greater than or equal to N. The offset voltage information table is used to indicate the offset voltage value corresponding to N. The controller is also configured to send a data read command to the memory, the data read command being used to instruct the memory to generate a read voltage based on the offset voltage value and apply the read voltage to the selected word line; The memory is configured to receive the data read command, and according to the data read command, generate and apply the read voltage to the selected word line.

12. The storage system according to claim 11, characterized in that, The controller is further configured to determine the offset voltage value corresponding to the selected character line based on N, the position information of the selected character line, and the offset voltage information table. The position information of the selected character line is used to indicate the position of the selected character line among the N character lines, and the offset voltage information table is also used to indicate the offset voltage value corresponding to N and the position information of the selected character line.

13. The storage system according to claim 12, characterized in that, The selected character line includes a first selected character line or a second selected character line. The first selected character line includes the 1st character line to the (N-1)th character line, and the second selected character line includes the Nth character line. The controller is further configured to determine the first offset voltage value corresponding to the first selected character line based on N, the position information of the first selected character line, and the offset voltage information table; or, The controller is further configured to determine a second offset voltage value corresponding to the second selected character line based on N, the position information of the second selected character line, and the offset voltage information table, wherein the first offset voltage value is less than the second offset voltage value.

14. The storage system according to claim 11, characterized in that, Of the K storage units, the storage unit coupled to the selected word line is programmed into multiple programming states; The controller is further configured to determine the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line, the preset read voltage of the selected memory unit, and the offset voltage information table. The selected memory unit is the memory unit coupled to the selected word line among the K memory units. The preset read voltage of the selected memory unit is the read voltage corresponding to the programming state of the selected memory unit. The offset voltage information table is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory unit.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed on a processor, causes the processor to perform an operation method of the storage system as described in any one of claims 1-5, or to perform a data reading method of the memory as described in any one of claims 6-10.

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