Redundancy replacement control circuit, memory array and flash memory

Abstract

The invention relates to the technical field of memories, in particular to a redundancy replacement control circuit, a memory array and a flash memory, and the redundancy replacement control circuit comprises an address segmentation comparison module which is used for segmenting and judging whether an operation word line address and a defect word line address are the same or not, a plurality of different segmented judgment signals and final judgment signals are output; an erasing judgment module; and the replacement control module is used for generating a replacement control signal according to the final judgment signal and the erasing judgment signal, and the replacement control signal is used for controlling the replacement state of the redundant word line corresponding to the defective word line. According to the redundancy replacement control circuit, the problem that existing redundancy replacement operation control logic is complex can be solved, the control logic is simple, redundancy replacement can be carried out only when the storage area needing to be erased contains a defective unit, and the erase operation for the storage area in any range can be smoothly executed.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a redundant replacement control circuit, a storage array and a flash memory. Background Art

[0002] When a memory cell in a memory array of a flash memory is defective or malfunctions, the operation performed by the flash memory on the defective or malfunctioning memory cell may go wrong. Some flash memories solve this problem based on a redundant replacement operation, that is, by setting a plurality of redundant bit lines composed of redundant cells, and when performing an operation on a defective or malfunctioning memory cell, the operation is performed based on the redundant bit line instead of the bit line where the defective or malfunctioning memory cell is located. However, since the existing redundant replacement operation process is generally performed based on the bit line, the control logic is complicated.

[0003] There is currently no effective technical solution to the above problems. Summary of the invention

[0004] The purpose of the present application is to provide a redundant replacement control circuit, a storage array and a flash memory, aiming to solve the problem of complex control logic of existing redundant replacement operations.

[0005] In a first aspect, the present application provides a redundancy replacement control circuit, which is applied in a flash memory and is used to perform redundancy replacement on a defective word line based on a redundant word line. The redundancy replacement control circuit includes: An address segmentation comparison module, whose input terminal inputs the operation word line address and the defective word line address, is used for segmentation determination whether the operation word line address and the defective word line address are the same, so as to output a plurality of different segmentation determination signals and a final determination signal; An erase judgment module, whose input end is connected to the output end of the address segment comparison module and inputs an erase enable, is used to judge whether the storage area to be erased includes a defective word line according to a plurality of segment judgment signals and the erase enable, and output an erase judgment signal; The replacement control module has an input end connected to the output end of the address segment comparison module and the output end of the erase judgment module, and is used to generate a replacement control signal according to the final judgment signal and the erase judgment signal. The replacement control signal is used to control the replacement state of the redundant word line corresponding to the defective word line.

[0006] The redundant replacement control circuit provided in the present application replaces the word line where the defective unit is located based on the redundant word line corresponding to the defective word line. The control logic is simple, and redundant replacement can be performed only when the storage area to be erased contains defective units, so that the erase operation for any range of storage areas can be performed smoothly.

[0007] Optionally, the erase enable includes a 64KB erase enable; The segment determination signal includes a first segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition greater than 64KB are consistent, and a second segment determination signal representing whether the address bits of the operation word line address and the defective cell address representing the partition of 64KB are consistent; The erasure judgment signal includes a first erasure judgment signal; The erasure judgment module includes a first judgment module; The input end of the first judgment module inputs 64KB erase enable, the first segment judgment signal and the second segment judgment signal, and the output end outputs the first erase judgment signal.

[0008] In this embodiment, the first judgment module of the present application outputs a first erase judgment signal based on the 64KB erase enable, the first segment judgment signal and the second segment judgment signal, and can accurately judge whether the 64KB partition to be erased includes a defective word line, thereby enabling the operation of erasing the 64KB partition to be executed normally.

[0009] Optionally, the first judgment module includes: A first NAND gate, a first input terminal and a second input terminal of which are respectively input with a 64KB erase enable signal and a first segment determination signal; The first NOR gate has a first input terminal connected to the output terminal of the first NAND gate, a second input terminal inputting the second segment determination signal, and an output terminal outputting the first erasure determination signal.

[0010] In this embodiment, the present application can output a first erase judgment signal with a high level only when the 64KB partition to be erased includes a defective word line, thereby enabling the redundant word line to correctly replace the word line where the defective unit is located when the 64KB partition needs to be erased.

[0011] Optionally, the erase enable further includes a 32KB erase enable; The segment determination signal also includes a third segment determination signal representing whether the address bits of the 32KB partitions representing the operation word line address and the defective word line address are consistent or not; The erasure judgment signal further includes a second erasure judgment signal; The erasure judgment module also includes a second judgment module; The second judgment module includes: A second NAND gate, a first input terminal, a second input terminal and a third input terminal of which are respectively input with a 32KB erase enable, a first segment determination signal and an inverted second segment determination signal; The second NOR gate has a first input terminal connected to the output terminal of the second NAND gate, a second input terminal inputting the third segment determination signal, and an output terminal outputting the second erasure determination signal.

[0012] Optionally, the erase enable further includes a 4KB erase enable; The segment determination signal further includes a fourth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition less than or equal to 64KB and greater than 8KB are consistent, a fifth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the 8KB partition are consistent, and a sixth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the 4KB partition are consistent; The erasure judgment signal further includes a third erasure judgment signal; The erasure judgment module also includes a third judgment module; The third judgment module includes: A third NOR gate, a first input terminal and a second input terminal of which are respectively input with the fifth segment determination signal and the sixth segment determination signal; A third NAND gate, a first input terminal of which is connected to the output terminal of the third NOR gate, and a second input terminal of which is input with a 4KB erase enable; A fourth NAND gate, wherein the first input terminal and the second input terminal of the fourth NAND gate are respectively input with the first segment determination signal and the fourth segment determination signal; The first input terminal and the second input terminal of the fourth NOR gate are respectively connected to the output terminal of the third NAND gate and the output terminal of the fourth NAND gate, and the output terminal outputs the third erasure judgment signal.

[0013] Optionally, the redundant replacement control circuit further includes: The fifth NOR gate has a first input terminal, a second input terminal and a third input terminal respectively inputting the first erasure judgment signal, the second erasure judgment signal and the third erasure judgment signal, and an output terminal connected to an input terminal of the replacement control module.

[0014] Optionally, the replacement control module comprises: a fifth NAND gate, a first input terminal of which is input with the final judgment signal, and a second input terminal of which is connected with the output terminal of the fifth NOR gate; The sixth NAND gate has a first input terminal connected to the output terminal of the fifth NAND gate, a second input terminal inputting an operation enable signal, and an output terminal generating a replacement control signal, wherein the operation enable signal is used to control the redundant word line corresponding to the defective word line to perform an operation.

[0015] Optionally, the erase enable also includes a full chip erase enable; The erasure judgment signal further includes a fourth erasure judgment signal; The erasure judgment module further includes a fourth judgment module; The fourth judgment module includes: A NOT gate, having an input terminal inputting a full-chip erase enable and an output terminal outputting a fourth erase judgment signal.

[0016] In a second aspect, the present application provides a storage array, comprising any redundant replacement control circuit as described above.

[0017] The storage array provided by the present application replaces the word line where the defective cell is located based on the redundant word line corresponding to the defective word line. The control logic is simple, and redundant replacement can be performed only when the storage area to be erased contains defective cells, so that the erase operation for any range of storage areas can be performed smoothly.

[0018] In a third aspect, the present application provides a flash memory, comprising any of the above redundant replacement control circuits or the above storage arrays.

[0019] The flash memory provided by the present application replaces the word line where the defective unit is located based on the redundant word line corresponding to the defective word line. The control logic is simple, and redundant replacement can be performed only when the storage area to be erased contains defective units, so that the erase operation for any range of storage areas can be executed smoothly.

[0020] As can be seen from the above, the present application provides a redundant replacement control circuit, a storage array and a flash memory, wherein the redundant replacement control circuit of the present application replaces the word line where the defective unit is located based on the redundant word line corresponding to the defective word line, the control logic is simple, and redundant replacement can be performed only when the storage area to be erased contains a defective unit, so that the erase operation for any range of the storage area can be performed smoothly. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of a redundant replacement control circuit provided in an embodiment of the present application.

[0022] Figure 2 A structural schematic diagram of a fourth judgment module provided in an embodiment of the present application.

[0023] Figure 3 A schematic diagram of the structure of an address segment comparison module suitable for a dual-bit split-gate flash memory provided in an embodiment of the present application.

[0024] Figure 4 A schematic diagram of the structure of an address segment comparison module suitable for a general flash memory provided in an embodiment of the present application.

[0025] Explanation of reference numerals: 1. address segment comparison module; 11. XOR gate; 12. sixth NOR gate; 13. seventh NAND gate; 2. erase judgment module; 21. first judgment module; 211. first NAND gate; 212. first NOR gate; 22. second judgment module; 221. second NAND gate; 222. second NOR gate; 23. third judgment module; 231. third NOR gate; 232. third NAND gate; 233. fourth NAND gate; 234. fourth NOR gate; 24. fourth judgment module; 241. NAND gate; 3. replacement control module; 31. fifth NAND gate; 32. sixth NAND gate; 4. fifth NOR gate. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0027] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0028] First, as Figure 1 As shown, the present application provides a redundancy replacement control circuit, which is applied in a flash memory and is used to perform redundancy replacement on a defective word line based on a redundant word line. The redundancy replacement control circuit includes: An address segmentation comparison module 1, whose input terminal inputs the operation word line address and the defective word line address, is used to segmentally determine whether the operation word line address and the defective word line address are the same, so as to output a plurality of different segmentation determination signals and a final determination signal; An erase judgment module 2, whose input end is connected to the output end of the address segment comparison module and inputs an erase enable, is used to judge whether the storage area to be erased includes a defective word line according to a plurality of segment judgment signals and the erase enable, and output an erase judgment signal; The replacement control module 3, whose input end is connected to the output end of the address segment comparison module and the output end of the erase judgment module 2, is used to generate a replacement control signal according to the final judgment signal and the erase judgment signal. The replacement control signal is used to control the replacement state of the redundant word line corresponding to the defective word line.

[0029] Specifically, in Figure 1 In the example, match is the replacement control signal, and Bad_cell is the final judgment signal.

[0030] More specifically, the operation word line address refers to the address of the word line that is the operation object; the defective word line address is the address of the defective word line, the defective word line is the word line where the defective unit is located, and the defective unit refers to a storage unit that is defective or functionally abnormal; segmented judgment of whether the operation word line address and the defective word line address are the same refers to dividing the operation word line address and the defective word line address into multiple operation word line address bit groups and defective word line address bit groups, respectively, and judging whether the corresponding operation word line address bit groups and defective word line address bit groups are the same, wherein the operation word line address bit groups and the defective word line address bit groups correspond one to one, and the corresponding operation word line address bit groups and defective word line address bit groups have the same number of address bits.

[0031] More specifically, the redundant word line corresponding to the defective word line refers to a redundant word line used to replace the word line where the defective cell is located.

[0032] More specifically, since the address segmentation comparison module 1 can determine whether the operation word line address and the defective word line address are the same, the erase judgment module 2 can control the replacement control module 3 to generate a replacement control signal based on the final judgment signal when the operation word line address and the defective word line address are exactly the same, so that the redundant word line corresponding to the defective word line replaces the word line where the defective unit is located, thereby enabling the redundant word line to replace the word line where the defective unit is located to perform the corresponding operation normally.

[0033] More specifically, for the operation word line address and the defective word line address, the number of word lines between the two is related to the similarities and differences in the address bits of the two word lines, and because the address segmentation comparison module 1 can determine in segments whether the operation word line address and the defective word line address are the same, the address segmentation comparison module 1 can, when it is necessary to perform an erase operation on a storage area, determine whether the word line as the object of the erase operation and the word line where the defective unit is located are located in the same storage area based on whether some address bits of the operation word line address and the defective word line address are the same. Therefore, when it is necessary to perform an erase operation on the storage area and the storage area includes a defective word line, the erase judgment module 2 outputs an erase judgment signal based on the segmentation judgment signal in cooperation with the erase enable control to control the replacement control module 3 to generate a replacement control signal, so that the redundant word line corresponding to the defective word line can replace the word line where the defective unit is located, so that the erase operation performed on the storage area where the defective unit is located can be smoothly executed.

[0034] The redundant replacement control circuit provided in the present application replaces the word line where the defective unit is located based on the redundant word line corresponding to the defective word line. The control logic is simple, and redundant replacement can be performed only when the storage area to be erased contains defective units, so that the erase operation for any range of storage areas can be performed smoothly.

[0035] In some preferred embodiments, the erase enable includes a 64KB erase enable; The segment determination signal includes a first segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition greater than 64KB are consistent, and a second segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition of 64KB are consistent; The erasure judgment signal includes a first erasure judgment signal; The erasure judgment module 2 includes a first judgment module 21; The first judgment module 21 has an input terminal that inputs 64KB erase enable, a first segment judgment signal, and a second segment judgment signal, and an output terminal that outputs a first erase judgment signal.

[0036] Specifically, in Figure 1 In the figure, BE64KB is 64KB erase enable, Addr_match_H is the first segment judgment signal, 64KB_flag is the second segment judgment signal; 64ERSSEL is the first erase judgment signal.

[0037] More specifically, taking a dual-bit split-gate flash memory as an example, a dual-bit split-gate flash memory is a flash memory in which one storage unit has two data storage bits. Therefore, for a dual-bit split-gate flash memory with 1024 word lines and 2048 bit lines and a size of 4Mbit, the seventh bit of its word line address corresponds to a 64KB partition, and the upper three bits of its word line address correspond to a partition greater than 64KB.

[0038] More specifically, for the word line address, when the address bit representing a partition larger than 64KB is increased or decreased by one, the amount of data between the word lines before and after the change is greater than 64KB; when the address bit representing a partition of 64KB is increased or decreased by one, the amount of data between the word lines before and after the change is 64KB.

[0039] More specifically, if the operation word line address and the defective word line address represent a partition greater than 64KB and the address bits representing the 64KB partition are consistent, it can be known that the storage area between the operation word line and the word line where the defective unit is located is less than 64KB, and the operation word line address and the defective word line address are located in the same 64KB partition. Therefore, in this embodiment, the first judgment module 21 of the present application outputs a first erase judgment signal based on the 64KB erase enable, the first segment judgment signal and the second segment judgment signal, and can accurately judge whether the 64KB partition to be erased includes a defective word line, so that the operation of erasing the 64KB partition can be executed normally.

[0040] In some preferred implementations, the first determination module 21 includes: A first NAND gate 211, a first input terminal and a second input terminal of which are respectively input with a 64KB erase enable signal and a first segment determination signal; The first NOR gate 212 has a first input terminal connected to the output terminal of the first NAND gate 211, a second input terminal inputting the second segment determination signal, and an output terminal outputting the first erasure determination signal.

[0041] Specifically, when the address bits representing the operation word line address and the defective word line address are both greater than the 64KB partition and the address bits representing the 64KB partition are consistent, and the 64KB partition needs to be erased, the 64KB partition that needs to be erased including the operation word line also includes the defective word line, the first segment judgment signal and the 64KB erase enable are both high-level signals and the second segment judgment signal is a low-level signal, so the first NAND gate 211 inputs a low-level signal to the first NOR gate 212, and the first erase judgment signal output by the first NOR gate 212 is a high-level signal; in other embodiments, the first erase judgment signal is a low-level signal. Therefore, in this embodiment, the present application can output a first erase judgment signal with a high level only when the 64KB partition that needs to be erased includes a defective word line, so that the redundant word line can correctly replace the word line where the defective unit is located when the 64KB partition needs to be erased.

[0042] In some preferred embodiments, the erase enable further includes a 32KB erase enable; The segment determination signal also includes a third segment determination signal representing whether the address bits of the 32KB partitions representing the operation word line address and the defective word line address are consistent or not; The erasure judgment signal further includes a second erasure judgment signal; The erasure judgment module 2 further includes a second judgment module 22; The second judgment module 22 includes: The second NAND gate 221, whose first input terminal, second input terminal and third input terminal respectively input the 32KB erase enable, the first segment determination signal and the inverted second segment determination signal; The second NOR gate 222 has a first input terminal connected to the output terminal of the second NAND gate 221, a second input terminal inputting the third segment determination signal, and an output terminal outputting the second erasure determination signal.

[0043] Specifically, in Figure 1 In the figure, BE32KB is 32KB erase enable, 32KB_flag is the third segment judgment signal, and 32ERSSEL is the second erase judgment signal.

[0044] More specifically, for a word line address, when the address bit representing a 32KB partition is increased or decreased by one, the word lines before and after the change are separated by 32KB of data.

[0045] More specifically, if the operating word line address and the defective word line address represent a partition greater than 64KB, and the address bits representing the 64KB partition and the 32KB partition are consistent, it can be known that the storage area between the operating word line and the word line where the defective unit is located is less than 32KB, and the operating word line address and the defective word line address are located in the same 32KB partition.

[0046] More specifically, when the address bits of the operation word line address and the defective word line address representing a partition greater than 64KB, representing a 64KB partition and representing a 32KB partition are consistent, and the 32KB partition needs to be erased, the 32KB partition that needs to be erased including the operation word line also includes a defective word line, the first segment judgment signal and the 32KB erase enable are both high-level signals, and the second segment judgment signal and the third segment judgment signal are both low-level signals, so the second NAND gate 221 inputs a low-level signal to the second NOR gate 222, and the second erase judgment signal output by the second NOR gate 222 is a high-level signal; in other embodiments, the second erase judgment signal is a low-level signal. Therefore, in this embodiment, the present application can output a second erase judgment signal with a high level only when the 32KB partition that needs to be erased includes a defective word line, so that the redundant word line can correctly replace the word line where the defective unit is located when the 32KB partition needs to be erased.

[0047] In some preferred embodiments, the erase enable further includes a 4KB erase enable; The segment determination signal further includes a fourth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition less than or equal to 64KB and greater than 8KB are consistent, a fifth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the 8KB partition are consistent, and a sixth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the 4KB partition are consistent; The erasure judgment signal further includes a third erasure judgment signal; The erasure judgment module 2 further includes a third judgment module 23; The third judgment module 23 includes: A third NOR gate 231, a first input terminal and a second input terminal of which are respectively input with the fifth segment determination signal and the sixth segment determination signal; A third NAND gate 232, a first input terminal of which is connected to the output terminal of the third NOR gate 231, and a second input terminal of which is input with a 4KB erase enable; A fourth NAND gate 233, whose first input terminal and second input terminal are respectively input with the first segment determination signal and the fourth segment determination signal; The fourth NOR gate 234 has a first input terminal and a second input terminal connected to the output terminal of the third NAND gate 232 and the output terminal of the fourth NAND gate 233 respectively, and an output terminal outputs a third erasure determination signal.

[0048] Specifically, in Figure 1 In the figure, SE4KB is 4KB erase enable, Addr_match_M is the fourth segment judgment signal, Unit_h is the fifth segment judgment signal, 4KB_flag is the sixth segment judgment signal, and SESERSSEL is the third erase judgment signal.

[0049] More specifically, for the word line address, when the address bit representing a partition less than or equal to 64KB and greater than 8KB is increased or decreased by one, the amount of data between the word lines before and after the change is less than or equal to 64KB and greater than 8KB; when the address bit representing an 8KB partition is increased or decreased by one, the word lines before and after the change are separated by 8KB of data; when the address bit representing a 4KB partition is increased or decreased by one, the word lines before and after the change are separated by 4KB of data.

[0050] More specifically, if the address bits of the operating word line address and the defective word line address representing a partition greater than 64KB, a partition less than or equal to 64KB and greater than 8KB, an 8KB partition, and a 4KB partition are all consistent, it can be seen that the storage area between the operating word line and the word line where the defective unit is located is less than 4KB, and the operating word line address and the defective word line address are located in the same 4KB partition.

[0051] More specifically, when the address bits of the operating word line address and the defective word line address representing a partition greater than 64KB, a partition less than or equal to 64KB and greater than 8KB, an 8KB partition, and a 4KB partition are all consistent, and the 4KB partition needs to be erased, the 4KB partition that needs to be erased including the operating word line also includes the defective word line, the first segment judgment signal, the fourth segment judgment signal, and the 4KB erase enable are all high-level signals and the fifth segment judgment signal and the sixth segment judgment signal are all low-level signals, so the third NOR gate 231 outputs a high-level signal to the third NAND gate 232, the third NAND gate 232 and the fourth NAND gate 233 output low-level signals to the fourth NOR gate 234, and the third erase judgment signal output by the fourth NOR gate 234 is a high-level signal; in other embodiments, the third erase judgment signal is a low-level signal. Therefore, in this embodiment, the present application can output a third erase judgment signal with a high level only when the 4KB partition to be erased includes a defective word line, thereby enabling the redundant word line to correctly replace the word line where the defective unit is located when the 4KB partition needs to be erased.

[0052] In some preferred embodiments, the redundant replacement control circuit further comprises: The fifth NOR gate 4 has a first input terminal, a second input terminal and a third input terminal respectively inputting the first erasure judgment signal, the second erasure judgment signal and the third erasure judgment signal, and an output terminal connected to an input terminal of the replacement control module 3 .

[0053] Specifically, when one or more of the first erasure judgment signal, the second erasure judgment signal, and the third erasure signal is a high-level signal, the fifth NOR gate 4 outputs a low-level signal to the replacement control module 3. Therefore, in this embodiment, the present application sets the fifth NOR gate 4, which can output signals with the same level to the replacement control module 3 when it is necessary to erase the 64KB partition, the 32KB partition, or the 4KB partition, so that the redundant word line can correctly replace the word line where the defective unit is located when it is necessary to erase the 64KB partition, the 32KB partition, or the 4KB partition.

[0054] In some preferred embodiments, the replacement control module 3 includes: A fifth NAND gate 31, a first input terminal of which inputs the final judgment signal, and a second input terminal of which is connected to the output terminal of the fifth NOR gate 4; The sixth NAND gate 32 has a first input terminal connected to the output terminal of the fifth NAND gate 31, a second input terminal inputting an operation enable signal, and an output terminal generating a replacement control signal. The operation enable signal is used to control the redundant word line corresponding to the defective word line to perform an operation.

[0055] Specifically, in Figure 1 EN is the operation enable signal.

[0056] More specifically, when the 64KB partition, 32KB partition or 4KB partition needs to be erased and the storage area to be erased includes a defective word line, the fifth NOR gate 4 inputs a low-level signal to the fifth NAND gate 31, the fifth NAND gate 31 outputs a high-level signal to the sixth NAND gate 32, and the sixth NAND gate 32 generates a replacement control signal with a low level; in other embodiments, the sixth NAND gate 32 generates a replacement control signal with a high level. Therefore, in this embodiment, the present application can output a replacement control signal with a low level only when the 64KB partition, 32KB partition or 4KB partition to be erased includes a defective word line, so that the redundant word line can correctly replace the defective word line when the 64KB partition, 32KB partition or 4KB partition needs to be erased. In addition, when the operation word line address and the defective word line address are completely consistent, the final judgment signal is a low-level signal, the fifth NOR gate 4 inputs a low-level signal to the fifth NAND gate 31, the fifth NAND gate 31 outputs a high-level signal to the sixth NAND gate 32, and the sixth NAND gate 32 generates a replacement control signal with a low level; therefore, in this embodiment, the present application can realize the correct replacement of the redundant word line with the word line where the defective unit is located when it is necessary to perform an operation on the word line where the defective unit is located separately.

[0057] like Figure 2 As shown, in some preferred embodiments, the erase enable further includes a full-chip erase enable; The erasure judgment signal further includes a fourth erasure judgment signal; The erasure judgment module 2 further includes a fourth judgment module 24; The fourth determination module 24 includes: The NOT gate 241 has an input terminal inputting the chip-wide erase enable signal, and an output terminal outputting the fourth erase determination signal.

[0058] Specifically, Chip_erase is the chip-wide erase enable, and ERSSEL is the fourth erase determination signal.

[0059] More specifically, full chip erasure refers to an erase operation performed on the entire storage array. When full chip erasure is required, full chip erase enable is a high level signal, and the fourth erase judgment signal output by the NOT gate 241 is a low level signal; when full chip erasure is not required, the fourth erase judgment signal is a high level signal. Therefore, in this embodiment, the present application can realize the correct replacement of the redundant word line with the word line where the defective unit is located when full chip erasure is required.

[0060] Preferably, the third input terminal of the fifth NAND gate 31 inputs the fourth erasure determination signal.

[0061] Specifically, when full chip erasure is required, the fourth erasure judgment signal input by the fourth judgment module 24 to the fifth NAND gate 31 is a low level signal, the fifth NAND gate 31 outputs a high level signal to the sixth NAND gate 32, and the sixth NAND gate 32 generates a replacement control signal with a low level. Therefore, in this embodiment, the present application can realize the correct replacement of the redundant word line with the word line where the defective unit is located when full chip erasure is required.

[0062] like Figure 3 As shown, preferably, the address segment comparison module 1 includes: Ten XOR gates 11, whose first input terminal and second input terminal respectively input ten address bits of the operation word line address and the defective word line address; Three sixth NOR gates 12, whose input ends are respectively connected to the output ends of three XOR gates 11 corresponding to the highest three bits of the operation word line address and the defective word line address, the output ends of three XOR gates 11 corresponding to the middle three bits of the operation word line address and the defective word line address, and the output ends of four XOR gates 11 corresponding to the lowest four bits of the operation word line address and the defective word line address, and the output ends respectively output the first segment judgment signal, the fourth segment judgment signal and the seventh segment judgment signal, and the seventh segment judgment signal is used to indicate whether the address bits of the operation word line address and the defective word line address representing the partition less than or equal to 8KB are consistent or not; A seventh NAND gate 13, whose first input terminal, second input terminal and third input terminal respectively input the first segment judgment signal, the fourth segment judgment signal and the seventh segment judgment signal, and whose output terminal outputs the final judgment signal; The output end of the XOR gate 11 corresponding to the seventh bit of the operation word line address and the defective word line address outputs a second segment judgment signal, the output end of the XOR gate 11 corresponding to the sixth bit of the operation word line address and the defective word line address outputs a third segment judgment signal, the output end of the XOR gate 11 corresponding to the fourth bit of the operation word line address and the defective word line address outputs a fifth segment judgment signal, and the output end of the XOR gate 11 corresponding to the third bit of the operation word line address and the defective word line address outputs a sixth segment judgment signal.

[0063] Specifically, in Figure 3 In the example, Input_addr<9:0> is the operation word line address, Bad_addr<9:0> is the defective word line address, and Addr_match_L is the seventh segment determination signal.

[0064] More specifically, the address segmentation comparison module 1 of the present embodiment is applicable to any dual-bit split-gate flash memory. In such flash memory, the highest three bits of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address indicating a partition greater than 64KB, the middle three bits of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address indicating a partition less than or equal to 64KB and greater than 8KB, the seventh bit of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address indicating a 64KB partition, the sixth bit of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address indicating a 32KB partition, the fourth bit of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address indicating an 8KB partition, and the third bit of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address indicating a 4KB partition.

[0065] In this embodiment, the present application can realize that the address segment comparison module 1 outputs a corresponding signal of appropriate level to the erase judgment module 2 and the replacement control module 3, so as to determine whether the storage area to be erased includes a defective word line, and can realize the correct replacement of the redundant word line with the word line where the defective unit is located when an operation needs to be performed on the word line where the defective unit is located.

[0066] like Figure 4 As shown, in some other implementations, the address segment comparison module 1 includes: Eleven XOR gates 11, whose first input terminal and second input terminal respectively input ten address bits of the operation word line address and the defective word line address; Three sixth NOR gates 12, whose input ends are respectively connected to the output ends of three XOR gates 11 corresponding to the highest three bits of the operation word line address and the defective word line address, the output ends of three XOR gates 11 corresponding to the middle three bits of the operation word line address and the defective word line address, and the output ends of four XOR gates 11 corresponding to the lowest five bits of the operation word line address and the defective word line address, and the output ends respectively output the first segment judgment signal, the fourth segment judgment signal and the seventh segment judgment signal, and the seventh segment judgment signal is used to indicate whether the address bits of the operation word line address and the defective word line address representing the partition less than or equal to 8KB are consistent or not; A seventh NAND gate 13, whose first input terminal, second input terminal and third input terminal respectively input the first segment judgment signal, the fourth segment judgment signal and the seventh segment judgment signal, and whose output terminal outputs the final judgment signal; The output end of the XOR gate 11 corresponding to the eighth bit of the operation word line address and the defective word line address outputs a second segment judgment signal, the output end of the XOR gate 11 corresponding to the seventh bit of the operation word line address and the defective word line address outputs a third segment judgment signal, the output end of the XOR gate 11 corresponding to the fifth bit of the operation word line address and the defective word line address outputs a fifth segment judgment signal, and the output end of the XOR gate 11 corresponding to the fourth bit of the operation word line address and the defective word line address outputs a sixth segment judgment signal.

[0067] Specifically, in Figure 4 In the example, Input_addr<10:0> is the operation word line address, Bad_addr<10:0> is the defective word line address, and Addr_match_L is the seventh segment determination signal.

[0068] More specifically, the address segmentation comparison module 1 of the present embodiment is applicable to a general flash memory, in which the top three bits of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address representing a partition greater than 64KB, the middle three bits of the operation word line address and the defective word line address are the address bits of the operation word line address and the defective word line address representing a partition less than or equal to 64KB and greater than 8KB, the eighth bit of the operation word line address and the defective word line address is the address bit of the operation word line address and the defective word line address representing a 64KB partition, the seventh bit of the operation word line address and the defective word line address is the address bit of the operation word line address and the defective word line address representing a 32KB partition, the fifth bit of the operation word line address and the defective word line address is the address bit of the operation word line address and the defective word line address representing an 8KB partition, and the fourth bit of the operation word line address and the defective word line address is the address bit of the operation word line address and the defective word line address representing a 4KB partition.

[0069] In this embodiment, the present application can realize that the address segment comparison module 1 outputs a corresponding signal of appropriate level to the erase judgment module 2 and the replacement control module 3, so as to determine whether the storage area to be erased includes a defective word line, and can realize the correct replacement of the redundant word line with the word line where the defective unit is located when an operation needs to be performed on the word line where the defective unit is located.

[0070] In a second aspect, the present application provides a storage array, comprising any redundant replacement control circuit as described above.

[0071] The storage array provided by the present application replaces the word line where the defective cell is located based on the redundant word line corresponding to the defective word line. The control logic is simple, and redundant replacement can be performed only when the storage area to be erased contains defective cells, so that the erase operation for any range of storage areas can be performed smoothly.

[0072] In a third aspect, the present application provides a flash memory, comprising any of the above redundant replacement control circuits or the above storage arrays.

[0073] The flash memory provided by the present application replaces the word line where the defective unit is located based on the redundant word line corresponding to the defective word line. The control logic is simple, and redundant replacement can be performed only when the storage area to be erased contains defective units, so that the erase operation for any range of storage areas can be executed smoothly.

[0074] In summary, the present application provides a redundant replacement control circuit, a storage array and a flash memory, wherein the redundant replacement control circuit of the present application replaces the word line where the defective unit is located based on the redundant word line corresponding to the defective word line, has a simple control logic, and can perform redundant replacement only when the storage area to be erased contains a defective unit, so that the erase operation for any range of the storage area can be performed smoothly.

[0075] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0076] In addition, the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple grid units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0077] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0078] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0079] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A redundant replacement control circuit, characterized in that: The invention is applied in a flash memory to replace a defective word line with redundancy based on a redundant word line. The redundant replacement control circuit includes: An address segmentation comparison module (1), whose input terminal inputs an operation word line address and a defective word line address, and is used for segmentation determination whether the operation word line address and the defective word line address are the same, so as to output a plurality of different segmentation determination signals and a final determination signal; An erase judgment module (2), whose input end is connected to the output end of the address segment comparison module and inputs an erase enable, and is used to judge whether the storage area to be erased includes a defective word line according to a plurality of segment judgment signals and the erase enable, and output an erase judgment signal; A replacement control module (3) having an input end connected to the output end of the address segment comparison module and the output end of the erase judgment module (2), and used to generate a replacement control signal according to the final judgment signal and the erase judgment signal, wherein the replacement control signal is used to control the replacement state of the redundant word line corresponding to the defective word line.

2. The redundant replacement control circuit according to claim 1, characterized in that: The erase enable includes a 64KB erase enable; The segment determination signal includes a first segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition greater than 64KB are consistent, and a second segment determination signal representing whether the address bits of the operation word line address and the defective cell address representing the partition of 64KB are consistent; The erasure judgment signal includes a first erasure judgment signal; The erasure judgment module (2) comprises a first judgment module (21); The first judgment module (21) inputs a 64KB erase enable, a first segment judgment signal and a second segment judgment signal at its input end, and outputs a first erase judgment signal at its output end.

3. The redundant replacement control circuit according to claim 2, characterized in that: The first judgment module (21) comprises: A first NAND gate (211), a first input terminal and a second input terminal of which are respectively input with a 64KB erase enable signal and a first segment determination signal; The first NOR gate (212) has a first input end connected to the output end of the first NAND gate (211), a second input end inputting the second segment determination signal, and an output end outputting the first erasure determination signal.

4. The redundant replacement control circuit according to claim 3, characterized in that: The erase enable also includes 32KB erase enable; The segment determination signal also includes a third segment determination signal representing whether the address bits of the 32KB partitions representing the operation word line address and the defective word line address are consistent or not; The erasure judgment signal also includes a second erasure judgment signal; The erasure judgment module (2) further includes a second judgment module (22); The second judgment module (22) comprises: A second NAND gate (221), a first input terminal, a second input terminal and a third input terminal of which are respectively input with a 32KB erase enable, a first segment determination signal and an inverted second segment determination signal; The second NOR gate (222) has a first input end connected to the output end of the second NAND gate (221), a second input end inputting the third segment determination signal, and an output end outputting the second erasure determination signal.

5. The redundant replacement control circuit according to claim 4, characterized in that: The erase enable also includes 4KB erase enable; The segment determination signal further includes a fourth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition of less than or equal to 64KB and greater than 8KB are consistent, a fifth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition of 8KB are consistent, and a sixth segment determination signal representing whether the address bits of the operation word line address and the defective word line address representing the partition of 4KB are consistent; The erasure judgment signal further includes a third erasure judgment signal; The erasure judgment module (2) further includes a third judgment module (23); The third judgment module (23) comprises: A third NOR gate (231), a first input terminal and a second input terminal of which are respectively input with the fifth segment determination signal and the sixth segment determination signal; A third NAND gate (232), a first input end of which is connected to the output end of the third NOR gate (231), and a second input end of which is input with a 4KB erase enable; A fourth NAND gate (233), a first input terminal and a second input terminal of which are respectively input with the first segment determination signal and the fourth segment determination signal; The first input terminal and the second input terminal of the fourth NOR gate (234) are respectively connected to the output terminal of the third NAND gate (232) and the output terminal of the fourth NAND gate (233), and the output terminal outputs a third erasure judgment signal.

6. The redundant replacement control circuit according to claim 5, characterized in that: The redundant replacement control circuit further includes: A fifth NOR gate (4) has a first input terminal, a second input terminal and a third input terminal respectively inputting the first erasure judgment signal, the second erasure judgment signal and the third erasure judgment signal, and an output terminal connected to an input terminal of the replacement control module (3).

7. The redundant replacement control circuit according to claim 6, characterized in that: The replacement control module (3) comprises: A fifth NAND gate (31), wherein a first input terminal thereof inputs a final judgment signal, and a second input terminal thereof is connected to an output terminal of the fifth NOR gate (4); A sixth NAND gate (32) has a first input terminal connected to the output terminal of the fifth NAND gate (31), a second input terminal inputting an operation enable signal, and an output terminal generating a replacement control signal, wherein the operation enable signal is used to control the redundant word line corresponding to the defective word line to perform an operation.

8. The redundant replacement control circuit according to claim 2, characterized in that: The erase enable also includes full chip erase enable; The erasure judgment signal further includes a fourth erasure judgment signal; The erasure judgment module (2) further includes a fourth judgment module (24); The fourth judgment module (24) comprises: A NOT gate (241) has an input terminal inputting a full-chip erase enable signal and an output terminal outputting a fourth erase determination signal.

9. A storage array, characterized in that: The method comprises the redundant replacement control circuit as claimed in any one of claims 1 to 8.

10. A flash memory, characterized in that: The method comprises the redundant replacement control circuit as claimed in any one of claims 1 to 8 or the storage array as claimed in claim 9.

Images