Semiconductor packaging piece, packaging method of semiconductor packaging piece and electronic equipment

Abstract

The invention provides a semiconductor packaging piece, a chip packaging method and electronic equipment. The semiconductor packaging piece comprises a chip, a stress buffer layer, an anti-warping functional layer and a substrate, wherein the stress buffer layer is located between the chip and the anti-warping functional layer, the chip is connected to the substrate, the semiconductor packaging piece can package the chip with relatively small thickness, and the packaged chip can not only improve the problem of poor wetting, but also reduce or prevent the possibility of warping of the chip.

Description

Technical Field

[0001] The present disclosure relates to the packaging field, and in particular to a semiconductor package, a packaging method of a semiconductor package, and an electronic device. Background Art

[0002] In the field of chip packaging, balancing chip package interaction stress CPI and poor wetting is an important issue. Summary of the invention

[0003] In a first aspect, the present disclosure provides a semiconductor package, comprising:

[0004] Chip, stress buffer layer, anti-warping functional layer and substrate;

[0005] The stress buffer layer is located between the chip and the anti-warping functional layer, and the chip is connected to the substrate. The semiconductor package disclosed in the present invention can package relatively thin chips, and the packaged chip not only has appropriate stress, but also can reduce or prevent the possibility of chip warping.

[0006] In one embodiment of the present disclosure, the anti-warping functional layer includes a homogeneous material.

[0007] In one embodiment of the present disclosure, the anti-warping functional layer includes a mirrordie.

[0008] In one embodiment of the present disclosure, the thickness of the light sheet is between 15-45 um, or the thickness of the light sheet is 30 um.

[0009] In one embodiment of the present disclosure, the stress buffer layer includes a connection film.

[0010] In one embodiment of the present disclosure, the thickness of the stress buffer layer is between 5-15 um, including end points; or, the thickness of the stress buffer layer is 10 um.

[0011] In one embodiment of the present disclosure, the thickness of the chip is less than 150 μm, or the thickness of the chip is between 80-100 microns, including the end values.

[0012] In one embodiment of the present disclosure, the sum of the thicknesses of the chip, the stress buffer layer and the anti-warping functional layer is between 140-160 um, including end points; or, the sum of the thicknesses of the chip, the stress buffer layer and the anti-warping functional layer is 150 um.

[0013] In a second aspect, the present disclosure provides a semiconductor package, comprising

[0014] A chip, a stress buffer layer, and an anti-warping functional layer, wherein the stress buffer layer is located between the chip and the anti-warping functional layer.

[0015] In a third aspect, the present disclosure provides a semiconductor package, comprising

[0016] A chip, the chip comprises an interconnection component, the chip is provided with an anti-warping functional layer, the anti-warping functional layer comprises a mirrordie, and the anti-warping functional layer is arranged on a side of the chip away from the interconnection component.

[0017] In a fourth aspect, the present disclosure provides a chip packaging method, wherein the packaging method is used to package a package as described in any one of the first aspects.

[0018] In a fifth aspect, the present disclosure provides an electronic device, comprising: a semiconductor package as shown in any one of the first aspect, the second aspect and the third aspect. It should be understood that the above general description and the following detailed description are only exemplary and explanatory and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0020] Figure 1 An analysis diagram of warpage values ​​of different die thicknesses provided in an embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of a flip chip packaging method in a related technology provided by an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of a flip chip packaging method in a related technology provided by an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of a chip provided in an embodiment of the present disclosure;

[0024] Figure 5 A flow chart of a chip packaging method provided by an embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of a chip packaging method provided by an embodiment of the present disclosure;

[0026] Figure 7 An example diagram of a chip packaging method provided by an embodiment of the present disclosure;

[0027] Figure 8A schematic diagram of the effect of a chip packaging method provided by an embodiment of the present disclosure;

[0028] Fig. 9 A schematic diagram of the effect of a chip packaging method provided by an embodiment of the present disclosure;

[0029] In the figure: chip 1, stress buffer layer 2, anti-warping functional layer 3, substrate 4. DETAILED DESCRIPTION

[0030] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0031] Figure 1 An analysis graph of the warpage values ​​for different die thicknesses is provided.

[0032] like Figure 1 As shown in the figure, under the same temperature conditions, the warpage of dies of different thicknesses is different. For thinner dies (such as 76μm thick), the warpage value is as high as 80um. In other words, under the same conditions, the thinner the die, the more likely it is to warp.

[0033] In addition, in the related art, thinner bare chips are prone to poor wetting (non-wetting) problems. Poor wetting means that the solder alloy at the solder joint is not well spread, so that a good solder joint cannot be obtained and directly affects the reliability of the solder joint. Poor wetting is prone to occur when the bare chip and the packaging substrate do not match.

[0034] However, the applicant has also found that increasing the die thickness can improve the warping and poor wetting problems, but increasing the die thickness will affect the chip-package interaction (CPI), resulting in excessive chip stress.

[0035] Therefore, balancing issues such as warpage and stress with chip thickness is a very important issue in the chip packaging field.

[0036] In the related art, a thin die is used to maintain good CPI performance. For the problem of poor wetting risk caused by the mismatch between die warpage and package substrate warpage, a cavity carrier solution is proposed. Figure 3 As shown in the figure, there is a cavity in the carrier. Driven by the vacuum negative pressure, the substrate will deform and contact the carrier cavity. As the warpage of the substrate increases, the gap between the substrate and the chip die becomes smaller, which can solve the poor wetting problem to a certain extent. However, as Figure 3 As shown, both the die warpage and substrate warpage present complex shapes. Even if both exhibit large concave or convex warpage, they may not be well matched. On the other hand, when the substrate thickness is thin, the substrate may break or crack when in contact with the cavity carrier.

[0037] In order to solve the above problems, the present disclosure provides a chip.

[0038] Figure 4 A schematic structural diagram of a semiconductor package according to an embodiment of the present disclosure is provided;

[0039] like Figure 4 As shown, the semiconductor package includes:

[0040] Chip 1 includes an interconnection component. By way of example, the interconnection component may include a solder bump or a copper pillar.

[0041] The semiconductor package also includes an anti-warping functional layer 3, which is connected to the chip 1 and is used to reduce the possibility of chip warping, or to reduce the warping degree of the chip. In some scenarios, the anti-warping functional layer can even prevent the chip from warping.

[0042] The semiconductor package may further include a stress buffer layer 2, which is arranged between the chip 1 and the anti-warping functional layer 3, and the stress buffer layer may be used to reduce the stress of the chip;

[0043] The substrate 4 is electrically connected to the chip.

[0044] The semiconductor package provided in the embodiment of the present disclosure can be used to prevent the chip from warping by providing an anti-warping functional layer, so that even if the chip is relatively thin, it is not easy to warp or even does not warp, and the stress is also reduced.

[0045] In addition, for the problem of poor wetting, the anti-warping layer and the chip can be regarded as a whole, which has a greater thickness than a single chip, and can ensure that the chip meets the relevant performance of wetting.

[0046] In some embodiments of the present disclosure, the type of chip 1 can be set by those skilled in the art as needed, for example, it can be a logic chip or a memory chip.

[0047] In some embodiments of the present disclosure, the thickness of the chip is less than 150 μm, or the thickness of the chip is between 80 and 100 microns, including the end values. In the related art, the thickness of the chip must be set to at least 150 μm to achieve a better wetting effect. The thickness of the chip of the present disclosure can be less than 150 μm, and can even be set at 80-100 μm. The chip 1 and the anti-warping functional layer 3 are combined with each other to still achieve a better wetting effect. In addition, the thickness of the chip is reduced, which achieves lower stress on the chip.

[0048] In some embodiments of the present disclosure, the anti-warping functional layer 3 is made of homogeneous material, such as a mirror die, a glass gasket, etc. The homogeneous material has the property of remaining flat at high and normal temperatures. The connection between the anti-warping functional layer 3 and the chip 1 can prevent the chip from warping during welding or use.

[0049] In some embodiments of the present disclosure, the anti-warping functional layer 3 is made of a homogeneous material, and the homogeneous material can be cut. After the homogeneous material is cut into a suitable size, it is connected above the chip 1, which is not limited in the present disclosure.

[0050] In some embodiments of the present disclosure, the anti-warping functional layer 3 is fixed on the chip 1, including fully covering or half covering the chip 1. In the embodiments of the present disclosure, the size of the anti-warping functional layer 3 is adapted to the size of the chip 1.

[0051] In another embodiment of the present disclosure, the anti-warping layer 3 may be respectively disposed in peripheral areas away from the central area of ​​the chip 1 to prevent warping in the peripheral areas.

[0052] In some embodiments of the present disclosure, the thickness of the anti-warping functional layer is between 15-45um, including the end value, or the thickness of the optical sheet is 30um. The anti-warping functional layer 3 has a certain mass and is fixed on the chip 1. It can apply a certain pressure to the chip 1 and also inhibit the chip 1 from warping.

[0053] In some embodiments of the present disclosure, the anti-warping functional layer 3 adopts a mirrordie, which is a pure silicon thin sheet, an incomplete exposure unit (Shot) cut from a wafer and containing a small number of grains. The mirrordie can be cut into a size matching the chip 1.

[0054] In some embodiments of the present disclosure, the stress buffer layer 2 is a connection film, wherein the connection film is an ultra-thin film adhesive used to connect a semiconductor chip to a packaging substrate, or between chips in a semiconductor packaging process. The stress buffer layer can release a portion of the stress of the anti-warping functional layer and improve the packaging performance of the chip 1.

[0055] In some embodiments of the present disclosure, the thickness of the stress buffer layer is between 5-15 um, including end points; or, the thickness of the stress buffer layer is 10 um.

[0056] In an embodiment of the present disclosure, the sum of the thicknesses of the chip, the stress buffer layer and the anti-warping functional layer is between 140-160 um, including end points; or, the sum of the thicknesses of the chip, the stress buffer layer and the anti-warping functional layer is 150 um.

[0057] Compared with the chip with a thickness of 150 microns used in the related art, the sum of the thickness of the chip, stress buffer layer and anti-warping functional layer disclosed in the present invention is close to the chip thickness in the related art, ensuring that the chip is subjected to less stress while meeting the wetting performance.

[0058] In some embodiments of the present disclosure, the anti-warping functional layer 3 uses an optical sheet and a stress buffer layer 2 as a connecting film. The optical sheet is fixed on the chip 1 through the connecting film. Specifically, the upper surface of the chip 1 is bonded to the lower surface of the connecting film 2, and the upper surface of the connecting film 3 is bonded to the lower surface of the optical sheet.

[0059] In some embodiments of the present disclosure, a non-curing connection film is preferably selected to ensure high adhesion between the connection film and the chip. Moreover, the non-curing connection film does not require a curing process and will not affect the flux cleaning process in chip packaging.

[0060] In the embodiments of the present disclosure, a thin chip will have better CPI stress, and the connecting film modulus is low enough, so it can be considered that there is no restriction on the deformation of the chip. The anti-warping functional layer is a homogeneous material and can remain flat at both high and normal temperatures. Fixing it on the chip can improve the deformation of the chip, so that the chip maintains a smaller warping and can better match the packaging substrate, thereby ensuring better CPI performance while avoiding poor wetting problems.

[0061] At the same time, the present disclosure also provides a packaging method for a semiconductor package, such as Figure 5 As shown, the method includes the following steps 101 and 102.

[0062] Step 101 : providing a chip, and forming an anti-warping functional layer on a side of the chip away from the interconnection component.

[0063] In some embodiments of the present disclosure, the chip 1 may be an unpackaged chip with independent functions, such as a bare chip die, a flip chip FC die (flip chip die), wherein a bare chip refers to a chip with complete functions that is cut from a wafer and is not packaged. Flip chip is a packaging technology that directly interconnects components downward to a substrate, a carrier or a circuit board through bumps on the chip, and an unpackaged flip chip is a flip chip.

[0064] For example, the interconnection components may include tin bumps or copper pillars, etc.

[0065] In some embodiments of the present disclosure, the thickness of the chip is less than 150 μm, or the thickness of the chip is between 80 and 100 microns, including the end values. In the related art, the thickness of the chip must be set to at least 150 μm to achieve a better wetting effect. The thickness of the chip of the present disclosure can be less than 150 μm, and can even be set at 80-100 μm. The chip 1 and the anti-warping functional layer 3 are combined with each other to still achieve a better wetting effect.

[0066] In some embodiments of the present disclosure, the anti-warping functional layer 3 is made of homogeneous material, such as a mirror die, a glass gasket, etc. The homogeneous material has the property of remaining flat at high and normal temperatures. The connection between the anti-warping functional layer 3 and the chip 1 can prevent the chip from warping during welding or use.

[0067] In some embodiments of the present disclosure, the anti-warping functional layer 3 is made of a homogeneous material, and the homogeneous material can be cut. After the homogeneous material is cut into a suitable size, it is connected above or on the side of the chip 1, which is not limited by the present disclosure.

[0068] In some embodiments of the present disclosure, the anti-warping functional layer 3 is fixed on the chip 1, including fully covering or half covering the chip 1. In the embodiments of the present disclosure, the size of the anti-warping functional layer 3 is adapted to the size of the chip 1.

[0069] In another embodiment of the present disclosure, the anti-warping layer 3 may be respectively disposed in peripheral areas away from the central area of ​​the chip 1 to prevent warping in the peripheral areas.

[0070] In some embodiments of the present disclosure, the thickness of the anti-warping functional layer is between 15-45um, including the end value, or the thickness of the optical sheet is 30um. The anti-warping functional layer 3 has a certain mass and is fixed on the chip 1. It can apply a certain pressure to the chip 1 and also inhibit the chip 1 from warping.

[0071] In some embodiments of the present disclosure, the anti-warping functional layer 3 adopts a mirrordie, which is a pure silicon thin sheet, an incomplete exposure unit (Shot) cut from a wafer and containing a small number of grains. The mirrordie can be cut into a size matching the chip 1.

[0072] In some embodiments of the present disclosure, the stress buffer layer 2 is a connection film, wherein the connection film is an ultra-thin film adhesive used to connect a semiconductor chip to a packaging substrate, or between chips in a semiconductor packaging process. The stress buffer layer can release a portion of the stress of the anti-warping functional layer and improve the packaging performance of the chip 1.

[0073] In some embodiments of the present disclosure, the thickness of the stress buffer layer is between 5-15 um, including end points; or, the thickness of the stress buffer layer is 10 um.

[0074] In an embodiment of the present disclosure, the sum of the thicknesses of the chip, the stress buffer layer and the anti-warping functional layer is between 140-160 um, including end points; or, the sum of the thicknesses of the chip, the stress buffer layer and the anti-warping functional layer is 150 um.

[0075] Compared with the related art using chips with a thickness of 150 microns, the sum of the thickness of the chip, stress buffer layer and anti-warping functional layer disclosed in the present invention is close to that, ensuring that the chip is subjected to less stress while meeting the wetting performance requirements.

[0076] In some embodiments of the present disclosure, the anti-warping functional layer 3 uses an optical sheet and a stress buffer layer 2 as a connecting film. The optical sheet is fixed on the chip 1 through the connecting film. Specifically, the upper surface of the chip 1 is bonded to the lower surface of the connecting film 2, and the upper surface of the connecting film 3 is bonded to the lower surface of the optical sheet.

[0077] In some embodiments of the present disclosure, a non-curing connection film is preferably selected to ensure high adhesion between the connection film and the chip. Moreover, the non-curing connection film does not require a curing process and will not affect the flux cleaning process in chip packaging.

[0078] In one embodiment of the present disclosure, providing a chip and forming an anti-warping functional layer on a side of the chip away from an interconnection component includes providing a chip and forming a stress buffer layer on a side of the chip away from the interconnection component, and forming an anti-warping functional layer on a side of the stress buffer layer away from the chip.

[0079] Step 102 , mounting the chip 1 on the substrate 4 .

[0080] In some embodiments of the present disclosure, the substrate 4 may be an ETS board or the like, which is not limited in the present disclosure.

[0081] In some embodiments of the present disclosure, Figure 5 As shown, the lower surface of the chip 1 is connected to the substrate 4 .

[0082] In some embodiments of the present disclosure, the connection between the chip 1 and the substrate 4 may be a welding connection or a non-welding connection, which is not limited in the present disclosure.

[0083] In some embodiments of the present disclosure, Figure 6 As shown, in the method disclosed in the present invention, a thin chip 1 is used, an anti-warping functional layer 3 is fixed on the chip through a stress buffer layer 2, and finally connected to a substrate 4. The thin chip has better CPI stress, and the optical sheet is a homogeneous material, which can remain flat at both high and normal temperatures, thereby improving the deformation of the chip, and keeping the chip at a smaller warping to better match the packaging substrate, thereby ensuring better CPI performance while avoiding poor wetting problems.

[0084] It should be noted that the method disclosed in the present invention can be applied to the field of flip chip semiconductor packaging, including FCCSP (Flip Chip Chip Scale Package) flip chip chip-scale packaging, FCBGA (Flip Chip Ball Grid Array Package) flip chip ball grid array packaging, FCQFN (Flip Chip Quad Flat No-lead Package) chip-mounted square flat no-lead packaging, HBPOP (Flip Chip High-Bandwidth Package On Package) chip-mounted high-frequency band packaging stacked packaging and other flip chip packaging fields.

[0085] Take FCCSP application as an example. Figure 7 As shown, after the chip is fixed to FC die attach, an additional step is required, that is, the optical sheet is fixed to mirror die attach. Similarly, in FCBGA applications, the step of fixing the optical sheet to mirror die attach is added after the chip is fixed to FC die attach. The application of the disclosed method in other flip chip semiconductor packaging fields is similar to the above, and this disclosure will not elaborate on it.

[0086] Figure 8 A simulation result analysis diagram of a chip packaging method disclosed in the present invention is shown, such as Figure 8As shown, the chip is a small silicon die cut from a silicon wafer, with a size of 11.7x10.9mm, the stress buffer layer 2 uses a connection film, the optical sheet 3 uses pure silicon, and the packaging substrate 4 uses a 3-layer ETS substrate with a thickness of 0.143mm. In the analysis table, the first simulation data is the simulation result of a flip chip packaged with a chip thickness of 90um without using the method disclosed in the present invention, the second simulation data is the simulation result of a flip chip packaged with a chip thickness of 150um without using the method disclosed in the present invention, and the third simulation data is the simulation result of a flip chip packaged with the method disclosed in the present invention. From the simulation data of the two columns of Normalized HT warpage and Normalized RT warpage, it can be seen that when the packaging method disclosed in the present invention is not used, a thick chip can maintain a smaller warpage, and a thin chip has a larger warpage. After using the packaging method disclosed in the present invention, the same 90um thin chip is used, and the warpage at high temperature is reduced by 29% compared with when it is not used. Therefore, it is beneficial to match with the packaging substrate 4, reduce the proportion of poor wetting, and improve the output rate of the product.

[0087] Fig. 9 A simulation result analysis diagram of a chip packaging method disclosed in the present invention is shown, such as Fig. 9 As shown, the chip is a small silicon die cut from a silicon wafer, with a size of 11.7x10.9mm, the stress buffer layer 2 uses a connection film, the optical sheet 3 uses pure silicon, and the packaging substrate 4 uses a 3-layer ETS substrate with a thickness of 0.143mm. In the analysis table, the first simulation data is the simulation result of the bump stress (bumpstress) of the flip chip packaged with a 90um thickness under the FAC working condition without using the method disclosed in the present invention, the second simulation data is the simulation result of the bump stress of the flip chip packaged with a 150um thickness under the FAC working condition without using the method disclosed in the present invention, and the third simulation data is the simulation result of the bump stress of the flip chip packaged with the method disclosed in the present invention under the FAC working condition. From the simulation data of the Normalized FCAbumpstress column, it can be seen that when the packaging method disclosed in the present invention is not used, the bump stress of a thick chip is smaller, and the bump stress of a thin chip is larger. After using the packaging method disclosed in the present invention, the bump stress is 17.2% lower than the stress of a 150um chip, and even 4% lower than the stress of a 90um chip, which can achieve good CPI performance and improve product reliability.

[0088] comprehensive, Figure 8 and Fig. 9It can be seen that the chip packaging method disclosed in the present invention can achieve both good CPI performance and reduced wetting poor risk without any compromise.

[0089] Based on the above embodiment, the embodiment of the present invention further provides a structural diagram of an electronic device, the electronic device comprising: Figure 4 Public chip.

[0090] In some embodiments, the electronic device may be a mobile phone, a computer, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0092] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0093] It should be understood that the various parts of the embodiments of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0094] A person skilled in the art may understand that all or part of the steps in the above-mentioned embodiment method may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0095] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0096] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A semiconductor package, characterized in that: include: Chip, stress buffer layer, anti-warping functional layer and substrate; Wherein, the stress buffer layer is located between the chip and the anti-warping functional layer, and the chip is connected to the substrate.

2. The semiconductor package according to claim 1, wherein: The anti-warping functional layer includes a homogeneous material.

3. The semiconductor package according to claim 1, wherein: The anti-warping functional layer includes a mirrordie. 4 . The semiconductor package according to claim 4 , wherein the thickness of the optical sheet is between 15-45 um; or, the thickness of the optical sheet is 30 um.

5. The semiconductor package according to claim 1, wherein: The stress buffer layer includes a connection film.

6. The semiconductor package according to claim 5, wherein: The thickness of the stress buffer layer is between 5-15 um, including end points; or, the thickness of the stress buffer layer is 10 um. 7 . The semiconductor package according to claim 1 , wherein the thickness of the chip is less than 150 μm; or, the thickness of the chip is between 80 and 100 microns, both inclusive.

8. The semiconductor package according to claim 1, wherein the sum of the thickness of the chip, the stress buffer layer and the anti-warping functional layer is between 140-160 um, including end points; or, the sum of the thickness of the chip, the stress buffer layer and the anti-warping functional layer is 150 um.

9. A semiconductor package, characterized in that: include A chip, a stress buffer layer, and an anti-warping functional layer, wherein the stress buffer layer is located between the chip and the anti-warping functional layer.

10. A semiconductor package, characterized in that: include A chip, the chip comprises an interconnection component, the chip is provided with an anti-warping functional layer, the anti-warping functional layer comprises a mirrordie, and the anti-warping functional layer is arranged on a side of the chip away from the interconnection component.

11. A chip packaging method, the packaging method being used to package the package as claimed in any one of claims 1 to 8.

12. An electronic device, characterized in that: include: A package as claimed in any one of claims 1 to 10.

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