High-voltage IGBT control system for transcranial magnetic stimulation

Abstract

The invention discloses a high-voltage IGBT control system for transcranial magnetic stimulation, and relates to the field of charging circuits. In the high-voltage IGBT control system, an upper computer sends stimulation parameters set by a user to a main control module; the stimulation parameters comprise stimulation intensity and stimulation frequency; the main control module is used for analyzing the stimulation parameters, generating a charging signal and a reference voltage and sending the charging signal and the reference voltage to the latch module; the sampling isolation module is used for collecting the voltage on the energy storage capacitor C and outputting the generated sampling voltage to the latch module after voltage division and isolation; the latch module is used for generating a driving signal according to the charging signal, the reference voltage and the sampling voltage and sending the driving signal to the switch driving module; and the switch driving module is used for driving the IGBT switch Q1 in an isolated manner according to the driving signal, and charging or stopping charging the energy storage capacitor C. The capacitor charging efficiency and the charging voltage control precision are improved, and the output requirements of a high-strength and high-frequency pulsed magnetic field are effectively met.

Description

Technical Field

[0001] The present application relates to the technical field of charging circuits, and in particular to a high-voltage IGBT control system for transcranial magnetic stimulation. Background Art

[0002] Transcranial Magnetic Stimulation (TMS) is a non-invasive neuromodulation technology that generates induced currents inside neurons by applying an alternating pulsed magnetic field to the central nervous system, thereby changing the membrane potential of nerve cells and affecting the transmission of neural signals. The typical TMS output circuit consists of an LC circuit. Capacitor C stores high voltage and charges the inductor after the switch is closed, generating an instantaneous large current in the coil and a strong pulsed magnetic field. The magnetic induction intensity is proportional to the voltage value stored in capacitor C. Therefore, high-intensity, high-frequency pulsed magnetic field output requires that the capacitor be charged to the highest possible voltage in the shortest possible time.

[0003] Traditional capacitor charging methods are usually based on H-bridges, which adjust the output current by adjusting the duty cycle of the PWM signal to achieve constant current charging. However, the conversion efficiency of the H-bridge limits the charging speed and is difficult to meet the requirements of high-intensity and high-frequency pulse magnetic fields. Summary of the invention

[0004] In view of the problems existing in the above-mentioned prior art, the purpose of this application is to provide a high-voltage IGBT control system for transcranial magnetic stimulation, so as to improve the capacitor charging efficiency and the charging voltage control accuracy, and effectively meet the output requirements of high-intensity, high-frequency pulsed magnetic fields.

[0005] To achieve the above objectives, this application provides the following solutions.

[0006] The present application provides a high-voltage IGBT control system for transcranial magnetic stimulation, comprising: an energy storage capacitor charging circuit, a high-voltage capacitor charging control circuit, and a host computer; the energy storage capacitor charging circuit is an RC charging circuit based on a high-voltage DC power supply-IGBT, comprising a high-voltage DC power supply V, an IGBT switch Q1, a current limiting resistor R, and an energy storage capacitor C connected in series;

[0007] The high-voltage capacitor charging control circuit includes a main control module, a latch module, a switch drive module, a sampling isolation module and a power module; the main control module is respectively connected to the host computer and the latch module; the latch module is respectively connected to the switch drive module and the sampling isolation module; the switch drive module is connected to the IGBT switch Q1; the sampling isolation module is connected to the energy storage capacitor C; the power module is respectively connected to the main control module, the latch module, the switch drive module and the sampling isolation module for power supply;

[0008] The host computer sends the stimulation parameters set by the user to the main control module; the stimulation parameters include stimulation intensity and stimulation frequency; the main control module is used to analyze the stimulation parameters, generate a charging signal and a reference voltage and send them to the latch module; the sampling isolation module is used to collect the voltage on the energy storage capacitor C and output the generated sampling voltage to the latch module after voltage division and isolation; the latch module is used to generate a driving signal according to the charging signal, the reference voltage and the sampling voltage and send it to the switch driving module; the switch driving module is used to drive the IGBT switch Q1 according to the driving signal isolation, and charge or stop charging the energy storage capacitor C.

[0009] Optionally, the main control module is used to analyze the stimulation parameters, generate a charging signal and a reference voltage, and send them to the latch module, specifically including:

[0010] The main control module interprets the stimulation intensity into a reference voltage TRIM, and generates a charging signal OR2 according to the stimulation frequency.

[0011] Optionally, the sampling isolation module includes a voltage divider circuit, an isolation amplifier U4, a capacitor C6 and a capacitor C11; the voltage divider circuit includes large resistors R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18 and R20 connected in series in sequence;

[0012] Among them, one end of the large resistor R6 is connected to the low voltage port CAP- of the energy storage capacitor C, and the other end of the large resistor R6 is connected to the large resistor R7; the capacitor C6 is connected in parallel with the large resistor R20; one end of the large resistor R20 is connected to the large resistor R18; the other end of the large resistor R20 and the pin 1 of the isolation amplifier U4 are both connected to the high voltage port CAP+ of the energy storage capacitor C; the common connection point of the large resistor R20 and the large resistor R18 is connected to the pin 2 of the isolation amplifier U4; the voltage of the common connection point of the large resistor R20 and the large resistor R18 is the sampling signal P-9; the pin 3 of the isolation amplifier U4 is connected to its pin 38; the pins 21 and 22 of the isolation amplifier U4 are grounded; the pin 20 of the isolation amplifier U4 is connected to the +15V voltage; the pin 19 of the isolation amplifier U4 is connected to one end of the capacitor C11; the other end of the capacitor C11 is grounded; the pin 19 of the isolation amplifier U4 generates the sampling voltage CMP_0.

[0013] Optionally, the latch module includes a comparator circuit and a latch circuit; the comparator circuit includes a comparator IC2B, a resistor R27, a resistor R31, a resistor R32, a capacitor C8 and a capacitor C41;

[0014] Among them, the positive input end of the comparator IC2B is connected to one end of the resistor R32; the other end of the resistor R32 is connected to the reference voltage TRIM; the reverse input end of the comparator IC2B is respectively connected to one end of the resistor R31, one end of the capacitor C8 and one end of the capacitor C41; the other end of the resistor R31 is connected to the sampling voltage CMP_0; the other end of the capacitor C41 is grounded; the other end of the capacitor C8 is connected to one end of the resistor R27; the other end of the resistor R27 is connected to the output end of the comparator IC2B; the output end of the comparator IC2B generates a comparison signal TV_1.

[0015] Optionally, the latch circuit includes a timer circuit and an AND gate circuit; the timer circuit includes a timer U8, a resistor R45, a resistor R46, a resistor R47, a capacitor C45, a capacitor C46 and a transistor Q2;

[0016] Among them, pin 1 of the timer U8 is grounded; pin 2 of the timer U8 is connected to the comparison signal TV_1; pin 3 of the timer U8 is connected to one end of the resistor R46; the other end of the resistor R46 is connected to the base of the transistor Q2; one end of the resistor R47 is connected to the +12V voltage; the other end of the resistor R47 is connected to the collector of the transistor Q2; the collector of the transistor Q2 generates a timer circuit output signal PF; the emitter of the transistor Q2 is grounded; pin 4 of the timer U8 is connected to the buffer output signal OR2BUF; pin 5 of the timer U8 is connected to one end of the capacitor C46; the other end of the capacitor C46 is grounded; pin 6 of the timer U8 is connected to one end of the resistor R46; the other end of the resistor R46 is grounded; pin 8 of the timer U8 and one end of the capacitor C45 are both connected to the +12V voltage; the other end of the capacitor C45 is grounded.

[0017] Optionally, the AND gate circuit includes an AND gate U2, a resistor R5 and a capacitor C3;

[0018] Among them, pin 1 of the AND gate U2 is connected to the timer circuit output signal PF; pin 2 of the AND gate U2 is connected to the charging signal OR2; pin 3 of the AND gate U2 generates a drive signal DRIVER; pin 4 of the AND gate U2 is connected to pin 4 of the timer U8; pin 4 of the AND gate U2 generates a buffered output signal OR2BUF; pins 5 and 6 of the AND gate U2 are both connected to the charging signal OR2; pin 7 of the AND gate U2 is grounded; pins 8, 9, 12 and 13 of the AND gate U2 are all connected to one end of the resistor R5; the other end of the resistor R5 is grounded; pin 14 of the AND gate U2 and one end of the capacitor C3 are both connected to a +12V voltage; the other end of the capacitor C3 is grounded.

[0019] Optionally, the switch driving module includes an optocoupler isolation driving chip U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a voltage regulator tube D1;

[0020] Among them, pin No. 2 of the optocoupler isolation driver chip U1 is connected to the drive signal DRIVER via the resistor R1; pin No. 6 of the optocoupler isolation driver chip U1 is connected to one end of the resistor R2; the other end of the resistor R2 is respectively connected to the cathode of the voltage regulator tube D1, one end of the resistor R3 and the gate of the IGBT switch Q1; the anode of the voltage regulator tube D1 and the other end of the resistor R3 are grounded; the collector of the IGBT switch Q1 is connected to the high-voltage port CAP+ of the energy storage capacitor C; the emitter of the IGBT switch Q1 is grounded; pin No. 8 of the optocoupler isolation driver chip U1, one end of the capacitor C1 and one end of the capacitor C2 are all connected to the isolated 12V DC power supply +12V2; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded.

[0021] Optionally, the charging process of the energy storage capacitor C specifically includes:

[0022] When the charging signal OR2 is at a high level, the buffer output signal OR2BUF generated by pin 4 of the AND gate U2 is also at a high level, driving the timer U8 to work; if the comparator circuit detects that the sampling voltage CMP_0 is less than the reference voltage TRIM at this time, the timer circuit output signal PF is at a high level, and after the timer circuit output signal PF and the charging signal OR2 are ANDed, the output drive signal DRIVER is still at a high level, thereby driving the IGBT switch Q1 to enter the on state, and the energy storage capacitor C starts to charge.

[0023] Optionally, the process of stopping charging of the energy storage capacitor C specifically includes:

[0024] When the energy storage capacitor C is charged to the set voltage, the comparator circuit detects that the sampling voltage CMP_0 will be greater than the reference voltage TRIM, that is, an overvoltage condition is detected. At this time, the bistable circuit of the timer U8 will jump from the reset steady state to the trigger steady state, causing the output state of the timer U8 to flip, and the timer circuit output signal PF to flip to a low level; after the timer circuit output signal PF and the charging signal OR2 are ANDed, a low-level drive signal DRIVER will be output, that is, the lock state is entered, and the IGBT switch Q1 is driven to be cut off. At this time, even if the charging signal OR2 remains at a high level, the energy storage capacitor C will stop charging; subsequently, when the charging signal OR2 returns to a low level, the bistable circuit of the timer U8 will also return to the reset steady state and wait for the next high level of the charging signal OR2 to arrive.

[0025] Optionally, the power supply module includes a low-voltage side power supply circuit and an isolated power supply circuit; the low-voltage side power supply circuit is used to generate a +15V voltage; and the isolated power supply circuit is used to generate an isolated 12V DC power supply +12V2.

[0026] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0027] The present application provides a high-voltage IGBT control system for transcranial magnetic stimulation. The sampling isolation module collects the voltage on the energy storage capacitor C and divides and isolates it, and then outputs the generated sampled voltage to the latch module; the latch module performs overvoltage detection based on the sampled voltage and the reference voltage, generates a drive signal and feeds it back to the switch drive module, and controls the on and off of the IGBT switch Q1 through the drive signal, thereby controlling the charging or stopping of the energy storage capacitor C. The high-voltage capacitor charging control circuit of the present application can stably and accurately control the charging time and charging voltage value of the energy storage capacitor, improve the stability and controllability of the transcranial magnetic stimulator, and meet the requirements of accurately controlling the stimulation intensity of high-frequency and high-intensity stimulation sequences. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 It is a schematic diagram of the overall structure of a high-voltage IGBT control system for transcranial magnetic stimulation;

[0030] Figure 2 It is a structural schematic diagram of the energy storage capacitor charging circuit;

[0031] Figure 3To improve the structural diagram of the PFC circuit;

[0032] Figure 4 This is the feedback control principle block diagram of the high voltage capacitor charging control circuit;

[0033] Figure 5 It is the program flowchart of the microcontroller in the main control module;

[0034] Figure 6 An exemplary circuit diagram of a sampling isolation module;

[0035] Figure 7 is an exemplary circuit diagram of a latch module;

[0036] Figure 8 is an exemplary circuit diagram of a switch driving module;

[0037] Fig. 9 is an exemplary circuit diagram of a power module;

[0038] Fig.10 This is the waveform diagram of the relevant signals during the charging process of the energy storage capacitor. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] The purpose of this application is to propose a high-voltage IGBT control system for transcranial magnetic stimulation, which uses a high-voltage DC power supply and an IGBT switch to charge the energy storage capacitor to significantly improve the capacitor charging efficiency and charging voltage control accuracy, and effectively meet the output requirements of high-intensity, high-frequency pulsed magnetic fields.

[0041] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0042] Transcranial magnetic stimulation (TMS) is a green and non-invasive treatment method that applies an alternating magnetic field to the cerebral cortex to change the excitability of neurons, thereby having an auxiliary therapeutic effect on a variety of nervous system-related diseases (such as insomnia, depression, anxiety, etc.), and has a wide range of application value in the field of neuroscience. From an electronic point of view, the transcranial magnetic stimulator needs to charge a large capacitor before stimulation, and when the stimulation trigger signal arrives, the LC loop is closed to discharge the large capacitor and charge the coil inductance. The generated time-varying large current will generate a pulsed magnetic field in space, and eventually generate an induced electric field in the cerebral cortex.

[0043] Transcranial magnetic stimulation (TMS) has a variety of stimulation modes, including single-pulse TMS (sTMS), paired-pulse TMS (ppTMS) and repetitive TMS (rTMS), as well as patterned TMS developed based on rTMS, such as theta burst stimulation (TBS) and quad pulse stimulation (QPS). Among them, rTMS is still one of the most widely used stimulation modes. Low-frequency rTMS usually has a frequency less than or equal to 1Hz, which has an inhibitory effect on the cerebral cortex, while high-frequency rTMS has a frequency greater than or equal to 5Hz, which has an excitatory effect. Due to its low frequency, rTMS usually has a longer treatment time (15 to 30 minutes). In order to shorten the treatment time and improve efficiency, more researchers have begun to pay attention to the application of theta burst stimulation (TBS) in recent years. The stimulation parameters of TBS include intra-cluster frequency, number of pulses, number of pulses between clusters and frequency. Each pulse cluster consists of 3 pulses, with an intra-cluster pulse frequency of 50Hz and an inter-cluster frequency of 5Hz. Currently, due to the limitations of equipment in terms of charging time and power, the commonly used parameters of TBS are 3 pulses per cluster and a frequency of 50Hz. If TBS is performed at a continuous repetition rate of 5 Hz, it is called continuous theta burst stimulation (cTBS), which can produce an inhibitory effect. Intermittent theta burst stimulation (iTBS) uses 2 seconds of cTBS with an interval of 8 seconds to produce an excitatory effect. The high-frequency mode of TBS can complete the number of pulses of rTMS for 15 to 30 minutes in a short period of time (1 to 3 minutes), thereby significantly improving the stimulation efficiency.

[0044] However, due to the high pulse release frequency of the TBS stimulation mode (typical value is 50Hz), the capacitor charging time reserved for the transcranial magnetic stimulator is short, and it is difficult for the capacitor to store enough energy in a short time. Therefore, many commercial TMS devices have the problem of output power reduction in high-frequency stimulation mode. To solve this problem, this application proposes a high-voltage capacitor charging control circuit (referred to as charging control circuit) based on the RC charging loop structure of the high-voltage DC power supply-IGBT to achieve rapid charging of the energy storage capacitor, and to achieve precise control of the capacitor charging voltage through overvoltage detection and latch circuits. Finally, the transcranial magnetic stimulator based on the charging control circuit can be repeatedly charged to 1400V at an operating frequency of 50Hz, and the voltage control accuracy above 800V can reach 1%. The following is a detailed introduction to a high-voltage IGBT control system for transcranial magnetic stimulation in this application.

[0045] In an exemplary embodiment, the present application provides a high-voltage IGBT control system for transcranial magnetic stimulation (hereinafter referred to as high-voltage IGBT control system) to meet the fast and accurate charging requirements of the transcranial magnetic stimulator. Figure 1 and Figure 2As shown, the high-voltage IGBT control system includes: an energy storage capacitor charging circuit, a high-voltage capacitor charging control circuit and a host computer. Figure 2 As shown, the energy storage capacitor charging circuit is an RC charging circuit based on a high-voltage DC power supply-IGBT, including a high-voltage DC power supply V, an IGBT switch Q1, a current limiting resistor R and an energy storage capacitor C connected in series. Among them, the high-voltage DC power supply V is composed of an improved PFC circuit, which can increase the output voltage to 1600V while improving the power factor through the settings of a rectifier circuit, a Boost circuit, a DC-DC isolation transformer circuit, etc. The current limiting resistor R is used to limit the instantaneous current of the energy storage capacitor C charging to prevent the IGBT switch Q1 from burning due to excessive current at the moment of conduction. The charging control circuit accurately controls the conduction time of the IGBT switch Q1 so that the voltage of the energy storage capacitor C is charged to the set value.

[0046] In the present application, the implementation method of the high voltage DC power supply V is to improve the traditional active PFC (Power Factor Correction) circuit. The composition of the improved PFC circuit used in the high voltage DC power supply V of the present application is as follows: Figure 3 As shown, it includes a filtering and surge protection circuit, a rectifier circuit, a Boost circuit, a Boost switch charging control circuit, a DC-DC isolation transformer circuit, a rectifier filtering circuit, and an overvoltage and overcurrent feedback charging control circuit. The basic principle of PFC is to improve the problem of low power factor of a single rectifier circuit. A single rectifier circuit only forms an AC to DC energy conversion through a rectifier bridge and a filter capacitor, and the capacitive load of the filter capacitor causes a large current to exist only during the conduction angle in the cycle, and no current at other times, thereby reducing the power factor and making the apparent power exceed the rated value of the fuse or fuse. The improved PFC circuit of this application adds a key Boost circuit on the basis of the rectifier circuit, which actively controls the switch to operate at a frequency far higher than the power frequency, effectively improving the power factor. The filtering and surge protection circuit is used to suppress interference from the AC power grid; the DC-DC isolation transformer circuit isolates the ground of the Boost circuit from the ground of the DC output. When the output DC is overcurrent or overvoltage, the conversion efficiency of the DC-DC isolation transformer circuit is controlled by the overvoltage and overcurrent feedback charging control circuit.

[0047] Furthermore, the application method of the high-voltage DC power supply V to the improved PFC circuit of the present application is to connect the 400V / 2kW power supplies of four improved PFC circuits in series, so that the four improved PFC circuits can output a maximum of 1600V / 8kW, which can meet the requirements of large current charging of the energy storage capacitor.

[0048] Figure 2In the control and feedback calculation method of the energy storage capacitor C, let the high voltage DC power supply voltage be Vs, the initial voltage of the energy storage capacitor be Vci, and the set value of the energy storage capacitor voltage (the final value of the capacitor voltage, also called the set voltage) be Vcf. Then the charging time t can be derived from the differential equation of the RC circuit:

[0049] t=-RC*ln[(Vcf-Vs) / (Vci-Vs)] (1)

[0050] In the formula, R and C are the resistance of the current limiting resistor and the capacitance of the energy storage capacitor, respectively, and ln is the natural logarithm. For example, for a system with a 1600V high-voltage DC power supply and a current limiting resistor of 15Ω, the IGBT turn-on instantaneous current is only 107A, and it only takes 8.3ms for the capacitor to charge from 0V to 1500V, which meets the fast charging requirements of most TBS series high-frequency and high-voltage. The actual DC power supply system (i.e. PFC) is limited by its output current limit, and the charging time will be slightly longer than the theoretical calculated value.

[0051] like Figure 1 As shown, the high-voltage capacitor charging control circuit specifically includes a main control module, a latch module, a switch drive module, a sampling isolation module and a power supply module. Figure 4 The core circuits and working principles of each module in the charging control circuit are introduced in detail.

[0052] like Figure 1 and Figure 4 As shown, the main control module is connected to the host computer and the latch module respectively. The latch module is connected to the switch drive module and the sampling isolation module respectively. The switch drive module is connected to the IGBT switch Q1. The sampling isolation module is connected to the energy storage capacitor C. The power supply module is connected to the main control module, the latch module, the switch drive module and the sampling isolation module for power supply. Among them, the host computer sends the stimulation parameters set by the user to the main control module; the stimulation parameters include stimulation intensity and stimulation frequency; the main control module is used to parse the stimulation parameters, generate a charging signal and a reference voltage and send them to the latch module; the sampling isolation module is used to collect the voltage on the energy storage capacitor C and output the generated sampling voltage to the latch module after voltage division and isolation; the latch module is used to generate a driving signal according to the charging signal, the reference voltage and the sampling voltage and send it to the switch drive module; the switch drive module is used to drive the IGBT switch Q1 according to the driving signal isolation, and charge or stop charging the energy storage capacitor C.

[0053] Specifically, the host computer is installed with magnetic stimulation control software, in which the user can set the required stimulation sequence and corresponding stimulation parameters. After encoding these parameters, the host computer sends them to the main control module through the serial port. The main control module is mainly composed of a microcontroller STM32F103VET6 and peripheral circuits. The microcontroller sends a pulse charging signal OR2 and a reference voltage TRIM of the corresponding stimulation intensity at a certain moment according to the stimulation sequence and corresponding stimulation parameters set by the user.

[0054] The most commonly used stimulation sequences are sTMS, rTMS, iTBS and cTBS. Each stimulation sequence has different stimulation duration, stimulation frequency and interval time. After the user inputs the stimulation sequence and the specific stimulation parameters corresponding to the stimulation sequence (such as stimulation intensity, stimulation frequency, number of pulses, string duration, string interval time), the microcontroller will calculate the specific charging signal OR2 and reference voltage TRIM according to the input stimulation parameters and output them. The program flowchart of the microcontroller is shown in the figure. Figure 5 As shown in the figure, the microcontroller reads the stimulation sequence and corresponding stimulation parameters input by the user through the serial port, and parses the stimulation parameters if it is judged to be valid data. The stimulation intensity value is parsed into a reference voltage value, and is transmitted to the internal DAC register according to the resolution to output the reference voltage TRIM; at the same time, the internal timer count value is configured according to the stimulation frequency and other parameters, and the stimulation is controlled to start, so as to drive the internal timer to output the charging signal OR2. After the stimulation ends, the stimulation status is transmitted back by the serial port, and this round of stimulation ends.

[0055] In an exemplary embodiment, the sampling isolation module circuit diagram is as follows Figure 6 As shown, the sampling isolation module includes a voltage divider circuit, an isolation amplifier U4, a capacitor C6 and a capacitor C11. The voltage divider circuit specifically includes large resistors R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18 and R20 connected in series. Figure 6 In the figure, CAP+ and CAP- are connected to the two ends of the energy storage capacitor C respectively, and the voltage of the energy storage capacitor C is represented as CAP. CAP+ refers to the high voltage port of the energy storage capacitor C, and CAP- refers to the low voltage port of the energy storage capacitor C.

[0056] like Figure 6As shown, one end of the large resistor R6 is connected to the low voltage port CAP- of the energy storage capacitor C, and the other end of the large resistor R6 is connected to the large resistor R7; the capacitor C6 is connected in parallel with the large resistor R20; one end of the large resistor R20 is connected to the large resistor R18; the other end of the large resistor R20 and the pin 1 of the isolation amplifier U4 are both connected to the high voltage port CAP+ of the energy storage capacitor C; the common connection point of the large resistor R20 and the large resistor R18 is connected to the pin 2 of the isolation amplifier U4; the voltage of the common connection point of the large resistor R20 and the large resistor R18 is the sampling signal P-9; the pin 3 of the isolation amplifier U4 is connected to its pin 38; the pins 21 and 22 of the isolation amplifier U4 are grounded; the pin 20 of the isolation amplifier U4 is connected to the +15V voltage; the pin 19 of the isolation amplifier U4 is connected to one end of the capacitor C11; the other end of the capacitor C11 is grounded; the pin 19 of the isolation amplifier U4 generates the sampling voltage CMP_0.

[0057] See also Figure 6 , the voltage of the energy storage capacitor C (connected to CAP+ and CAP-) passes through a voltage divider circuit composed of a series of large resistors R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18 and R20, and the voltage divider circuit outputs a small voltage value according to the ratio of the resistance (four thousandths) as the sampling signal P-9. However, since the ground of the sampling signal P-9 is still on the high-voltage side, it cannot be directly used as the input end of the comparator circuit. Therefore, this application uses the AD202KN chip as the isolation amplifier U4, which has a common-mode voltage isolation of ±2kV and a maximum nonlinearity of ±0.025%. After the sampling signal P-9 passes through the isolation amplifier U4, it can be output to the low-voltage side at a ratio of 1:1 as the sampling voltage input CMP_0 of the latch module.

[0058] In an exemplary embodiment, the latch module circuit diagram is as follows: Figure 7 As shown, the latch module specifically includes a comparator circuit and a latch circuit. Among them, the comparator circuit includes a comparator IC2B, a resistor R27, a resistor R31, a resistor R32, a capacitor C8 and a capacitor C41. The latch circuit includes a timer circuit and an AND gate circuit. The timer circuit includes a timer U8, a resistor R45, a resistor R46, a resistor R47, a capacitor C45, a capacitor C46 and a transistor Q2. The AND gate circuit includes an AND gate U2, a resistor R5 and a capacitor C3.

[0059] like Figure 7As shown in part (a), the positive input end of the comparator IC2B is connected to one end of the resistor R32; the other end of the resistor R32 is connected to the reference voltage TRIM; the reverse input end of the comparator IC2B is respectively connected to one end of the resistor R31, one end of the capacitor C8 and one end of the capacitor C41; the other end of the resistor R31 is connected to the sampling voltage CMP_0; the other end of the capacitor C41 is grounded; the other end of the capacitor C8 is connected to one end of the resistor R27; the other end of the resistor R27 is connected to the output end of the comparator IC2B; the output end of the comparator IC2B generates a comparison signal TV_1.

[0060] like Figure 7 As shown in part (b), pin 1 of the timer U8 is grounded; pin 2 of the timer U8 is connected to the comparison signal TV_1; pin 3 of the timer U8 is connected to one end of the resistor R46; the other end of the resistor R46 is connected to the base of the transistor Q2; one end of the resistor R47 is connected to the +12V voltage; the other end of the resistor R47 is connected to the collector of the transistor Q2; the collector of the transistor Q2 generates a timer circuit output signal PF; the emitter of the transistor Q2 is grounded; pin 4 of the timer U8 is connected to the buffer output signal OR2BUF; pin 5 of the timer U8 is connected to one end of the capacitor C46; the other end of the capacitor C46 is grounded; pin 6 of the timer U8 is connected to one end of the resistor R46; the other end of the resistor R46 is grounded; pin 8 of the timer U8 and one end of the capacitor C45 are both connected to the +12V voltage; the other end of the capacitor C45 is grounded.

[0061] like Figure 7 As shown in part (c), pin 1 of the AND gate U2 is connected to the timer circuit output signal PF; pin 2 of the AND gate U2 is connected to the charging signal OR2; pin 3 of the AND gate U2 generates a drive signal DRIVER; pin 4 of the AND gate U2 is connected to pin 4 of the timer U8; pin 4 of the AND gate U2 generates a buffer output signal OR2BUF; pins 5 and 6 of the AND gate U2 are both connected to the charging signal OR2; pin 7 of the AND gate U2 is grounded; pins 8, 9, 12 and 13 of the AND gate U2 are all connected to one end of the resistor R5; the other end of the resistor R5 is grounded; pin 14 of the AND gate U2 and one end of the capacitor C3 are both connected to a +12V voltage; the other end of the capacitor C3 is grounded.

[0062] Specifically, in the latch module, an operational amplifier LM358 is used as the comparator IC2B; the timer U8 uses a 555 timer chip; and the AND gate U2 uses a CD4081 AND gate chip. The CD4081 AND gate chip is a CMOS logic device with four 2-input AND gates. The pins of each path are defined as follows: pins 1 and 2 are AND operation inputs, and pin 3 is their AND operation result; pins 5 and 6 are AND operation inputs, and pin 4 is their AND operation result; pins 8 and 9 are AND operation inputs, and pin 10 is their AND operation result; pins 12 and 13 are AND operation inputs, and pin 11 is their AND operation result. In addition, pins 14 and 7 are power supply and ground, respectively. Only two AND gates are used in the AND gate circuit of the present application, one of which (pins 1, 2, and 3) is used to perform AND gate operation on the charging signal OR2 and the timer circuit output signal PF to control the IGBT switch Q1 to be turned off when overvoltage occurs; the other AND gate (pins 4, 5, and 6) is used to buffer the charging signal OR2 and input the buffered output signal OR2BUF to the RESET pin of the 555 timer to meet the noise tolerance requirements of the RESET pin of the 555 timer. Q2 is a general-purpose NPN transistor 8050, which is used to invert the output logic of the 555 timer, equivalent to a NOT gate.

[0063] See also Figure 7 In the latch module of the present application, an operational amplifier LM358 is used as a comparator IC2B to compare the reference voltage TRIM from the main control module with the sample voltage CMP_0 from the sampling isolation module, and the comparison result is output to the latch circuit as a comparison signal TV_1. The latch circuit includes a timer U8 and an AND gate U2. When the main control module outputs a charging signal OR2 at a low level, the AND gate output signal (i.e., the drive signal) DRIVER will output a low level, driving Figure 4 The IGBT switch Q1 is turned off, and the timer U8 is in a reset steady state. When the charging signal OR2 is at a high level, the timer U8 is driven to work through another AND gate output signal (i.e., buffer output signal) OR2BUF. If the comparator circuit detects that the sampling voltage CMP_0 is still less than the reference voltage TRIM at this time, and the corresponding comparison signal TV_1 is at a high level, the timer circuit output signal PF is at a high level, and after performing an AND gate operation with the charging signal OR2, the output drive signal DRIVER is still at a high level, thereby driving the IGBT switch Q1 into the on state, and the energy storage capacitor C starts to charge.

[0064] When the energy storage capacitor C is charged to the set value, the comparator circuit detects that the sampling voltage CMP_0 will be greater than the reference voltage TRIM, that is, an overvoltage condition is detected, and the 555 timer bistable circuit will jump from the reset steady state to the trigger steady state, causing the output state of the timer U8 to flip, and the timer circuit output signal PF will flip to a low level. After the timer circuit output signal PF and the original charging signal OR2 are ANDed, a low level will be output (the drive signal DRIVER is a low level), that is, the locked state is entered, and the IGBT switch Q1 is driven to be cut off. At this time, even if the charging signal OR2 remains at a high level, the energy storage capacitor C will stop charging to prevent the capacitor from being overcharged. Subsequently, when the charging signal OR2 returns to a low level, the 555 timer bistable circuit will also return to the reset steady state and wait for the next high level of the charging signal OR2.

[0065] As the core component of this application, the latch module ensures that the pulse signal DRIVER driving the IGBT has a stable square wave shape through the microsecond comparison response time of the operational amplifier LM358 and the bistable circuit characteristics formed by the 555 timer, and ensures that the energy storage capacitor is charged to the set voltage value, thereby improving the system's response speed and the anti-interference ability of the driving signal, and effectively protecting the reliability and safety of the IGBT under high frequency and high voltage operation.

[0066] The circuit diagram of the switch drive module is as follows Figure 8 As shown, the switch driving module includes an optical coupling isolation driving chip U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a voltage regulator D1. The optical coupling isolation driving chip U1 is a TLP250H chip.

[0067] like Figure 8 As shown, pin 2 of the optocoupler isolation driver chip U1 is connected to the drive signal DRIVER via the resistor R1; pin 6 of the optocoupler isolation driver chip U1 is connected to one end of the resistor R2; the other end of the resistor R2 is respectively connected to the cathode of the voltage regulator tube D1, one end of the resistor R3 and the gate of the IGBT switch Q1; the anode of the voltage regulator tube D1 and the other end of the resistor R3 are grounded; the collector of the IGBT switch Q1 is connected to the high-voltage port CAP+ of the energy storage capacitor C; the emitter of the IGBT switch Q1 is grounded; pin 8 of the optocoupler isolation driver chip U1, one end of the capacitor C1 and one end of the capacitor C2 are all connected to the isolated 12V DC power supply +12V2; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded.

[0068] See also Figure 8, the drive signal DRIVER output by the latch module is transmitted to the gate of the IGBT switch Q1 through the optocoupler isolation driver chip TLP250H, and GATE refers to the gate signal of Q1. The TLP250H chip has a maximum transmission delay time of 500ns and an isolation voltage of 10kV. The low delay ensures the voltage control accuracy during the capacitor charging process, and the high isolation effectively prevents the high-voltage side signal from interfering with the normal operation of the low-voltage side circuit, thereby improving the stability of the circuit. In addition, in order to further enhance the anti-interference ability of the drive signal, gate current limiting resistors R2, R3 and Zener diode D2 are also added to the design to prevent overvoltage shocks and electromagnetic interference that may occur during the switching process, thereby better protecting the reliability of IGBT devices in high-frequency and high-voltage operating environments.

[0069] The purpose of setting the charging control circuit in this application is to accurately control the conduction time of the IGBT switch Q1 to ensure that the voltage in the energy storage capacitor C is consistent with the stimulation intensity, frequency and other parameters set by the user in the host computer. Specifically, the microcontroller in the main control module sends a pulse charging signal OR2 and a reference voltage TRIM of the corresponding stimulation intensity at a certain moment according to the stimulation intensity and stimulation frequency set by the user in the host computer, and the optocoupler isolation drive of the switch drive module controls the IGBT switch Q1 to turn on, and the energy storage capacitor C starts to charge. When the energy storage capacitor C is charged to the set voltage value, the voltage on the energy storage capacitor C passes through the voltage divider circuit and isolation amplifier of the signal sampling isolation module, and the sampling voltage CMP_0 output by the energy storage capacitor C will be higher than the reference voltage TRIM output by the microcontroller, and the comparator circuit will output a low-level comparison signal TV_1, and then the drive signal DRIVER is locked to a low level through the latch circuit, thereby controlling the IGBT switch Q1 to turn off, and the energy storage capacitor C stops charging. The drive signal DRIVER is supplied by an optocoupler isolation driver chip powered by an isolated power supply to isolate the high-voltage system from the low-voltage system and drive the gate of the IGBT switch Q1.

[0070] Therefore, the charging process of the energy storage capacitor C specifically includes:

[0071] When the charging signal OR2 is at a high level, the buffer output signal OR2BUF generated by pin 4 of the AND gate U2 is also at a high level, driving the timer U8 to work; if the comparator circuit detects that the sampling voltage CMP_0 is less than the reference voltage TRIM at this time, the timer circuit output signal PF is at a high level, and after the timer circuit output signal PF and the charging signal OR2 are ANDed, the output drive signal DRIVER is still at a high level, thereby driving the IGBT switch Q1 to enter the on state, and the energy storage capacitor C starts to charge.

[0072] The process of stopping charging of the energy storage capacitor C specifically includes:

[0073] When the energy storage capacitor C is charged to the set voltage, the comparator circuit detects that the sampling voltage CMP_0 will be greater than the reference voltage TRIM, that is, an overvoltage condition is detected. At this time, the bistable circuit of the timer U8 will jump from the reset steady state to the trigger steady state, causing the output state of the timer U8 to flip, and the timer circuit output signal PF to flip to a low level; after the timer circuit output signal PF and the charging signal OR2 are ANDed, a low-level drive signal DRIVER will be output, that is, the lock state is entered, and the IGBT switch Q1 is driven to be cut off. At this time, even if the charging signal OR2 remains at a high level, the energy storage capacitor C will stop charging; subsequently, when the charging signal OR2 returns to a low level, the bistable circuit of the timer U8 will also return to the reset steady state and wait for the next high level of the charging signal OR2 to arrive.

[0074] The power module circuit diagram of this application is as follows Fig. 9 As shown, the power supply module includes a low-voltage side power supply circuit and an isolated power supply circuit. The low-voltage side power supply circuit uses an isolated AC / DC chip U5 to generate a +15V voltage to provide power for the sampling isolation module, and the remaining low-voltage circuits +12V are powered by the main control module. The isolated power supply circuit uses an isolated power chip U3 to generate an isolated 12V DC power supply +12V2, which supplies power to the gate GATE of the high-voltage side IGBT switch Q1.

[0075] Specifically, Fig. 9 As shown in part (b), the low-voltage side power supply circuit includes an isolated AC / DC chip U5, a terminal J1, a capacitor CX1, a varistor ZR4, a capacitor C12 and a capacitor C13. Among them, the isolated AC / DC chip U5 uses the IRM-5-15 chip, and its pin No. 1 is connected to the pin No. 1 of the terminal J1 for connecting to the AC live wire AC-L; its pin No. 2 is connected to the pin No. 3 of the terminal J1 for connecting to the AC neutral wire AC-N. Capacitor CX1 and varistor ZR4 are connected in parallel between the AC live wire AC-L and the AC neutral wire AC-N. Pin No. 3 of the IRM-5-15 chip is grounded. Pin No. 4 of the IRM-5-15 chip outputs a +15V voltage. On the other hand, pin No. 4 of the IRM-5-15 chip is grounded through capacitors C12 and C13 connected in parallel.

[0076] like Fig. 9 As shown in part (a), the isolated power supply circuit includes an isolated power supply chip U3, a capacitor C4 and a capacitor C5. The isolated power supply chip U3 uses the F1512S-2WR3L chip, and its pin 1 is connected to the +15V voltage on the one hand, and is grounded through the capacitor C4 on the other hand; its pins 2 and 5 are directly grounded; its pin 7 generates an isolated 12V DC power supply +12V2 on the one hand, and is grounded through the capacitor C5 on the other hand.

[0077] The power module is powered by the IRM-5-15 chip on the low voltage side, and the high voltage side is powered by the F1512S-2WR3L chip to obtain an isolated 12V DC power supply +12V2. The isolated power supply circuit has a total isolation degree of 3kV.

[0078] The biggest difficulty of the charging control circuit proposed in this application is to use the feedback loop to provide the driving circuit with an accurate timing to stop charging, so as to meet the requirements of accurate and stable IGBT control. Fig.10 As shown. The microcontroller only provides a charging signal OR2 with a fixed pulse width, but the actual charging time t is not only related to the set voltage Vcf, but also affected by factors such as the initial capacitor voltage Vci and the DC power supply overcurrent protection. Therefore, it is difficult to accurately calculate the required charging time. In order to solve this problem, the feedback loop designed in this application adopts an overvoltage detection method to control the shutdown of the IGBT device. The feedback loop design idea is as follows.

[0079] The high voltage on the energy storage capacitor C is converted into a small voltage sampling signal P-9 after passing through the large resistor voltage divider network in the sampling isolation module. Although the voltage of the sampling signal P-9 is reduced, the input port still has a common-mode voltage to ground of thousands of volts. Therefore, an isolation amplifier is used to convert the sampling signal P-9 to the low-voltage side to obtain the sampling voltage CMP_0. The sampling voltage CMP_0 and the reference voltage TRIM are used as the input port voltages of the comparator circuit for voltage comparison. If the energy storage capacitor C is in an overvoltage state (CMP_0>TRIM), the output drive signal DRIVER is a low level and the IGBT device is turned off. Otherwise, a high level is output. Obviously, it seems that only the charging signal OR2 and the comparison signal TV_1 output by the comparator need to be ANDed to stop the output when overvoltage occurs. However, in this way, when the IGBT is cut off after overvoltage, the sampling voltage CMP_0 is very close to the reference voltage TRIM, and the weak high-frequency noise on the sampling signal will be coupled to the output of the comparator, resulting in the following Fig.10 The high-frequency noise shown in the figure will be coupled to the IGBT drive signal DRIVER through the AND gate operation, causing the IGBT to be turned on and off repeatedly. Figure 2 The charging circuit load shown is capacitive. A large instantaneous current (>100A) will be generated each time the IGBT is turned on. Therefore, high-frequency turn-on and turn-off (>10kHz) will easily cause the IGBT to exceed its specified safe operating area (SOA), causing the IGBT to burn out.

[0080] To solve this problem, this application designs a bistable latch circuit based on a 555 timer to lock the state of the output signal (i.e., enter the triggered steady state) to ensure that the IGBT will not turn on again after being turned off. The control accuracy of overvoltage detection is jointly determined by the transmission delay time of each level of circuit, including the sampling voltage delay time, the isolation amplifier transmission delay time, the latch module transmission delay time, the optocoupler isolation transmission delay time and the IGBT turn-off time. The measured results show that the measured voltage above 800V is within the error range of 1% of the set voltage value, which meets the requirements of high-precision transcranial magnetic stimulation.

[0081] The present application provides a high-voltage IGBT control system for transcranial magnetic stimulation, and its control part includes: a host computer, a main control module, a latch module, a switch drive module and a sampling isolation module. The host computer communicates with the main control module according to the stimulation parameters set by the user; the main control module is used to send corresponding control signals (including charging signals and reference voltages); the latch module will output a high level when receiving a high level charging signal, and will output a low level and lock when receiving a reset or comparator output low level comparison signal; the switch drive module is used to isolate and drive the high-voltage switch IGBT; the sampling isolation module collects the voltage on the energy storage capacitor and outputs it to the latch module after voltage division and isolation; the power supply module provides power for all electronic systems. The method of the present application feeds back the voltage on the energy storage capacitor to the latch circuit through overvoltage detection, which can stably and accurately control the charging time and charging voltage value of the energy storage capacitor, improve the stability and controllability of the transcranial magnetic stimulator, and meet the requirements of accurately controlling the stimulation intensity of high-frequency and high-intensity sequences (such as TBS sequences).

[0082] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A high voltage IGBT control system for transcranial magnetic stimulation, characterized in that: include: Energy storage capacitor charging circuit, high-voltage capacitor charging control circuit and host computer; the energy storage capacitor charging circuit is an RC charging circuit based on a high-voltage DC power supply-IGBT, including a high-voltage DC power supply V, an IGBT switch Q1, a current limiting resistor R and an energy storage capacitor C connected in series; The high-voltage capacitor charging control circuit includes a main control module, a latch module, a switch drive module, a sampling isolation module and a power module; the main control module is respectively connected to the host computer and the latch module; the latch module is respectively connected to the switch drive module and the sampling isolation module; the switch drive module is connected to the IGBT switch Q1; the sampling isolation module is connected to the energy storage capacitor C; the power module is respectively connected to the main control module, the latch module, the switch drive module and the sampling isolation module for power supply; The host computer sends the stimulation parameters set by the user to the main control module; the stimulation parameters include stimulation intensity and stimulation frequency; the main control module is used to analyze the stimulation parameters, generate a charging signal and a reference voltage and send them to the latch module; the sampling isolation module is used to collect the voltage on the energy storage capacitor C and output the generated sampling voltage to the latch module after voltage division and isolation; the latch module is used to generate a driving signal according to the charging signal, the reference voltage and the sampling voltage and send it to the switch driving module; the switch driving module is used to drive the IGBT switch Q1 according to the driving signal isolation, and charge or stop charging the energy storage capacitor C.

2. The high-voltage IGBT control system for transcranial magnetic stimulation according to claim 1, characterized in that: The main control module is used to analyze stimulation parameters, generate charging signals and reference voltages, and send them to the latch module, specifically including: The main control module interprets the stimulation intensity into a reference voltage TRIM, and generates a charging signal OR2 according to the stimulation frequency.

3. The high voltage IGBT control system for transcranial magnetic stimulation according to claim 2, characterized in that: The sampling isolation module includes a voltage divider circuit, an isolation amplifier U4, a capacitor C6 and a capacitor C11; the voltage divider circuit includes large resistors R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18 and R20 connected in series in sequence; Among them, one end of the large resistor R6 is connected to the low voltage port CAP- of the energy storage capacitor C, and the other end of the large resistor R6 is connected to the large resistor R7; the capacitor C6 is connected in parallel with the large resistor R20; one end of the large resistor R20 is connected to the large resistor R18; the other end of the large resistor R20 and the pin 1 of the isolation amplifier U4 are both connected to the high voltage port CAP+ of the energy storage capacitor C; the common connection point of the large resistor R20 and the large resistor R18 is connected to the pin 2 of the isolation amplifier U4; the voltage of the common connection point of the large resistor R20 and the large resistor R18 is the sampling signal P-9; the pin 3 of the isolation amplifier U4 is connected to its pin 38; the pins 21 and 22 of the isolation amplifier U4 are grounded; the pin 20 of the isolation amplifier U4 is connected to the +15V voltage; the pin 19 of the isolation amplifier U4 is connected to one end of the capacitor C11; the other end of the capacitor C11 is grounded; the pin 19 of the isolation amplifier U4 generates the sampling voltage CMP_0.

4. The high-voltage IGBT control system for transcranial magnetic stimulation according to claim 3, characterized in that: The latch module includes a comparator circuit and a latch circuit; the comparator circuit includes a comparator IC2B, a resistor R27, a resistor R31, a resistor R32, a capacitor C8 and a capacitor C41; Among them, the positive input end of the comparator IC2B is connected to one end of the resistor R32; the other end of the resistor R32 is connected to the reference voltage TRIM; the reverse input end of the comparator IC2B is respectively connected to one end of the resistor R31, one end of the capacitor C8 and one end of the capacitor C41; the other end of the resistor R31 is connected to the sampling voltage CMP_0; the other end of the capacitor C41 is grounded; the other end of the capacitor C8 is connected to one end of the resistor R27; the other end of the resistor R27 is connected to the output end of the comparator IC2B; the output end of the comparator IC2B generates a comparison signal TV_1.

5. The high voltage IGBT control system for transcranial magnetic stimulation according to claim 4, characterized in that: The latch circuit includes a timer circuit and an AND gate circuit; the timer circuit includes a timer U8, a resistor R45, a resistor R46, a resistor R47, a capacitor C45, a capacitor C46 and a transistor Q2; Among them, pin 1 of the timer U8 is grounded; pin 2 of the timer U8 is connected to the comparison signal TV_1; pin 3 of the timer U8 is connected to one end of the resistor R46; the other end of the resistor R46 is connected to the base of the transistor Q2; one end of the resistor R47 is connected to the +12V voltage; the other end of the resistor R47 is connected to the collector of the transistor Q2; the collector of the transistor Q2 generates a timer circuit output signal PF; the emitter of the transistor Q2 is grounded; pin 4 of the timer U8 is connected to the buffer output signal OR2BUF; pin 5 of the timer U8 is connected to one end of the capacitor C46; the other end of the capacitor C46 is grounded; pin 6 of the timer U8 is connected to one end of the resistor R46; the other end of the resistor R46 is grounded; pin 8 of the timer U8 and one end of the capacitor C45 are both connected to the +12V voltage; the other end of the capacitor C45 is grounded.

6. The high voltage IGBT control system for transcranial magnetic stimulation according to claim 5, characterized in that: The AND gate circuit includes an AND gate U2, a resistor R5 and a capacitor C3; Among them, pin 1 of the AND gate U2 is connected to the timer circuit output signal PF; pin 2 of the AND gate U2 is connected to the charging signal OR2; pin 3 of the AND gate U2 generates a drive signal DRIVER; pin 4 of the AND gate U2 is connected to pin 4 of the timer U8; pin 4 of the AND gate U2 generates a buffered output signal OR2BUF; pins 5 and 6 of the AND gate U2 are both connected to the charging signal OR2; pin 7 of the AND gate U2 is grounded; pins 8, 9, 12 and 13 of the AND gate U2 are all connected to one end of the resistor R5; the other end of the resistor R5 is grounded; pin 14 of the AND gate U2 and one end of the capacitor C3 are both connected to a +12V voltage; the other end of the capacitor C3 is grounded.

7. The high voltage IGBT control system for transcranial magnetic stimulation according to claim 6, characterized in that: The switch driving module includes an optocoupler isolation driving chip U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a voltage regulator tube D1; Among them, pin No. 2 of the optocoupler isolation driver chip U1 is connected to the drive signal DRIVER via the resistor R1; pin No. 6 of the optocoupler isolation driver chip U1 is connected to one end of the resistor R2; the other end of the resistor R2 is respectively connected to the cathode of the voltage regulator tube D1, one end of the resistor R3 and the gate of the IGBT switch Q1; the anode of the voltage regulator tube D1 and the other end of the resistor R3 are grounded; the collector of the IGBT switch Q1 is connected to the high-voltage port CAP+ of the energy storage capacitor C; the emitter of the IGBT switch Q1 is grounded; pin No. 8 of the optocoupler isolation driver chip U1, one end of the capacitor C1 and one end of the capacitor C2 are all connected to the isolated 12V DC power supply +12V2; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded.

8. The high-voltage IGBT control system for transcranial magnetic stimulation according to claim 7, characterized in that: The charging process of the energy storage capacitor C specifically includes: When the charging signal OR2 is at a high level, the buffer output signal OR2BUF generated by pin 4 of the AND gate U2 is also at a high level, driving the timer U8 to work; if the comparator circuit detects that the sampling voltage CMP_0 is less than the reference voltage TRIM at this time, the timer circuit output signal PF is at a high level, and after the timer circuit output signal PF and the charging signal OR2 are ANDed, the output drive signal DRIVER is still at a high level, thereby driving the IGBT switch Q1 to enter the on state, and the energy storage capacitor C starts to charge.

9. The high voltage IGBT control system for transcranial magnetic stimulation according to claim 8, characterized in that: The process of stopping charging of the energy storage capacitor C specifically includes: When the energy storage capacitor C is charged to the set voltage, the comparator circuit detects that the sampling voltage CMP_0 will be greater than the reference voltage TRIM, that is, an overvoltage condition is detected. At this time, the bistable circuit of the timer U8 will jump from the reset steady state to the trigger steady state, causing the output state of the timer U8 to flip, and the timer circuit output signal PF to flip to a low level; after the timer circuit output signal PF and the charging signal OR2 are ANDed, a low-level drive signal DRIVER will be output, that is, the lock state is entered, and the IGBT switch Q1 is driven to be cut off. At this time, even if the charging signal OR2 remains at a high level, the energy storage capacitor C will stop charging; subsequently, when the charging signal OR2 returns to a low level, the bistable circuit of the timer U8 will also return to the reset steady state and wait for the next high level of the charging signal OR2 to arrive.

10. The high voltage IGBT control system for transcranial magnetic stimulation according to claim 1, characterized in that: The power supply module includes a low-voltage side power supply circuit and an isolated power supply circuit; the low-voltage side power supply circuit is used to generate a +15V voltage; the isolated power supply circuit is used to generate an isolated 12V DC power supply +12V2.

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