Digital-to-analog conversion circuit, digital-to-analog converter and electronic equipment

Abstract

The invention provides a digital-to-analog conversion circuit, a digital-to-analog converter and electronic equipment, and relates to the technical field of integrated circuits. Comprising at least one conversion unit and a plurality of buffer units, the at least one conversion unit is connected with the plurality of buffer units; the at least one conversion unit is configured to receive a digital quantity signal, determine a gated target buffer unit according to the digital quantity signal and convert the digital quantity signal into a corresponding analog quantity signal; the plurality of buffer units are configured to transmit an analog quantity signal to a post-stage circuit. According to the digital-to-analog conversion circuit, a resistor string multiplexing mode is adopted in the structure, key nodes between resistor strings are mutually connected, it is guaranteed that analog output quantities of the resistor strings are basically consistent, nonlinearity of the circuit is reduced, and high conversion precision is achieved. In addition, the number of the resistor strings can be effectively reduced by multiplexing the resistor strings, the area overhead is reduced, the complexity of the layout structure is reduced, and the digital-to-analog conversion precision requirement is met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a digital-to-analog conversion circuit, a digital-to-analog converter and an electronic device. Background Art

[0002] Generally, digital signals are single-channel, and the output analog signal range is not enough to meet the requirements of the subsequent circuit, making it difficult to drive the subsequent circuit load to work. The most common multi-channel structure of traditional digital-to-analog converters requires multiple digital-to-analog conversion circuits (DACs) composed of multiple resistor strings and multiple clocks. The digital logic and clock settings of such circuits are complex.

[0003] At present, most of the traditional digital-to-analog conversion circuit architectures use a resistor string as a digital-to-analog converter circuit (DAC) to drive a buffer (BUFFER), and each channel works independently. The BUFFER uses negative feedback to follow the analog output of the digital-to-analog conversion circuit (DAC). However, the number of resistor strings is large, which not only makes the layout structure complex and the area overhead large, but also the node voltages between each resistor string are not equal, resulting in the analog output of the digital-to-analog conversion circuit (DAC) is not completely consistent, and some of them are quite different, resulting in low accuracy of the digital-to-analog conversion circuit (DAC), which cannot meet the needs of digital-to-analog conversion well. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a digital-to-analog conversion circuit, a digital-to-analog converter and an electronic device that solve the above problems or partially solve the above problems.

[0005] A first aspect of an embodiment of the present invention provides a digital-to-analog conversion circuit, the digital-to-analog conversion circuit comprising: at least one conversion unit and a plurality of buffer units; At least one of the conversion units is connected to a plurality of the buffer units; At least one of the conversion units is configured to receive a digital quantity signal, determine a selected target buffer unit according to the digital quantity signal, convert the digital quantity signal into a corresponding analog quantity signal, and transmit the analog quantity signal to the target buffer unit; The plurality of buffer units are configured to transmit the analog signal to a subsequent circuit; Wherein, one of the conversion units is connected to at least two of the buffer units; The number of input register units connected to one of the conversion units is equal to the number of cache units connected to it.

[0006] Optionally, the conversion unit includes: a plurality of groups of gate switches and a plurality of unit resistors, wherein each group of gate switches includes: a row switch and a column switch; The number of groups of the gating switches is the same as the number of the cache units, and one group of the gating switches is connected to one cache unit; a plurality of the unit resistors are connected in series in a serpentine connection between the reference voltage terminal and the low potential terminal to form a resistor string, the first row being a row connected to the reference voltage terminal, and the last row being a row connected to the low potential terminal; Each row in the resistor string is provided with a plurality of row switches, and the number of row switches corresponding to each row is the same as the number of connected buffer units; Both ends of each of the multiple unit resistors are connected to multiple column switches, and the number of column switches connected to each end of the unit resistor is the same as the number of row switches in the row where the unit resistor is located. One end of the first column switch among the multiple column switches is connected to the unit resistor, and the other end is connected to one end of the first row switch in the row where the unit resistor is located, and the other end of the first row switch is connected to a buffer unit, one end of the second column switch is connected to the unit resistor, and the other end is connected to one end of the second row switch in the row where the unit resistor is located, and the other end of the second row switch is connected to another buffer unit.

[0007] Optionally, the row switch is controlled by a row selection signal; the column switch is controlled by a column selection signal; The row selection signal and the column selection signal are determined by the number of bits of the digital signal; When the number of bits of the digital signal is N=M+L, the row selection signal is the upper M bits of the number N, and the column selection signal is the lower L bits of the number N.

[0008] Optionally, in a resistor string structure formed by connecting a plurality of unit resistors in a serpentine manner, the number of the unit resistors is determined by the number of bits N, and the number of rows of the resistor string structure is determined by M in the number of bits N; The total number of unit resistors is 2 N , the number of rows is 2 M .

[0009] Optionally, when there are two or more conversion units, in the resistor string structure of each conversion unit, each row is provided with a key node, and the key node is the end of the last unit resistor in each row of unit resistors connected in series, and the end is connected to the beginning of the first unit resistor in the next row.

[0010] Optionally, when M=6 and the number of rows is 64, two or more conversion units are connected via 64 key nodes, and key nodes corresponding to the same number of rows are connected, while key nodes corresponding to different numbers of rows are not connected.

[0011] Optionally, the digital-to-analog conversion circuit further includes: a plurality of selection switches and a plurality of the input register units; One of the selection switches is connected to one of the input register units; A plurality of the input register units are connected to at least one of the conversion units; The plurality of selection switches are configured to be turned on or off according to the selection signal, and transmit the digital quantity signal to the correspondingly connected input register unit when turned on; The plurality of input register units are configured to send the digital quantity signal to the corresponding target conversion unit; The number of the plurality of input register units is equal to the number of the plurality of buffer units, and the number of the input register units connected to one conversion unit is equal to the number of the connected buffer units; When one of the conversion units is connected to the first input register unit and the second input register unit, the conversion unit receives a first digital quantity signal from the first input register unit, or receives a second digital quantity signal from the second input register unit, wherein the first input register unit and the second input register unit decide whether to send a digital quantity signal to the conversion unit according to the selection signal; When the conversion unit receives the first digital signal, the conversion unit transmits an analog signal corresponding to the first digital signal to a first cache unit connected thereto through a group of selection switches; When the conversion unit receives the second digital signal, the conversion unit transmits an analog signal corresponding to the second digital signal to a second cache unit connected thereto through another group of selection switches.

[0012] Optionally, when the bit number N is 12 bits, the upper M bits are 6 bits, the lower L bits are 6 bits, the row selection signal is 6 bits, and the column selection signal is 6 bits.

[0013] A second aspect of an embodiment of the present invention provides a digital-to-analog converter, the digital-to-analog converter comprising: a digital-to-analog conversion circuit as described in any one of the first aspects.

[0014] A third aspect of an embodiment of the present invention provides an electronic device, comprising the digital-to-analog converter as described in the second aspect.

[0015] The digital-to-analog conversion circuit provided by the present invention includes: at least one conversion unit and multiple buffer units; at least one conversion unit is connected to multiple buffer units; at least one conversion unit is configured to receive a digital quantity signal, determine a selected target buffer unit according to the digital quantity signal, convert the digital quantity signal into a corresponding analog quantity signal, and transmit the analog quantity signal to the target buffer unit; multiple buffer units are configured to transmit the analog quantity signal to a subsequent circuit. Among them, one conversion unit is connected to at least two buffer units; the number of input register units connected to one conversion unit is equal to the number of cache units connected to it.

[0016] The digital-to-analog conversion circuit proposed in the present invention creatively proposes a structure of multiplexing conversion units. Instead of using one digital-to-analog conversion unit for one channel, multiple channels share one conversion unit, and one conversion unit is connected to at least two or more BUFFERs (i.e., cache units). The BUFFER is selected to be turned on by a digital signal. The conversion unit structure uses a resistor string multiplexing method to connect the BUFFER, which has a strong load driving capability. The key nodes between the resistor strings are interconnected to ensure that the analog output (i.e., analog voltage value) of the resistor string is basically consistent, which not only reduces the nonlinearity of the circuit to a certain extent, but also realizes a digital-to-analog conversion unit with better accuracy, reduces the number of resistor strings, reduces the area overhead, reduces the complexity of the layout structure, and well meets the needs of digital-to-analog conversion, and has a high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0018] Figure 1 This is a schematic diagram of the traditional 8-way digital-to-analog conversion circuit structure; Figure 2 is an exemplary structural schematic diagram of a preferred multi-channel digital-to-analog conversion circuit in an embodiment of the present invention and an exemplary modular schematic diagram of an exemplary digital-to-analog conversion circuit; Figure 3 It is an exemplary structural diagram of a preferred conversion unit, two groups of selection switches, and two buffer units in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not used to limit the present invention.

[0020] The inventors have found that most of the current traditional digital-to-analog conversion circuit architectures use one digital-to-analog conversion unit to drive one buffer, and each channel works independently. Figure 1 The schematic diagram of the traditional 8-way digital-to-analog conversion unit is shown in FIG. Input shift register and control logic ( Figure 1INPUT SHIFT REGISTER AND CONTROL LOGIC) simultaneously inputs signals to 8 channels, and the 8 channels use their own input registers ( Figure 1 INPUT REGISTER1~INPUTREGISTER8) stores and forwards digital quantities and control logic to their corresponding digital-to-analog conversion units ( Figure 1 DAC1~DAC8), each digital-to-analog conversion unit performs digital-to-analog conversion and outputs its own analog output (generally the voltage corresponding to the digital quantity) to its corresponding buffer ( Figure 1 BUFFER1~BUFFER8).

[0021] The reason for using BUFFER is that it adopts the form of negative feedback, can follow the analog output of the digital-to-analog conversion unit, and through the form of unit negative feedback, the output has good driving ability. However, the inventors further discovered that: under this architecture, the number of resistor strings is large, and each path requires a resistor string. Not only is the layout structure (referring to the integrated circuit layout) complex and the area overhead is large, but the timing logic control also requires multiple clocks to control separately in synchronization. In addition, the digital-to-analog conversion units corresponding to each resistor string receive digital quantities, and based on their own characteristics, the analog outputs of each digital-to-analog conversion unit are not completely consistent, and some even differ greatly, which cannot meet the needs of digital-to-analog conversion well.

[0022] Based on the above problems, the inventor creatively proposed a digital-to-analog conversion circuit, a digital-to-analog converter and an electronic device of the present invention. The technical solution of the present invention is explained and illustrated in detail below.

[0023] The digital-to-analog conversion circuit of the embodiment of the present invention comprises: at least one conversion unit and a plurality of buffer units. The at least one conversion unit is connected to the plurality of buffer units.

[0024] At least one conversion unit is configured to receive a digital signal, determine a selected target buffer unit according to the digital signal, convert the digital signal into a corresponding analog signal, and transmit the analog signal to the target buffer unit; multiple buffer units are configured to transmit analog signals to subsequent circuits. Among them, one conversion unit is connected to at least two buffer units; the number of input register units connected to one conversion unit is equal to the number of cache units connected to it.

[0025] The conversion unit includes: multiple groups of gating switches and multiple unit resistors, wherein each group of gating switches includes: row switches and column switches; the number of groups of gating switches is the same as the number of cache units, and one group of gating switches is connected to one cache unit. That is: multiple groups of gating switches share one resistor string.

[0026] Multiple unit resistors are connected in series and connected in a serpentine shape between the reference voltage terminal and the low potential terminal to form a resistor string, and the first row is defined as a row connected to the reference voltage terminal, and the tail row is defined as a row connected to the low potential terminal; then multiple unit resistors are connected in series in a serpentine shape to form a resistor string, and the number of row switches corresponding to each row is the same as the number of connected buffer units. That is, when a resistor string is connected to 2 groups of gate switches and 2 buffer units, assuming that there are 64 rows in the resistor string, each of the 64 rows is provided with 2 row switches. For example: 1 resistor string is connected to 2 groups of gate switches and 2 buffer units, and 2 resistor strings are connected to 4 groups of gate switches and 4 buffer units. Of course, in theory, 1 resistor string can correspond to 3 or more buffer units (there are also 3 or more groups of gate switches), but due to the limitations of factors such as layout structure in the manufacturing process of physical object integrated circuits, when 1 resistor string is connected to more, such as 4 or more buffer units, based on the current layout layout, it will lead to a complex layout and a large occupied area. After repeated actual tests and demonstrations by the inventors, the structure of connecting one resistor string with two buffer units is the best choice in terms of layout. In the foreseeable future, when the integrated circuit manufacturing process breaks through the existing technology and breaks the existing layout design method, the best choice can break the current optimal structure of connecting one resistor string with two buffer units, and realize a structure of connecting one resistor string with four or more buffer units with a simple layout from a physical level.

[0027] For each conversion unit, the structure is the same, and a preferred structure includes: multiple groups of gate switches and multiple unit resistors. Each group of gate switches includes: row switches and column switches. For example: if one conversion unit is connected to two buffer units, then there are two groups of gate switches.

[0028] Both ends of each of the multiple unit resistors are connected to multiple column switches, the number of column switches connected to each end of the unit resistor is the same as the number of row switches in the row where the unit resistor is located, one end of the first column switch of the multiple column switches is connected to the unit resistor, and the other end is connected to one end of the first row switch in the row where the unit resistor is located, and the other end of the first row switch is connected to a buffer unit, one end of the second column switch is connected to the unit resistor, and the other end is connected to one end of the second row switch in the row where the unit resistor is located, and the other end of the second row switch is connected to another buffer unit. For example: when one conversion unit is connected to two buffer units (defined as 1# and 2# buffer units), assuming that the resistor string has 64 rows and each row is provided with two row switches (defined as 1# and 2# row switches), then both ends of each unit resistor are connected to two column switches respectively, one end of each of the two column switches is connected to the unit resistor, and the other end of one of the column switches is connected to one end of the 1# row switch of the two row switches in the row where the unit resistor is located, and the other end of the 1# row switch is connected to the 1# buffer unit of the two buffer units; the other end of the other column switch is connected to one end of the 2# row switch of the two row switches in the row where the unit resistor is located, and the other end of the 2# row switch is connected to the 2# buffer unit of the two buffer units.

[0029] In the case of two or more conversion units, in the resistor string structure of each conversion unit, each row is provided with a key node, which is the end of the last unit resistor in each row of unit resistors connected in series, and the end is connected to the beginning of the first unit resistor in the next row. For example: there are 4 conversion units, and the resistor string structure of each conversion unit is 64 rows, so there are 64 key nodes in total. The first key node is located at the end of the last unit resistor in the first row of unit resistors, and the end is connected to the beginning of the first unit resistor in the second row of unit resistors. The second key node is located at the end of the last unit resistor in the second row of unit resistors, and the end is connected to the beginning of the first unit resistor in the third row of unit resistors, and the rest of the cases are analogous. Then the first key node of each of the four conversion units is connected, and the second key node of each is connected. The first key node cannot be connected to any key node other than the first key node in the remaining conversion units. In this way, it can be ensured that the value of the analog signal output by any conversion unit according to the digital signal is equal to the value of the analog signal output by other conversion units.

[0030] In order to better understand the structure of the above conversion unit, refer to Figure 2 A schematic diagram of an exemplary structure of a preferred multi-channel digital-to-analog conversion circuit is shown, referring to Figure 3 A schematic diagram of an exemplary structure of a preferred conversion unit, two groups of selection switches and two buffer units is shown. Figure 2 X represents X channels, corresponding to X input register units ( Figure 3 Chinese INPUT REGISTER1, INPUT REGISTER2, INPUT REGISTER3,...INPUT REGISTER X-2 、INPUTREGISTER X-1 、INPUT REGISTER X Indicates), X buffer units ( Figure 2 Chinese BUFFER1, BUFFER2, BUFFER3,...BUFFER X-2 BUFFER X-1 BUFFER X Assume that both INPUT REGISTER1 and INPUT REGISTER2 are connected to N bit resistor string 1, then BUFFER1 receives the analog signal corresponding to the digital signal of INPUT REGISTER1, and BUFFER2 receives the analog signal corresponding to the digital signal of INPUT REGISTER2.

[0031] Each input register unit is connected to a selector switch ( Figure 3 SELECT[1], SELECT[2], SELECT[3], ...SELECT[X-2], SELECT[X-1], SELECT[X] represent selection switches), selection signals and N-bit digital signals ( Figure 3 In the S ELECT[X] +INPUT(N)), which selection switch is turned on according to the selection signal, the N-bit digital signal is transmitted to its corresponding input register unit after the selection switch is turned on. For example: after the first selection switch is turned on, the N-bit digital signal is transmitted to the first input register unit INPUT REGISTER1. Generally, the input N-bit digital signal is a serial signal, which becomes a parallel signal D1[N:1] after passing through INPUT REGISTER1. This parallel signal D1[N:1] is used as the control signal of the selection switch to control the corresponding selection switch ( Figure 2 In the example, MUX represents the select switch), and the corresponding select switch controls the N-bit resistor string 1 to convert the N-bit digital signal output by INPUT REGISTER1 into the corresponding analog signal and transmit it to BUFFER1. The output of BUFFER1 is used as the output V of a conversion unit. DAC1 transmitted to the subsequent circuit.

[0032] Figure 3 In the exemplary embodiment, the resistor string of the conversion unit 1 (that is, corresponding to Figure 2Taking the N bit resistor string 1 structure in the figure as an example, combined with its row switches and column switches, the connection relationship between it and two groups of selection switches and two buffer units BUFFER1 and BUFFER2 is shown. In the resistor string structure formed by multiple unit resistors connected in a serpentine manner, the number of unit resistors is determined by the number of bits N, and the number of rows of the resistor string structure is determined by the number of bits N; the total number of unit resistors is 2 N , the number of rows is 2 M That is, N=M+L, the row selection signal is the high M bits in the number of bits N, and the column selection signal is the low L bits in the number of bits N. N The unit resistance is evenly distributed in 2 M On the line.

[0033] The resistor string is connected in a snake shape between the reference voltage terminal VREF and the low potential terminal ( Figure 3 Indicated by the ground symbol in the figure). Figure 3 For simplicity of illustration, 4 rows are shown as an example, and each row has 2 row switches ( Figure 3 The two row switches X1<2 of the corresponding row are exemplarily identified in M >、X2<2 M >、X1<2 M -1>、X2<2 M -1>, X1<2>, X2<2>, X1<1>, X2<1>).

[0034] Similarly, four columns of resistors are shown, taking the first unit resistor R1 as an example: the two ends of the unit resistor R1 are connected to two column switches, and there are four column switches 1#, 2#, 3#, and 4# at both ends. One end of each column switch is connected to one end of the unit resistor R1, and the other ends of column switches 1# and 2# are connected to row switches X1<2 of the row where the unit resistor R1 is located. M > one end is connected, the switch X1 of this row is<2 M The second end of the column switches 3# and 4# are connected to the row switch X2<2 of the row where the unit resistor R1 is located. M > one end is connected, the switch X2<2 M The second end of > is connected to the buffer unit BUFFER2. For any row j, the voltage VR<2 j >、First row voltage VR<2 M +1>, tail voltage VR<1>:

[0035] Figure 2 Except for the first row voltage VR<2 M +1>, tail voltage VR<1>, other voltages VR<2 M >、VR<2 M-1>, ...VR<3>, VR<2>, etc. all represent the voltages of key nodes.

[0036] Taking the digital quantity signal of 12 bits as an example, the row selection signal and column selection signal need to be determined by the 12-bit digital quantity signal. The row selection signal is 6 bits, and the column selection signal is 6 bits. The row switch is controlled by the row selection signal; the column switch is controlled by the column selection signal.

[0037] Figure 3 The middle and high-order decoders 1 and 2 represent the decoding of the high M bits corresponding to the two input register units, and the low-order decoders 1 and 2 represent the decoding of the low L bits corresponding to the two input register units. When the bit number N=12bit, the row selection signal is 6bit and the column selection signal is 6bit. Assuming that the current channel 1 is selected, the high M bits of the N-bit digital signal output by INPUT REGISTER1 pass through the high-order decoder 1 to control the row selection switch, and the low L bits pass through the low-order decoder 1 to control the column selection switch, so that the corresponding row switch and column switch are closed, and the resistor string outputs the corresponding voltage value to BUFFER1; it can be understood that if channel 2 is selected, the high M bits of the N-bit digital signal output by INPUTREGISTER2 pass through the high-order decoder 2 to control the row selection switch, and the low L bits pass through the low-order decoder 2 to control the column selection switch, so that the corresponding row switch and column switch are closed, and the resistor string outputs the corresponding voltage value to BUFFER2. This design and the design of key nodes in the resistor string are combined to reduce the mismatch of the resistor strings in multiple conversion units and ensure that all key nodes selected in each resistor string can obtain relatively equal voltages, thereby ensuring that the analog output (i.e., analog voltage value) is basically consistent.

[0038] Since a conversion unit is connected to multiple buffer units, for the entire digital-to-analog conversion circuit, the connection method of the input register unit that provides digital quantities for the conversion unit is also different from the traditional structure. Preferably, the digital-to-analog conversion circuit also includes: multiple selection switches and multiple input register units; a selection switch is connected to an input register unit; multiple input register units are connected to at least one conversion unit; multiple selection switches are configured to be turned on or off according to the selection signal, and transmit digital quantity signals to the corresponding connected input register units when turned on; multiple input register units are configured to send digital quantity signals to the corresponding target conversion units.

[0039] Among them, the number of multiple input register units is equal to the number of multiple buffer units, and the number of input register units connected to one conversion unit is equal to the number of connected buffer units. That is, when there are 8 buffer units, there are 8 input register units, and if one resistor string is connected to two groups of selection switches and two buffer units, then one resistor string is connected to two input register units.

[0040] When a conversion unit is connected to a first input register unit and a second input register unit, the conversion unit receives a first digital quantity signal from the first input register unit, or receives a second digital quantity signal from the second input register unit, wherein the first input register unit and the second input register unit decide whether to send a digital quantity signal to the conversion unit according to a selection signal, that is, assuming that a conversion unit is connected to two input register units, then the digital quantity signal output by which input register unit the conversion unit specifically receives is determined by the selection signal. Therefore, when the conversion unit receives a first digital quantity signal, an analog quantity signal corresponding to the first digital quantity signal is transmitted to the first cache unit connected thereto through a group of selection switches; when the conversion unit receives a second digital quantity signal, an analog quantity signal corresponding to the second digital quantity signal is transmitted to the second cache unit connected thereto through another group of selection switches.

[0041] By connecting the BUFFER to the output of the conversion unit, the conversion unit as a whole can have a stronger driving force, and the overall power consumption and delay of the circuit with the BUFFER are both at a better value. The input range of the BUFFER is full swing, which also ensures the range of the input signal. The monotonicity of the resistor string in the conversion unit structure also ensures that the circuit has good linearity. The resistor string multiplexing method (each resistor string is multiplexed by two buffer units) is used to drive multiple loads. The key nodes between the resistor strings are interconnected to ensure that the voltage of the resistor strings is basically consistent, so that each conversion unit has good accuracy.

[0042] Based on the above digital-to-analog conversion circuit, an embodiment of the present invention further provides a digital-to-analog converter, and the digital-to-analog converter includes: any digital-to-analog conversion circuit as described above.

[0043] Based on the above digital-to-analog converter, an embodiment of the present invention further provides an electronic device, wherein the electronic device includes the above digital-to-analog converter.

[0044] In summary, the digital-to-analog conversion circuit provided by the present invention includes: at least one conversion unit and multiple buffer units; at least one conversion unit is connected to multiple buffer units; at least one conversion unit is configured to receive a digital quantity signal, determine a selected target buffer unit according to the digital quantity signal, convert the digital quantity signal into a corresponding analog quantity signal, and transmit the analog quantity signal to the target buffer unit; multiple buffer units are configured to transmit the analog quantity signal to the subsequent circuit. Among them, one conversion unit is connected to at least two buffer units; the number of input register units connected to one conversion unit is equal to the number of cache units connected to it.

[0045] The digital-to-analog conversion circuit proposed in the present invention creatively proposes a conversion unit multiplexing structure. Instead of using one resistor string for one path, multiple paths share one conversion unit, and one conversion unit is connected to at least two or more BUFFERs (i.e., cache units). The selected BUFFER is turned on by controlling the input control signal. The conversion unit structure uses a resistor string multiplexing method to connect the BUFFER, which has a strong load driving capability. The key nodes between the resistor strings are interconnected to ensure that the analog output (i.e., analog voltage value) of the resistor string is basically consistent, which not only reduces the nonlinearity of the circuit to a certain extent, but also realizes a digital-to-analog conversion unit with better accuracy, reduces the number of resistor strings, reduces the area overhead, and reduces the complexity of the layout structure, which well meets the needs of digital-to-analog conversion and has a high practical value.

[0046] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0047] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0048] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A digital-to-analog conversion circuit, characterized in that: The digital-to-analog conversion circuit comprises: at least one conversion unit and a plurality of buffer units; At least one of the conversion units is connected to a plurality of the buffer units; At least one of the conversion units is configured to receive a digital quantity signal, determine a selected target buffer unit according to the digital quantity signal, convert the digital quantity signal into a corresponding analog quantity signal, and transmit the analog quantity signal to the target buffer unit; The plurality of buffer units are configured to transmit the analog signal to a subsequent circuit; Wherein, one of the conversion units is connected to at least two of the buffer units; The number of input register units connected to one of the conversion units is equal to the number of cache units connected to it.

2. The digital-to-analog conversion circuit according to claim 1, characterized in that: The conversion unit includes: a plurality of groups of gate switches and a plurality of unit resistors, wherein each group of gate switches includes: a row switch and a column switch; The number of groups of the gating switches is the same as the number of the cache units, and one group of the gating switches is connected to one cache unit; a plurality of the unit resistors are connected in series in a serpentine connection between the reference voltage terminal and the low potential terminal to form a resistor string, the first row being a row connected to the reference voltage terminal, and the last row being a row connected to the low potential terminal; Each row in the resistor string is provided with a plurality of row switches, and the number of row switches corresponding to each row is the same as the number of connected buffer units; Both ends of each of the multiple unit resistors are connected to multiple column switches, and the number of column switches connected to each end of the unit resistor is the same as the number of row switches in the row where the unit resistor is located. One end of the first column switch among the multiple column switches is connected to the unit resistor, and the other end is connected to one end of the first row switch in the row where the unit resistor is located, and the other end of the first row switch is connected to a buffer unit, one end of the second column switch is connected to the unit resistor, and the other end is connected to one end of the second row switch in the row where the unit resistor is located, and the other end of the second row switch is connected to another buffer unit.

3. The digital-to-analog conversion circuit according to claim 2, characterized in that: The row switch is controlled by a row selection signal; the column switch is controlled by a column selection signal; The row selection signal and the column selection signal are determined by the number of bits of the digital signal; When the number of bits of the digital signal is N=M+L, the row selection signal is the upper M bits of the number N, and the column selection signal is the lower L bits of the number N.

4. The digital-to-analog conversion circuit according to claim 3, characterized in that: In a resistor string structure formed by connecting a plurality of unit resistors in a serpentine manner, the number of the unit resistors is determined by the number of bits N, and the number of rows of the resistor string structure is determined by M of the number of bits N; The total number of unit resistors is 2 N , the number of rows is 2 M .

5. The digital-to-analog conversion circuit according to claim 4, characterized in that: When there are two or more conversion units, in the resistor string structure of each conversion unit, each row is provided with a key node, and the key node is the end of the last unit resistor in each row of series-connected unit resistors, and the end is connected to the beginning of the first unit resistor in the next row.

6. The digital-to-analog conversion circuit according to claim 5, characterized in that: When M=6, the number of rows is 64, and two or more conversion units are connected through 64 key nodes, and the key nodes corresponding to the same number of rows are connected, and the key nodes corresponding to different numbers of rows are not connected.

7. The digital-to-analog conversion circuit according to claim 1, characterized in that: The digital-to-analog conversion circuit further includes: a plurality of selection switches and a plurality of the input register units; One of the selection switches is connected to one of the input register units; A plurality of the input register units are connected to at least one of the conversion units; The plurality of selection switches are configured to be turned on or off according to the selection signal, and transmit the digital quantity signal to the correspondingly connected input register unit when turned on; The plurality of input register units are configured to send the digital quantity signal to the corresponding target conversion unit; The number of the plurality of input register units is equal to the number of the plurality of buffer units, and the number of the input register units connected to one conversion unit is equal to the number of the connected buffer units; When one of the conversion units is connected to the first input register unit and the second input register unit, the conversion unit receives a first digital quantity signal from the first input register unit, or receives a second digital quantity signal from the second input register unit, wherein the first input register unit and the second input register unit decide whether to send a digital quantity signal to the conversion unit according to the selection signal; When the conversion unit receives the first digital signal, the conversion unit transmits an analog signal corresponding to the first digital signal to a first cache unit connected thereto through a group of selection switches; When the conversion unit receives the second digital signal, the conversion unit transmits an analog signal corresponding to the second digital signal to a second cache unit connected thereto through another group of selection switches.

8. The digital-to-analog conversion circuit according to claim 3, characterized in that: When the bit number N is 12 bits, the upper M bits are 6 bits, the lower L bits are 6 bits, the row selection signal is 6 bits, and the column selection signal is 6 bits.

9. A digital-to-analog converter, characterized in that: The digital-to-analog converter comprises: a digital-to-analog conversion circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that: The electronic device comprises the digital-to-analog converter as claimed in claim 9.

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