PCB manufacturing method for improving collapse of gold layer or damage of gold-plated bonding pad

Abstract

The invention discloses a PCB (Printed Circuit Board) manufacturing method for improving gold layer collapse or gold-plated bonding pad damage, which comprises the following steps of: firstly, manufacturing a required circuit pattern on a board body, manufacturing a gold-plated lead on the board body, and enabling the copper thickness of the gold-plated lead to be smaller than that of the gold-plated bonding pad; carrying out gold plating treatment on the board body on which the circuit pattern and the gold-plated lead are manufactured; and carrying out etching treatment on the plate body subjected to gold plating treatment. When the gold-plated lead is etched and removed, even if over-etching exists, only part of the copper layer can be etched inwards from the position of the original gold-plated lead, the situation that the gold layer collapses or the gold-plated bonding pad is damaged cannot occur, and as the circuit pattern and the gold-plated lead are manufactured separately, a lead widening part cannot occur at the joint of the gold-plated lead and the bonding pad, and the service life of the gold-plated lead is prolonged. The condition that the etching surface is sunken due to the stress problem is avoided, the integrity of the side part of the gold-plated bonding pad is not influenced, and the performance of the PCB is not influenced.

Description

Technical Field

[0001] The invention relates to the technical field of PCBs, and in particular to a PCB manufacturing method for improving gold layer collapse or gold-plated pad damage. Background Art

[0002] Nowadays, many PCB manufacturing processes use gold plating technology, and the gold plating process requires the production of gold-plated leads. In the prior art, the required circuit pattern and the gold-plated leads are generally processed and produced at the same time, and the gold-plated leads are removed by etching after gold plating. Figure 1 As shown in FIG. 1 , the copper thickness of the obtained gold-plated pad is consistent with the copper thickness of the gold-plated lead. Figure 2 As shown in the figure, when the gold-plated leads are subsequently etched away, if there is overetching, the etching solution will continue to etch inward at the edge of the pad corresponding to the original gold-plated leads, causing the copper layer at the bottom of the gold layer near this position to be completely removed. The bottom of the gold layer here is completely hollowed out, without the support of the copper layer, resulting in the collapse of the gold layer or damage to the gold-plated pad, affecting the quality of the pad and the use of the user. In addition, since the circuit pattern and the gold-plated leads are processed and manufactured at the same time, refer to Figure 6 When etching the pattern, the solution at the junction of the gold-plated lead 2 and the pad 1 to be gold-plated flows slowly and the solution exchange is insufficient, resulting in the appearance of a wire widening portion 6 in the final etched pattern, and the wire widening portion 6 presents a certain arc shape, which is non-linear. Figure 7 When the gold plating process is performed, the gold-plated lead 2 needs to be covered with a wet film 7, and there is a clearance between the wet film 7 and the pad 1. Figure 8 Due to the existence of clearance, the gold-plated lead wire 2 within the clearance, including the wire widening portion 6, will be plated with the gold layer 3. The width of the gold layer 3 in the clearance is inconsistent. The width of the gold layer near the gold-plated pad is larger, while the width of the gold layer far from the gold-plated pad is smaller. Fig. 9 When the wet film 7 is subsequently removed to etch the gold-plated lead 2, the presence of the non-linear wire widening portion 6 affects the etching at the junction of the gold-plated lead 2 and the gold layer 3, and will cause a depression at the etching surface due to stress problems, resulting in a first protruding structure 8 with protrusions on both sides and a depression in the middle. The edge of the first protruding structure 8 is non-linear, which affects the integrity of the side of the gold-plated pad, causing damage to the edge of the gold-plated pad, affecting the performance of the PCB, such as affecting the transmission of electrical signals and causing signal interference and other problems. Summary of the invention

[0003] In order to overcome the deficiencies of the prior art, the purpose of the present invention is to provide a PCB manufacturing method that improves the collapse of the gold layer or the damage of the gold-plated pad, which can improve the quality of the pad and ensure the normal use of the PCB.

[0004] In order to solve the above problems, the technical solution adopted by the present invention is as follows: A PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, characterized in that it comprises the following steps: Step S110, firstly making the required circuit pattern on the board, the made circuit pattern includes the pad to be gold plated; Step S120, making a gold-plated lead on the board, and the copper thickness of the gold-plated lead is less than the copper thickness of the pad to be gold-plated; Step S200, performing gold plating on the board with the circuit pattern and gold-plated leads, so as to plate a gold layer on the surface and side of the pad to be gold-plated; Step S300, etching the plate after the gold plating to remove the gold-plated leads.

[0005] Compared with the prior art, the present invention has at least the following beneficial effects: when the required circuit pattern and gold-plated leads are prepared by the method, the copper thickness of the gold-plated leads is made smaller than the copper thickness of the pads; during the gold-plating process, not only the surface of the pads will be plated with a gold layer, but also the side of the pads close to the gold-plated leads will be plated with a gold layer; when the gold-plated leads are subsequently etched away, the side of the pads close to the gold-plated leads will be protected by the gold layer; even if over-etching occurs, only part of the copper layer can be etched away from the original position of the gold-plated leads, and there is still a copper layer on the top of the position where the copper layer is etched away to support the top gold layer, so that the gold layer will not collapse or the gold-plated pads will not be damaged, thereby ensuring the integrity of the pads, improving the quality of the pads, and ensuring the normal use of the PCB. In addition, since the circuit pattern and the gold-plated lead are made separately, there will be no widened part of the wire, and the width of the gold layer within the clearance is consistent, which will not affect the etching at the junction of the gold-plated lead and the gold layer, and will not cause depressions in the etched surface due to stress problems. It will not affect the integrity of the side of the gold-plated pad, and thus will not affect the performance of the PCB.

[0006] The above-mentioned PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, step S110 includes the following steps: Step S111, preparing a production and processing file according to a photolithography file related to a required circuit pattern, wherein the production and processing file does not include a gold-plated lead; Step S112, cutting or laminating; Step S113, drilling; Step S114, copper deposition; Step S115, graphic transfer; Step S116, electroplating; Step S117, alkaline etching; Step S118, inspection.

[0007] In the above-mentioned PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, step S120 includes the following steps: Step S121, copper plating the entire board; Step S122, graphic transfer; Step S123, electroplating; Step S124, alkaline etching; Step S125, inspection.

[0008] In the above-mentioned PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, in step S121, the copper plating thickness is 5μm~6μm.

[0009] The above-mentioned PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, step S200 includes the following steps: Step S210, attaching a protective film on the board, leaving only the pads to be gold plated exposed; Step S220, gold plating; Step S230, removing the film.

[0010] In the above-mentioned PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, the protective film in step S210 is a wet film.

[0011] The above-mentioned PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, step S300 includes the following steps: Step S310, attaching a protective film to the board, leaving only the gold-plated leads exposed; Step S320: alkaline etching; Step S330, film stripping and inspection.

[0012] In the above-mentioned PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, the protective film in step S310 is a dry film.

[0013] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the copper thickness of the gold-plated pad and the gold-plated lead in the prior art; Figure 2 It is a schematic diagram of a pad during over-etching in the prior art; Figure 3 A production flow chart of an embodiment of the present invention; Figure 4 It is a schematic diagram of the embodiment of the present invention in which the copper thickness of the gold-plated lead is smaller than the copper thickness of the pad to be gold-plated; Figure 5 is a schematic diagram of a pad during overetching according to an embodiment of the present invention; Figure 6 It is a schematic diagram of the widened portion of the wire in the prior art; Figure 7 It is a schematic diagram of attaching a wet film on a gold-plated lead in the prior art; Figure 8 A schematic diagram of plating a gold layer on the gold-plated lead wire and the widened portion of the wire within the clearance during gold plating in the prior art; Fig. 9 It is a schematic diagram after etching the gold-plated lead in the prior art; Fig.10 This is a schematic diagram of the embodiment of the present invention after the gold-plated pads and gold-plated leads are manufactured; Fig.11 It is a schematic diagram of applying a wet film on a gold-plated lead wire according to an embodiment of the present invention; Fig.12 It is a schematic diagram of plating a gold layer on the gold-plated lead wire within the clearance during gold plating in an embodiment of the present invention; Fig.13 This is a schematic diagram of etching the gold-plated leads according to an embodiment of the present invention.

[0015] Explanation of the accompanying drawings: 1 soldering pad, 2 gold-plated lead, 3 gold layer, 4 first hollow structure, 5 second hollow structure, 6 wire widening portion, 7 wet film, 8 first protruding structure, 9 second protruding structure. DETAILED DESCRIPTION

[0016] The embodiments of the present invention are described in detail below. Figure 3 The embodiment of the present invention provides a PCB manufacturing method for improving the collapse of the gold layer or the damage of the gold-plated pad, comprising the following steps: Step S100, manufacturing the required circuit pattern and gold-plated lead 2 on the board, wherein the manufactured circuit pattern includes the pad 1 to be gold-plated, and the copper thickness of the gold-plated lead 2 is less than the copper thickness of the pad 1 to be gold-plated; Step S200, performing gold plating on the board with the circuit pattern and the gold-plated lead 2, so as to plate a gold layer 3 on the surface of the gold-plated pad 1 and the side of the gold-plated pad 1 close to the gold-plated lead 2; Step S300 , etching the plate after the gold plating to remove the gold-plated leads 2 .

[0017] Reference Figure 1 and Figure 2In the prior art, when the circuit pattern and the gold-plated lead 2 are made at the same time, the copper thickness of the obtained gold-plated pad 1 is consistent with the copper thickness of the gold-plated lead 2. When the gold-plated lead 2 is subsequently etched away, if there is overetching, the etching solution will continue to etch inward at the position of the edge of the pad 1 corresponding to the original gold-plated lead 2, resulting in the copper layer at the bottom of the gold layer 3 near the position being completely removed. Here, a first hollow structure 4 appears at the bottom of the gold layer 3, and the first hollow structure 4 is completely hollow, and there is no copper layer to support the gold layer 3 at the top of the first hollow structure 4, so that the gold layer 3 collapses or the gold-plated pad 1 is damaged, affecting the quality of the pad 1 and the use of the user.

[0018] Reference Figure 4 When the required circuit pattern and the gold-plated lead 2 are prepared by this method, the copper thickness of the gold-plated lead 2 is made smaller than the copper thickness of the pad 1. During the gold-plating process, not only the surface of the pad 1 will be plated with the gold layer 3, but also the side of the pad 1 close to the gold-plated lead 2 will be plated with the gold layer 3. When the gold-plated lead 2 is subsequently etched away, the side of the pad 1 close to the gold-plated lead 2 will be protected by the gold layer 3. Figure 5 Even if over-etching occurs, only part of the copper layer can be etched away from the original position of the gold-plated lead 2, and a second hollow structure 5 appears at the position where the copper layer is etched away. However, there is still a copper layer on the top of the second hollow structure 5 to support the gold layer 3 on the top, so the gold layer 3 will not collapse or the gold-plated pad 1 will not be damaged, thereby ensuring the integrity of the pad 1, improving the quality of the pad 1, and ensuring the normal use of the PCB.

[0019] Furthermore, in step S100, different methods can be used to achieve that the copper thickness of the gold-plated lead 2 is less than the copper thickness of the pad 1 to be gold-plated. For example, after the required circuit pattern and the gold-plated lead 2 are manufactured at the same time, the copper thickness of the required circuit pattern is increased separately. For another example, after the required circuit pattern and the gold-plated lead 2 are manufactured at the same time, the copper thickness of the gold-plated lead 2 is reduced separately. Regarding step S100, the present invention provides a specific embodiment: Step S100 includes the following steps: Step S110, making the required circuit pattern on the board; Step S120, making gold-plated leads 2 on the board.

[0020] In the above embodiment, the circuit pattern and the gold-plated lead 2 are made separately, and the gold-plated lead 2 is made later, so that the copper thickness of the gold-plated lead 2 can be made smaller than the copper thickness of the circuit pattern. Figures 6 to 9 In the prior art, in order to improve production efficiency, generally, the circuit pattern and the gold-plated lead 2 are made at the same time. Figure 6When etching the pattern, the solution at the junction of the gold-plated lead 2 and the pad 1 to be gold-plated flows slowly and the solution exchange is insufficient, resulting in the appearance of a wire widening portion 6 in the final etched pattern, and the wire widening portion 6 presents a certain arc shape, which is non-linear. Figure 7 When the gold plating process is performed, the gold-plated lead 2 needs to be covered with a wet film 7, and there is a clearance between the wet film 7 and the pad 1. Figure 8 Due to the existence of the clearance, the gold-plated lead wire 2 within the clearance, including the wire widening portion 6, will be plated with the gold layer 3. Fig. 9 When the wet film 7 is subsequently removed to etch the gold-plated lead 2, the presence of the non-linear wire widening portion 6 affects the etching of the junction of the gold-plated lead 2 and the gold layer 3, and will also cause a depression on the etched surface due to stress problems, resulting in a first protruding structure 8 with protrusions on both sides and a depression in the middle. The edge of the first protruding structure 8 is non-linear, which affects the integrity of the side of the gold-plated pad, causing damage to the edge of the gold-plated pad, affecting the performance of the PCB, such as tip discharge, affecting electrical signal transmission, and causing signal interference. In this embodiment, the circuit pattern and the gold-plated lead 2 are made separately, so the wire widening portion 6 does not appear. Refer to Fig.10 After the circuit pattern and the gold-plated lead 2 are made, the intersection of the gold-plated lead 2 and the pad 1 is at a right angle. Fig.11 When the gold plating process is performed, the gold-plated lead 2 also needs to be covered with a wet film 7, and there is also a clearance between the wet film 7 and the pad 1. Fig.12 After the gold plating treatment, the gold-plated lead wire 2 in the clearance will also be plated with the gold layer 3, but there is only the rectangular part of the gold-plated lead wire 2 in the clearance, and there is no wire widening part 6. Therefore, the gold layer 3 in the clearance is rectangular, that is, the width of the gold layer 3 in the clearance is consistent, which does not affect the etching of the junction between the gold-plated lead wire 2 and the gold layer 3, and will not cause the etched surface to be concave due to stress problems. Fig.13 After etching away the gold-plated lead 2, a second protruding structure 9 appears at the edge of the pad 1, but the second protruding structure 9 is rectangular, and the edge of the second protruding structure 9 is straight, regular and complete, and does not affect the integrity of the side of the gold-plated pad 1, thereby not affecting the performance of the PCB.

[0021] Furthermore, in step S110, the required circuit pattern is manufactured according to the normal process flow, and step S110 includes the following steps: Step S111, preparing a production and processing file according to a photolithography file related to a required circuit pattern, wherein the production and processing file does not include a gold-plated lead 2; Step S112, cutting or laminating; Step S113, drilling holes, which may be holes for realizing electrical connection between different layers or holes for installing electronic components, and may be adjusted according to the actual required circuit pattern; Step S114, copper deposition: a copper layer is coated on the hole wall to ensure electrical connection; Step S115, pattern transfer: after steps such as exposure and development, the required circuit pattern is transferred to the board. This step is a conventional process in the prior art and will not be described in detail here. Step S116, electroplating: copper plating to ensure the performance of the circuit and the hole, and then tin plating to protect the copper layer of the circuit and the hole wall; Step S117, alkaline etching: etching out the required circuit pattern; Step S118, inspection.

[0022] Furthermore, after the required circuit pattern is made, the gold-plated lead 2 is made according to the following steps: Step S121, copper plating the whole board, the copper thickness of the whole board is 5μm~6μm, before copper plating the whole board, copper plasma deposition and whole board copper deposition and other steps can be performed according to actual needs; Step S122, pattern transfer: transferring the pattern of the gold-plated lead 2 to the board; Step S123, electroplating: only tin plating, no copper plating; Step S124, alkaline etching: etching out the pattern of the gold-plated lead 2: Step S125, inspection.

[0023] Furthermore, after the required circuit pattern and the gold-plated lead 2 are prepared, electroplating is performed according to the following steps: Step S210, attaching a protective film on the board, the gold-plated lead 2 and other positions are all covered with the protective film, only the pad to be gold-plated is exposed, and the protective film 1 is a wet film; Step S220, gold plating, plating a gold layer 3 on the surface of the gold-plated pad 1 and the side of the gold-plated pad 1 close to the gold-plated lead 2; Step S230, removing the film.

[0024] After gold plating, follow the steps below to remove the gold plated leads2: Step S310, attaching a protective film on the board, the circuit pattern and other positions are all covered with the protective film, only the gold-plated lead 2 is exposed, and the protective film is a dry film; Step S320, alkaline etching: etching and removing the gold-plated lead 2. In this process, even if over-etching occurs, the gold layer 3 will not collapse or the gold-plated pad 1 will not be damaged; Step S330, film stripping and inspection.

[0025] It should be noted that in the description of the present invention, if there are any orientation descriptions, such as up, down, front, back, left, right, etc., the orientations or positional relationships indicated are all based on the orientations or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation, and cannot be understood as a limitation on the present invention.

[0026] In the description of the present invention, "several" means one or more, "more" means two or more, "greater than", "less than", "exceed" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used to distinguish the technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0027] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0028] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A PCB manufacturing method for improving gold layer collapse or gold-plated pad damage, characterized in that: The steps include: Step S110, firstly making a required circuit pattern on the board, the made circuit pattern including the pad to be gold plated (1); Step S120, making a gold-plated lead (2) on the board, wherein the copper thickness of the gold-plated lead (2) is less than the copper thickness of the pad to be gold-plated (1); Step S200, performing a gold plating process on the board body with the circuit pattern and the gold-plated lead wire (2) so as to plate a gold layer (3) on the surface and side of the pad (1) to be gold-plated; Step S300, etching the plate that has been gold plated to remove the gold plated leads (2).

2. The PCB manufacturing method for improving gold layer collapse or gold-plated pad damage according to claim 1, characterized in that: Step S110 includes the following steps: Step S111, preparing a production and processing file according to a photolithography file related to a required circuit pattern, wherein the production and processing file does not include a gold-plated lead (2); Step S112, cutting or laminating; Step S113, drilling; Step S114, copper deposition; Step S115, graphic transfer; Step S116, electroplating; Step S117, alkaline etching; Step S118, inspection.

3. The PCB manufacturing method for improving gold layer collapse or gold-plated pad damage according to claim 1, characterized in that: Step S120 includes the following steps: Step S121, copper plating the entire board; Step S122, graphic transfer; Step S123, electroplating; Step S124, alkaline etching; Step S125, inspection.

4. The PCB manufacturing method for improving gold layer collapse or gold-plated pad damage according to claim 3, characterized in that: In step S121 , the copper plating thickness is 5 μm to 6 μm.

5. The PCB manufacturing method for improving gold layer collapse or gold-plated pad damage according to claim 1, characterized in that: Step S200 includes the following steps: Step S210, attaching a protective film on the board, leaving only the pad to be gold plated (1) exposed; Step S220, gold plating; Step S230, removing the film.

6. The PCB manufacturing method for improving gold layer collapse or gold-plated pad damage according to claim 5, characterized in that: The protective film in step S210 is a wet film.

7. The PCB manufacturing method for improving gold layer collapse or gold-plated pad damage according to claim 1, characterized in that: Step S300 includes the following steps: Step S310, attaching a protective film to the board, leaving only the gold-plated leads (2) exposed; Step S320: alkaline etching; Step S330, film stripping and inspection.

8. The PCB manufacturing method for improving gold layer collapse or gold-plated pad damage according to claim 7, characterized in that: The protective film in step S310 is a dry film.

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