Growth method of gate oxide layer, preparation method of semiconductor device and semiconductor device

Abstract

The invention discloses a gate oxide layer growth method, a semiconductor device preparation method and a semiconductor device, and relates to the technical field of semiconductor preparation. The method comprises the following steps: forming a floating gate layer on a first gate oxide layer corresponding to a high-voltage well region; forming an ONO structure film layer on the floating gate layer; etching the first gate oxide layer on the low-voltage well region of the substrate and a first silicon oxide film layer deposited on the back surface of the substrate when the ONO structure film layer is formed; the silicon nitride film layer and the second silicon oxide film layer are deposited on the back face of the substrate when the ONO structure film layer is formed through etching; and forming a second gate oxide layer on the low-voltage well region of the substrate through a thermal diffusion growth process. Through the technical means, the ONO structure film layer deposited on the back surface of the wafer can be removed before the gate oxide layer is grown, the problem that the oxygen flow and the uniformity are reduced when the gate oxide layer is grown on the lower wafer in the prior art is solved, and the thickness of the gate oxide layer generated by the lower wafer is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a gate oxide layer growth method, a semiconductor device manufacturing method and a semiconductor device. Background Art

[0002] The gate oxide layer, also called the gate oxide layer or the gate insulating layer, is an extremely thin silicon oxide film located between the gate and the substrate in the semiconductor structure. The main function of the gate oxide layer in the device is to serve as a charge isolation layer, which can effectively improve the conductivity, control the current to prevent the device from overheating or short circuit caused by excessive current, and form a charge channel to control the flow of electrons in the device, thereby improving the stability of the device and protecting the device. Therefore, in the process of semiconductor device manufacturing, the preparation of the gate oxide layer requires strict control of its uniformity and thickness.

[0003] In the prior art, in the manufacturing process of 0.95nm EPROM products, an ONO structure film layer is often used as a dielectric layer to store charges. The ONO structure film layer is a special film layer composed of three layers of an oxide layer, a nitride layer and an oxide layer. After the ONO structure film layer grows, a gate oxide layer is grown. However, the ONO structure film layer will not only be formed on the front side of the wafer during growth, but also on the back side of the wafer. The structure film layer on the back side of the wafer will consume oxygen during formation, resulting in a decrease in the oxygen flow and uniformity on the front side of the wafer below it, which in turn has a certain impact on the gate oxide layer grown on the front side of the wafer below it, making the thickness of the gate oxide layer grown on the front side of the wafer below it low. The low gate oxide layer thickness has a direct impact on the basic performance and stability of the device, reducing the yield of the device. Summary of the invention

[0004] The present application provides a gate oxide layer growth method, a semiconductor device preparation method and a semiconductor device, so as to remove the ONO structure film layer deposited on the back side of the wafer before growing the gate oxide layer, solve the problem of reduced oxygen flow and uniformity when growing the gate oxide layer of the lower wafer in the prior art, ensure the thickness of the gate oxide layer generated by the lower wafer, improve the basic performance and stability of the device, and thus improve the yield of the device.

[0005] In a first aspect, the present application provides a gate oxide layer growth method, comprising:

[0006] forming a floating gate layer on the first gate oxide layer corresponding to the high-voltage well region;

[0007] forming an ONO structure film layer on the floating gate layer;

[0008] Etching a first gate oxide layer on the low-voltage well region of the substrate and a first silicon oxide film layer deposited on the back side of the substrate when forming the ONO structure film layer;

[0009] The silicon nitride film layer and the second silicon oxide film layer deposited on the back side of the substrate when etching to form the ONO structure film layer;

[0010] A second gate oxide layer is formed on the low voltage well region of the substrate by a thermal diffusion growth process.

[0011] Optionally, forming a floating gate layer on the first gate oxide layer corresponding to the high-voltage well region includes:

[0012] Depositing polysilicon material on the front and back sides of the substrate by a furnace process;

[0013] The polysilicon material deposited on the front side of the substrate is etched so that the polysilicon material remaining on the first gate oxide layer corresponding to the high-voltage well region forms a floating gate layer.

[0014] Optionally, the thickness of the polysilicon material deposited on the back side of the substrate is greater than 300 nm, and the etching transmittance of the polysilicon material deposited on the front side of the substrate is greater than 75%.

[0015] Optionally, before forming the first gate oxide layer on the high-voltage well region and the low-voltage well region of the substrate, the method further includes:

[0016] forming a high-voltage well region and a low-voltage well region in the substrate by an ion implantation process;

[0017] A shallow trench isolation channel is etched between the high-voltage well region and the low-voltage well region, and silicon oxide is deposited in the shallow trench isolation channel.

[0018] Optionally, forming a first gate oxide layer on the high-voltage well region and the low-voltage well region of the substrate includes:

[0019] Silicon oxide is deposited on the high-voltage well region and the low-voltage well region of the substrate through a furnace process to form a first gate oxide layer, and silicon oxide is deposited on the back side of the substrate to form an oxide layer.

[0020] Optionally, forming an ONO structure film layer on the floating gate layer includes:

[0021] Depositing silicon oxide material, silicon nitride material and silicon oxide material in sequence on the front and back sides of the substrate by a furnace tube process to form a second silicon oxide film layer, a silicon nitride film layer and a first silicon oxide film layer from outside to inside on the front and back sides of the substrate;

[0022] The second silicon oxide film layer, the silicon nitride film layer and the first silicon oxide film layer on the front side of the substrate are etched so that the second silicon oxide film layer, the silicon nitride film layer and the first silicon oxide film layer remaining on the floating gate layer form an ONO structure film layer.

[0023] Optionally, the etching of the first gate oxide layer on the low voltage well region of the substrate and the first silicon oxide film layer deposited on the back side of the substrate when forming the ONO structure film layer comprises:

[0024] Coating a layer of photoresist on the front side of the substrate;

[0025] Developing the photoresist on the first gate oxide layer on the low voltage well region to expose the first gate oxide layer on the low voltage well region;

[0026] Etching the first gate oxide layer on the low voltage well region and the first silicon oxide film layer on the back side of the substrate by means of a hydrofluoric acid solution;

[0027] The remaining photoresist on the front side of the substrate is removed.

[0028] Optionally, the silicon nitride film layer and the second silicon oxide film layer deposited on the back side of the substrate when etching to form the ONO structure film layer include:

[0029] The silicon nitride film layer and the second silicon oxide film layer on the back side of the substrate are etched by a hydrofluoric acid solution.

[0030] In a second aspect, the present application provides a method for preparing a semiconductor device, including the gate oxide layer growth method as described in the first aspect.

[0031] In a third aspect, the present application provides a semiconductor device manufactured using the discrete device manufacturing method described in the second aspect.

[0032] In the present application, a first gate oxide layer is formed on a high-voltage well region and a low-voltage well region of a substrate; a floating gate layer is formed on the first gate oxide layer corresponding to the high-voltage well region; an ONO structural film layer is formed on the floating gate layer; the first gate oxide layer on the low-voltage well region of the substrate and the first silicon oxide film layer deposited on the back side of the substrate when the ONO structural film layer is formed are etched; the silicon nitride film layer and the second silicon oxide film layer deposited on the back side of the substrate when the ONO structural film layer is formed are etched; and a second gate oxide layer is formed on the low-voltage well region of the substrate through a thermal diffusion growth process. Through the above technical means, before growing the second gate oxide layer, the first silicon oxide film layer, the silicon nitride film layer and the second silicon oxide film layer deposited on the back of the wafer during the ONO structure film layer formation process can be removed, so that when the second gate oxide layer is grown on multiple stacked wafers at the same time through the furnace tube process, the problem of silicon nitride material and silicon oxide material on the back of the upper wafer consuming oxygen on the front of the lower wafer will not occur. The front of the lower wafer has sufficient and uniform oxygen to generate a second gate oxide layer with a larger thickness and uniform thickness, thereby improving the basic performance and stability of the device, thereby improving the yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flow chart of a gate oxide layer growth method provided in an embodiment of the present application;

[0034] Figure 2 is a schematic structural diagram of a substrate provided in an embodiment of the present application;

[0035] Figure 3 It is one of the structural schematic diagrams of the wafer provided in the embodiment of the present application;

[0036] Figure 4 This is the second structural schematic diagram of the wafer provided in the embodiment of the present application;

[0037] Figure 5 This is the third structural schematic diagram of the wafer provided in the embodiment of the present application;

[0038] Figure 6 This is the fourth structural schematic diagram of the wafer provided in the embodiment of the present application;

[0039] Figure 7 This is the fifth structural schematic diagram of the wafer provided in the embodiment of the present application;

[0040] Figure 8 This is the sixth structural schematic diagram of the wafer provided in the embodiment of the present application;

[0041] Fig. 9 is a schematic diagram of a wafer in a furnace tube provided in an embodiment of the present application;

[0042] Fig.10 This is the seventh structural schematic diagram of the wafer provided in the embodiment of the present application;

[0043] Fig.11 This is the eighth structural schematic diagram of the wafer provided in the embodiment of the present application;

[0044] Fig.12 It is a schematic diagram of the growth effect of the second gate oxide layer before and after the film layer on the back side of the wafer is removed according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present application clearer, the specific embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. It is understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for the convenience of description, only the part related to the present application but not all the contents are shown in the accompanying drawings. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow chart describes each operation (or step) as a sequential process, many of the operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of each operation can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0046] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0047] In the more common existing implementation method, in the product manufacturing process of 0.95nm EPROM, an ONO structure film layer is often used as a dielectric layer to store charge. The ONO structure film layer is a special film layer composed of three layers of oxide layer, nitride layer and oxide layer. After the ONO structure film layer grows, the gate oxide layer is grown. However, the ONO structure film layer will not only be formed on the front side of the wafer, but also on the back side of the wafer during growth. When the wafer grows the gate oxide layer, the gate oxide layer is grown on multiple wafers at the same time through the furnace tube process, and the multiple wafers are stacked up and down. Since the ONO structure film layer on the back side of the wafer consumes oxygen during formation, the ONO structure film layer deposited on the back side of the upper wafer will cause the oxygen flow and uniformity on the front side of the lower wafer to decrease, thereby causing the gate oxide layer grown on the front side of the lower wafer to have a low thickness and poor uniformity. The gate oxide layer with low thickness and poor uniformity affects the basic performance and stability of the device, and reduces the yield of the device.

[0048] To solve the above problems, the present embodiment provides a gate oxide layer growth method, a semiconductor device preparation method and a semiconductor device, so as to remove the ONO structure film layer deposited on the back side of the wafer before growing the gate oxide layer, so as to prevent the ONO structure film layer deposited on the back side of the wafer from affecting the oxygen flow and uniformity on the front side of the wafer below, thereby ensuring the thickness of the gate oxide layer generated on the wafer below, improving the basic performance and stability of the device, and thus improving the yield of the device.

[0049] Figure 1 A flow chart of a gate oxide layer growth method provided in an embodiment of the present application is given. Figure 1 As shown, the gate oxide layer growth method includes:

[0050] S110 , forming a first gate oxide layer on the high-voltage well region and the low-voltage well region of the substrate.

[0051] Exemplarily, for the sake of convenience of description, the substrate and the various structural layers formed on the substrate are collectively referred to as wafers. The substrate of the wafer is a semiconductor material, especially a semiconductor material suitable for preparing embedded flash memory, such as silicon, germanium, etc. A high-voltage well region and a low-voltage well region are formed in the substrate. The high-voltage well region can be an N-type high-voltage well region (HNVW) or a P-type high-voltage well region (HPVW), and the low-voltage well region can be an N-type low-voltage well region (LNVW) or a P-type low-voltage well region (LPVW). The high-voltage well region and the low-voltage well region in the substrate are separated by a shallow trench isolation structure. Exemplarily, Figure 2 Schematic diagram of the structure of the substrate provided in the embodiment of the present application. Figure 2 As shown, a low voltage well region 12 and a high voltage well region 13 are formed on the upper portion of the substrate 11 , and a shallow trench isolation structure 14 is formed between the high voltage well region 13 and the low voltage well region 12 .

[0052] In this embodiment, before forming the first gate oxide layer, a high-voltage well region and a low-voltage well region can be formed in the substrate by an ion implantation process; a shallow trench isolation channel is etched between the high-voltage well region and the low-voltage well region, and silicon oxide is deposited in the shallow trench isolation channel. Exemplarily, a photoresist is coated on the substrate, and the photoresist is exposed using a photolithography mask with a high-voltage well region pattern, and the exposed photoresist is removed by a development process to leave a pattern corresponding to the high-voltage well region pattern on the substrate to expose the area on the substrate where the high-voltage well region needs to be formed. If an N-type high-voltage well region is formed in the substrate, an N-type impurity is implanted into the exposed substrate with high energy and high dose by an ion implantation process to form a high-concentration N-type region, i.e., an N-type high-voltage well region, in the substrate. After the ion implantation is completed, the surface photoresist is removed, the silicon wafer is cleaned, and then the substrate is annealed. Afterwards, a photoresist is coated on the substrate, and a photolithography mask with a low-voltage well region pattern is used to expose the photoresist. The exposed photoresist is removed through a development process to leave a pattern corresponding to the low-voltage well region pattern on the substrate, so as to expose the area on the substrate where the low-voltage well region needs to be formed. If a P-type low-voltage well region is formed in the substrate, a P-type impurity is implanted into the exposed substrate with appropriate energy and dosage through an ion implantation process to form a low-concentration P-type region, i.e., a P-type low-voltage well region, in the substrate. After the ion implantation is completed, the photoresist on the surface is removed, the silicon wafer is cleaned, and the substrate is annealed. Finally, a photoresist is coated on the substrate, and a photolithography mask with a shallow trench isolation channel pattern is used to expose the photoresist. The exposed photoresist is removed through a development process to leave a pattern corresponding to the shallow trench isolation channel pattern on the substrate, so as to expose the area on the substrate where the shallow trench isolation channel needs to be formed. A shallow trench isolation trench is etched in the exposed area of ​​the substrate by a dry etching process, and silicon oxide is deposited in the shallow trench isolation trench by a chemical vapor deposition process to form a shallow trench isolation structure that isolates the high-voltage well region and the low-voltage well region in the substrate.

[0053] After forming a high-voltage well region, a low-voltage well region and a shallow trench isolation structure in the substrate, silicon oxide can be deposited on the high-voltage well region and the low-voltage well region of the substrate by a furnace tube process to form a first gate oxide layer, and silicon oxide can be deposited on the back of the substrate to form an oxide layer. Exemplarily, the first gate oxide layer is formed by using a thermal diffusion growth process in a furnace tube. Due to the characteristics of the furnace tube process, silicon oxide materials corresponding to the first gate oxide layer will be deposited on both the front and back sides of the wafer at the same time. Therefore, when silicon oxide is deposited on the high-voltage well region and the low-voltage well region of the substrate by a thermal diffusion growth process in the furnace tube to form the first gate oxide layer on the front side of the wafer, silicon oxide will also be deposited on the back side of the substrate to form an oxide layer on the back side of the wafer. Figure 3 This is one of the schematic diagrams of the structure of the wafer provided in the embodiment of the present application. Figure 3As shown, after the first gate oxide layer is grown by the furnace process, a first gate oxide layer 15 is formed on the high voltage well region 13 and the low voltage well region 12 , and an oxide layer 16 is formed on the back side of the wafer, that is, the back side of the substrate 11 .

[0054] S120, forming a floating gate layer on the first gate oxide layer corresponding to the high-voltage well region.

[0055] Exemplarily, a floating gate material is deposited on the first gate oxide layer above the high-voltage well region of the substrate to form a floating gate layer. Generally, the floating gate material may be a polysilicon material.

[0056] In this embodiment, the formation process of the floating gate layer can be to deposit polysilicon material on the front side of the wafer, and then selectively etch the polysilicon material to retain the polysilicon material on the first gate oxide layer above the high-voltage well region to form a floating gate layer. The specific implementation process is: depositing polysilicon material on the front and back sides of the substrate through a furnace tube process; etching the polysilicon material deposited on the front side of the substrate so that the polysilicon material retained on the first gate oxide layer corresponding to the high-voltage well region forms a floating gate layer. Exemplarily, polysilicon material is deposited on the front side of the wafer using a chemical vapor deposition process in a furnace tube. Due to the characteristics of the furnace tube process, polysilicon material will be deposited on both the front and back sides of the wafer at the same time. Therefore, when polysilicon material is deposited on the wafer by a chemical vapor deposition process in a furnace tube, a polysilicon film layer will be formed on the front and back sides of the wafer at the same time. Afterwards, a photoresist is coated on the polysilicon film layer on the front side of the wafer, and the photoresist is exposed using a photolithography mask with a floating gate layer pattern. The unexposed photoresist is removed through a development process to leave a pattern corresponding to the floating gate layer pattern on the polysilicon film layer on the front side of the wafer, exposing an area on the polysilicon film layer where a floating gate layer is not required to be formed. The polysilicon film layer exposed on the front side of the wafer is etched through a wet etching process or a dry etching process to etch the polysilicon material on the front side of the wafer except for the area on the first gate oxide layer corresponding to the high-voltage well region, and the polysilicon material retained on the first gate oxide layer corresponding to the high-voltage well region forms a floating gate layer. The polysilicon film layer is retained on the back side of the wafer, that is, on the back side of the oxide layer on the back side of the substrate. Figure 4 This is the second schematic diagram of the structure of the wafer provided in the embodiment of the present application. Figure 4 As shown, after the polysilicon material is deposited through the furnace tube process, a polysilicon film layer 17 is formed on the front and back sides of the wafer. Figure 5 This is the third schematic diagram of the structure of the wafer provided in the embodiment of the present application. Figure 5 As shown, after the floating gate layer is etched, a floating gate layer 18 is formed on the front side of the first gate oxide layer 15 above the high-voltage well region 13 , and a polysilicon film layer 17 is retained on the back side of the oxide layer 16 on the back side of the substrate 11 .

[0057] Furthermore, the thickness of the polysilicon material deposited on the back of the substrate is greater than 300nm, that is, the thickness of the polysilicon film layer formed on the back of the substrate is greater than 300nm. The etching transmittance of the polysilicon material deposited on the front of the substrate is greater than 75%, wherein the etching transmittance is the ratio of the polysilicon material etched on the front of the substrate to the area of ​​the polysilicon material deposited on the front of the substrate, that is, the area of ​​the floating gate layer in the polysilicon film layer on the front of the wafer is less than 25%, and more than 75% of the area of ​​the polysilicon film layer on the front of the wafer must be etched to form a floating gate layer. It should be noted that when the etching transmittance of the polysilicon film layer on the front of the wafer is greater than 75%, a large amount of polysilicon material deposited on the front of the wafer will be removed, resulting in a sudden change in the stress distribution of the wafer, thereby affecting the degree of bending of the wafer. However, since a thick polysilicon film layer is retained on the back of the wafer, the degree of bending of the wafer will not cause the wafer to break. If the polysilicon film layer on the back of the wafer is pulled out before the second gate oxide layer is subsequently formed, the stress of the wafer will suddenly change again at the moment the thick polysilicon film layer is pulled out. The stress of the wafer will no longer be balanced, resulting in the problem of wafer breakage. In order to avoid the problem of wafer cracking due to sudden stress change, the polysilicon film layer on the back of the wafer can be retained and only the ONO structure film layer on the back of the wafer can be removed.

[0058] S130, forming an ONO structure film layer on the floating gate layer.

[0059] Exemplarily, silicon oxide material, silicon nitride material and silicon nitride material are sequentially deposited on the floating gate layer to form an ONO structure film layer on the floating gate layer, which is formed by sequentially stacking an oxide layer, a nitride layer and an oxide layer. The ONO structure film layer can be used as a dielectric layer.

[0060] In this embodiment, the formation process of the ONO structure film layer can be to deposit silicon oxide material, silicon nitride material and silicon nitride material on the front side of the wafer in sequence, and then selectively etch the silicon oxide material, silicon nitride material and silicon nitride material in a partial area to retain the silicon oxide material, silicon nitride material and silicon nitride material above the floating gate layer, thereby forming the ONO structure film layer. The specific implementation process is: depositing silicon oxide material, silicon nitride material and silicon oxide material in sequence on the front and back sides of the substrate through a furnace tube process to form a second silicon oxide film layer, a silicon nitride film layer and a first silicon oxide film layer from the outside to the inside on the front and back sides of the substrate; etching the second silicon oxide film layer, the silicon nitride film layer and the first silicon oxide film layer on the front side of the substrate, so that the second silicon oxide film layer, the silicon nitride film layer and the first silicon oxide film layer retained on the floating gate layer form the ONO structure film layer. Exemplarily, silicon oxide material, silicon nitride material and silicon oxide material are sequentially deposited on the front side of the wafer by a gas phase chemical vapor deposition process in a furnace tube. Due to the characteristics of the furnace tube process, the material of the ONO structure film layer will be deposited on both the front and back sides of the wafer at the same time. Therefore, after silicon oxide material, silicon nitride material and silicon oxide material are sequentially deposited on the wafer by a chemical vapor deposition process in the furnace tube, a second silicon oxide film layer, a silicon nitride film layer and a first silicon oxide film layer will be sequentially formed from the outside to the inside on the front and back sides of the wafer at the same time. Afterwards, a photoresist is coated on the polysilicon film layer on the front side of the wafer, and the photoresist is exposed using a photolithography mask with an ONO structure film layer. The unexposed photoresist is removed by a development process to leave a pattern corresponding to the ONO structure film layer pattern on the second silicon oxide film layer on the front side of the wafer, exposing the area where the second silicon oxide film layer does not need to form an ONO structure film layer. The second silicon oxide film layer exposed on the front side of the wafer and the silicon nitride film layer and the first silicon oxide film layer below the corresponding position are etched by a wet etching process to etch the second silicon oxide film layer, silicon nitride film layer and the first silicon oxide film layer on the front side of the wafer except for the area above the floating gate layer, and the second silicon oxide film layer, silicon nitride film layer and the first silicon oxide film layer retained on the floating gate layer form an ONO structure film layer. The second silicon oxide film layer, silicon nitride film layer and the first silicon oxide film layer are retained on the back side of the wafer, that is, the back side of the polysilicon film layer. Figure 6 This is the fourth structural diagram of the wafer provided in the embodiment of the present application. Figure 6 As shown, after silicon oxide material, silicon nitride material and silicon oxide material are deposited in sequence through a furnace tube process, a second silicon oxide film layer 21, a silicon nitride film layer 20 and a first silicon oxide film layer 19 are formed in sequence on the front and back sides of the wafer from the outside to the inside. Figure 7 This is the fifth structural diagram of the wafer provided in the embodiment of the present application. Figure 7 As shown, after the etching process of the ONO structure film layer, an ONO structure film layer 22 is formed on the front side of the floating gate layer 18 , and a second silicon oxide film layer 21 , a silicon nitride film layer 20 and a first silicon oxide film layer 19 are retained on the back side of the polysilicon film layer 17 .

[0061] S140, etching the first gate oxide layer on the low voltage well region of the substrate and the first silicon oxide film layer deposited on the back side of the substrate when forming the ONO structure film layer.

[0062] Exemplarily, the second gate oxide layer is formed on the low-voltage well region of the substrate, so before growing the second gate oxide layer on the low-voltage well region, the first gate oxide layer on the low-voltage well region can be etched first. While etching the first gate oxide layer, the solution used to etch the first gate oxide layer will also chemically react with the first silicon oxide film layer on the back of the wafer, thereby removing the first silicon oxide film layer.

[0063] In this embodiment, the first gate oxide layer on the low voltage well region of the substrate and the first silicon oxide film layer on the back side of the substrate may be etched by a hydrofluoric acid solution. Figure 8 This is the sixth structural diagram of the wafer provided in the embodiment of the present application. Figure 8 As shown, after the etching process of the first gate oxide layer 15, the first gate oxide layer 15 on the low voltage well region 12 is etched away to expose the low voltage well region 12. The first silicon oxide film layer 21 on the back of the wafer is also etched away by the hydrofluoric acid solution in the etching process, so that the silicon nitride film layer 20 on the back of the wafer is exposed.

[0064] Optionally, the process of etching the first gate oxide layer and the first silicon oxide film layer on the back of the substrate is: coating a layer of photoresist on the front of the substrate; developing the photoresist on the first gate oxide layer on the low-voltage well region to expose the first gate oxide layer on the low-voltage well region; etching the first gate oxide layer on the low-voltage well region and the first silicon oxide film layer on the back of the substrate by a hydrofluoric acid solution; and removing the remaining photoresist on the front of the substrate. Exemplarily, a layer of photoresist is first coated on the front of the wafer, and then the photoresist above the first gate oxide layer is developed to expose the first gate oxide layer, and the exposed first gate oxide layer and the first silicon oxide film layer on the back of the substrate are wet-etched with a hydrofluoric acid solution, thereby removing the first gate oxide layer and the first silicon oxide film layer on the back of the substrate. For the silicon oxide in the shallow trench isolation structure and the first silicon oxide film layer of the ONO structure film layer, there is photoresist protection during wet etching, so the silicon oxide in the shallow trench isolation structure and the first silicon oxide film layer of the ONO structure film layer will not be removed. After removing the first gate oxide layer and the first silicon oxide film layer on the back of the substrate, the photoresist on the shallow trench isolation structure and the first silicon oxide film layer of the ONO structure film layer is removed to obtain Figure 8 The wafer structure is shown.

[0065] It should be noted that since the first silicon oxide film layer is formed during the process of etching the first gate oxide layer, if the etching time of the first gate oxide layer is short or the concentration of the etching solution is low, the first silicon oxide film layer may still remain on the back of the wafer. If the etching time of the first gate oxide layer is long or the concentration of the etching solution is high, part of the silicon nitride film layer on the back of the wafer will also be etched away. However, in either case, the remaining ONO structural film layer material on the back of the wafer will be etched by a hydrofluoric acid solution before the second gate oxide layer is grown, to ensure that no ONO structural film layer material remains on the back of the wafer.

[0066] S150, etching the silicon nitride film layer and the second silicon oxide film layer deposited on the back side of the substrate when forming the ONO structure film layer.

[0067] For example, the second gate oxide layer is grown by a furnace tube process, and multiple wafers are stacked in the furnace tube at the same time. When the second gate oxide layer is grown, the silicon nitride film layer and the second silicon oxide film layer on the back of the wafer will chemically react with oxygen, so the thickness of the second gate oxide layer grown on the front of the lower wafer will be affected by the silicon nitride film layer and the second silicon oxide film layer on the back of the upper wafer. For example, Fig. 9 Schematic diagram of a wafer in a furnace tube provided in an embodiment of the present application. Fig. 9 As shown, a first wafer 25, a second wafer 26 and a third wafer 27 are stacked in a furnace tube 24, and a silicon nitride film layer 21 is formed on the back side of the first wafer 25, the second wafer 26 and the third wafer 27. If the second gate oxide layer 23 is grown on the front side of the first wafer 25, the second wafer 26 and the third wafer 27, and the silicon nitride film layer 21 still remains on the back side of the first wafer 25, the second wafer 26 and the third wafer 27, the silicon nitride film layer 21 will chemically react with the oxygen thereunder, thereby causing the second gate oxide layer 13 located below the silicon nitride film layer 21 to grow into a thinner and unevenly thick second gate oxide layer 13 due to insufficient oxygen flow and poor uniformity during growth. That is, the silicon nitride film layer 21 on the back of the first wafer 25 will cause a second gate oxide layer 23 with a relatively thin thickness and uneven thickness to grow on the front of the second wafer 26 , and the silicon nitride film layer 21 on the back of the second wafer 26 will cause a second gate oxide layer 23 with a relatively thin thickness and uneven thickness to grow on the front of the third wafer 27 .

[0068] In this embodiment, in order to prevent the silicon nitride film layer and the second silicon oxide film layer on the back of the upper wafer from affecting the second gate oxide layer grown on the front of the lower wafer, the second silicon oxide film layer and the silicon nitride film layer on the back of the wafer may be removed before growing the second gate oxide layer.

[0069] In this embodiment, the silicon nitride film layer and the second silicon oxide film layer on the back side of the substrate can be etched by a hydrofluoric acid solution. Fig.10This is the seventh structural diagram of the wafer provided in the embodiment of the present application. Fig.10 As shown, after the etching process of the silicon nitride film layer and the second silicon oxide film layer, the silicon nitride film layer 20 and the second silicon oxide film layer 19 on the back side of the wafer are etched away, so that the polysilicon film layer 17 on the back side of the wafer is exposed. Of course, if the first silicon oxide film layer 19 still remains on the back side of the wafer after the etching of the first gate oxide layer, the first silicon oxide film layer 19 can be etched first by a hydrofluoric acid solution, and then the silicon nitride film layer 20 and the second silicon oxide film layer 19 are etched in sequence, and finally stay on the polysilicon film layer 17.

[0070] It should be noted that since the polysilicon material does not chemically react with the hydrofluoric acid solution, it can accurately stay on the polysilicon film layer on the back of the wafer when etching with the hydrofluoric acid solution, avoiding the problem of wafer cracking caused by a sudden change in the stress of the wafer after the polysilicon film layer is etched. Furthermore, although the polysilicon material will also chemically react with oxygen when the second gate oxide layer grows, the oxygen consumed on the back of the wafer is greatly reduced after the material of the ONO structure film layer on the back of the polysilicon film layer is removed, and the thickness and uniformity of the second gate oxide layer will not be greatly affected while retaining the polysilicon film layer. Moreover, retaining the polysilicon film layer not only eliminates the process of etching the polysilicon film layer and thus improves the efficiency of device preparation, but also reduces to a certain extent the probability of wafer cracking due to the removal of the polysilicon film layer, especially when the etching transmittance of the polysilicon film layer on the front side of the wafer is greater than 75% and the thickness of the polysilicon film layer on the back side of the wafer is greater than 300nm, which effectively prevents the wafer from cracking due to sudden changes in the stress of the polysilicon film layer.

[0071] S160, forming a second gate oxide layer on the low voltage well region of the substrate through a thermal diffusion growth process.

[0072] For example, after the material of the ONO structure film layer on the back side of the wafer is removed, silicon oxide may be grown on the low voltage well region of the substrate in a furnace tube by a thermal diffusion growth process to form a second gate oxide layer. Fig.11 This is the eighth schematic diagram of the structure of the wafer provided in the embodiment of the present application. Fig.11 As shown, after the second gate oxide layer 23 is grown by the furnace tube process, a second gate oxide layer 23 is formed above the low voltage well region 12. It should be noted that when the silicon oxide is grown by the thermal diffusion growth process, oxygen will only react chemically with the silicon material to form silicon oxide. Fig.10It can be seen from the shown content that except for the low-voltage well region 12 which belongs to the substrate of silicon material, other regions such as the shallow trench isolation structure 14, the first silicon oxide film layer of the ONO structure film layer 22 and the silicon nitride film layer 20 on the back side of the substrate are all silicide materials, that is, silicon oxide will not grow in these regions, so only the second gate oxide layer 23 will be formed above the low-voltage well region 12.

[0073] In one embodiment, three wafers are stacked in a furnace tube and a second gate oxide layer is grown simultaneously. The material of the ONO structure film layer on the back of the second wafer is removed from the three wafers, while the material of the ONO structure film layer is retained on the back of the remaining wafers. Table 1 is an experimental data table of the second gate oxide layer grown on three wafers provided in an embodiment of the present application.

[0074] Table 1

[0075]

[0076] As shown in Table 1, the wafers marked 1 to 3 are stacked in the furnace tube from top to bottom. For wafer No. 1, there is no wafer above it, so the thickness of the second gate oxide layer grown on it meets the requirements of process stability, and wafer No. 1 is normal. For wafer No. 2, wafer No. 1 is arranged above it, and the material of the ONO structural film layer is retained on the back of wafer No. 1. The thickness of the second gate oxide layer grown on wafer No. 2 is relatively thin, which does not meet the requirements of process stability, and wafer No. 2 is abnormal. For wafer No. 3, wafer No. 2 is arranged above it, and the material of the ONO structural film layer is cleared on the back of wafer No. 2. The thickness of the second gate oxide layer grown on wafer No. 3 meets the requirements of process stability, and wafer No. 3 is normal. Therefore, it can be obtained through experiments that by effectively clearing the material of the ONO structural film layer on the back of the wafer, the second gate oxide layer grown on the corresponding lower wafer can meet the requirements of process stability. Furthermore, Fig.12 Schematic diagram of the growth effect of the second gate oxide layer before and after the film layer on the back of the wafer is removed according to an embodiment of the present application. Fig.12 As shown, after monitoring the thickness of the second gate oxide layer grown on the wafer for a period of time, it was found that before the material of the ONO structural film layer on the back of the wafer was removed, the thickness of the second gate oxide layer was relatively thin and did not meet the requirements of process stability. After the material of the ONO structural film layer on the back of the wafer was removed, the thickness of the second gate oxide layer increased significantly and met the requirements of process stability. Therefore, removing the material of the ONO structural film layer on the back of the wafer can effectively improve the problem of thin growth thickness and long uniformity of the second gate oxide layer.

[0077] On the basis of the above-mentioned embodiments, the embodiments of the present application also provide a method for preparing a semiconductor device and a semiconductor device obtained by using the method for preparing a semiconductor device, and the method for preparing a semiconductor device includes a gate oxide layer growth method as described in the above-mentioned embodiments. In the process of preparing a semiconductor device in this embodiment, the gate oxide layer growth method provided in the above-mentioned embodiments is used to remove the material of the ONO structure film layer deposited on the back of the wafer before growing the second gate oxide layer, so as to avoid the material of the ONO structure film layer on the back of the wafer from reacting with oxygen, thereby affecting the flow rate and uniformity of oxygen used by the lower wafer to grow the second gate oxide layer, solving the problem of reduced oxygen flow rate and uniformity when growing the gate oxide layer in the lower wafer in the prior art, ensuring the thickness of the gate oxide layer generated by the lower wafer, improving the basic performance and stability of the device, and thus improving the yield of the device.

[0078] In summary, the gate oxide layer growth method, semiconductor device preparation method and semiconductor device provided in the embodiments of the present application are achieved by forming a first gate oxide layer on the high-voltage well region and the low-voltage well region of the substrate; forming a floating gate layer on the first gate oxide layer corresponding to the high-voltage well region; forming an ONO structural film layer on the floating gate layer; etching the first gate oxide layer on the low-voltage well region of the substrate and the first silicon oxide film layer deposited on the back side of the substrate when forming the ONO structural film layer; etching the silicon nitride film layer and the second silicon oxide film layer deposited on the back side of the substrate when forming the ONO structural film layer; and forming a second gate oxide layer on the low-voltage well region of the substrate through a thermal diffusion growth process. Through the above technical means, before growing the second gate oxide layer, the first silicon oxide film layer, the silicon nitride film layer and the second silicon oxide film layer deposited on the back of the wafer during the ONO structure film layer formation process can be removed, so that when the second gate oxide layer is grown on multiple stacked wafers at the same time through the furnace tube process, the problem of silicon nitride material and silicon oxide material on the back of the upper wafer consuming oxygen on the front of the lower wafer will not occur. The front of the lower wafer has sufficient and uniform oxygen to generate a second gate oxide layer with a larger thickness and uniform thickness, thereby improving the basic performance and stability of the device, thereby improving the yield of the device.

[0079] The above are only preferred embodiments of the present application and the technical principles used. The present application is not limited to the specific embodiments herein, and various obvious changes, readjustments and substitutions that can be made by those skilled in the art will not deviate from the protection scope of the present application. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A gate oxide layer growth method, characterized in that: include: forming a first gate oxide layer on the high-voltage well region and the low-voltage well region of the substrate; forming a floating gate layer on the first gate oxide layer corresponding to the high-voltage well region; forming an ONO structure film layer on the floating gate layer; Etching a first gate oxide layer on the low-voltage well region of the substrate and a first silicon oxide film layer deposited on the back side of the substrate when forming the ONO structure film layer; The silicon nitride film layer and the second silicon oxide film layer deposited on the back side of the substrate when etching to form the ONO structure film layer; A second gate oxide layer is formed on the low voltage well region of the substrate by a thermal diffusion growth process.

2. The gate oxide layer growth method according to claim 1, characterized in that: Forming a floating gate layer on the first gate oxide layer corresponding to the high-voltage well region, comprising: Depositing polysilicon material on the front and back sides of the substrate by a furnace process; The polysilicon material deposited on the front side of the substrate is etched so that the polysilicon material remaining on the first gate oxide layer corresponding to the high-voltage well region forms a floating gate layer.

3. The gate oxide layer growth method according to claim 2, characterized in that: The thickness of the polysilicon material deposited on the back side of the substrate is greater than 300 nm, and the etching transmittance of the polysilicon material deposited on the front side of the substrate is greater than 75%.

4. The gate oxide layer growth method according to claim 1, characterized in that: Before forming the first gate oxide layer on the high-voltage well region and the low-voltage well region of the substrate, the method further includes: forming a high-voltage well region and a low-voltage well region in the substrate by an ion implantation process; A shallow trench isolation channel is etched between the high-voltage well region and the low-voltage well region, and silicon oxide is deposited in the shallow trench isolation channel.

5. The gate oxide layer growth method according to claim 1, characterized in that: The step of forming a first gate oxide layer on the high-voltage well region and the low-voltage well region of the substrate comprises: Silicon oxide is deposited on the high-voltage well region and the low-voltage well region of the substrate through a furnace process to form a first gate oxide layer, and silicon oxide is deposited on the back side of the substrate to form an oxide layer.

6. The gate oxide layer growth method according to claim 1, characterized in that: The forming of an ONO structure film layer on the floating gate layer comprises: Depositing silicon oxide material, silicon nitride material and silicon oxide material in sequence on the front and back sides of the substrate by a furnace tube process to form a second silicon oxide film layer, a silicon nitride film layer and a first silicon oxide film layer from outside to inside on the front and back sides of the substrate; The second silicon oxide film layer, the silicon nitride film layer and the first silicon oxide film layer on the front side of the substrate are etched so that the second silicon oxide film layer, the silicon nitride film layer and the first silicon oxide film layer remaining on the floating gate layer form an ONO structure film layer.

7. The gate oxide layer growth method according to claim 1, characterized in that: The etching of the first gate oxide layer on the low-voltage well region of the substrate and the first silicon oxide film layer deposited on the back side of the substrate when forming the ONO structure film layer comprises: Coating a layer of photoresist on the front side of the substrate; Developing the photoresist on the first gate oxide layer on the low voltage well region to expose the first gate oxide layer on the low voltage well region; Etching the first gate oxide layer on the low voltage well region and the first silicon oxide film layer on the back side of the substrate by means of a hydrofluoric acid solution; The remaining photoresist on the front side of the substrate is removed.

8. The gate oxide layer growth method according to claim 1, characterized in that: The silicon nitride film layer and the second silicon oxide film layer deposited on the back side of the substrate when etching to form the ONO structure film layer include: The silicon nitride film layer and the second silicon oxide film layer on the back side of the substrate are etched by a hydrofluoric acid solution.

9. A method for preparing a semiconductor device, characterized in that: The method comprises a gate oxide layer growth method as described in any one of claims 1 to 8.

10. A semiconductor device, characterized in that: The semiconductor device is prepared using the method for preparing the semiconductor device as claimed in claim 9.

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