Ga2O3 field effect transistor based on heterojunction hole super injection and preparation method thereof

Abstract

The invention discloses a gallium oxide field effect transistor based on heterojunction hole super injection and a preparation method of the gallium oxide field effect transistor. The problem that the current density of a gallium oxide field effect transistor is small is solved. A P-type heterostructure region is additionally arranged, a Ga2O3 epitaxial layer channel and source metal are arranged on a Ga2O3 substrate, and the P-type heterostructure region is arranged at the two ends of the Ga2O3 epitaxial layer channel; and the P-type heterogeneous material region and the Ga2O3 epitaxial layer channel form a heterogeneous PN junction. The method comprises pretreatment; etching a table board; growing source electrode metal; ohmic annealing; growing a drain heterojunction and an electrode material; gate dielectric preparation and trepanning are carried out; and growing gate metal. A P-type heterogeneous material and a channel form a heterojunction, and drain metal and the P-type heterogeneous material adopt a self-alignment process; a p-type NiO material is used as a replacement of a p-type gallium oxide material, and the reverse breakdown voltage is improved and the forward on-resistance is reduced by utilizing the hole super injection effect of p-NiO and n-Ga2O3. The method can be used for power electronic equipment such as an inverter with the working voltage larger than 5V.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and mainly relates to a field effect transistor, in particular to a Ga2O3 field effect transistor based on heterojunction hole superinjection and a preparation method thereof, which can be used in power electronic equipment such as inverters. Technical Background

[0002] As an emerging ultra-wide bandgap semiconductor material, Ga2O3 has a bandgap width of 4.5-4.9eV and a critical breakdown field strength of about 8MV / cm. Its theoretical power can reach more than twice that of SiC and GaN. And due to its relatively low crystal price and extremely superior thermal stability, it is one of the most popular and important materials in the field of power semiconductor devices.

[0003] For a power device, the power figure of merit P-FOM is often used to evaluate the comprehensive level of the device under power application; the two most important indicators considered in the power figure of merit are the characteristic on-resistance R on,sp and breakdown voltage BV. Thanks to the ultra-wide bandgap and high critical breakdown field strength of Ga2O3, as well as the researchers' optimized design of the device field plate and terminal structure, the breakdown voltage of Ga2O3 field effect transistors has reached an extremely high level. At present, Ga2O3 transistors with a breakdown voltage exceeding 10kV have been designed and realized, thereby achieving ultra-high power merit. However, the forward conduction performance is worthy of attention. The difficulty in increasing the current density will distort the high power merit brought by the ultra-high withstand voltage in the actual power performance in practical applications.

[0004] Unlike breakdown voltage, which can be easily improved by designing device size, building field plates, etc., the characteristic on-resistance is often limited by the material's own properties. The existing methods for modulating the on-resistance of transistors are very limited. The resistance of transistor devices generally considers two major parts: source-drain ohmic resistance and channel resistance. The general idea is to reduce the ohmic contact resistance of the transistor source and drain through various experimental means, or to reduce the resistance of these two parts separately by designing the channel width-to-length ratio, etc., to achieve a reduction in the overall resistance level. Generally speaking, the obstacles that hinder further improvement of current density are the channel mobility level and channel scattering, as well as the channel carrier density. When the material is stable, it is difficult for general design methods to affect these factors.

[0005] In summary, Ga2O3 field-effect transistors face the huge obstacle of reducing the characteristic on-resistance. The inherent channel mobility level and channel scattering effect of gallium oxide materials hinder the further improvement of current density. The overall level of the device is difficult to reach the limit of Ga2O3 transistors. Summary of the invention

[0006] The purpose of the present invention is to address the difficulty in improving the current density of the gallium oxide field effect transistor mentioned above, and to propose a Ga2O3 field effect transistor based on heterojunction hole superinjection with improved current density, thereby improving the practicability of the device.

[0007] The invention discloses a Ga2O3 field effect transistor based on heterojunction hole super injection. The structure of the Ga2O3 field effect transistor comprises: a Ga2O3 substrate, a Ga2O3 epitaxial layer channel, a source metal, a drain metal, a gate dielectric and a gate metal. The invention is characterized in that the Ga2O3 field effect transistor also comprises a P-type heterostructure region. The overall structure is as follows: the Ga2O3 substrate is used as the base of the device, and a Ga2O3 epitaxial layer channel is arranged thereon; the source metal and the P-type heterogeneous material region are respectively arranged at two ends above the Ga2O3 epitaxial layer channel, the drain metal is arranged just above the P-type heterogeneous material region, the lower surface of the drain metal forms an ohmic contact with the material of the P-type heterojunction region, the gate dielectric is arranged between the P-type heterogeneous material region and the source metal, and the gate metal is arranged above the gate dielectric; the P-type heterogeneous material region forms a heterogeneous PN junction with the upper surface of the Ga2O3 epitaxial layer channel, and the Ga2O3 field effect transistor based on heterojunction hole super injection with a large current density is constituted as a whole.

[0008] The present invention is also a method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection, which is carried out for any Ga2O3 field effect transistor based on heterojunction hole superinjection according to claims 1 to 6, and is characterized in that after the same step of photolithography masking, two layers of materials, a P-type heterogeneous material region and a drain metal, are grown in sequence to achieve a self-alignment process of the P-type heterogeneous material region and the drain metal, and the specific preparation process includes the following steps:

[0009] Step 1: Sample selection and pretreatment: Use Ga2O3 homogeneous epitaxial wafers, wash with acetone, isopropanol and deionized water respectively, and blow dry with nitrogen;

[0010] Step 2: Mesa etching: Etching the epitaxial wafer to form a mesa of a channel and source and drain metals, and the mesa retains the main part of a MOSFET such as source and drain;

[0011] Step 3: Source metal growth: mask the sample and perform photolithography, then grow the source metal; Step 4: Ohmic annealing: anneal the sample after the source metal is grown to form an ohmic contact;

[0012] Step 5: Growth of drain heterojunction and electrode materials: After using a thick photoresist AZ 4620 mask above the Ga2O3 epitaxial layer channel, a hole is photolithographically opened on the side of the Ga2O3 epitaxial layer channel where the source metal is not grown, and a heterojunction material is grown by magnetron sputtering; after the growth of the P-type heterogeneous material area is completed, the photoresist is not stripped off, and a layer of drain metal forming an ohmic contact is continued to grow above the P-type heterogeneous material area, and then the sample with the completed P-type heterogeneous material area and the overall structure of the drain metal is stripped off to complete the growth of the drain heterojunction and electrode materials;

[0013] Step 6: Preparation and opening of gate dielectric: Grow gate dielectric material on the entire sample that has completed the above steps; then perform photolithography opening on the upper surface of the source metal and the drain metal, and open holes in the grown dielectric material by using a semiconductor dielectric etcher RIE to expose the source and drain metal;

[0014] Step 7: Growth of gate metal: Finally, use a photoresist mask to photolithographically grow gate metal on the side of the middle of the channel near the source above the gate dielectric layer, and then peel off to complete the device manufacturing.

[0015] The present invention provides a new technical means to solve the problem of low current density. In the prior art, gallium oxide field effect transistors do not have the means to regulate carrier density through homogeneous pn junctions. The present invention uses p-type NiO material as a substitute for p-type gallium oxide material, and utilizes the hole superinjection effect generated in the heterojunction formed by p-NiO and n-Ga2O3 to significantly increase the reverse breakdown voltage and reduce the forward on-resistance.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] Effectively reduce the characteristic on-resistance: The present invention utilizes the hole superinjection phenomenon found in Ga2O3 heterojunction diodes. Under a certain voltage level, the conductivity modulation effect produced by the participation of minority carriers in conduction can effectively increase the current density in the channel and reduce the characteristic on-resistance of the field effect transistor.

[0018] Reducing static loss and improving device reliability: The present invention introduces a pn junction gate control structure into the MOSFET to form an enhanced gallium oxide device, so that when the gate voltage is in a zero bias state, the device is in an off state, thereby reducing the static loss of the device and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1This is a schematic diagram of the structure of the gallium oxide field effect transistor based on drain heterojunction hole superinjection of the present invention. In the figure, 1 is the Ga2O3 substrate, 2 is the Ga2O3 epitaxial layer channel, 3 is the source metal, 4 is the heterojunction region above the channel below the drain electrode that can form a heterojunction with Ga2O3, 5 is the drain metal, 6 is the gate dielectric, and 7 is the gate metal.

[0020] Figure 2 This is a specific embodiment of a vertical device of the present invention, and its principle is the same as that of a horizontal device. In the figure, 1 is a Ga2O3 substrate, 2 is a Ga2O3 epitaxial layer channel, 3 is a source metal, 4 is a heterojunction region above the channel below the drain electrode that can form a heterojunction with Ga2O3, 5 is a drain metal, 6 is a gate dielectric, and 7 is a gate metal.

[0021] Figure 3 This is a process flow chart of the present invention. In the figure, (a) is a gallium oxide substrate with a homoepitaxial layer; (b) is the table etching to obtain the source and drain table and the channel area; (c) is the growth of the source metal; (d) is the growth of the heterojunction area; (e) is the growth of the drain area; (f) is the growth of the gate dielectric and the construction of the gate.

[0022] Figure 4 The present invention is a flowchart of the preparation method. Specific implementation plan

[0023] Embodiment 1:

[0024] In the prior art, gallium oxide field effect transistors do not have a means to regulate carrier density through a pn junction, and it is difficult to increase the current density of the gallium oxide field effect transistor channel. To address these problems, the present invention proposes a Ga2O3 field effect transistor based on heterojunction hole superinjection through research and experiments.

[0025] The present invention is a Ga2O3 field effect transistor based on heterojunction hole super injection. Aiming at the difficulty of improving the current density of the gallium oxide field effect transistor, the present invention proposes a structure including: Ga2O3 substrate, Ga2O3 epitaxial layer channel, source metal, drain metal, gate dielectric, and gate metal. Figure 1 , Figure 1This is a schematic diagram of the structure of the gallium oxide field effect transistor based on drain heterojunction hole superinjection of the present invention. The present invention also includes a P-type heterostructure region 4, using p-type NiO material as a substitute for p-type gallium oxide material, and utilizing the hole superinjection effect generated in the heterojunction formed by p-NiO and n-Ga2O3 to significantly increase the reverse breakdown voltage and reduce the forward on-resistance. The overall structure of the present invention is as follows: a Ga2O3 substrate 1 is used as the substrate of the device, on which a Ga2O3 epitaxial layer channel 2 is provided, and a source metal 3, a gate dielectric 6 and a P-type heterogeneous material region 4 are arranged on the upper surface of the Ga2O3 epitaxial layer channel 2, a drain metal 5 is provided on the P-type heterogeneous material region 4, and a gate metal 7 is provided on the gate dielectric 6; the source metal 3 and the P-type heterogeneous material region 4 are respectively arranged at both ends above the Ga2O3 epitaxial layer channel 2, the drain metal 5 is arranged directly above the P-type heterogeneous material region 4, and the drain metal 5 is arranged directly above the P-type heterogeneous material region 4. 5 forms an ohmic contact with the material of the P-type heterojunction region 4, the gate dielectric 6 is arranged between the P-type heterogeneous material region 4 and the source metal 3, and the gate metal 7 is arranged above the gate dielectric 6; the P-type heterogeneous material region 4 arranged below the drain metal 5 forms a heterogeneous PN junction with the upper surface of the Ga2O3 epitaxial layer channel 2, and the whole constitutes a Ga2O3 field effect transistor based on heterojunction hole super injection with a large current density, which effectively reduces the characteristic on-resistance, reduces the static loss, and improves the device reliability.

[0026] The present invention is an overall technical solution. The present invention introduces a P-type heterogeneous material region 4 which is arranged on the Ga2O3 epitaxial layer channel 2 to form a heterogeneous PN junction with the upper surface of the Ga2O3 epitaxial layer channel 2.

[0027] The present invention uses p-NiO as a substitute for p-type gallium oxide material to form a heterojunction with n-Ga2O3, and utilizes the conductivity modulation effect in the n-Ga2O3 / p-NiO heterojunction. When forward biased, the hole barrier is lowered, and the holes in the p-region jump over the PN heterojunction into the n-region. When the hole concentration is higher than the electron concentration, the electron concentration is induced to increase, thereby reducing the on-resistance.

[0028] Embodiment 2:

[0029] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection is the same as that of Example 1. The Ga2O3 epitaxial layer channel 2 of the present invention is based on the Ga2O3 homoepitaxial material grown by hydride vapor phase epitaxy HVPE high temperature. The thickness of the Ga2O3 epitaxial layer is 200nm-800nm; the doping concentration of the Ga2O3 epitaxial layer is 1×10 15 cm -3 -1×10 18 cm -3 .

[0030] The thickness of the Ga2O3 epitaxial layer in the present invention is given in the range of 200nm-800nm. In practical applications, the thickness range can be adjusted according to the actual application situation. The purpose is to select an epitaxial layer with a suitable thickness so that the etching process can etch the epitaxial layer through the substrate to obtain a mesa conductive channel. As long as the mesa etching depth is greater than the epitaxial layer thickness, the isolation of the device is guaranteed. When the etching depth is 200nm, the thickness of the Ga2O3 epitaxial layer can be 300nm, and when the etching depth is 900nm, the thickness of the Ga2O3 epitaxial layer can be 800nm;

[0031] In the present invention, the doping concentration of the Ga2O3 epitaxial layer is 1×10 15 cm -3 -1×10 18 cm -3 In practical applications, it can be adjusted according to the actual application situation, and different current levels and withstand voltage conditions can be measured and adjusted specifically to ensure that it is turned on under the applied bias. For example, when the design standard of a device is a blocking withstand voltage BV of 1.5kV, the doping concentration of the epitaxial layer can be 1×10 15 cm -3 The design standard of the device is that the doping concentration of the epitaxial layer can be 1×10 18 cm -3

[0032] This example shows that the production method of the epitaxial layer of the present invention is Ga2O3 homoepitaxial material grown at high temperature by HVPE. Its advantage is that during the device preparation process, the epitaxial layer grown at high temperature by HVPE can maintain stable performance during the annealing process.

[0033] Embodiment 3:

[0034] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection is the same as that of Examples 1-2. The material of the P-type heterojunction region 4 of the present invention is either nickel oxide P-type semiconductor material or chromium oxide P-type semiconductor material, that is, nickel oxide or chromium oxide P-type semiconductor material.

[0035] This embodiment forms a heterojunction with an n-type gallium oxide material by introducing one of a p-type NiO film and a p-type CrO2 film. The main advantage is that a significant hole superinjection effect is generated by forming a heterojunction with the n-type gallium oxide material through the semiconductor heterogeneous material, thereby improving the withstand voltage of the current Ga2O3 field effect transistor and significantly reducing the on-resistance.

[0036] Embodiment 4:

[0037] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection is the same as that of Examples 1-3. The metal material used for the drain metal 5 is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum. The drain metal 5 forms an ohmic contact with the material of the P-type heterojunction region 4.

[0038] In this example, multiple choices of drain metal 5 are given. Different metal materials can be selected to form ohmic contact with different P-type heterojunction region 4 materials, thereby ensuring stable output characteristics of the Ga2O3 field effect tube.

[0039] Embodiment 5:

[0040] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection is the same as that of Examples 1-4. The metal material used for the source metal 3 is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum. The source metal 3 forms an ohmic contact with the Ga2O3 epitaxial layer channel 2; the metal material used for the gate metal 7 is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum.

[0041] In this example, multiple options for source metal 3 and gate metal 7 are provided to ensure stable output characteristics of the Ga2O3 field effect transistor. The advantage is that a well-contacted source electrode can reduce contact resistance, further achieving the purpose of reducing the overall resistance level.

[0042] Embodiment 6:

[0043] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection is the same as that of Example 1. The material of the gate dielectric 6 is one or more of aluminum oxide, silicon oxide, and hafnium oxide. The thickness of the gate dielectric 6 is 15nm-20nm.

[0044] The present invention introduces one or more of aluminum oxide, silicon oxide, and hafnium oxide as gate dielectric materials. In a general scheme, one or more of them can be used. The present invention provides a gate dielectric thickness of 15nm-20nm, which can be specifically adjusted according to the design standards during actual implementation. When the designed subthreshold swing is 120 / dec, the gate dielectric thickness can be 20nm; when the designed subthreshold swing is 100 / dec, the gate dielectric thickness can be 15nm.

[0045] Its advantages include high dielectric constant of the material, which can reduce the thickness of the dielectric material to improve the gate control capability; during the process, RIE dielectric etching can be used to open holes, and the process cost is low.

[0046] Embodiment 7:

[0047] The present invention is also a method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection, which is carried out for any Ga2O3 field effect transistor based on heterojunction hole superinjection of Examples 1-6. After the same photolithography mask, two layers of materials, a P-type heterogeneous material region 4 and a drain metal 5, are grown in sequence to achieve a self-alignment process of the P-type heterogeneous material region 4 and the drain metal 5. The specific preparation process includes the following steps:

[0048] Step 1: Sample selection and pretreatment: Use Ga2O3 homogeneous epitaxial wafers, clean them with acetone, isopropanol and deionized water respectively, and blow dry them with nitrogen.

[0049] Step 2: Mesa etching: Etch the epitaxial wafer to form a mesa of the channel and source and drain metals. The mesa retains the main part of a MOSFET such as the source and drain.

[0050] Step 3: Source metal growth: After masking the above sample, perform photolithography and then grow the source metal.

[0051] Step 4: Ohmic annealing: Anneal the sample after growing the source metal to form an ohmic contact.

[0052] Step 5: Growth of drain heterojunction and electrode materials: After using a thick photoresist AZ 4620 mask above the Ga2O3 epitaxial layer channel, a hole is photolithographically opened on the side of the Ga2O3 epitaxial layer channel where the source metal is not grown, and the heterojunction material is grown by magnetron sputtering; after the growth of the P-type heterogeneous material area is completed, the photoresist is not stripped off, and a layer of drain metal forming an ohmic contact is continued to grow above the P-type heterogeneous material area, and then the sample with the completed P-type heterogeneous material area and the overall structure of the drain metal is stripped off to complete the growth of the drain heterojunction and electrode materials.

[0053] Step 6: Preparation and opening of gate dielectric: Grow gate dielectric material on the entire sample that has completed the above steps; then perform photolithography openings on the upper surfaces of the source metal and the drain metal, and use a semiconductor dielectric etcher RIE to open holes in the grown dielectric material to expose the source and drain metals.

[0054] Step 7: Growth of gate metal: Finally, use a photoresist mask to photolithographically grow gate metal on the side of the middle of the channel near the source above the gate dielectric layer, and then peel off to complete the device manufacturing.

[0055] The present invention is an overall technical solution. On the basis of Ga2O3 field effect tube, thick photoresist AZ 4620 photolithography is used. After the growth of P-type heterogeneous material area is completed, the photoresist is not stripped, and a layer of drain metal forming ohmic contact is continued to grow above the P-type heterogeneous material area. Then, the sample with the completed P-type heterogeneous material area and drain metal overall structure is stripped.

[0056] Its advantage is that the growth of the P-type heterogeneous material area and the drain metal uses the same self-alignment process of photolithography, ensuring that the edge of the drain metal perfectly covers the edge of the P-type heterogeneous material area, reducing process errors, ensuring that the drain current is regulated by the heterojunction, and increasing the current density.

[0057] Embodiment 8:

[0058] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection and the preparation method thereof is the same as that of Example 7. Step 4, ohmic annealing is performed by using a rapid thermal annealing device RTA, and the process conditions are as follows:

[0059] Reaction chamber gas: N2;

[0060] Gas flow rate: 1200 sccm;

[0061] Cavity pressure: atmospheric pressure;

[0062] Annealing temperature: 475℃;

[0063] Annealing time: 60s.

[0064] The process conditions provided by the present invention can ensure, through experiments and verification, that the source metal and the gallium oxide channel form an ohmic contact with the minimum contact resistance and guarantee the carrier concentration of the epitaxial layer channel.

[0065] Embodiment 9:

[0066] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection and the preparation method thereof is the same as that of Examples 7-8. In step 5, the heterojunction region material is obtained by magnetron sputtering, and the process conditions are as follows:

[0067] Reaction chamber pressure: 10mTorr;

[0068] Ionization voltage: 1kV-3kV;

[0069] Reaction chamber gases: O2, N2, Ar.

[0070] The process conditions provided by the present invention can be used to prepare high-quality P-type heterogeneous material films through experiments and verification, and generate flat NiO films with a thickness of 100 nm and good surface roughness.

[0071] Embodiment 10:

[0072] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection is the same as that of Examples 1-9. In step 6, the gate dielectric is obtained by atomic layer deposition system ALD, which has a low interface fixed charge. The process conditions are as follows:

[0073] Reaction chamber pressure: 5Pa;

[0074] Reaction chamber gas: N2;

[0075] Gas flow rate: 300 sccm;

[0076] Growth rate: 0.15nm / cycle.

[0077] The process conditions provided by the present invention have been experimentally verified and it has been found that the above process conditions enable the present invention to deposit Al2O3 material with a low impurity concentration in a high-purity nitrogen environment. At a gas flow rate of 300sccm, an Al2O3 isolation layer with a smooth surface and a thickness of 20nm can be deposited after 40 minutes.

[0078] Embodiment 11:

[0079] The overall scheme of the Ga2O3 field effect transistor based on heterojunction hole superinjection and its preparation method is the same as that of Examples 1-10. A Ga2O3 homogeneous epitaxial wafer is used, the substrate is UID n-type β-Ga2O3, the thickness is 650μm; the epitaxial layer is Si-doped β-Ga2O3 film, the thickness is 500nm, and it is cleaned with acetone, isopropanol and deionized water respectively, and dried with nitrogen;

[0080] like Figure 3 As shown in (b), the above epitaxial wafer is masked and then etched using ICP etching technology, with an etching gas BCl3 / Ar flow ratio of 70:10, RF power of 300w, etching time of 5min, and etching depth of 800nm. The Ga2O3 epitaxial layer is etched through, leaving only the device mesa and epitaxial layer channel, and the channel width is 2um.

[0081] like Figure 3 As shown in (c), after the device photolithography mask is completed for the mesa etching, metal Ti / Au=60 / 150nm is evaporated in the source area by electron beam evaporation to serve as the source electrode; after stripping the photoresist, rapid thermal annealing is used with an annealing temperature of 475°C and an annealing time of 1 min to form an ohmic contact.

[0082] like Figure 3 As shown in (d), thick resist AZ6130 is used for photolithography, and then magnetron sputtering is used to grow a heterojunction in the drain region. In the present invention, the p-type material is NiO, and two layers with different doping concentrations are evaporated. The thickness and doping concentration of each layer are 60nm and 1×10 18 cm -3 The lower layer and a layer of 30nm, 1×10 19 cm -3 The upper layer of nickel oxide forms a specific heterojunction area.

[0083] After completion, Figure 3As shown in (e), the NiO grown sample is not peeled off first, and a layer of metal is evaporated on the same area by self-alignment process, and the metal type and thickness are Ni / Au=60 / 120nm. Then, it is peeled off by hot water bath NMP solution to complete the production of the sample drain area.

[0084] like Figure 3 As shown in (f), first grow a gate dielectric layer. The dielectric material and thickness used in this embodiment are Al2O3, 20nm, obtained by atomic layer deposition ALD, and the process temperature is 200℃. After the dielectric is grown, the source and drain areas of the sample are opened by wet etching to expose the source and drain metal electrodes; finally, the gate metal is grown after photolithography. The metal type is Ti / Au, the thickness is 60 / 150nm, and the gate-drain spacing L GD =5um, source-drain distance L GS =1.5um, gate width L G =2um. After peeling, the device is fabricated.

[0085] Embodiment 12:

[0086] This embodiment is a preparation process of a vertical gallium oxide field effect transistor based on heterojunction hole superinjection, and its structural schematic diagram is shown in FIG. Figure 2 As shown. A Ga2O3 substrate 1 is used as a base, and a Ga2O3 epitaxial layer channel 2 is covered thereon, a source metal 3 covers the lower surface of the Ga2O3 substrate 1, a P-type heterogeneous material region 4 is located directly above the Ga2O3 epitaxial layer channel 2, and forms a pn heterojunction therewith, and a drain metal 5 is located directly above the P-type heterogeneous material region 4. A gate dielectric 6 covers both ends of the step sidewall formed by the Ga2O3 epitaxial layer channel 2, the P-type heterogeneous material region 4, and the drain metal 5. A gate metal 7 is disposed above the gate dielectric 6, and at both ends of the step sidewall formed by the Ga2O3 epitaxial layer channel 2, the P-type heterogeneous material region 4, and the drain metal 5.

[0087] The preparation process includes:

[0088] First, a Ga2O3 homogeneous epitaxial wafer was used, the substrate was UID's n-type β-Ga2O3, with a thickness of 650μm; the epitaxial layer was Si-doped β-Ga2O3 film, with a thickness of 500nm, which was cleaned with acetone, isopropanol and deionized water respectively, and dried with nitrogen;

[0089] On the back side of the sample, metal Ti / Au=60 / 150nm was evaporated in the source region by electron beam evaporation to serve as the source electrode; then rapid thermal annealing was used with an annealing temperature of 475°C and an annealing time of 1 min to form a source ohmic contact.

[0090] The Ga2O3 epitaxial layer was etched by ICP method to form a Ga2O3 vertical channel, with the BCl3 / Ar flow ratio set to 70:10, RF power 300w, and etching time 50min. The height of the etched Ga2O3 vertical channel was 800nm ​​and the width was 600nm.

[0091] Photolithography, and then magnetron sputtering is used to grow a heterojunction in the drain region after etching. In the present invention, the p-type material is NiO, and two layers with different doping concentrations are evaporated, and their thickness and doping concentration are 60nm and 1×10 18 cm -3 The lower layer and a layer of 30nm, 1×10 19 cm -3 The upper layer of nickel oxide forms a specific heterojunction area.

[0092] After completion, the NiO-grown sample is not peeled off first, and a layer of metal is evaporated on the same area by self-alignment process, and the metal type and thickness are Ni / Au=60 / 120nm. Then, it is peeled off in a hot water bath NMP solution to complete the production of the sample drain area.

[0093] Grow the gate dielectric layer. The dielectric material and thickness used in this embodiment are HrO2, 20nm, obtained by atomic layer deposition ALD, and the process temperature is 200°C. After the dielectric is grown, the source and drain areas of the sample are opened by wet etching to expose the source and drain metal electrodes; finally, the gate metal is grown after photolithography, the metal type is Ti / Au, the thickness is 60 / 150nm, and the device is completed after peeling.

[0094] In summary, the present invention is a gallium oxide field effect transistor based on heterojunction hole superinjection and a preparation method thereof, which solves the problem that the gallium oxide field effect transistor in the prior art does not have a means to regulate the carrier density through the pn junction. The present invention uses p-type NiO material as a substitute for p-type gallium oxide material, and utilizes the hole superinjection effect generated in the heterojunction formed by p-NiO and n-Ga2O3, thereby significantly improving the reverse breakdown voltage and reducing the forward on-resistance. The invention discloses a Ga2O3 field effect transistor based on heterojunction hole superinjection, and the structure thereof comprises: a Ga2O3 substrate, a Ga2O3 epitaxial layer channel, a source metal, a drain metal, a gate dielectric, and a gate metal, and is characterized in that it also comprises a P-type heterostructure region; the overall structure thereof is: the Ga2O3 substrate is used as the base of the device, and a Ga2O3 epitaxial layer channel is arranged thereon; the source metal and the P-type heterogeneous material region are respectively arranged at two ends above the Ga2O3 epitaxial layer channel, the drain metal is arranged just above the P-type heterogeneous material region, the lower surface of the drain metal forms an ohmic contact with the material of the P-type heterojunction region, the gate dielectric is arranged between the P-type heterogeneous material region and the source metal, and the gate metal is arranged above the gate dielectric; the P-type heterogeneous material region forms a heterogeneous PN junction with the upper surface of the Ga2O3 epitaxial layer channel, and the whole constitutes a Ga2O3 field effect transistor based on heterojunction hole superinjection with a large current density. The preparation method of the present method includes: sample selection and pretreatment; table etching; source metal growth; ohmic annealing; drain heterojunction and electrode material growth; gate dielectric preparation and opening; gate metal growth. The innovation of the present invention is that a P-type heterogeneous material is arranged on one side of the channel to form a heterojunction with the channel, and the growth of the drain metal and the growth of the P-type heterogeneous material adopt a self-aligned process. Its advantage is that the hole superinjection effect generated in the heterojunction formed by p-NiO and n-Ga2O3 is utilized to significantly increase the reverse breakdown voltage and reduce the forward on-resistance. The self-aligned process ensures that the edge of the drain metal perfectly covers the edge of the P-type heterogeneous material area, reduces the process error, ensures that the drain current is regulated by the heterojunction, and increases the current density. It can be used for power electronic equipment such as inverters with a drain operating voltage greater than 5V.

Claims

1. A Ga2O3 field effect transistor based on heterojunction hole superinjection, the structure of which includes: a Ga2O3 substrate, a Ga2O3 epitaxial layer channel, a source metal, a drain metal, a gate dielectric, and a gate metal, characterized in that: It also includes a P-type heterostructure area; its overall structure is: a Ga2O3 substrate is used as the base of the device, and a Ga2O3 epitaxial layer channel is arranged on it; the source metal and the P-type heterogeneous material area are respectively arranged at the two ends above the Ga2O3 epitaxial layer channel, the drain metal is arranged directly above the P-type heterogeneous material area, the lower surface of the drain metal forms an ohmic contact with the material of the P-type heterojunction area, the gate dielectric is arranged between the P-type heterogeneous material area and the source metal, and the gate metal is arranged above the gate dielectric; the P-type heterogeneous material area forms a heterogeneous PN junction with the upper surface of the Ga2O3 epitaxial layer channel, and the whole constitutes a Ga2O3 field effect transistor based on heterojunction hole superinjection with a large current density.

2. The Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 1, characterized in that: The Ga2O3 epitaxial layer channel is based on the Ga2O3 homoepitaxial material grown by hydride vapor phase epitaxy (HVPE) at high temperature. The thickness of the Ga2O3 epitaxial layer is 200nm-800nm. The doping concentration of the Ga2O3 epitaxial layer is 1×10 15 cm -3 -1×10 18 cm -3 .

3. The Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 1, characterized in that: The material of the P-type heterojunction region is either nickel oxide P-type semiconductor material or chromium oxide P-type semiconductor material.

4. The Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 1, characterized in that: The metal material used for the drain metal is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum, and the drain metal forms an ohmic contact with the material of the P-type heterojunction region.

5. The Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 1, characterized in that: The metal material used for the source metal is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum, and the source metal forms an ohmic contact with the Ga2O3 epitaxial layer channel; the metal material used for the gate metal is one or more of titanium, aluminum, nickel, gold, platinum, iridium, and molybdenum.

6. The Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 1, characterized in that: The material of the gate dielectric is one or more of aluminum oxide, silicon oxide, and hafnium oxide, and the thickness of the gate dielectric is 15nm-20nm.

7. A method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection, which is carried out for any Ga2O3 field effect transistor based on heterojunction hole superinjection according to any one of claims 1 to 6, characterized in that: After the photolithography mask is formed in the same step, two layers of materials, a P-type heterogeneous material region and a drain metal, are grown in sequence to realize a self-alignment process of the P-type heterogeneous material region and the drain metal. The specific preparation process includes the following steps: Step 1: Sample selection and pretreatment: Use Ga2O3 homogeneous epitaxial wafers, wash with acetone, isopropanol and deionized water respectively, and blow dry with nitrogen; Step 2: Mesa etching: Etching the epitaxial wafer to form a mesa of a channel and source and drain metals, and the mesa retains the main part of a MOSFET such as source and drain; Step 3: Source metal growth: mask the sample and perform photolithography, then grow the source metal; Step 4: Ohmic annealing: anneal the sample after the source metal is grown to form an ohmic contact; Step 5: Growth of drain heterojunction and electrode materials: After using a thick photoresist AZ 4620 mask above the Ga2O3 epitaxial layer channel, a hole is photolithographically opened on the side of the Ga2O3 epitaxial layer channel where the source metal is not grown, and a heterojunction material is grown by magnetron sputtering; after the growth of the P-type heterogeneous material area is completed, the photoresist is not stripped off, and a layer of drain metal forming an ohmic contact is continued to grow above the P-type heterogeneous material area, and then the sample with the completed P-type heterogeneous material area and the overall structure of the drain metal is stripped off to complete the growth of the drain heterojunction and electrode materials; Step 6: Preparation and opening of gate dielectric: Grow gate dielectric material on the entire sample that has completed the above steps; then perform photolithography opening on the upper surface of the source metal and the drain metal, and open holes in the grown dielectric material by using a semiconductor dielectric etcher RIE to expose the source and drain metal; Step 7: Growth of gate metal: Finally, use a photoresist mask to photolithographically grow gate metal on the side of the middle of the channel near the source above the gate dielectric layer, and then peel off to complete the device manufacturing.

8. The method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 7, characterized in that: Step 4: Ohmic annealing is performed using a rapid thermal annealing device (RTA), and the process conditions are as follows: Reaction chamber gas: N2; Gas flow rate: 1200 sccm; Cavity pressure: atmospheric pressure; Annealing temperature: 475℃; Annealing time: 60s.

9. The method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 7, characterized in that: In step 5, the heterojunction region material is obtained by magnetron sputtering, and the process conditions are as follows: Reaction chamber pressure: 10mTorr; Ionization voltage: 1kV-3kV; Reaction chamber gases: O2, N2, Ar.

10. The method for preparing a Ga2O3 field effect transistor based on heterojunction hole superinjection according to claim 7, characterized in that: In step 6, the gate dielectric is obtained by using an atomic layer deposition system ALD, which has a low interface fixed charge. The process conditions are as follows: Reaction chamber pressure: 5Pa; Reaction chamber gas: N2; Gas flow rate: 300 sccm; Growth rate: 0.15nm / cycle.

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