Method for forming a semiconductor device

Abstract

The present invention provides a method for forming a semiconductor device. The pad oxide layer in the source region and the drain region of the high voltage region is removed while the pad oxide layer in the medium voltage region is removed, but the pad oxide layer residue is not removed when etching the second gate oxide layer, thereby removing the pad oxide layer with a bird's beak defect, that is, no residual pad oxide layer exists in the source region and the drain region of the high voltage region in the subsequent etching to form a gate structure, so that the metal silicide layer subsequently formed on the semiconductor substrate in the source region and the drain region of the high voltage region is not affected, and the contact between the plug formed in the source region and the drain region of the high voltage region and the substrate is not affected, so that the electrical properties and reliability of the high voltage device are not affected.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor device. Background Art

[0002] In the high-voltage device process at the 28nm technology node, such as Figure 1 As shown, after the gate region G (i.e., gate oxide region) of the high voltage device region HV is opened, when the first gate oxide layer 12 is formed, water vapor at high temperature passes through the interface between the STI (shallow trench isolation structure) at the opening wall and other material layers and enters the silicon substrate 10 of the source region S and the drain region D, and reacts with the silicon substrate 10 to increase the thickness of the pad oxide layer 11 of the source region S and the drain region D, especially in the source region S and the drain region D on one side of the region close to the first gate oxide layer 12. The bird's beak-shaped pad oxide layer 12 (as shown in FIG. Figure 2 As shown in FIG. 1 ), the bird's beak-shaped pad oxide layer 12 cannot be completely removed (as shown in FIG. 1 ). Figure 3 As shown in the figure, it affects the metal silicide layer subsequently formed on the silicon substrate 10 of the source region S and the drain region D, and also affects the contact between the plugs subsequently formed on the source region S and the drain region D and the silicon substrate, thereby affecting the electrical properties and reliability of the high-voltage device. Summary of the invention

[0003] The object of the present invention is to provide a method for forming a semiconductor device, which can solve the defect of a bird's beak-shaped pad oxide layer.

[0004] In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the following steps:

[0005] A semiconductor substrate is provided, wherein the semiconductor substrate has a high-voltage region and a medium-voltage region arranged adjacent to each other, the high-voltage region includes a gate region, a source region and a drain region, the gate region is arranged between the source region and the drain region, a first gate oxide layer is arranged on the semiconductor substrate of the gate region, a pad oxide layer is arranged on the semiconductor substrate of the source region, the drain region and the medium-voltage region, and the pad oxide layer of the source region and the pad oxide layer of the drain region have a bird's beak defect on a side close to the first gate oxide layer;

[0006] Sequentially removing the pad oxide layers of the medium voltage region, the source region and the drain region of the high voltage region;

[0007] forming a second gate oxide layer and a polysilicon film layer in sequence on the semiconductor substrate in the medium voltage region, wherein a portion of the second gate oxide layer also covers the semiconductor substrate in the source region and the drain region of the high voltage region, and the first gate oxide layer, and the polysilicon film layer covers the second gate oxide layer;

[0008] The polysilicon film layer and the second gate oxide layer are sequentially etched to form a high-voltage gate structure in the gate region and a medium-voltage gate structure in the medium-voltage region.

[0009] Optionally, the method for forming the pad oxide layer having a bird's beak defect is:

[0010] A semiconductor substrate is provided, wherein the high voltage region and the medium voltage region are isolated by a shallow trench isolation structure, and the gate region and the source region, and the gate region and the drain region are isolated by a shallow trench isolation structure;

[0011] Sequentially forming a pad oxide layer and a first silicon nitride layer on the semiconductor substrate in the high voltage region and the medium voltage region, wherein the first silicon nitride layer also covers the shallow trench isolation structure and the pad oxide layer;

[0012] Etching the first silicon nitride layer by a dry etching process to form an opening in the gate region, wherein the opening exposes the semiconductor substrate of the gate region;

[0013] Depositing a first gate oxide layer in the semiconductor substrate in the gate region;

[0014] The first silicon nitride layer is removed by a wet etching process to expose the pad oxide layer.

[0015] Optionally, the method of sequentially removing the pad oxide layers of the medium voltage region, the source region, and the drain region of the high voltage region is:

[0016] forming a second silicon nitride layer on the pad oxide layer and the first gate oxide layer by a deposition process;

[0017] Etching the second silicon nitride layer, retaining the second silicon nitride layer in the gate region, and exposing the pad oxide layer in the medium voltage region, the source region of the high voltage region, and the drain region;

[0018] The second silicon nitride layer in the gate region is removed by etching to expose the first gate oxide layer.

[0019] Furthermore, when the pad oxide layer is etched by a dry etching process, the etching selectivity ratio of the etching gas to oxide and silicon is greater than 10:1.

[0020] Furthermore, when the pad oxide layer is etched by a dry etching process, the etching selectivity ratio of the etching gas to oxide and silicon is greater than 5:1.

[0021] Furthermore, the method for forming the second gate oxide layer is:

[0022] Depositing a first oxide layer, wherein the first oxide layer covers the source region, the drain region of the high voltage region and the semiconductor substrate of the medium voltage region;

[0023] A second oxide layer is deposited, wherein the second oxide layer covers the first oxide layer and the first gate oxide layer, and also covers the shallow trench isolation structure, and the first oxide layer and the second oxide layer together constitute a second gate oxide layer.

[0024] Furthermore, the first oxide layer and the first gate oxide layer are both formed by an ISSG process.

[0025] Furthermore, the second oxide layer is a HTO layer.

[0026] Optionally, the method of forming the high voltage gate structure and the medium voltage gate structure is:

[0027] The polysilicon film layer, the second gate oxide layer and the first gate oxide layer are sequentially etched by a dry etching process in multiple steps to form a high-voltage polysilicon gate and a medium-voltage polysilicon gate, thereby forming a high-voltage gate structure and a medium-voltage gate structure, while also exposing the semiconductor substrate of the source region and the drain region of the high-voltage region, and the semiconductor substrate outside the medium-voltage gate structure in the medium-voltage region.

[0028] Furthermore, after forming the high voltage gate structure and the medium voltage gate structure, the method further includes:

[0029] Using the high-voltage gate structure and the medium-voltage gate structure as masks, a high-voltage source is formed in the source region of the high-voltage region, a high-voltage drain is formed in the drain region, and a medium-voltage source and a medium-voltage drain are formed in the semiconductor substrate on both sides of the medium-voltage gate structure through an ion implantation process.

[0030] Compared with the prior art, the present invention has the following unexpected technical effects:

[0031] The present invention provides a method for forming a semiconductor device, comprising the following steps: providing a semiconductor substrate, wherein the semiconductor substrate has a high-voltage region and a medium-voltage region arranged adjacent to each other, the high-voltage region comprising a gate region, a source region and a drain region, the gate region being arranged between the source region and the drain region, and a first gate oxide layer being arranged on the semiconductor substrate of the gate region, and a pad oxide layer being arranged on the semiconductor substrate of the source region, the drain region and the medium-voltage region, wherein the pad oxide layer of the source region and the pad oxide layer of the drain region have a bird's beak defect on a side close to the first gate oxide layer; sequentially removing the pad oxide layers of the medium-voltage region, the source region and the drain region of the high-voltage region; sequentially forming a second gate oxide layer and a polysilicon film layer on the semiconductor substrate of the medium-voltage region, wherein a part of the second gate oxide layer also covers the semiconductor substrate of the source region and the drain region of the high-voltage region, and the first gate oxide layer, and the polysilicon film layer covers the second gate oxide layer; sequentially etching the polysilicon film layer and the second gate oxide layer to form a high-voltage gate structure in the gate region and a medium-voltage gate structure in the medium-voltage region. The present invention removes the pad oxide layer with a bird's beak defect by removing the pad oxide layer in the source region and the drain region of the high voltage region while removing the pad oxide layer in the medium voltage region, rather than removing the pad oxide layer together when etching the second gate oxide layer to cause the pad oxide layer residue, that is, no residual pad oxide layer exists in the source region and the drain region of the high voltage region in the subsequent etching to form the gate structure, so that the metal silicide layer subsequently formed on the semiconductor substrate in the source region and the drain region of the high voltage region is not affected, and the contact between the plug formed subsequently on the source region and the drain region of the high voltage region and the substrate is not affected, so that the electrical properties and reliability of the high voltage device are not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure when a gate oxide layer is formed for a high-voltage semiconductor device.

[0033] Figure 2 for Figure 1 Schematic diagram of the structure of the bird's beak-shaped pad oxide layer in area A.

[0034] Figure 3 It is a schematic diagram of the structure of a high-voltage semiconductor device when etching to form a gate structure.

[0035] Figure 4 A schematic structural diagram of a semiconductor substrate provided in one embodiment of the present invention.

[0036] Figure 5 It is a schematic diagram of the structure after the opening is formed according to an embodiment of the present invention.

[0037] Figure 6 It is a schematic diagram of the structure after forming the first gate oxide layer according to an embodiment of the present invention.

[0038] Figure 7FIG. 4 is a schematic diagram of a structure after forming a second silicon nitride layer according to an embodiment of the present invention.

[0039] Figure 8 It is a schematic diagram of the structure after etching the second silicon nitride layer according to an embodiment of the present invention.

[0040] Fig. 9 It is a schematic diagram of the structure after forming the second gate oxide layer according to an embodiment of the present invention.

[0041] Fig.10 It is a schematic diagram of the structure after forming the gate oxide layer of the high voltage gate structure and the medium voltage gate structure according to one embodiment of the present invention.

[0042] Description of reference numerals:

[0043] Figure 1-Figure 3 Middle: 10-substrate; 11-pad oxide layer; 12-first gate oxide layer; S-source region; D-drain region; G-gate region;

[0044] Figure 4-Figure 10 middle:

[0045] I-high voltage region; I1-source region; I2-gate region; I3-drain region; II-medium voltage region;

[0046] 100 - semiconductor substrate; 101 - shallow trench isolation structure; 102 - opening; 110 - pad oxide layer; 120 - first silicon nitride layer; 130 - first gate oxide layer; 140 - second silicon nitride layer; 151 - first oxide layer; 152 - second oxide layer; 210 - high voltage polysilicon gate; 220 - medium voltage polysilicon gate. DETAILED DESCRIPTION

[0047] The following is a further detailed description of a method for forming a semiconductor device of the present invention. The present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0048] For the sake of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail because they would clutter the invention with unnecessary detail. It should be recognized that in the development of any actual embodiment, a large number of implementation details must be made to achieve the developer's specific goals, such as changing from one embodiment to another according to the limitations of the relevant system or the relevant business. In addition, it should be recognized that such development work may be complex and time-consuming, but it is just a routine task for those skilled in the art.

[0049] In order to make the purpose and features of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0050] This embodiment provides a method for forming a semiconductor device, comprising the following steps:

[0051] Step S1: providing a semiconductor substrate, wherein the semiconductor substrate has a high-voltage region and a medium-voltage region adjacent to each other, the high-voltage region includes a gate region, a source region and a drain region, the gate region is arranged between the source region and the drain region, a first gate oxide layer is arranged on the semiconductor substrate of the gate region, a pad oxide layer is arranged on the semiconductor substrate of the source region, the drain region and the medium-voltage region, and the pad oxide layer of the source region and the pad oxide layer of the drain region have a bird's beak defect on a side close to the first gate oxide layer;

[0052] Step S2: sequentially removing the pad oxide layers of the medium voltage region, the source region and the drain region of the high voltage region;

[0053] Step S3: forming a second gate oxide layer and a polysilicon film layer in sequence on the semiconductor substrate in the medium voltage region, wherein a portion of the second gate oxide layer also covers the semiconductor substrate in the source region and the drain region of the high voltage region, and the first gate oxide layer, and the polysilicon film layer covers the second gate oxide layer;

[0054] Step S4: etching the polysilicon film layer and the second gate oxide layer in sequence to form a high-voltage gate structure in the gate region and a medium-voltage gate structure in the medium-voltage region.

[0055] The following combination Figure 4-Figure 10 A method for forming a semiconductor device provided in this embodiment is described in detail.

[0056] See also Figure 4-Figure 6 First, step S1 is performed to provide a semiconductor substrate 100, wherein the semiconductor substrate 100 has a high-voltage region I and a medium-voltage region II that are adjacently arranged, wherein the high-voltage region I includes a gate region I2, a source region I1 and a drain region I3, wherein the gate region I2 is arranged between the source region I1 and the drain region I3, and a first gate oxide layer 130 is arranged on the semiconductor substrate 100 of the gate region I2, and a pad oxide layer 110 is arranged on the semiconductor substrate 100 of the source region I1, the drain region I3 and the medium-voltage region II, wherein the pad oxide layer 110 of the source region I1 and the pad oxide layer 110 of the drain region I3 have a bird's beak defect on a side close to the first gate oxide layer 130.

[0057] This step specifically includes the following steps:

[0058] like Figure 4As shown, first, a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 has a high voltage region I and a medium voltage region II arranged adjacent to each other, and the high voltage region I and the medium voltage region II are isolated and arranged by a shallow trench isolation structure 101. The high voltage region I includes a gate region I2, a source region I1 and a drain region I3, and the gate region I2 and the source region I1 as well as the gate region I2 and the drain region I3 are isolated and arranged by a shallow trench isolation structure 101, that is, the gate region I2 and the source region I1 are isolated by a shallow trench isolation structure 101, and the gate region I2 and the drain region I3 are isolated by a shallow trench isolation structure 101. A pad oxide layer 110 and a first silicon nitride layer 120 are sequentially formed on the semiconductor substrate 100 in the high voltage region I and the medium voltage region II, and the first silicon nitride layer 120 also covers the shallow trench isolation structure 101 and the pad oxide layer 110. Wherein, the semiconductor substrate 100 is, for example, a silicon substrate.

[0059] like Figure 5 As shown, next, the first silicon nitride layer 120 is etched by a dry etching process to form an opening 102 in the gate region I2 , wherein the opening 102 exposes the semiconductor substrate 100 in the gate region I2 . In detail, a patterned first photoresist layer is first formed on the first silicon nitride layer 120, and the patterned first photoresist layer covers the semiconductor substrate 100 outside the gate region I2, and also exposes a portion of the shallow trench isolation structure 101 around the gate region I2; then, the patterned first photoresist layer is used as a mask, and the first silicon nitride layer 120 is etched by a dry etching process, and the etching stops in the semiconductor substrate 100. At the same time, a portion of the depth of the exposed shallow trench isolation structure 101 is also etched, so that the surface of the exposed shallow trench isolation structure 101 is flush with the semiconductor substrate 100 after etching, and an opening 102 is formed in the gate region I2, and the opening 102 exposes the semiconductor substrate 100 and a portion of the shallow trench isolation structure 101 around the gate region I2; finally, the first photoresist layer is removed.

[0060] like Figure 6As shown, then, a first gate oxide layer 130 is deposited in the semiconductor substrate 100 of the gate region I2. In detail, in a high temperature environment, water vapor reacts with the semiconductor substrate 100 of the gate region I2 to generate the first gate oxide layer 130 (i.e., the first gate oxide layer 130 is deposited by the ISSG process), and at the same time, water vapor enters the semiconductor substrate 100 of the source region I1 and the drain region I3 through the interface between the first silicon nitride layer 120 and the shallow trench isolation structure 101 at the opening 102, and reacts with the semiconductor substrate 100 of the source region I1 and the drain region I3 along the interface between the pad oxide layer 110 and the shallow trench isolation structure 101, causing the thickness of the pad oxide layer 110 of the source region I1 and the drain region I3 close to the gate region I2 to increase, thereby forming a bird's beak defect of the pad oxide layer 110.

[0061] Next, the first silicon nitride layer 120 is removed by a wet etching process to expose the pad oxide layer 110 .

[0062] See also Figure 8 Then, step S2 is performed to sequentially remove the source region I1, the drain region I3 and the pad oxide layer 110 of the medium voltage region II in the high voltage region. This step specifically includes the following steps:

[0063] like Figure 7 As shown, first, a second silicon nitride layer 140 is formed on the pad oxide layer 110 and the first gate oxide layer 130 by a deposition process.

[0064] like Figure 8 As shown, then, the second silicon nitride layer 140 is etched, and the second silicon nitride layer 140 of the gate region I2 is retained, while the pad oxide layer 110 of the source region I1, the drain region I3 and the medium voltage region II is exposed. In detail, a patterned second photoresist layer is first formed on the second silicon nitride layer 140, and the patterned second photoresist layer covers the second silicon nitride layer 140 of the gate region I2; then, the second silicon nitride layer 140 is etched by a dry etching process using the patterned second photoresist layer as a mask, and the pad oxide layer 110 is exposed; and then, the pad oxide layer 110 is further etched by a dry etching process to remove the pad oxide layer 110 of the source region I1, the drain region I3 and the medium voltage region II.

[0065] When etching the pad oxide layer 110, the pad oxide layer 110 is etched by a dry etching process using a high etching selectivity gas. For example, the etching selectivity of the etching gas to oxide and silicon is greater than 10:1, and further, the etching selectivity of the etching gas to oxide and silicon is greater than 5:1. This allows this step to etch less of the semiconductor substrate 100 when etching the bottom oxide layer, and at the same time, the pad oxide layer 110 that is locally thicker can be well etched clean.

[0066] In this step, the pad oxide layer 110 with the bird's beak defect is etched away, that is, there is no residual pad oxide layer 110 in the source region I1 and the drain region I3 in the subsequent etching to form the gate structure, so that the metal silicide layer subsequently formed on the semiconductor substrate 100 in the source region I1 and the drain region I3 is not affected, and the contact between the plug subsequently formed on the source region I1 and the drain region I3 and the substrate is not affected, thereby not affecting the electrical properties and reliability of the high-voltage device.

[0067] Next, the second photoresist layer is removed first, and then the second silicon nitride layer 140 of the gate region 12 is removed by etching to expose the first gate oxide layer 130 .

[0068] See also Figure 9-10 Then, step S3 is performed to sequentially form a second gate oxide layer and a polysilicon film layer on the semiconductor substrate 100 in the medium voltage region II, wherein a portion of the second gate oxide layer also covers the semiconductor substrate 100 in the source region I1 and the drain region I3, as well as the first gate oxide layer 130, and the polysilicon film layer covers the second gate oxide layer.

[0069] This step specifically includes:

[0070] like Fig. 9 As shown, first, a first oxide layer 151 is deposited by an ISSG process, and the first oxide layer 151 covers the source region I1 and the drain region I3 of the high voltage region and the semiconductor substrate 100 of the medium voltage region II.

[0071] Next, a second oxide layer 152 is deposited, and the second oxide layer 152 covers the first oxide layer 151 and the first gate oxide layer 130, and also covers the shallow trench isolation structure 101. The first oxide layer 151 and the second oxide layer 152 together constitute a second gate oxide layer. The second oxide layer 152 is a HTO (High Temperature Oxide) layer.

[0072] Next, a polysilicon film layer is deposited on the second oxide layer 152 .

[0073] See also Fig.10 Then, step S4 is performed to sequentially etch the polysilicon film layer and the second gate oxide layer to form a high-voltage gate structure in the gate region I2 and a medium-voltage gate structure in the medium-voltage region II.

[0074] In detail, a patterned third photoresist layer is first formed on the polysilicon film layer, and the patterned third photoresist layer covers the second gate oxide layer of the gate area I2, and also covers the second gate oxide layer of the medium voltage area II for forming a medium voltage gate structure area; then, using the patterned third photoresist layer as a mask, the polysilicon film layer, the second gate oxide layer and the first gate oxide layer 130 are sequentially etched by a dry etching process in multiple steps to form a high-voltage polysilicon gate 210 and a medium-voltage polysilicon gate 220, thereby forming a high-voltage gate structure and a medium-voltage gate structure, and at the same time, the semiconductor substrate 100 of the source area I1 and the drain area I3 of the high-voltage area, and the semiconductor substrate 100 outside the medium-voltage gate structure in the medium-voltage area II are exposed.

[0075] Next, the third photoresist layer is removed.

[0076] Next, using the high-voltage gate structure and the medium-voltage gate structure as masks, an ion implantation process is performed to form a high-voltage source in the source region I1, a high-voltage drain in the drain region I3, and a medium-voltage source and a medium-voltage drain in the semiconductor substrate 100 on both sides of the medium-voltage gate structure.

[0077] In summary, the present invention provides a method for forming a semiconductor device, comprising the following steps: providing a semiconductor substrate, the semiconductor substrate having a high-voltage region and a medium-voltage region arranged adjacent to each other, the high-voltage region comprising a gate region, a source region and a drain region, the gate region being arranged between the source region and the drain region, and a first gate oxide layer being arranged on the semiconductor substrate of the gate region, a pad oxide layer being arranged on the semiconductor substrate of the source region, the drain region and the medium-voltage region, the pad oxide layer of the source region and the pad oxide layer of the drain region having a bird's beak defect on a side close to the first gate oxide layer; sequentially removing the source region, the drain region and the pad oxide layer of the medium-voltage region; sequentially forming a second gate oxide layer and a polysilicon film layer on the semiconductor substrate of the medium-voltage region, a portion of the second gate oxide layer also covering the semiconductor substrate of the source region and the drain region of the high-voltage region, and the first gate oxide layer, and the polysilicon film layer covering the second gate oxide layer; sequentially etching the polysilicon film layer and the second gate oxide layer to form a high-voltage gate structure in the gate region and a medium-voltage gate structure in the medium-voltage region. The present invention removes the pad oxide layer with a bird's beak defect by removing the pad oxide layer in the source region and the drain region of the high voltage region while removing the pad oxide layer in the medium voltage region, rather than removing the pad oxide layer together when etching the second gate oxide layer to cause the pad oxide layer residue, that is, no residual pad oxide layer exists in the source region and the drain region of the high voltage region in the subsequent etching to form the gate structure, so that the metal silicide layer subsequently formed on the semiconductor substrate in the source region and the drain region of the high voltage region is not affected, and the contact between the plug formed subsequently on the source region and the drain region of the high voltage region and the substrate is not affected, so that the electrical properties and reliability of the high voltage device are not affected.

[0078] In addition, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0079] It is to be understood that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that: The following steps are involved: A semiconductor substrate is provided, wherein the semiconductor substrate has a high-voltage region and a medium-voltage region arranged adjacent to each other, the high-voltage region includes a gate region, a source region and a drain region, the gate region is arranged between the source region and the drain region, a first gate oxide layer is arranged on the semiconductor substrate of the gate region, a pad oxide layer is arranged on the semiconductor substrate of the source region, the drain region and the medium-voltage region, and the pad oxide layer of the source region and the pad oxide layer of the drain region have a bird's beak defect on a side close to the first gate oxide layer; forming a second silicon nitride layer on the pad oxide layer and the first gate oxide layer by a deposition process; Etching the second silicon nitride layer, retaining the second silicon nitride layer in the gate region, and exposing the pad oxide layer in the medium voltage region, the source region of the high voltage region, and the drain region; Etching and removing the second silicon nitride layer in the gate region to expose the first gate oxide layer; forming a second gate oxide layer and a polysilicon film layer in sequence on the semiconductor substrate in the medium voltage region, wherein a portion of the second gate oxide layer also covers the semiconductor substrate in the source region and the drain region of the high voltage region, and the first gate oxide layer, and the polysilicon film layer covers the second gate oxide layer; The polysilicon film layer and the second gate oxide layer are sequentially etched to form a high-voltage gate structure in the gate region and a medium-voltage gate structure in the medium-voltage region.

2. The method for forming a semiconductor device according to claim 1, wherein: The method for forming the pad oxide layer having a bird's beak defect is as follows: A semiconductor substrate is provided, wherein the high voltage region and the medium voltage region are isolated by a shallow trench isolation structure, and the gate region and the source region, as well as the gate region and the drain region, are isolated by a shallow trench isolation structure; Sequentially forming a pad oxide layer and a first silicon nitride layer on the semiconductor substrate in the high voltage region and the medium voltage region, wherein the first silicon nitride layer also covers the shallow trench isolation structure and the pad oxide layer; Etching the first silicon nitride layer by a dry etching process to form an opening in the gate region, wherein the opening exposes the semiconductor substrate of the gate region; Depositing a first gate oxide layer in the semiconductor substrate in the gate region; The first silicon nitride layer is removed by a wet etching process to expose the pad oxide layer.

3. The method for forming a semiconductor device according to claim 2, wherein: When the pad oxide layer is etched by dry etching, the etching selectivity ratio of the etching gas to oxide and silicon is greater than 10:

1.

4. The method for forming a semiconductor device according to claim 3, wherein: When the pad oxide layer is etched by a dry etching process, the etching selectivity ratio of the etching gas to oxide and silicon is greater than 5:

1.

5. The method for forming a semiconductor device according to claim 2, wherein: The method of forming the second gate oxide layer is: Depositing a first oxide layer, wherein the first oxide layer covers the source region, the drain region of the high voltage region and the semiconductor substrate of the medium voltage region; A second oxide layer is deposited, wherein the second oxide layer covers the first oxide layer and the first gate oxide layer, and also covers the shallow trench isolation structure, and the first oxide layer and the second oxide layer together constitute a second gate oxide layer.

6. The method for forming a semiconductor device according to claim 5, wherein: The first oxide layer and the first gate oxide layer are both formed by an ISSG process.

7. The method for forming a semiconductor device according to claim 5, wherein: The second oxide layer is a HTO layer.

8. The method for forming a semiconductor device according to claim 1, wherein: The method of forming the high voltage gate structure and the medium voltage gate structure is: The polysilicon film layer, the second gate oxide layer and the first gate oxide layer are sequentially etched by a dry etching process in multiple steps to form a high-voltage polysilicon gate and a medium-voltage polysilicon gate, thereby forming a high-voltage gate structure and a medium-voltage gate structure, while also exposing the semiconductor substrate of the source region and the drain region of the high-voltage region, and the semiconductor substrate outside the medium-voltage gate structure in the medium-voltage region.

9. The method for forming a semiconductor device according to claim 8, wherein: After forming the high voltage gate structure and the medium voltage gate structure, the method further includes: Using the high-voltage gate structure and the medium-voltage gate structure as masks, a high-voltage source is formed in the source region of the high-voltage region, a high-voltage drain is formed in the drain region, and a medium-voltage source and a medium-voltage drain are formed in the semiconductor substrate on both sides of the medium-voltage gate structure through an ion implantation process.

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