SiCVD MOSFET structure for inhibiting drain-source voltage overshoot and preparation method thereof

By depositing a polysilicon doped layer inside the semiconductor epitaxial layer of the SiC VDMOSFET device and installing a doped N-layer, the problem of drain-source voltage overshooting under long-term switching is solved, and better voltage stabilization performance and switching characteristics are achieved.

CN119653833AActive Publication Date: 2025-03-18HANGZHOU SPECTRUM SEMICON TECH CO LTD
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Patent Information

Application Number
CN202510181639.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-02-19
Publication Date
2025-03-18
Estimated Expiration
2045-02-19

AI Technical Summary

Technical Problem

When existing SiC VDMOSFET devices are used for a long switching time, the drain-source voltage is prone to overshoot, resulting in the voltage stabilization performance and parasitic capacitors that cannot be optimally matched, limiting the full performance of device performance.

Method used

By deposition inside the semiconductor epitaxial layer, a polysilicon doped layer is formed, and a doped N layer is provided below the polysilicon doped layer, a reverse electric field is formed to reduce drain-source voltage overshoot, and the doping concentration and depth are optimized in the device design to reduce the concentration of the electric field during the switching process.

Benefits of technology

It effectively suppresses the concentration of high electric fields, avoids breakdown phenomenon at high voltages, reduces the impact of drain-source voltage overshoot, and thus improves the voltage stabilization performance and switching characteristics of the device.

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Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a SiCVD MOSFET structure for inhibiting drain-source voltage overshoot, which comprises a metal drain electrode, a semiconductor epitaxial layer, a metal source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that the semiconductor epitaxial layer comprises an N substrate layer, a diffusion layer, a P well layer, a doped P layer and an N well layer; the profile of the cross section of the grid electrode is in an inverted U shape, and a polycrystalline silicon doping layer is arranged below the grid electrode; the profile of the cross section of the P well layer is L-shaped, and the height of the cross section of the P well layer is higher than that of the cross section of the polycrystalline silicon doped layer; and an N-doped layer is arranged below the polycrystalline silicon doped layer, wherein the N-doped layer blocks the direct contact between the polycrystalline silicon doped layer and the diffusion layer. The polycrystalline silicon doping layer is formed in the semiconductor epitaxial layer through deposition, the polycrystalline silicon doping layer can reduce the influence of drain-source voltage overshoot, concentration of a high electric field is effectively restrained, and the breakdown phenomenon under high voltage is avoided.
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