Power device with improved short-circuit current capability and manufacturing method thereof

Abstract

The invention provides a power device with improved short-circuit current capability and a manufacturing method thereof. The power device comprises at least one cell. The cell is divided into two half cells along the width direction of the cell. Each half cell comprises a drift region, a source doped region and a source metal connected with the source doped region. The source doped region includes a source region and a plurality of contact regions. The source region comprises at least one first extension region, the plurality of contact regions are arranged in the length direction of the cell, and any two adjacent contact regions are spaced by the first extension region. And configuring the connection state of the source metal and the source doped region to be local connection of the source metal of at least one half-cell and at least one first extension region. According to the power device, the on-resistance is increased by prolonging the path of current flowing through the source region, and the short-circuit current capability is improved. The gate structures of part of the cells of the power device are adjusted, so that the short-circuit current capability and the conduction current capability of the device are further balanced. The manufacturing method is simple in steps.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor devices and manufacturing technology, and relates to a power device with improved short-circuit current capability and a manufacturing method thereof. Background Art

[0002] Silicon carbide (SiC) is a third-generation semiconductor material. Compared with silicon, it has a larger bandgap, higher electron saturation mobility, higher thermal conductivity and higher critical breakdown electric field. Compared with traditional silicon-based devices, silicon carbide devices exhibit higher temperature, lower loss, higher voltage resistance, radiation resistance and temperature stability, showing broad application prospects in many fields.

[0003] However, since the critical breakdown field strength of silicon carbide material is much higher than that of silicon material, under the same blocking voltage and rated current capacity, the chip area of ​​silicon carbide devices can be smaller and the current density can be higher. The high current density causes the heating area of ​​the device to be more concentrated, resulting in the short-circuit current capability being weaker than that of silicon-based devices, which in turn directly affects the reliability and life of the device.

[0004] Therefore, how to provide a power device with improved short-circuit current capability and a manufacturing method thereof to improve the short-circuit current capability of the power device and enhance the reliability of the device has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a power device with improved short-circuit current capability and a manufacturing method thereof, so as to solve the problem that the short-circuit current of the power device in the prior art needs to be improved.

[0007] To achieve the above-mentioned object and other related objects, in a first aspect, a power device with improved short-circuit current capability is provided, comprising at least one cell, wherein the cell is divided into two half cells along the width direction of the cell, and each of the half cells comprises:

[0008] Drift zone;

[0009] a source doping region, located in the drift region, the source doping region comprising a source region and a plurality of contact regions, the source region comprising at least one first extension region, the plurality of contact regions being arranged in the length direction of the cell, and any two adjacent contact regions being spaced apart by the first extension region, and the length direction of the cell being perpendicular to the width direction of the cell;

[0010] A source metal, located above the drift region, the source metal also connected to the source doped region;

[0011] In the cell, the connection state between the source metal and the source doping region is configured as follows: the source metal in at least one of the half cells is partially connected to at least one of the first extension regions.

[0012] Optionally, each of the half cells further comprises a source contact hole; the source contact hole is located above the drift region, and the source metal is filled into the source contact hole; wherein the source contact hole in at least one of the half cells exposes a portion of the first extension region;

[0013] In the width direction of the cell, the width of the source contact hole that partially exposes the first extension region is W1, the width of the contact region is W2, and the range of W1 / W2 is 0.7-0.8.

[0014] Optionally, in the length direction of the cell, the length of the cell is L1, the length of the first extension area is L2, and the range of L2 / L1 is 0.23 to 0.29.

[0015] Optionally, in the width direction of the cell, the source regions of the two half cells are connected, and each of the contact regions of the two half cells are respectively connected; or, in the width direction of the cell, the source regions of the two half cells are separated, and each of the contact regions of the two half cells are respectively separated.

[0016] Optionally, the source doping region further includes a well region, and the source region and each of the contact regions are located in the well region; and the cell further includes:

[0017] A JFET region, wherein in the width direction of the cell, the JFET region spans the drift regions of the two half cells, and the JFET region is located between the well regions of the two half cells;

[0018] A gate spans over the drift regions of the two half cells, and the gate covers at least a portion of the JFET region.

[0019] Optionally, the power device includes at least one first cell, and the gate in the first cell completely covers the JFET region.

[0020] Optionally, the power device further includes at least one second cell, the gate in the second cell includes a first sub-gate and a second sub-gate, the first sub-gate and the second sub-gate are separated in the width direction of the cell, and the first sub-gate and the second sub-gate both cover a portion of the JFET area.

[0021] Optionally, in the second cell: a ratio of an area of ​​the JFET region covered by the gate to an area of ​​the JFET region is in a range of 0.1 to 0.4.

[0022] Optionally, in the power device, the number of the first cells is equal to the number of the second cells.

[0023] In a second aspect, an embodiment of the present application further provides a method for manufacturing a power device with improved short-circuit current capability, the manufacturing method being used to manufacture the power device as described in the first aspect, the power device comprising at least one cell, and the cell being divided into two half cells along the width direction of the cell, the manufacturing method comprising the following steps:

[0024] forming a drift layer, wherein the drift layer includes two drift regions distributed along the width direction of the cell;

[0025] A source doping region is formed in each of the drift regions, wherein the source doping region includes a source region and a plurality of contact regions, wherein the source region includes at least one first extension region, wherein the plurality of contact regions are arranged in the length direction of the cell, and any two adjacent contact regions are spaced apart by the first extension region, and the length direction of the cell is perpendicular to the width direction of the cell;

[0026] forming a source metal above each of the drift regions, wherein the source metal is also connected to the source doped region;

[0027] Each of the drift regions, the source doping region formed in the drift region, and the source metal formed above the drift region are used to form a half cell;

[0028] In the cell, the connection state between the source metal and the source doping region is configured as follows: the source metal in at least one of the half cells is partially connected to at least one of the first extension regions.

[0029] As described above, the power device with improved short-circuit current capability of the present application has the following technical effects: First, by dividing the cell of the power device into two half cells, connecting the source metal of each half cell to the source doping region, and connecting the source metal in at least one half cell to a part of at least one first extension region, the path length of the current flowing through the source region is extended, thereby increasing the on-resistance and achieving the improvement of the short-circuit current capability of the device. Secondly, by optimizing the ratio of the length of the first extension region to the cell length, and optimizing the ratio of the width of the source contact hole for exposing the local first extension region to the width of the contact region, while improving the short-circuit current capability of the device, a good balance between the on-current capability of the device and the short-circuit circuit capability is achieved. Thirdly, by adjusting the gate structure of at least one cell (i.e., the second cell) in the power device, so that the gate structure does not completely cover the JFET region, the on-resistance is increased from an angle other than increasing the source resistance, and on the basis of adjusting the contact position between the source metal and the source doping region to improve the short-circuit current capability of the device, its short-circuit current capability is further improved. Finally, by co-optimizing the ratio range of the length of the first extension region to the length of the cell and the ratio range of the area of ​​the JFET region covered by the gate to the area of ​​the JFET region, a balance between the short-circuit current capability and the on-current capability of the device can be achieved, thereby ensuring the working performance of the device.

[0030] The method for manufacturing a power device with improved short-circuit current capability of the present application can manufacture a power device with improved short-circuit current capability, and has simple process steps, low cost, and is easy to achieve large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A partial cross-sectional view of a power device in the related art is shown;

[0032] Figure 2 A schematic cross-sectional view of a cell in a power device with improved short-circuit current capability provided by an embodiment of the present application in a first embodiment;

[0033] Figure 3 Display as Figure 2 A schematic diagram of the first cross section of the I-I' portion;

[0034] Figure 4 Display as Figure 2 A schematic diagram of the second cross section of the I-I' portion;

[0035] Figure 5 Display as Figure 2 A schematic diagram of the third cross section at the I-I' position;

[0036] Figure 6 Display as Figure 2 A schematic diagram of the fourth cross section at the I-I' position;

[0037] Figure 7 Display as Figure 3 A schematic cross-sectional view of the structure in the middle when the source metal is not filled;

[0038] Figure 8 Display as Figure 2 A schematic cross-sectional view of the II-II' portion;

[0039] Fig. 9 A curve diagram showing a change in on-resistance of a power device with improved short-circuit current capability as a function of L2 / L1 provided in an embodiment of the present application;

[0040] Fig.10 A curve diagram showing the change of short-circuit current time / on-resistance with L2 / L1 of a power device with improved short-circuit current capability provided by an embodiment of the present application;

[0041] Fig.11 Display as Figure 2 A fifth cross-sectional view of the I-I' region;

[0042] Fig.12 A cross-sectional schematic diagram showing a power device with improved short-circuit current capability in a second embodiment provided by an embodiment of the present application;

[0043] Fig.13 A flowchart showing the steps of a method for manufacturing a power device with improved short-circuit current capability provided by an embodiment of the present application is shown.

[0044] Description of reference numerals:

[0045] 10-substrate, 20-drift region, 21-JFET region, 30-source doping region, 31-source region, 31a-first extension region, 31b-second extension region, 32-contact region, 33-well region, 40-source metal, 50-source contact hole, 60-gate, 61-first sub-gate, 62-second sub-gate, 70-gate dielectric layer, 80-interlayer dielectric layer, 90-drain metal, A-half cell, A1-first half cell, A2-second half cell, C-cell, C1-first cell, C2-second cell, S1~S3-steps. DETAILED DESCRIPTION

[0046] The following describes the implementation of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0047] See also Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] See also Figure 1 , Figure 1 The schematic diagram of a partial top view of a power device is shown. The cells in the power device are distributed in a strip shape. The cells include a source region 31, a contact region 32, a gate 60, a source contact hole (not marked in the figure) and a source metal 40. Part of the source region 31 is embedded in the contact region 32. The source contact hole is arranged in a "one" shape parallel to the gate 60. The source contact hole completely exposes the contact region 32 and the part of the source region 31 embedded in the contact region 32. The source metal 40 is filled into the source contact hole and connected to the source region 31 and the contact region 32. When the power device is in the on state, the current flows directly from the source metal 40 after passing through a very short source region 31 area ( Figure 1 The dashed arrow in the middle shows the current flow path schematically). Although it shows good conduction performance, under short-circuit conditions, the short-circuit current time is short and the short-circuit current capacity is relatively weak.

[0049] Embodiment 1

[0050] This embodiment provides a power device with improved short-circuit current capability (hereinafter referred to as "power device"), see Figure 2 , Figure 2 A schematic cross-sectional view of a cell in the power device is shown, and the power device includes at least one cell C. Along the width direction X of the cell C, the cell C is divided into two half cells A, and each of the half cells A includes: a drift region 20, a source doping region 30, and a source metal 40. To facilitate a detailed introduction to the structure of the cell C, the two half cells A in the same cell C are respectively a first half cell A1 and a second half cell A2.

[0051] Specifically, the source doping region 30 is located in the drift region 20. The source doping region 30 includes a source region 31 and a plurality of contact regions 32. The source region 31 includes at least one first extension region 31a, and the plurality of contact regions 32 are arranged in the length direction of the cell C, and any two adjacent contact regions 32 are separated by the first extension region 31a, and the length direction Y of the cell is perpendicular to the width direction X of the cell C. The source metal 40 is located above the drift region 20. Please refer to Figures 3 to 6 ,in, Figures 3 to 6 The Figure 2Four cross-sectional schematic diagrams at I-I' in the cell C. In the cell C, the connection state between the source metal 40 and the source doping region 30 is: the source metal 40 in at least one of the half cells A is partially connected to at least one of the first extension regions 31a (it should be noted that the source metal 40 here is partially connected to at least one of the first extension regions 31a in the same half cell A). At the same time, the source metal 40 partially connected to the first extension region 31a is also partially connected to each of the contact regions 32 in the same half cell A.

[0052] It should be noted that the term "multiple" herein refers to more than or equal to two, for example, "multiple contact areas 32" refers to at least two contact areas 32. The term "partial" herein refers to only a portion of the corresponding structure, for example, "partially connected to at least one of the first extension areas 31a" means "only connected to a portion of at least one of the first extension areas 31a", which can be connected to a portion of a first extension area 31a (please refer to Figure 3 and Figure 4 ), or each of the plurality of first extension regions 31a may be uniformly connected (please refer to Figure 5 and Figure 6 In addition, the partial or full connection between the source metal 40 and the first extension region 31a described herein refers to the partial or full connection with the upper surface (the side away from the substrate) of the first extension portion 31a, rather than the partial or full connection in a three-dimensional state.

[0053] In the present application example, comparison Figure 1 and Figure 3 , by configuring the connection state of the source metal 40 and the source doping region 30: the source metal 40 in at least one of the half-cells A is partially connected to at least one of the first extension regions 31a, so that the current in the corresponding half-cell A needs to pass through the longer source region 31 before it can flow out of the source metal 40 (i.e., extend the path length of the current flowing through the source region 31), so that the overall on-resistance of the device is increased, thereby reducing the saturation current of the power device, thereby improving the short-circuit current capability of the device. At the same time, since the contact area between the source metal 40 and the source region 31 and each of the contact regions 32 is reduced, the contact resistance of the source metal 40 is increased, which also improves the on-resistance of the device to a certain extent. Therefore, in the embodiment of the present application, the short-circuit current capability of the device is improved by sacrificing part of the on-resistance, thereby improving the reliability of the device.

[0054] In one embodiment, if Figure 3As shown, in one of the two half cells A, the source metal 40 is locally connected to the first extension region 31a (for example, the first half cell A1), and in the other half cell A of the two half cells A, the source metal 40 is also locally connected to the first extension region 31a (for example, the second half cell A2).

[0055] In another embodiment, if Figure 4 As shown. In one of the two half cells A, the source metal 40 is partially connected to at least one of the first extension regions 31a (for example, the first half cell A1), and in the other half cell A of the two half cells A, the source metal 40 is completely connected to the first extension region 31a (for example, the second half cell A2).

[0056] In addition, it is easy to understand that, since there are multiple contact regions 32 in each half cell A, and the first extension region 31a is extended into two adjacent contact regions 32, it means that there is at least one first extension region 31a in the source region 31. Then, correspondingly, at least one of the two source metal electrodes 40a is connected to a part of one first extension region 31a in the same half cell A, or is connected to a part of multiple first extension regions 31a in the same half cell A, or is connected to a part of all first extension regions 31a in the same half cell A.

[0057] In yet another embodiment, Figure 5 and Figure 6 As shown, in the case where each half cell A includes more than two contact regions 32 (for example, 3), the source region 31 of the half cell A includes more than one first extension region 31a (for example, 2). One of the source metals 40 in the two half cells A (for example, the first cell A1) is connected to a portion of the first extension region 31a in the corresponding half cell A, and is connected to the entire portion of the first extension region 31a in the corresponding half cell A. At this time, the connection area between the source metal 40 and the source doping region 30 is close to the edge of one side of the other half cell A (for example, as shown in E1) and is tooth-shaped, and / or the other of the source metals 40 in the two half cells A (for example, the second cell A2) is connected to a portion of the first extension region 31a in the corresponding half cell, and is connected to the entire portion of the first extension region 31a in the corresponding half cell A.

[0058] For example, when the source metal 40 of the first half cell A1 is partially connected to a portion of the first extension region 31a in the first half cell A1 and is completely connected to the remaining first extension region 31a in the first half cell A1, the connection state of the source metal 40 of the second half cell A2 can be the following three situations: the source metal 40 is partially connected to any one of the first extension regions 31a in the second half cell A2 (please refer to FIG. Figure 3 The structure of the source metal 40 of the second half cell A2 in FIG. 1 ), the source metal 40 is connected to all of the first extension regions 31a of any one of the second half cells A2 (please refer to FIG. 1 ). Figure 4 The structure of the source metal 40 of the second half cell A2 in FIG. 1 ), and the source metal 40 is partially connected to a portion of the first extension region 31a in the second half cell A2 and is fully connected to the remaining portion of the first extension region 31a in the second half cell A2 (please refer to FIG. 1 ). Figure 5 and Figure 6 In the third case, the connection region between the source metal 40 and the source doping region 30 in the first half cell A1 and the edge of one side of the second half cell A2 may be axially symmetrical with the connection region between the source metal 40 and the source doping region 30 in the second half cell A2 and the edge of one side of the first half cell A1 (e.g. Figure 5 as shown) or inversely symmetrical (as Figure 6 shown). Figure 5 and Figure 6 The structure of the cell C shown can achieve uniform extension of the current path of the cell C in the width direction of the cell C, thereby improving the working stability of the device. By flexibly designing the connection position of the source metal 40 of the two half cells A, the power device can be applied to a variety of application scenarios.

[0059] In the optional embodiment, to facilitate the display of the device structure, please refer to Figure 7 , Figure 7 Shows Figure 3 A schematic cross-sectional view of the structure in which the source contact hole is not filled with source metal. Each of the half cells A further comprises a source contact hole 50, and the source contact hole 50 is located above the drift region 20. The source metal 40 is filled into the source contact hole 50. Among them, the source contact hole 30 in at least one of the half cells A reveals a part of the first extension region 31a. Corresponding to the contact conditions of the source metal 40 in the two half cells A, the two half cells A respectively comprise one source contact hole 50, and at least one of the two source contact holes 50 in the cell C reveals a part of the first extension region 31a in the corresponding half cell A.

[0060] In an optional embodiment, if Figure 7 As shown, in the width direction X of the cell, the width of the source contact hole 50 that exposes the part of the first extension area 31a is W1 (this width is actually the width of the connection surface between the source metal 40 and the source doping area 30), the width of the contact area 32 is W2, and the range of W1 / W2 is 0.7 to 0.8 (including the end value), which can be 0.75. That is, the contact position and contact area of ​​the source metal 40 and the source doping area 30 are defined by the source contact hole 50. During the manufacturing process, the contact position and contact area of ​​the source metal 40 can be easily adjusted by adjusting the mask for etching the source contact hole 50, without additionally increasing the process difficulty.

[0061] In an optional embodiment, if Figure 7 As shown, in the length direction Y of the cell, the length of the cell C is L1, the length of the first extension area 31a is L2, and the range of L2 / L1 is 0.23 to 0.29 (including endpoint values), which can be 0.24, 0.26 or 0.28.

[0062] In the present application, please refer to Fig. 9 , Fig. 9 FIG. 4 shows a curve diagram showing the on-resistance of the power device as L2 / L1 changes. Fig. 9 It can be seen that the on-resistance of the power device increases as the value of L2 / L1 decreases, which shows that by adjusting the value of L2 / L1, the on-resistance of the device can be accurately controlled to adjust the short-circuit current capability of the device. Of course, this also shows that the short-circuit current capability of the device is achieved by sacrificing a part of the on-current capability of the device. In order to balance the short-circuit current capability of the device with the on-current capability of the device, please refer to Fig.10 , Fig.10 The graph shows the ratio of the short-circuit current time (SC) to the on-resistance (Rsp) of the device as L2 / L1 changes. The larger the ratio of the short-circuit current time to the on-resistance, the better the balance between the short-circuit current capability and the on-current capability of the power device, and the better the overall working performance. Fig.10 As can be seen from the figure, SC / Rs increases first and then decreases with the increase of L2 / L1. Fig.10 In this embodiment, L2 / L1 is preferably 0.23-0.26, especially when L2 / L1 is 0.25, the two achieve the best balance. At this time, only a small on-current capability is sacrificed to effectively improve the short-circuit current capability of the device.

[0063] In the optional embodiment, please refer to Figure 2 and Figure 8 ,in, Figure 8 Display as Figure 2 A cross-sectional schematic diagram of the II-II' portion in FIG. 1 , the source doping region 30 further includes a well region 33, and the source region 31 and each of the contact regions 32 in the same half cell A are located in the well region 33. The cell C further includes a JFET region 21 and a gate 60. In the width direction of the cell, the JFET region 21 spans across the drift regions 20 of the two half cells A. And the JFET region 21 is located between the well regions 33 of the two half cells A. The gate 60 spans over the drift regions 20 of the two half cells A. And the gate 60 covers at least a portion of the JFET region 21. In this embodiment, the gate 60 covers the entire JFET region 21.

[0064] In an optional embodiment, if Figures 2 to 8 As shown, the source region 31 further includes a second extension region 31b, the second extension regions 31b in the two half cells A are opposite, and the second extension region 31b in the same half cell A is adjacent to each of the first extension regions 31a and each of the contact regions 32. The gate 60 covers a portion of the second extension region 31b.

[0065] In an optional embodiment, if Figure 2 As shown, the cell C further includes a gate dielectric layer 70 and an interlayer dielectric layer 80. The gate dielectric layer 70 is located between the drift region 20 and the gate 60. The interlayer dielectric layer 80 is located above the drift region 20 and covers the gate 60. The source contact hole 50 is obtained by etching the interlayer dielectric layer 80 (i.e., the source contact hole 50 passes through the interlayer dielectric layer 80).

[0066] In an optional embodiment, if Figure 2 As shown, the cell C also includes a substrate 10 and a drain metal 90, the drift region 20 is located above the substrate 10, and the drain metal 90 is located below the substrate 10, so as to realize a vertical power device. Optionally, the material of the substrate 10 includes silicon carbide (that is, the power device can be a planar silicon carbide device). The material of the gate 60 includes polysilicon.

[0067] In one embodiment, in the width direction X of the cell, the source regions 31 of the two half cells A are separated, and each of the contact regions 32 of the two half cells A are separated respectively. At this time, the cell C in the power device has a long strip structure, such as Figures 3 to 8 In the case where the half cell A further includes a well region 33, the well regions 33 of the two half cells A are also separated. At this time, the plurality of contact regions 32 in each half cell A are spaced apart in the length direction of the cell A.

[0068] In another embodiment, see Fig.11 , Fig.11 Shown along Figure 2 The fifth cross-sectional diagram at I-I' in the figure. In the width direction of the cell, the source regions 31 of the two half cells A are connected, and the two contact regions 32 of the two half cells A are connected respectively (at this time, the two contact regions 32 in each half cell A are also arranged in the width direction of the cell C). At this time, the cell C of the power device has a square, circular or polygonal structure. In the case where the half cell A also includes a well region 33, the well regions 33 of the two half cells A are also connected. It should be noted that Fig.11 A square-shaped cell C is used as an example for illustration. In actual application, the cell C may have other regular or irregular shapes.

[0069] In an optional embodiment, the substrate 10, the drift region 20 and the source region 31 are all of the first conductivity type, and the contact region 32 and the well region 32 are all of the second conductivity type. For example, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.

[0070] The power device with improved short-circuit current capability of the present embodiment divides the cell C of the power device into two half cells, connects the source metal of each half cell to the source doping region, and locally connects the source metal of at least one of the two half cells to at least one first extension region of the source region, thereby extending the path length of the current flowing through the source region, thereby increasing the on-resistance and improving the short-circuit current capability of the device. Furthermore, by optimizing the ratio of the length of the first extension region to the length of the cell, and optimizing the ratio of the width of the local source contact hole for exposing the first extension region to the width of the contact region, while improving the short-circuit current capability of the device, a good balance between the on-current capability of the device and the short-circuit current capability is achieved. In addition, by flexibly designing the connection position of the source metal of the two half cells, the power device can be applied to a variety of application scenarios.

[0071] Embodiment 2

[0072] The present embodiment provides a power device with improved short-circuit current capability (hereinafter referred to as "power device"). The difference between the present embodiment and the first embodiment is that the gate of the cell C in the power device described in the first embodiment completely covers the JFET region (i.e., the first cell C described below), while the power device described in the present embodiment includes a cell C whose gate does not completely cover the JFET region (i.e., the second cell C described below). A cross-sectional schematic diagram of the cell C in the power device is shown.

[0073] See also Fig.12 , which is a cross-sectional schematic diagram of the power device, wherein the power device includes at least one cell C, and along the width direction X of the cell C, the cell C is divided into two half cells A( Fig.12 Not shown, please refer to Figure 2 ), each of the half cells A includes: a drift region 20, a source doping region 30 and a source metal 40.

[0074] Specifically, the source doping region 30 is located in the drift region 20. The source doping region 30 includes a source region 31 and a plurality of contact regions 32. The source region 31 includes at least one first extension region 31a, and the plurality of contact regions 32 are arranged in the length direction of the cell C, and any two adjacent contact regions 32 are spaced apart by the first extension region 31a, and the length direction Y of the cell is perpendicular to the width direction X of the cell. The source metal 40 is located above the drift region 20. In the cell C, the connection state between the source metal 40 and the source doping region 30 is configured as follows: the source metal 40 in at least one of the half cells A is connected to a portion of at least one of the first extension regions 31a. At the same time, the source metal 40 connected to a portion of the first extension region 31a is also connected to a portion of each of the contact regions 32 in the same half cell A.

[0075] In an optional embodiment, if Fig.12 As shown, the power device includes at least one first cell C1 , and the gate 60 in the first cell C1 completely covers the JFET region 21 .

[0076] In an optional embodiment, if Fig.12 As shown, the power device further includes at least one second cell C2, the gate 60 in the second cell C2 includes a first split gate 61 and a second split gate 62, the first split gate 61 and the second split gate 62 are separately arranged in the width direction of the cell, and the first split gate 61 and the second split gate 62 both cover a portion of the JFET region 21. It should be noted that although the gate 60 here includes the first split gate 61 and the second split gate 62 that are separately arranged, the gate 60 can still achieve good gate control capability.

[0077] In the embodiment of the present application, under the premise that the gate 60 realizes the gate control capability, the structure of at least one cell C in the power device is adjusted so that the gate 60 in the cell C includes a first sub-gate 61 and a second sub-gate 62 that are separately arranged. Due to the separate arrangement of the first sub-gate 61 and the second sub-gate 62, a portion of the JFET region 21 located below the gate 60 is not covered by the gate 60, thereby increasing the resistance of the accumulation layer formed on the surface of the JFET region 21 close to the gate 60, thereby increasing the on-resistance of the device at an angle other than the source resistance, thereby improving the short-circuit current capability of the device.

[0078] In an optional embodiment, in the second cell C2: the ratio of the area S2 of the JFET region 21 covered by the gate 60 to the area S1 of the JFET region 21 is in the range of 0.1 to 0.4 (including the endpoint values), including 0.2 or 0.3. Among them, the area of ​​the JFET region 21 covered by the gate 60 is the sum of the area of ​​the JFET region 21 covered by the first sub-gate 61 and the area of ​​the JFET region 21 covered by the second sub-gate 62. Although not shown in the figure, it is found through the change relationship between the above ratio and the on-resistance of the device that the on-resistance of the device increases with the decrease of the above ratio, which indicates that the short-circuit current capability of the device can be effectively adjusted by adjusting the above ratio.

[0079] Further, in the length direction of the cell, the length of the cell C is L1, the length of the first extension area 31a is L2, the range of L2 / L1 is 0.23 to 0.29 (including the endpoint values), which can be 0.24, 0.26 or 0.28, and the length direction of the cell is perpendicular to the width direction of the cell. In this embodiment, L2 / L1 is preferably 0.27 to 0.29. In this embodiment, the short-circuit current capability of the device is improved by adjusting the source resistance and the accumulation layer resistance of the device. S2 / S1 and L2 / L1 are two synergistic parameters. When L2 / L1 is 0.27 to 0.29 and S2 / S1 is 0.3 to 0.4, the effect of effectively improving the short-circuit current capability of the device can be achieved. Therefore, there is no need to lose more device conduction current capability beyond the above range, and the good working performance of the device can be achieved.

[0080] In an optional embodiment, in the power device, the number of the first cells C1 is equal to the number of the second cells C2. For example, in the width direction of the cells, the first cells C1 and the second cells C2 are arranged alternately to ensure the performance balance of the power device in various regions.

[0081] The power device with improved short-circuit current capability of the present embodiment includes a first cell and a second cell, wherein the gate in the second cell includes a first sub-gate and a second sub-gate that are separately arranged, so that the gate structure does not completely cover the JFET region, and the on-resistance is increased from an angle other than increasing the source resistance, and the short-circuit current capability of the device is further improved on the basis of adjusting the contact position between the source metal and the source doping region to improve the short-circuit current capability of the device. In addition, by co-optimizing the ratio range of the length of the first extension region to the length of the cell and the ratio range of the area of ​​the JFET region covered by the gate to the area of ​​the JFET region, the balance between the short-circuit current capability and the on-current capability of the device can be achieved, and the working performance of the device (for example, static parameters such as conduction loss) can be guaranteed.

[0082] Embodiment 3

[0083] This embodiment provides a method for manufacturing a power device with improved short-circuit current capability, which can be used to manufacture the power device as described in the first or second embodiment, wherein the power device comprises at least one cell C, and the cell C is divided into two half cells A along the width direction of the cell. Fig.13 , Fig.13 The power device includes a plurality of cells C, and the manufacturing method includes the following steps:

[0084] S1: forming a drift layer, wherein the drift layer includes two drift regions distributed along the width direction of the cell;

[0085] S2: forming a source doping region in each of the drift regions, wherein the source doping region includes a source region and a plurality of contact regions, wherein the source region includes at least one first extension region, the plurality of contact regions are arranged in the length direction of the cell, and any two adjacent contact regions are spaced apart by the first extension region, and the length direction of the cell is perpendicular to the width direction of the cell;

[0086] S3: A source metal is formed above each of the drift regions, and the source metal is also connected to the source doped region; each of the drift regions, the source doped region formed in the drift region, and the source metal formed above the drift region are used to constitute a half cell; in the cell, the connection state between the source metal and the source doped region is configured as follows: the source metal in at least one of the half cells is partially connected to at least one of the first extension regions.

[0087] For an alternative embodiment, see Figure 2 and Fig.12Before executing step S1, the method further includes providing a substrate 10, and then executing step S1 to form the drift layer (not shown in the figure) on the substrate 10, wherein the drift layer includes two drift regions 20 distributed along the width direction of the cell.

[0088] Next, step S2 is performed to form a source doping region 30 in each of the drift regions 20, wherein the source doping region 30 includes a source region 31 and a plurality of contact regions 32. In the width direction of the cell, the source region 31 includes at least one first extension region 31a, and the plurality of contact regions 32 are arranged in the length direction Y of the cell C, and any two adjacent contact regions 32 are spaced apart by the first extension region 31a. The length direction Y of the cell C is perpendicular to the width direction X of the cell C.

[0089] In an optional embodiment, the source doping region 30 further includes a well region 33, and step S2 includes the following steps: forming a well region 33 on the upper surface layer of the drift region 20 (the surface layer of the drift region 20 away from the substrate 10), and then forming the source region 31 and a plurality of contact regions 32 on the upper surface layer of the well region 33, wherein the source region 31, the plurality of contact regions 32 and the well region 33 constitute the source doping region 30. The cell C further includes a JFET region 21, and in the width direction of the cell, the JFET region 21 spans the drift regions 20 of the two half cells A, and the JFET region 21 is located between the well regions 33 of the two half cells A.

[0090] In an optional embodiment, before executing step S3, the step of forming a gate dielectric layer 70 and a gate 60 above the drift region 20 is also included, wherein the gate dielectric layer 70 is located between the drift region 20 and the gate 60, and the gate 60 spans above the drift region 30 of the two half cells A, and the gate 60 covers at least a portion of the JFET region 21 and a portion of the source region 31 in each of the half cells A.

[0091] Furthermore, in an optional embodiment, after forming the gate 60, a step of forming an interlayer dielectric layer 80 above the drift layer is also included, wherein the interlayer dielectric layer 80 covers the surface of the gate 60 and the drift region 20 not covered by the gate dielectric and the gate 60; then, the interlayer dielectric layer 80 is etched to form a source contact hole 50, and at least one of the source contact holes 50 in the two half cells A exposes a portion of the first extension region 31a.

[0092] Next, step S3 is performed to form a source metal 40 above each drift region 20, and the source metal 40 is also connected to the source doping region 30; each drift region 20, the source doping region 30 formed in the drift region 20, and the source metal 40 formed above the drift region 20 are used to form a half cell A. Please refer to Figures 3 to 6 In the cell C, the connection state between the source metal 40 and the source doping region 30 is: the source metal 40 of at least one of the two half cells A is partially connected to at least one of the first extension regions 31a. In the case where the source contact hole 50 is formed, the source metal 40 is filled into the source contact hole 50. In the case where the source contact hole 50 is not formed, the source metal 40 may also be formed by a metal lift-off process.

[0093] The method for manufacturing a power device with improved short-circuit current capability of the present embodiment can manufacture a power device with improved short-circuit current capability, and has simple process steps, low cost, and is easy to implement large-scale production.

[0094] In summary, the power device with improved short-circuit current capability of the present application, firstly, by dividing the cell of the power device into two half cells, connecting the source metal of each half cell to the source doping region, and locally connecting the source metal in at least one half cell to at least one first extension region of the source region, the path length of the current flowing through the source region is extended, thereby increasing the on-resistance and achieving the improvement of the short-circuit current capability of the device. Secondly, by optimizing the ratio of the length of the first extension region to the cell length, and optimizing the ratio of the width of the source contact hole for exposing the local first extension region to the width of the contact region, while improving the short-circuit current capability of the device, a good balance between the on-current capability of the device and the short-circuit circuit capability is achieved. Thirdly, by adjusting the gate structure of at least one cell (for example, the second cell) in the power device, so that the gate structure does not completely cover the JFET region, the on-resistance is increased from an angle other than increasing the source resistance, and on the basis of adjusting the contact position between the source metal and the source doping region to improve the short-circuit current capability of the device, its short-circuit current capability is further improved. Finally, by co-optimizing the ratio range of the length of the first extension region to the length of the cell and the ratio range of the area of ​​the JFET region covered by the gate to the area of ​​the JFET region, the short-circuit current capability and the on-current capability of the device can be balanced to ensure the working performance of the device. The method for manufacturing a power device with improved short-circuit current capability of the present application can manufacture a power device with improved short-circuit current capability, and the process steps are simple, the cost is low, and it is easy to achieve large-scale production. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A power device with improved short-circuit current capability, characterized in that: The invention comprises at least one cell, wherein the cell is divided into two half cells along the width direction of the cell, and each of the half cells comprises: Drift zone; a source doping region, located in the drift region, the source doping region comprising a source region and a plurality of contact regions, the source region comprising at least one first extension region, the plurality of contact regions being arranged in the length direction of the cell, and any two adjacent contact regions being spaced apart by the first extension region, and the length direction of the cell being perpendicular to the width direction of the cell; A source metal, located above the drift region, the source metal also connected to the source doped region; In the cell, the connection state between the source metal and the source doping region is configured as follows: the source metal in at least one of the half cells is partially connected to at least one of the first extension regions.

2. The power device with improved short-circuit current capability according to claim 1, characterized in that: Each of the half cells further comprises a source contact hole; the source contact hole is located above the drift region, and the source metal is filled into the source contact hole; wherein the source contact hole in at least one of the half cells exposes a portion of the first extension region; In the width direction of the cell, the width of the source contact hole that partially exposes the first extension region is W1, the width of the contact region is W2, and the range of W1 / W2 is 0.7-0.

8.

3. The power device with improved short-circuit current capability according to claim 2, characterized in that: In the length direction of the cell, the length of the cell is L1, the length of the first extension area is L2, and the range of L2 / L1 is 0.23 to 0.

29.

4. The power device with improved short-circuit current capability according to claim 1, characterized in that: In the width direction of the cell, the source regions of the two half cells are connected, and each of the contact regions of the two half cells is connected respectively; Alternatively, in the width direction of the cell, the source regions of the two half cells are separated, and each of the contact regions of the two half cells are separated respectively.

5. The power device with improved short-circuit current capability according to claim 1, characterized in that: The source doping region further includes a well region, and the source region and each of the contact regions are located in the well region; the cell further includes: A JFET region, wherein in the width direction of the cell, the JFET region spans the drift regions of the two half cells, and the JFET region is located between the well regions of the two half cells; A gate spans over the drift regions of the two half cells, and the gate covers at least a portion of the JFET region.

6. The power device with improved short-circuit current capability according to claim 5, characterized in that: The power device includes at least one first cell, and the gate in the first cell completely covers the JFET region.

7. The power device with improved short-circuit current capability according to claim 6, characterized in that: The power device also includes at least one second cell, the gate in the second cell includes a first sub-gate and a second sub-gate, the first sub-gate and the second sub-gate are separated and arranged in the width direction of the cell, and the first sub-gate and the second sub-gate both cover a portion of the JFET area.

8. The power device with improved short-circuit current capability according to claim 7, characterized in that: In the second cell: a ratio of an area of ​​the JFET region covered by the gate to an area of ​​the JFET region is in a range of 0.1 to 0.

4.

9. The power device with improved short-circuit current capability according to claim 7, characterized in that: In the power device, the number of the first cells is equal to the number of the second cells.

10. A method for manufacturing a power device with improved short-circuit current capability, characterized in that: The manufacturing method is used to manufacture the power device according to any one of claims 1 to 9, wherein the power device comprises at least one cell, and along the width direction of the cell, the cell is divided into two half cells, and the manufacturing method comprises the following steps: forming a drift layer, wherein the drift layer includes two drift regions distributed along the width direction of the cell; A source doping region is formed in each of the drift regions, wherein the source doping region includes a source region and a plurality of contact regions, wherein the source region includes at least one first extension region, wherein the plurality of contact regions are arranged in the length direction of the cell, and any two adjacent contact regions are spaced apart by the first extension region, and the length direction of the cell is perpendicular to the width direction of the cell; forming a source metal above each of the drift regions, wherein the source metal is also connected to the source doped region; Each of the drift regions, the source doping region formed in the drift region, and the source metal formed above the drift region are used to form a half cell; In the cell, the connection state between the source metal and the source doping region is configured as follows: the source metal of at least one half cell is partially connected to at least one first extension region.

Images