Method for preparing silicon carbide field-effect power transistor with integrated Schottky diode

Abstract

The present invention belongs to the field of semiconductor power device technology and relates to a novel method for preparing metal contacts for silicon carbide power devices. Specifically, a method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode is provided, which simplifies the preparation process, reduces preparation costs, and shortens the manufacturing cycle, making it particularly suitable for large-scale industrial production. During the device electrode preparation process, the present invention uses a single mask to produce Schottky contact holes and gate contact holes through a single etching process. Ohmic contact is achieved above the source electrode using nickel metal through a photomask, and Schottky contact is formed above the Schottky region and gate using titanium metal through a photomask. This ensures that both ohmic and Schottky contacts achieve good performance, and not only saves manufacturing costs in large-scale production, but also reduces the device manufacturing cycle.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, relates to a novel method for preparing metal contacts of a silicon carbide power device, and specifically provides a method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode. Background Art

[0002] As one of the most popular third-generation semiconductor materials, silicon carbide (SiC) is experiencing rapid development in its manufacturing process and is gradually being commercialized in certain high-temperature and high-voltage applications. Field-effect transistor (FET) power devices with integrated Schottky diodes are attracting significant attention due to their excellent reverse recovery performance and superior ability to suppress bipolar degradation. In SiC power device manufacturing, the annealing temperature for ohmic contacts ranges from 950°C to 1050°C, while the formation temperature for Schottky contacts is only 400°C to 600°C. Conventional technology requires the formation of contact holes for each device electrode through photolithography and etching processes using multiple masks of different shapes. For FET power devices with integrated Schottky diodes, Schottky contacts, source ohmic contacts, and gate contacts must be etched. If each electrode contact hole is fabricated using a separate mask, this inevitably leads to high costs and long manufacturing cycles in large-scale industrial production. Summary of the Invention

[0003] The present invention aims to provide a method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode, so as to simplify the preparation process, reduce the preparation cost, shorten the manufacturing cycle, and is particularly suitable for large-scale industrial production.

[0004] To achieve the above object, the technical solution adopted by the present invention is:

[0005] A method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode, characterized by comprising the following steps:

[0006] Step 1: Using the oxide layer as a patterned shielding layer, perform first conductivity type lightly doped ion implantation on the silicon carbide substrate to form first conductivity type lightly doped regions on both sides of the silicon carbide substrate.

[0007] Step 2. The first conductivity type lightly doped region is shielded again with an oxide layer, and second conductivity type lightly doped ions are implanted on the silicon carbide substrate to form a second conductivity type well region between the first conductivity type lightly doped regions on both sides.

[0008] Step 3. Using a self-aligned process to perform ion implantation mask growth, a mask is formed on the oxide layer and the areas on both sides of the second conductivity type well region in step 2, and first conductivity type heavily doped ions are implanted on the second conductivity type well region to form a first conductivity type active region in the middle area above the second conductivity type well region;

[0009] Step 4. Using the oxide layer as a patterned shielding layer again, heavily doped ions of the second conductivity type are implanted into the second conductivity type well region to form a second conductivity type active region adjacent to the left side of the first conductivity type active region, with the left side of the second conductivity type active region adjacent to the first conductivity type lightly doped region;

[0010] Step 5. Annealing the device in step 4 at 1700°C;

[0011] Step 6. Depositing an oxide layer on the device surface to cover a portion of the upper right side of the second conductivity type active region, the first conductivity type well region to the right of the second conductivity type active region, and the first conductivity type lightly doped region to the right, and then depositing a polysilicon gate on the oxide layer;

[0012] Step 7. Deposit an oxide layer again on the device surface to cover the entire device;

[0013] Step 8. Using the first mask, the oxide layer is etched by photolithography to form ohmic contact windows above the first conductivity type active region and the second conductivity type active region;

[0014] Step 9. Depositing metallic nickel in the ohmic contact window using an electron beam evaporation process to form a metallic nickel layer, wherein the metallic nickel layer forms ohmic contacts with the first conductive type active region and the second conductive type active region;

[0015] Step 10. Annealing the device in step 9 at 950° C. to 1050° C.;

[0016] Step 11. Using a second mask, etch the oxide layer through a photolithography process to form a Schottky contact window above the first conductivity type lightly doped region 4 on the left side and a gate contact window above the polysilicon gate;

[0017] Step 12. Using the first mask again, titanium is deposited on the nickel layer to form a titanium layer. The titanium layer forms an ohmic contact with the nickel layer. Using the second mask again, titanium is deposited in the Schottky contact window and the gate contact window to form a titanium layer. The titanium layer forms a Schottky contact with the first conductivity type lightly doped region, and the titanium layer forms an ohmic contact with the polysilicon gate.

[0018] Step 13. Anneal the device in step 12 at 400-600° C. to obtain a silicon carbide field-effect power transistor with an integrated Schottky diode.

[0019] Furthermore, the oxide layer is deposited using a low pressure chemical vapor deposition (LPCVD) process.

[0020] Furthermore, the metal nickel layer and the metal titanium layer are deposited by electron beam evaporation process.

[0021] Based on the above technical solution, the beneficial effects of the present invention are:

[0022] The present invention provides a method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode. During the preparation of device electrodes, Schottky contact holes and gate contact holes are produced using a single mask through a single etching process. Ohmic contact is achieved above the source electrode using nickel metal through a photomask, and Schottky contact is formed above the Schottky region and the gate electrode using titanium metal through a photomask. This method ensures that both the ohmic contact and the Schottky contact achieve good performance, and in large-scale production, not only saves manufacturing costs but also reduces the manufacturing cycle of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of the theoretical structure of the silicon carbide field effect power transistor with integrated Schottky diode in the present invention.

[0024] Figure 2 The figure is a schematic diagram of the actual structure of the silicon carbide field effect power transistor with integrated Schottky diode in the present invention.

[0025] Figure 3 Schematic diagram of the process of step 1 of the method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode in the present invention.

[0026] Figure 4 This is a flow chart of step 2 of the method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode in the present invention.

[0027] Figure 5 This is a flow chart of step 3 of the method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode in the present invention.

[0028] Figure 6 Schematic diagram of the process of step 4 of the method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode in the present invention.

[0029] Figure 7 Schematic diagram of the process of step 6 of the method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode in the present invention.

[0030] Figure 8Schematic diagram of the process of step 7 of the method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode in the present invention.

[0031] Figure 9 Schematic diagram of the process of step 8 of the method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode in the present invention.

[0032] Figure 10 Schematic diagram of the process of step 9 of the method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode in the present invention.

[0033] Figure 11 1 is a flow chart of step 11 of the method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode in the present invention.

[0034] Figure 12 1 is a flow chart of step 12 of the method for preparing a silicon carbide field-effect power transistor with an integrated Schottky diode in the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and beneficial effects of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0036] This embodiment provides a method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode. The theoretical structure of the silicon carbide field effect power transistor is as follows: Figure 1 As shown, the actual structure of the silicon carbide field effect power transistor prepared in this embodiment is as follows Figure 2 As shown, it specifically includes: a silicon carbide substrate 5, a metallized drain 6 arranged below the silicon carbide substrate, a first conductive type lightly doped region 4 and a first conductive type well region 7 arranged above the silicon carbide substrate, and the first conductive type well region is arranged between the two first conductive type lightly doped regions, a first conductive type active region 2 and a second conductive type active region 3 arranged in the first conductive type well region, as well as a metal source and a polysilicon gate; the second conductive type active region is adjacent to the left side of the first conductive type active region and is adjacent to the first conductive type lightly doped region on the left side, the first conductive type active region 2 and the second conductive type active region 3 are adjacent to each other. A nickel metal layer 10 is arranged across the second conductive type active area 3 to form an ohmic contact, and a titanium metal layer 20 is arranged on the first conductive type lightly doped area on the left and on the nickel metal layer 10 as a metallized source 8, and the first conductive type lightly doped area on the left forms a Schottky contact with the titanium metal layer; an oxide layer 1 is arranged on other areas on the second conductive type active area 3 and on the first conductive type well area on its right, as well as on the first conductive type lightly doped area on the right, a polysilicon gate 9 is arranged on the oxide layer 1, a titanium metal layer is arranged on the polysilicon gate 9 as a metallized gate, and the polysilicon gate forms an ohmic contact with the titanium metal layer.

[0037] Specifically, the method for preparing the above-mentioned silicon carbide field-effect power transistor with integrated Schottky diode comprises the following steps:

[0038] Step 1. Using the oxide layer as a patterned shielding layer, perform first conductivity type lightly doped ion implantation on the silicon carbide substrate to form first conductivity type lightly doped regions on both sides of the silicon carbide substrate, such as Figure 3 As shown;

[0039] Step 2. Use the oxide layer to shield the first conductive type lightly doped region again, and perform second conductive type lightly doped ion implantation on the silicon carbide substrate to form a second conductive type well region between the first conductive type lightly doped regions on both sides, as shown in FIG. Figure 4 As shown;

[0040] Step 3. Use a self-aligned process to grow an ion implantation mask. In step 2, a mask 11 is formed on the oxide layer and the upper and lower regions of the second conductive type well region. The mask is made of oxide or polysilicon. The first conductive type heavily doped ion implantation is performed on the second conductive type well region. The first conductive type active region is formed in the middle region of the second conductive type well region. Figure 5 As shown;

[0041] Step 4. Using the oxide layer as a patterned shielding layer again, perform second conductivity type heavily doped ion implantation on the second conductivity type well region to form a second conductivity type active region adjacent to the left side of the first conductivity type active region, and the left side of the second conductivity type active region is adjacent to the first conductivity type lightly doped region, as shown in FIG. Figure 6 As shown;

[0042] Step 5. Anneal the device in step 4 at 1700°C to activate the impurities and perform lattice repair after the ion implantation is completed;

[0043] Step 6. Use low pressure chemical vapor deposition (LPCVD) to deposit an oxide layer 1 on the device surface. The oxide layer covers the right portion of the second conductivity type active area 3, the first conductivity type well area on the right side of the second conductivity type active area 3, and the first conductivity type lightly doped area on the right side. Then, a polysilicon gate 9 is deposited on the oxide layer. Figure 7 As shown;

[0044] Step 7. Use low pressure chemical vapor deposition (LPCVD) process to deposit an oxide layer on the device surface again to cover the entire device. The oxide layer has high purity, uniform thickness and good step coverage. Figure 8 As shown;

[0045] Step 8. Use the first mask 30 to etch the oxide layer through a photolithography process to form an ohmic contact window above the first conductive type active area 2 and the second conductive type active area 3. Figure 9 As shown;

[0046] Step 9. Use electron beam evaporation process to deposit metal nickel on the ohmic contact window to form a metal nickel layer, such as Figure 10 As shown;

[0047] Step 10. Annealing the device in step 9 at 950° C. to 1050° C. so that the metal nickel layer forms a low-resistance ohmic contact electrode with the first conductive type active region 2 and the second conductive type active region 3;

[0048] Step 11. Use the second mask 31 to etch the oxide layer through a photolithography process to form a Schottky contact window above the first conductivity type lightly doped region 4 on the left side and a gate contact window above the polysilicon gate. Figure 11 As shown; in the silicon carbide process, the ideal metal for Schottky contact is titanium, and the metal of the gate contact hole and the ohmic contact hole can also be connected with titanium. Therefore, in order to reduce production costs, the Schottky contact layer and the gate contact layer are prepared at the same time in the process design;

[0049] Step 12. Use the first mask 30 and the second mask 31 again, and use the electron beam evaporation process to deposit metal titanium in the Schottky contact window and the gate contact window to form a metal titanium layer. The metal titanium layer forms a Schottky contact with the first conductive type lightly doped region, and the metal titanium layer forms an ohmic contact with the polysilicon gate; the combination of the first mask 30 and the second mask 31 forms the effect of the third mask 32, as shown in FIG. Figure 12 As shown;

[0050] Step 13. Anneal the device in step 12 at 400-600° C. to obtain a silicon carbide field-effect power transistor with an integrated Schottky diode.

[0051] In this embodiment, the first conductive type region is an N-type impurity doped region, and the second conductive type region is a P-type impurity doped region; it should be noted that, in other embodiments, the first conductive type region may be a P-type impurity doped region, and the second conductive type region may correspond to an N-type impurity doped region.

[0052] The above description is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode, characterized in that: The following steps are involved: Step 1: Using the oxide layer as a patterned shielding layer, perform first conductivity type lightly doped ion implantation on the silicon carbide substrate to form first conductivity type lightly doped regions on both sides of the silicon carbide substrate. Step 2. The first conductivity type lightly doped region is shielded again with an oxide layer, and second conductivity type lightly doped ions are implanted on the silicon carbide substrate to form a second conductivity type well region between the first conductivity type lightly doped regions on both sides. Step 3. Using a self-aligned process to perform ion implantation mask growth, a mask is formed on the oxide layer and the areas on both sides of the second conductivity type well region in step 2, and first conductivity type heavily doped ions are implanted on the second conductivity type well region to form a first conductivity type active region in the middle area above the second conductivity type well region; Step 4. Using the oxide layer as a patterned shielding layer again, heavily doped ions of the second conductivity type are implanted into the second conductivity type well region to form a second conductivity type active region adjacent to the left side of the first conductivity type active region, with the left side of the second conductivity type active region adjacent to the first conductivity type lightly doped region; Step 5. Annealing the device in step 4 under a preset temperature condition; Step 6. Depositing an oxide layer on the device surface to cover a portion of the upper right side of the second conductivity type active region, the first conductivity type well region to the right of the second conductivity type active region, and the first conductivity type lightly doped region to the right, and then depositing a polysilicon gate on the oxide layer; Step 7. Deposit an oxide layer again on the device surface to cover the entire device; Step 8. Using the first mask, the oxide layer is etched by photolithography to form ohmic contact windows above the first conductivity type active region and the second conductivity type active region; Step 9. Depositing metallic nickel in the ohmic contact window using an electron beam evaporation process to form a metallic nickel layer, wherein the metallic nickel layer forms ohmic contacts with the first conductive type active region and the second conductive type active region; Step 10. Annealing the device in step 9 under a preset temperature condition; Step 11. Using a second mask, etch the oxide layer through a photolithography process to form a Schottky contact window above the first conductivity type lightly doped region 4 on the left side and a gate contact window above the polysilicon gate; Step 12. Using the first mask again, titanium is deposited on the nickel layer to form a titanium layer. The titanium layer forms an ohmic contact with the nickel layer. Using the second mask again, titanium is deposited in the Schottky contact window and the gate contact window to form a titanium layer. The titanium layer forms a Schottky contact with the first conductivity type lightly doped region, and the titanium layer forms an ohmic contact with the polysilicon gate. Step 13. Anneal the device in step 12 under preset temperature conditions to obtain a silicon carbide field-effect power transistor with an integrated Schottky diode.

2. The method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode according to claim 1, wherein: The annealing temperature in step 5 is 1700°C.

3. The method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode according to claim 1, wherein: The annealing temperature in step 10 is 950°C to 1050°C.

4. The method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode according to claim 1, wherein: The annealing temperature in step 13 is 400-600°C.

5. The method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode according to claim 1, wherein: The oxide layer is deposited using a low-pressure chemical vapor deposition (LPCVD) process.

6. The method for preparing a silicon carbide field effect power transistor with an integrated Schottky diode according to claim 1, wherein: The metal nickel layer and the metal titanium layer are deposited by electron beam evaporation process.

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