Array substrate and display panel

Abstract

An embodiment of the present application provides an array substrate and a display panel. The array substrate comprises an interlayer insulating layer including a first insulating layer. The nitrogen content in the interlayer insulating layer and the first insulating layer located in the light-transmitting area is less than the oxygen content. This can at least reduce the silicon nitride material in the interlayer insulating layer located in the light-transmitting area, thereby improving the transmittance of the light-transmitting area. In addition, the hydrogen atom content per unit volume of the portion of the first insulating layer close to the gate layer is less than the hydrogen atom content per unit volume of the portion of the first insulating layer far from the gate layer. When forming the array substrate, hydrogen can be replenished in the active layer by diffusion, so that the electrical performance of the active layer is better, thereby taking into account both the transmittance and performance stability of the array substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] TFT-LCDs (thin film transistor-liquid crystal displays) are widely used due to their long lifespan, mature technology, and low price. Existing LCD devices use drive circuits based on LTPS (low-temperature polysilicon) technology to power their display panels. However, in actual use, these devices have been found to have low transmittance. To improve transmittance, existing LCD devices often adjust the film structure, but this can have adverse effects.

[0003] Therefore, existing liquid crystal display devices have the technical problem of being unable to balance light transmittance and performance stability. Summary of the Invention

[0004] The embodiments of the present application provide an array substrate and a display panel to solve the technical problem of existing liquid crystal display devices that cannot balance light transmittance and performance stability.

[0005] To achieve the above-mentioned object, according to a first aspect of the present application, an array substrate is provided, the array substrate including a pixel region, the pixel region including a light-transmitting region and a non-light-transmitting region located on at least one side of the light-transmitting region, the array substrate comprising:

[0006] substrate;

[0007] An active layer is provided on one side of the substrate;

[0008] a gate layer, disposed on a side of the active layer away from the substrate;

[0009] an interlayer insulating layer, disposed on a side of the gate layer away from the active layer, the interlayer insulating layer comprising a first insulating layer, wherein a nitrogen content in the interlayer insulating layer and the first insulating layer located in the light-transmitting region is less than a content of oxygen;

[0010] The hydrogen content per unit volume of a portion of the first insulating layer close to the gate layer is smaller than the hydrogen content per unit volume of a portion of the first insulating layer far from the gate layer.

[0011] Optionally, the array substrate further includes a source-drain layer, which is arranged on a side of the interlayer insulating layer away from the gate layer, one side of the first insulating layer is in direct contact with the source-drain layer, and the other side of the first insulating layer is in direct contact with the gate layer.

[0012] Optionally, the interlayer insulating layer further includes a second insulating layer, the material of the second insulating layer is silicon nitride, the second insulating layer is arranged on a side of the first insulating layer away from the gate layer, and the second insulating layer is arranged in the non-light-transmitting area.

[0013] Optionally, the array substrate further includes a source-drain layer, the width of the surface of the source-drain layer on the side in contact with the second insulating layer is equal to the width of the surface of the second insulating layer on the side in contact with the source-drain layer, and the sidewalls of the source-drain layer and the corresponding sidewalls of the second insulating layer are on the same plane.

[0014] Optionally, the array substrate further includes a source-drain electrode layer, and a width of a surface of the source-drain electrode layer in contact with the second insulating layer is smaller than a width of a surface of the second insulating layer in contact with the source-drain electrode layer.

[0015] Optionally, an angle between a sidewall of the source / drain layer and a bottom surface of the source / drain layer is smaller than or equal to an angle between a sidewall of the second insulating layer and a bottom surface of the second insulating layer.

[0016] Optionally, the material of the first insulating layer includes silicon oxide.

[0017] Optionally, the array substrate further includes a buffer layer, which is disposed between the substrate and the active layer, and a portion of the buffer layer located in the light-transmitting area is made of silicon oxide.

[0018] Optionally, the buffer layer includes a third insulating layer and a fourth insulating layer, the third insulating layer is made of silicon oxide, the fourth insulating layer is made of silicon nitride, and the fourth insulating layer is disposed in the non-light-transmitting area.

[0019] Optionally, the array substrate further includes a light shielding layer, which is arranged between the fourth insulating layer and the substrate, the fourth insulating layer is arranged between the light shielding layer and the third insulating layer, and the fourth insulating layer covers the light shielding layer.

[0020] Optionally, the array substrate further includes a light shielding layer, the fourth insulating layer is arranged between the light shielding layer and the substrate, and the third insulating layer is arranged on a side of the light shielding layer away from the fourth insulating layer.

[0021] Optionally, the projection of the surface of the light-shielding layer close to the fourth insulating layer on the substrate coincides with the projection of the surface of the fourth insulating layer close to the light-shielding layer on the substrate, and the side wall of the light-shielding layer and the corresponding side wall in the fourth insulating layer are on the same plane.

[0022] Optionally, the buffer layer includes a third insulating layer, the array substrate further includes a light-shielding layer, one side of the third insulating layer is in contact with the light-shielding layer, and the other side of the third insulating layer is in contact with the active layer, and the material of the portion of the buffer layer located in the non-light-transmitting area is silicon oxide.

[0023] Optionally, the array substrate further includes a source-drain electrode layer, a planarization layer, a first electrode layer, a passivation layer, and a second electrode layer, wherein the source-drain electrode layer is arranged on a side of the interlayer insulating layer away from the gate layer, the planarization layer is arranged on a side of the source-drain electrode layer away from the interlayer insulating layer, the first electrode layer is arranged on a side of the planarization layer away from the source-drain electrode layer, the passivation layer is arranged on a side of the first electrode layer away from the planarization layer, and the second electrode layer is arranged on a side of the passivation layer away from the first electrode layer;

[0024] Wherein, the material of the passivation layer is silicon oxide or silicon oxynitride.

[0025] According to a second aspect of the present application, a display panel is provided, comprising the array substrate as described in any one of the above embodiments.

[0026] An embodiment of the present application provides an array substrate and a display panel. The array substrate comprises an interlayer insulating layer including a first insulating layer. The nitrogen content in the interlayer insulating layer and the first insulating layer located in the light-transmitting area is less than the oxygen content. This can at least reduce the silicon nitride material in the interlayer insulating layer located in the light-transmitting area, thereby improving the transmittance of the light-transmitting area. In addition, the hydrogen atom content per unit volume of the portion of the first insulating layer close to the gate layer is less than the hydrogen atom content per unit volume of the portion of the first insulating layer far from the gate layer. When forming the array substrate, hydrogen can be replenished in the active layer by diffusion, so that the electrical performance of the active layer is better, thereby taking into account both the transmittance and performance stability of the array substrate.

[0027] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0029] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0030] Figure 1 Schematic diagram of a comparative display device provided in an embodiment of the present application.

[0031] Figure 2 A schematic plan view of an array substrate provided in an embodiment of the present application.

[0032] Figure 3 This is a first cross-sectional schematic diagram of an array substrate provided in an embodiment of the present application.

[0033] Figure 4 This is a second cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0034] Figure 5 This is a third cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0035] Figure 6 This is a fourth cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0036] Figure 7 This is a fifth cross-sectional schematic diagram of the array substrate provided in an embodiment of the present application.

[0037] Figure 8 This is a schematic structural diagram of an array substrate corresponding to each step of the method for preparing an array substrate provided in an embodiment of the present application.

[0038] Figure 9 This is a comparison curve diagram of the hydrogen atom concentration in a comparative display device formed by using a rapid thermal annealing process and not using a rapid thermal annealing process provided in an embodiment of the present application.

[0039] Figure 10 Schematic diagram of the diffusion of hydrogen elements in a comparative display device and an array substrate provided in an embodiment of the present application.

[0040] Figure 11 This is a comparison chart of the threshold voltage, mobility and on-state current of the comparative display device and array substrate provided in the embodiments of the present application.

[0041] Figure 12 This is a comparison chart of the subthreshold swing and leakage current of the display device and array substrate provided in the embodiments of the present application.

[0042] Figure 13 A schematic diagram of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0044] In order to illustrate the principle of the technical problem in the embodiment of the present application, a comparative display device is provided. It is understood that the comparative display device cannot be regarded as the prior art of the present application. Figure 1 As shown, the comparative display device includes a substrate 111, a shading metal 112, a silicon nitride buffer film 113a, a silicon oxide buffer film 113b, a semiconductor film 114, a gate insulating film 115, a gate film 116, a silicon nitride interlayer insulating film 117a, a silicon oxide interlayer insulating film 117b, a source and drain film 118, a planarization film 119, a first electrode film 121, a passivation film 122 and a second electrode film 123. The material of the silicon nitride buffer film 113a is silicon nitride, the material of the silicon oxide buffer film 113b is silicon oxide, the material of the silicon nitride interlayer insulating film 117a is silicon nitride, and the material of the silicon oxide interlayer insulating film 117b is silicon oxide. To prevent ions from diffusing from substrate 111 into semiconductor film 114, which could alter the performance of the thin-film transistor, the comparative display device utilizes a buffer film stacked with a silicon nitride buffer film and a silicon oxide buffer film. The silicon nitride blocks ions from substrate 111. Furthermore, to increase the hydrogen content in semiconductor film 114, the interlayer insulating film utilizes a stacked structure of a silicon nitride interlayer insulating film 117a and a silicon oxide interlayer insulating film 117b. However, because silicon nitride has a lower light transmittance than silicon oxide, and the interface between silicon nitride and silicon oxide causes light to refract, further reducing the refractive index, the comparative display device exhibits lower light transmittance.

[0045] To address these issues, some comparative display devices modify the film structure to improve their light transmittance, but this can lead to poor performance of thin-film transistors. Consequently, existing liquid crystal display devices suffer from the technical problem of being unable to balance light transmittance with performance stability.

[0046] like Figures 2 to 7As shown, an embodiment of the present application provides an array substrate, the array substrate 2 including a pixel area 201, the pixel area 201 including a light-transmitting area 201a and a non-light-transmitting area 201b located on at least one side of the light-transmitting area 201a, the array substrate 2 including a substrate 211, an active layer 214, a gate layer 216 and an interlayer insulating layer 217; the active layer 214 is arranged on one side of the substrate 211; the gate layer 216 is arranged on a side of the active layer 214 away from the substrate 211; the interlayer insulating layer 217 is arranged on a side of the gate layer 216 away from the active layer 214, the interlayer insulating layer 217 includes a first insulating layer 217a, and the nitrogen content in the interlayer insulating layer and the first insulating layer located in the light-transmitting area 201a is less than the oxygen content;

[0047] The hydrogen content per unit volume of the portion of the first insulating layer 217 a close to the gate layer 216 is smaller than the hydrogen content per unit volume of the portion of the first insulating layer 217 a far from the gate layer 216 .

[0048] An embodiment of the present application provides an array substrate, which comprises an interlayer insulating layer including a first insulating layer. The interlayer insulating layer and the first insulating layer located in the light-transmitting area have nitrogen contents less than oxygen contents, thereby at least reducing the silicon nitride material located in the light-transmitting area in the interlayer insulating layer, thereby improving the transmittance of the light-transmitting area. In addition, the content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. When forming the array substrate, hydrogen can be replenished in the active layer by diffusion, so that the electrical performance of the active layer is better, thereby taking into account both the transmittance and performance stability of the array substrate.

[0049] Specifically, the proportion of hydrogen per unit volume can be detected by mass spectrometry analysis to compare the hydrogen content per unit volume of different parts.

[0050] Specifically, such as Figure 2 As shown, the array substrate 2 includes a pixel area 201 and a non-pixel area 202 arranged on at least one side of the pixel area 201. It can be understood that the pixel area corresponds to the display area in the display panel, and the non-pixel area corresponds to the non-display area in the display panel.

[0051] Specifically, such as Figure 2 As shown, the non-pixel area 202 is arranged around the pixel area 201, but the embodiment of the present application is not limited thereto. The non-pixel area 202 can be arranged on one side, two sides or three sides of the pixel area 201.

[0052] Specifically, such as Figure 3 As shown, Figure 3As shown in the figure, the light-transmitting area 201a is located on one side of the non-light-transmitting area 201b. In actual design, the non-light-transmitting area 201b can be arranged around the light-transmitting area 201a.

[0053] Specifically, the array substrate includes thin film transistors.

[0054] In some embodiments, the material of the first insulating layer includes silicon oxide, and the silicon nitride material in the light-transmitting region of the interlayer insulating layer may be reduced or removed, thereby improving the light transmittance of the light-transmitting region.

[0055] Specifically, the material of the portion of the interlayer insulating layer located in the light-transmitting area can be made of silicon oxide, and the silicon nitride material in the interlayer insulating layer located in the light-transmitting area can be removed to improve the transmittance of the light-transmitting area. Alternatively, the silicon nitride in the portion of the interlayer insulating layer located in the light-transmitting area can be made less than silicon oxide, for example, by reducing the thickness of the silicon nitride material, thereby improving the transmittance of the light-transmitting area.

[0056] In some embodiments, as Figure 4 As shown, the array substrate 2 further includes a source-drain electrode layer 218, which is disposed on a side of the interlayer insulating layer 217 away from the gate layer 216. One side of the first insulating layer 217a is in direct contact with the source-drain electrode layer 218, and the other side of the first insulating layer 217a is in direct contact with the gate layer 216. By having one side of the first insulating layer in direct contact with the source-drain electrode layer and the other side of the first insulating layer in direct contact with the gate layer, the interlayer insulating layer can include only one first insulating layer, eliminating the silicon nitride layer, improving the light transmittance of the array substrate and reducing the thickness of the array substrate. Furthermore, the hydrogen content per unit volume of the portion of the first insulating layer near the gate layer is lower than the hydrogen content per unit volume of the portion of the first insulating layer away from the gate layer, allowing hydrogen atoms to diffuse into the active layer to replenish hydrogen in the active layer, thereby improving the electrical performance of the active layer, thereby achieving both light transmittance and performance stability of the array substrate.

[0057] Specifically, compared with the current display device, the silicon nitride interlayer insulating film is arranged between the silicon oxide interlayer insulating film and the gate layer. If the silicon nitride interlayer insulating film is removed and only the silicon oxide interlayer insulating film is formed, there will be no hydrogen element to replenish the active layer, which will lead to poor performance of the active layer. In the embodiment of the present application, the hydrogen element content per unit volume of the portion of the first insulating layer close to the gate layer is less than the hydrogen element content per unit volume of the portion of the first insulating layer far from the gate layer. When forming the array substrate, a hydrogen-containing film layer (such as a silicon nitride layer) can be provided on the first insulating layer to allow the hydrogen in the hydrogen-containing film layer to diffuse downward to the active layer to replenish the active layer with hydrogen, and then the hydrogen-containing film layer can be removed or partially removed. Therefore, when achieving normal hydrogen replenishment of the active layer, the transmittance of the array substrate is improved, thereby taking into account both the transmittance and performance stability of the array substrate.

[0058] In some embodiments, as Figure 3 、 Figure 5 As shown, the interlayer insulating layer 217 further includes a second insulating layer 217b. The material of the second insulating layer 217b is silicon nitride. The second insulating layer 217b is disposed on the side of the first insulating layer 217a away from the gate layer 216. The second insulating layer 217b is disposed within the non-light-transmitting area 201b. By including a second insulating layer in the interlayer insulating layer, the second insulating layer is disposed on the side of the first insulating layer away from the gate layer, and the second insulating layer is disposed within the non-light-transmitting area, the light transmittance of the array substrate can be improved by removing the portion of the second insulating layer located in the light-transmitting area. The second insulating layer is disposed on the first insulating layer, which facilitates the removal of the portion of the second insulating layer located in the light-transmitting area. This can also improve color shift and enhance display quality.

[0059] Specifically, compared with the second insulating layer being set between the first insulating layer and the gate layer, when the second insulating layer is patterned or removed, it is necessary to first pattern the second insulating layer or remove the second insulating layer before forming the first insulating layer, which will result in poor hydrogen replenishment effect and a more complicated process; while in the embodiment of the present application, the first insulating layer is set between the second insulating layer and the gate layer, then after the first insulating layer and the second insulating layer are formed, the active layer can be hydrogen replenished first, and then the second insulating layer can be patterned or removed. Since the hydrogen replenishment is completed, the performance of the active layer is better, and the removal or patterning of the second insulating layer has little effect, and the second insulating layer can be etched, patterned or removed at the same time as other film layers, simplifying the process.

[0060] Specifically, the second insulating layer may be provided on the entire surface of the non-light-transmitting area.

[0061] In some embodiments, the source and drain electrode layer and the second insulating layer can be etched through the same mask; thus, no additional mask is required, thereby reducing process steps and costs.

[0062] In some embodiments, as Figure 3 、 Figure 5As shown, the array substrate 2 further includes a source-drain electrode layer 218. The width of the surface of the source-drain electrode layer 218 on the side in contact with the second insulating layer 217b is equal to the width of the surface of the second insulating layer 217b on the side in contact with the source-drain electrode layer 218. The sidewalls of the source-drain electrode layer 218 and the corresponding sidewalls of the second insulating layer 217b are coplanar. By ensuring that the width of the surface of the source-drain electrode layer on the side in contact with the second insulating layer is equal to the width of the surface of the second insulating layer on the side in contact with the source-drain electrode layer, and that the sidewalls of the source-drain electrode layer and the corresponding sidewalls of the second insulating layer are coplanar, the source-drain electrode layer and the second insulating layer can be etched simultaneously without adding a new mask, reducing process steps and improving the efficiency of array substrate preparation.

[0063] In some embodiments, as Figure 7 As shown, the array substrate 2 further includes a source-drain electrode layer 218. The width of the surface of the source-drain electrode layer 218 in contact with the second insulating layer 217b is smaller than the width of the surface of the second insulating layer 217b in contact with the source-drain electrode layer 218. By making the width of the surface of the second insulating layer in contact with the source-drain electrode layer larger than the width of the surface of the source-drain electrode layer in contact with the second insulating layer, a stepped structure is formed between the second insulating layer and the source-drain electrode layer. This prevents the formation of chamfers or undercuts between the second insulating layer and the source-drain electrode layer, which could result in an inability to fill the chamfers or undercuts and lead to poor display or reduced reliability.

[0064] In some embodiments, as Figure 7 As shown, the angle a1 between the sidewall of the source / drain electrode layer 218 and the bottom surface of the source / drain electrode layer 218 is less than or equal to the angle a2 between the sidewall of the second insulating layer 217b and the bottom surface of the second insulating layer 217b. When forming the source / drain electrode layer and the second insulating layer, the second insulating layer can be formed first, and then the source / drain electrode layer can be formed on the second insulating layer. Due to the stacking of the film layers, the slope angle of the source / drain layer can be less than or equal to the slope angle of the second insulating layer, resulting in a gentler slope of each film layer.

[0065] Specifically, the above embodiment is described by taking the angle a1 between the side wall of the source-drain layer 218 and the bottom surface of the source-drain layer 218 as less than or equal to the angle a2 between the side wall of the second insulating layer 217b and the bottom surface of the second insulating layer 217b as an example, but the embodiments of the present application are not limited to this, and the angle between the side wall of the source-drain layer and the bottom surface of the source-drain layer can be greater than the angle between the side wall of the second insulating layer and the bottom surface of the second insulating layer.

[0066] Specifically, the angle between the sidewall of the source / drain layer 218 and the bottom surface of the source / drain layer 218 is in a range of 10 degrees to 55 degrees.

[0067] Specifically, when using the same mask to form the source / drain layer and the second insulating layer, the etching rate can be controlled so that the second insulating layer extends beyond the source / drain layer, thereby avoiding the formation of chamfers or undercuts between the second insulating layer and the source / drain layer, thereby improving the yield and reliability of the array substrate. Furthermore, when using the same mask to form the source / drain layer and the second insulating layer, the etching rate can be controlled so that the width of the surface of the source / drain layer in contact with the second insulating layer is equal to the width of the surface of the second insulating layer in contact with the source / drain layer, thereby improving the aperture ratio of the array substrate.

[0068] Specifically, when the same mask is used to form the source-drain layer and the second insulating layer, the etching rate can be controlled so that the angle between the side wall of the source-drain layer and the bottom surface of the source-drain layer is less than or equal to the angle between the side wall of the second insulating layer and the bottom surface of the second insulating layer; the etching rate can also be controlled so that the angle between the side wall of the source-drain layer and the bottom surface of the source-drain layer is greater than the angle between the side wall of the second insulating layer and the bottom surface of the second insulating layer.

[0069] Specifically, the embodiment of the present application is described by taking the upper surface of part of the film layer as a flat surface as an example. It can be understood that due to the patterning of part of the film layer, when the thickness of the film layer is made more uniform, part of the film layer will form steps, for example, Figure 6 In the embodiment, the fourth insulating layer 213a and the light shielding layer 212 in the buffer layer are patterned so that when the third insulating layer 213b is formed, the third insulating layer will form multiple portions of different heights at the locations where the fourth insulating layer 213a and the light shielding layer 212 are set, so that steps are formed between the portions. That is, multiple portions of the upper surface of the buffer layer are located on different horizontal planes, and there is a height difference between the portions and the portions are connected to each other to form steps. Accordingly, steps are formed in the active layer. Similarly, steps are also formed for other film layers, which will not be described in detail here. It can be understood that for each embodiment, steps can be formed in the areas corresponding to the patterned other film layers.

[0070] Specifically, it can be understood that when the substrate to the second electrode layer are formed in sequence, due to the accumulation of the film layers, when the film layers are patterned, due to the accumulation of the film layers, the climbing angles of the film layers can be gradually slowed down.

[0071] Specifically, after forming the source / drain electrode layer and the second insulating layer, the source / drain electrode layer and the second insulating layer can be etched simultaneously through the same mask plate without adding a new mask plate, and only the portion of the second insulating layer located under the source / drain electrode layer is retained, which can further improve the light transmittance of the array substrate. Figure 3As shown, it can be seen that the width of the bottom surface of the source and drain layer in contact with the second insulating layer is equal to the width of the top surface of the second insulating layer in contact with the source and drain layer, that is, the spacing from the left to the right side of the bottom surface of the source and drain layer is equal to the spacing from the left to the right side of the top surface of the second insulating layer. It can be understood that due to the difference in etching rates of different materials, there may be slight differences between the width of the bottom surface of the source and drain layer in contact with the second insulating layer and the width of the top surface of the second insulating layer in contact with the source and drain layer. At this time, it is still considered that the width of the bottom surface of the source and drain layer in contact with the second insulating layer is equal to the width of the top surface of the second insulating layer in contact with the source and drain layer.

[0072] Specifically, it can be understood that when the same mask plate is used to pattern the source and drain layer and the second insulating layer, due to process limitations, there may be certain differences in the edges of the various patterns of the source and drain layer and the second insulating layer. For example, during etching, the edges of each pattern will form a climbing area. Due to the difference in etching rates of different materials, the climbing angles of the side walls of the pattern of the second insulating layer located at the lower layer and the side walls of the pattern of the source and drain layer may have certain differences. The planes where the two are located may have a certain inclination and are not completely located in the same plane. At this time, the side walls of the source and drain layers are still defined as being on the same plane as the corresponding side walls in the second insulating layer.

[0073] Specifically, Figure 3 and Figure 5 Part of the structure of the source and drain layer, such as the source, drain and touch metal, is shown, and the second insulating layer located under the source, drain and touch metal is correspondingly shown. It can be understood that when the source and drain layer also includes other structures, part of the second insulating layer is correspondingly provided under the other structures.

[0074] In some embodiments, as Figures 3 to 5 As shown, the array substrate 2 further includes a buffer layer 213, which is disposed between the substrate 211 and the active layer 214. The portion of the buffer layer 213 located in the light-transmitting region 201a is made of silicon oxide. By making the portion of the buffer layer located in the light-transmitting region of silicon oxide and removing the silicon nitride in the buffer layer located in the light-transmitting region, the light transmittance of the array substrate can be further improved.

[0075] Specifically, the buffer layer in the current display device is a stack of silicon nitride and silicon oxide. The embodiment of the present application makes the material of the portion of the buffer layer located in the light-transmitting area silicon oxide, removes the silicon nitride in the buffer layer located in the light-transmitting area, and improves the transmittance of the array substrate.

[0076] In some embodiments, as Figures 3 and 4 、 Figure 6As shown, the buffer layer 213 includes a third insulating layer 213b and a fourth insulating layer 213a. The third insulating layer 213b is made of silicon oxide, and the fourth insulating layer 213a is made of silicon nitride. The fourth insulating layer 213a is disposed within the non-light-transmitting region 201b. By including the third and fourth insulating layers in the buffer layer and disposing the fourth insulating layer within the non-light-transmitting region, the portion of the fourth insulating layer located in the light-transmitting region can be removed, thereby improving the light transmittance of the array substrate. Furthermore, the portion of the fourth insulating layer located in the non-light-transmitting region can block ions in the substrate, preventing them from diffusing into the active layer and causing performance changes, thereby improving the performance stability of the array substrate. This balance between light transmittance and performance stability is achieved.

[0077] Specifically, the entire fourth insulating layer may be disposed in the non-light-transmitting area.

[0078] Specifically, compared with the current display device in which the buffer layer is a stack of silicon nitride and silicon oxide, directly removing the silicon nitride layer will cause the performance of the active layer to change. The fourth insulating layer can be set in the non-light-transmitting area to protect the active layer and improve the performance stability of the array substrate.

[0079] Specifically, the fourth insulating layer may be provided corresponding to the active layer.

[0080] In some embodiments, as Figure 3 、 Figure 4 As shown, the array substrate 2 further includes a light-shielding layer 212, which is disposed between the fourth insulating layer 213a and the substrate 211, and between the fourth insulating layer 213a and the third insulating layer 213b, with the fourth insulating layer 213a covering the light-shielding layer 212. By disposing the light-shielding layer between the fourth insulating layer and the substrate, the fourth insulating layer between the light-shielding layer and the third insulating layer, and the fourth insulating layer covering the light-shielding layer, the fourth insulating layer can block ions in the substrate from diffusing to the active layer, thereby blocking the path for ions to diffuse from the light-shielding layer to the active layer, thereby improving the performance stability of the array substrate.

[0081] Specifically, when forming the fourth insulating layer, a photomask may be used to pattern the fourth insulating layer, thereby removing the fourth insulating layer in the light-transmitting area and retaining the fourth insulating layer in other areas.

[0082] Specifically, only the portion of the fourth insulating layer corresponding to the active layer may be retained to further improve the light transmittance of the array substrate.

[0083] In some embodiments, as Figure 6As shown, the array substrate 2 further includes a light-shielding layer 212, the fourth insulating layer 213a is disposed between the light-shielding layer 212 and the substrate 211, and the third insulating layer 213b is disposed on a side of the light-shielding layer 212 away from the fourth insulating layer 213a. By disposing the fourth insulating layer between the light-shielding layer and the substrate, and disposing the fourth insulating layer on a side of the light-shielding layer away from the fourth insulating layer, the fourth insulating layer can prevent ions in the substrate from diffusing into the active layer, thereby improving the performance stability of the array substrate.

[0084] In some embodiments, as Figure 6 As shown, the projection of the surface of the light-shielding layer 212 on the side close to the fourth insulating layer 213a on the substrate 211 overlaps with the projection of the surface of the fourth insulating layer 213a on the side close to the light-shielding layer 212 on the substrate 211, and the sidewalls of the light-shielding layer 212 and the corresponding sidewalls of the fourth insulating layer 213a are coplanar. By making the projection of the surface of the light-shielding layer on the substrate close to the fourth insulating layer overlap with the projection of the surface of the fourth insulating layer on the substrate close to the light-shielding layer, the sidewalls of the light-shielding layer and the corresponding sidewalls of the fourth insulating layer are coplanar, and the light-shielding layer and the fourth insulating layer can be etched simultaneously without adding a new mask, reducing process steps and improving the production efficiency of the array substrate.

[0085] Specifically, after forming the fourth insulating layer and the light-shielding layer, the same mask can be used to etch the fourth insulating layer and the light-shielding layer without adding a new mask, and only the portion of the fourth insulating layer located under the light-shielding layer is retained, which can further improve the transmittance of the array substrate.

[0086] Specifically, it can be understood that when the same mask is used to pattern the fourth insulating layer and the light-shielding layer, due to process limitations, there may be certain differences in the edges of the various patterns of the fourth insulating layer and the light-shielding layer. For example, during etching, the edges of each pattern will form a climbing area. Due to the differences in the etching rates of different materials, the climbing angles of the side walls of the pattern of the fourth insulating layer located in the lower layer and the side walls of the pattern of the light-shielding layer may have certain differences, and the planes where the two are located may have a certain inclination and are not completely located in the same plane. At this time, the side walls of the light-shielding layer are still defined as being on the same plane as the corresponding side walls in the fourth insulating layer.

[0087] Specifically, the projection of the fourth insulating layer on the substrate can be made larger than the projection of the light-shielding layer on the substrate. The fourth insulating layer and the light-shielding layer can be etched through a semi-transparent mask to reduce the process steps. The projection of the fourth insulating layer on the substrate can be made larger than the projection of the light-shielding layer on the substrate, thereby further preventing ions in the substrate from diffusing into the active layer and improving the performance stability of the array substrate.

[0088] In some embodiments, as Figure 5 As shown, the buffer layer 213 includes a third insulating layer 213b, and the material of the third insulating layer 213b is silicon oxide. The array substrate 2 also includes a light shielding layer 212, one side of the third insulating layer 213b is in contact with the light shielding layer 212, and the other side of the third insulating layer 213b is in contact with the active layer 214. The portion of the buffer layer 213 located in the non-light-transmitting area 201b is made of silicon oxide. By making the buffer layer only include the third insulating layer, the light transmittance of the array substrate can be further improved. Since the silicon nitride material in the buffer layer does not need to be etched, a mask plate can be saved, the process steps can be reduced, and the production efficiency of the array substrate can be improved.

[0089] In some embodiments, as Figures 3 to 6 As shown, the array substrate 2 further includes a source-drain electrode layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222, and a second electrode layer 223. The source-drain electrode layer 218 is disposed on a side of the interlayer insulating layer 217 away from the gate layer 216, the planarization layer 219 is disposed on a side of the source-drain electrode layer 218 away from the interlayer insulating layer 217, the first electrode layer 221 is disposed on a side of the planarization layer 219 away from the source-drain electrode layer 218, the passivation layer 222 is disposed on a side of the first electrode layer 221 away from the planarization layer 219, and the second electrode layer 223 is disposed on a side of the passivation layer 222 away from the first electrode layer 221. The passivation layer 222 is made of silicon oxide or silicon oxynitride. By making the passivation layer of silicon oxide or silicon oxynitride, the light transmittance of the array substrate can be further improved.

[0090] Specifically, the above embodiment is described by taking the array substrate including the first electrode layer and the second electrode layer as an example, but the embodiments of the present application are not limited thereto, and the array substrate may have only the first electrode layer or the second electrode layer.

[0091] Specifically, simulations of array substrates have shown that, compared to comparative display devices, the present embodiment can improve the light transmittance of the array substrate by 3% by removing the silicon nitride material in the light-transmitting region of the buffer layer and the silicon nitride material in the light-transmitting region of the interlayer insulating layer. Furthermore, by changing the passivation layer material from silicon nitride to silicon oxide or silicon oxynitride, the light transmittance of the array substrate can be increased by 5%, thereby improving the light transmittance of the array substrate and reducing power consumption.

[0092] Specifically, the array substrate 2 further includes a gate insulating layer 215 , which is disposed between the active layer 214 and the gate layer 216 .

[0093] Specifically, the material of the substrate includes glass.

[0094] Specifically, the material of the gate insulating layer may be silicon oxide.

[0095] Specifically, the active layer is made of low-temperature polysilicon. The active layer 214 includes a channel portion 214a, a lightly doped portion 214b, and a heavily doped portion 214c. The doping ion concentration of the heavily doped portion 214c is greater than that of the lightly doped portion.

[0096] Specifically, the materials of the light shielding layer, the gate layer and the source and drain electrode layers may be metals, such as a stack of titanium, aluminum and titanium, or a titanium layer and an aluminum layer.

[0097] Specifically, the material of the first electrode layer and the second electrode layer may be indium tin oxide.

[0098] Specifically, the hydrogen content per unit volume from the portion of the first insulating layer away from the gate layer to the portion of the first insulating layer close to the gate layer is in the range of 1e 22 hydrogen atoms / cm3 to 1e 21 hydrogen atoms / cubic centimeter, and the hydrogen content per unit volume of the portion of the first insulating layer away from the gate layer can be greater than 1e 22 hydrogen atoms per cubic centimeter.

[0099] Specifically, the above embodiments provide a detailed description of the array substrate from the perspective of different film layers and the relative positions and connection relationships of each film layer. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the array substrate also includes a source-drain layer, and the source-drain layer is arranged on the side of the interlayer insulating layer away from the gate layer. One side of the first insulating layer is in direct contact with the source-drain layer, and the other side of the first insulating layer is in direct contact with the gate layer. The array substrate also includes a buffer layer, and the buffer layer is arranged between the substrate and the active layer. The material of the portion of the buffer layer located in the light-transmitting area is silicon oxide.

[0100] Specifically, such as Figure 3As shown, the array substrate 2 includes a substrate 211, a light-shielding layer 212, a fourth insulating layer 213a, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a second insulating layer 217b, a source-drain layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222, and a second electrode layer 223, which are arranged in sequence. The content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. By arranging the fourth insulating layer in the buffer layer in the non-light-transmitting area, the transmittance of the array substrate can be improved, and the fourth insulating layer can block ions in the substrate from entering the active layer, thereby improving the performance of the array substrate. The projection of the second insulating layer on the substrate is made to coincide with the projection of the source-drain layer on the substrate, thereby improving the transmittance of the array substrate without adding a mask plate and process.

[0101] Specifically, such as Figure 4 As shown, the array substrate 2 includes a substrate 211, a light-shielding layer 212, a fourth insulating layer 213a, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a source-drain layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222 and a second electrode layer 223, which are arranged in sequence. The content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. By setting the fourth insulating layer in the buffer layer in the non-light-transmitting area, the transmittance of the array substrate can be improved, and the fourth insulating layer can block ions in the substrate from entering the active layer, thereby improving the performance of the array substrate. The interlayer insulating layer is made to include only the first insulating layer, which can improve the transmittance of the array substrate.

[0102] Specifically, such as Figure 5 As shown, the array substrate 2 includes a substrate 211, a light-shielding layer 212, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a second insulating layer 217b, a source-drain layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222 and a second electrode layer 223, which are arranged in sequence. The content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than the content of hydrogen atoms per unit volume of the portion of the first insulating layer far from the gate layer. By making the buffer layer only include the third insulating layer, the transmittance of the array substrate can be improved, and the projection of the second insulating layer on the substrate is made to coincide with the projection of the source-drain layer on the substrate, thereby improving the transmittance of the array substrate without adding a mask plate and a process.

[0103] Specifically, such as Figure 6As shown, the array substrate 2 includes a substrate 211, a fourth insulating layer 213a, a light shielding layer 212, a third insulating layer 213b, an active layer 214, a gate insulating layer 215, a gate layer 216, a first insulating layer 217a, a second insulating layer 217b, a source-drain layer 218, a planarization layer 219, a first electrode layer 221, a passivation layer 222, and a second electrode layer 223, which are arranged in sequence. The content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer is less than that of the portion of the first insulating layer far from the gate layer. The content of hydrogen atoms in the volume of the buffer layer is reduced; by setting the fourth insulating layer in the buffer layer in the non-light-transmitting area, the transmittance of the array substrate can be improved, and the fourth insulating layer can block ions in the substrate from entering the active layer, thereby improving the performance of the array substrate, and the projection of the fourth insulating layer on the substrate coincides with the projection of the light-shielding layer on the substrate, without adding a mask plate, simplifying the process steps, and improving the preparation efficiency of the array substrate. The projection of the second insulating layer on the substrate coincides with the projection of the source and drain layer on the substrate, which can improve the transmittance of the array substrate without adding a mask plate and process.

[0104] It can be understood that the above embodiments combine some film layers and their structures in different ways to obtain different array substrate structures. The above embodiments are not the structures of all array substrates in the embodiments of the present application. When there is no conflict between the film layers and their structures, the film layers and their structures can be combined to obtain other array substrate structures.

[0105] At the same time, an embodiment of the present application provides a method for preparing an array substrate, which prepares the array substrate as described in any of the above embodiments.

[0106] Specifically, the method for preparing the array substrate includes:

[0107] Provide a substrate, and sequentially form a light shielding layer and a fourth insulating layer on the substrate; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (a);

[0108] The fourth insulating layer is patterned; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (b);

[0109] A third insulating layer, an active layer, a gate insulating layer and a gate layer are formed on the fourth insulating layer; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (c);

[0110] A first insulating layer and a second insulating layer are formed on the gate layer; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (d);

[0111] The array substrate is subjected to rapid thermal annealing, and the second insulating layer is etched to form openings, and a source-drain electrode layer is formed on the second insulating layer; the structure of the array substrate corresponding to this step is as follows Figure 8 As shown in (e);

[0112] The source and drain layers and the second insulating layer are etched simultaneously; the structure of the array substrate corresponding to this step is as follows: Figure 8 As shown in (f);

[0113] A planarization layer, a first electrode layer, a passivation layer, and a second electrode layer are sequentially formed on the source and drain electrode layers; the structure of the array substrate corresponding to this step is as follows: Figure 3 shown.

[0114] Specifically, when forming an array substrate, regardless of whether the second insulating layer is retained, the second insulating layer can be first formed on the first insulating layer, and then the array substrate is subjected to a rapid thermal annealing process to activate the hydrogen in the second insulating layer and diffuse it to the active layer to combine with the dangling bonds in the active layer, thereby reducing defects in the active layer. Then, the second insulating layer can be completely removed or a portion of the second insulating layer can be retained, for example, by etching the second insulating layer and the source and drain layers at the same time. Both methods do not require the addition of a mask plate, thereby reducing costs and improving preparation efficiency.

[0115] Specifically, such as Figure 9 As shown, Figure 1 Taking the structure of the comparative display device shown in FIG2 as an example, in order to replenish hydrogen in the active film, a rapid thermal annealing process is performed after forming the interlayer insulating film. By comparing the hydrogen atom concentration in the comparative display device formed with and without the rapid thermal annealing process, it is obtained that Figure 9 The graph shown, Figure 9 The horizontal axis represents the depth from the upper surface of the silicon oxide interlayer insulating film 117b, in nanometers. For example, a depth of 100 indicates that the distance from the upper surface of the silicon oxide interlayer insulating film is 100 nanometers, and a depth of 0 indicates the position of the upper surface of the silicon oxide interlayer insulating film. Figure 9 The vertical axis in the graph represents the hydrogen atom concentration, expressed in units of hydrogen atoms per cubic centimeter. Curve 1 shows the data obtained by testing the peripheral region of the motherboard corresponding to the comparative display device when the comparative display device was formed using a rapid thermal annealing process. Curve 2 shows the data obtained by testing the central region of the motherboard corresponding to the comparative display device when the comparative display device was formed using a rapid thermal annealing process. Curve 3 shows the data obtained by testing the peripheral region of the motherboard corresponding to the comparative display device when the comparative display device was formed without the rapid thermal annealing process. Curve 4 shows the data obtained by testing the central region of the motherboard corresponding to the comparative display device when the comparative display device was formed without the rapid thermal annealing process. Figure 9 It can be seen that when the rapid thermal annealing process is used, the hydrogen atom concentration of each film layer is relatively high.

[0116] like Figure 10 As shown, Figure 10 (a) is a schematic diagram of the diffusion of hydrogen elements in a comparative display device provided in an embodiment of the present application. Figure 10 (b) is a schematic diagram of the diffusion of hydrogen elements in an array substrate provided in an embodiment of the present application. Figure 10 As can be seen in FIG, when the array substrate is subjected to rapid thermal annealing, the hydrogen atoms 31 in the silicon nitride layer diffuse into the channel portion of the active layer. Figure 10 In (a), the silicon nitride interlayer insulating film 117a is located between the silicon oxide interlayer insulating film 117b and the gate film 116. Therefore, the concentration of hydrogen atoms in the portion of the silicon oxide interlayer insulating film close to the silicon nitride interlayer insulating film is greater than the concentration of hydrogen atoms in the portion of the silicon oxide interlayer insulating film far from the silicon nitride interlayer insulating film. Specifically, the concentration of hydrogen atoms in the silicon oxide interlayer insulating film from the portion far from the silicon nitride interlayer insulating film to the portion close to the silicon nitride interlayer insulating film ranges from 0 to 1e 22 hydrogen atoms / cubic centimeter, and in the embodiment of the present application, Figure 10 As shown in (b), the second insulating layer is provided on the side of the first insulating layer away from the gate layer. Therefore, the content of hydrogen atoms per unit volume of the portion of the first insulating layer away from the gate layer is greater than the content of hydrogen atoms per unit volume of the portion of the first insulating layer close to the gate layer. The range of the content of hydrogen atoms per unit volume from the portion of the first insulating layer away from the gate layer to the portion of the first insulating layer close to the gate layer is 1e 22 hydrogen atoms / cm3 to 1e 21 hydrogen atoms per cubic centimeter.

[0117] Specifically, based on Figure 1 The comparison shows that the device and Figure 3 The electrical properties of the thin film transistors are tested on the array substrate. Figure 11 、 Figure 12 The data shown, Figure 11 (a) is a comparison diagram of the threshold voltage Vth of the thin film transistor in the display device and the threshold voltage Vth of the thin film transistor of the array substrate in the embodiment of the present application, Figure 11 (b) is a comparison diagram of the mobility Mob of the thin film transistor in the display device and the mobility Mob of the thin film transistor of the array substrate in the embodiment of the present application, Figure 11 (c) is a comparison diagram of the on-state current Ion of the thin film transistor in the display device and the on-state current Ion of the thin film transistor of the array substrate in the embodiment of the present application, Figure 12(a) is a comparison diagram of the subthreshold swing SS of the thin film transistor in the display device and the subthreshold swing SS of the thin film transistor of the array substrate in the embodiment of the present application. Figure 12 (b) is a comparison diagram of the leakage current loff of the thin film transistor in the display device and the leakage current loff of the thin film transistor of the array substrate in the embodiment of the present application. Figure 11 (a) to Figure 11 (c) Figure 12 (a) to Figure 12 STD1 in the horizontal axis of (b) represents the result obtained by the first test of the comparative display device, STD2 represents the result obtained by the second test of the comparative display device, ILD Reverse1 represents the result obtained by the first test of the array substrate in the embodiment of the present application, and ILD Reverse2 represents the result obtained by the second test of the array substrate in the embodiment of the present application. Figure 11 The vertical axis of (a) is the threshold voltage, the unit is V, that is, volts, Figure 11 The vertical axis of (b) is the mobility, in cm 2 / (V*s), that is, square centimeter / (volt*second), Figure 11 The vertical axis of (c) is the on-state current, the unit is A, that is, ampere, Figure 12 The vertical axis of (a) is the subthreshold swing, and the unit is mV / dec, that is, millivolt / decade. Figure 12 The vertical axis of (b) is the leakage current, and the unit is A, i.e. ampere.

[0118] from Figure 11 、 Figure 12 It can be seen that the performance of the thin film transistor of the array substrate in the embodiment of the present application is similar to the performance of the thin film transistor in the comparative display device, that is, the electrical properties of the two are similar.

[0119] At the same time, an embodiment of the present application provides a display panel, which includes the array substrate as described in any of the above embodiments.

[0120] Specifically, such as Figure 13 As shown, the display panel 4 includes an array substrate 2 , a color filter substrate 41 , and a liquid crystal layer 42 disposed between the array substrate 2 and the color filter substrate 41 .

[0121] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0122] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0124] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: The array substrate includes a pixel area, wherein the pixel area includes a light-transmitting area and a non-light-transmitting area located on at least one side of the light-transmitting area. The array substrate includes: substrate; An active layer is provided on one side of the substrate; a gate layer, disposed on a side of the active layer away from the substrate; an interlayer insulating layer, disposed on a side of the gate layer away from the active layer, the interlayer insulating layer comprising a first insulating layer, wherein a nitrogen content in the interlayer insulating layer and the first insulating layer located in the light-transmitting region is less than a content of oxygen; The hydrogen content per unit volume of a portion of the first insulating layer close to the gate layer is smaller than the hydrogen content per unit volume of a portion of the first insulating layer far from the gate layer.

2. The array substrate according to claim 1, wherein: The array substrate further includes a source-drain layer, which is arranged on a side of the interlayer insulating layer away from the gate layer. One side of the first insulating layer is in direct contact with the source-drain layer, and the other side of the first insulating layer is in direct contact with the gate layer.

3. The array substrate according to claim 1, wherein: The interlayer insulating layer further includes a second insulating layer. The material of the second insulating layer is silicon nitride. The second insulating layer is arranged on a side of the first insulating layer away from the gate layer. The second insulating layer is arranged in the non-light-transmitting area.

4. The array substrate according to claim 3, wherein: The array substrate also includes a source-drain layer, the width of the surface of the source-drain layer on the side in contact with the second insulating layer is equal to the width of the surface of the second insulating layer on the side in contact with the source-drain layer, and the sidewall of the source-drain layer and the corresponding sidewall of the second insulating layer are on the same plane.

5. The array substrate according to claim 3, wherein: The array substrate further includes a source-drain electrode layer, wherein a width of a surface of the source-drain electrode layer in contact with the second insulating layer is smaller than a width of a surface of the second insulating layer in contact with the source-drain electrode layer.

6. The array substrate according to claim 5, wherein: An included angle between the sidewall of the source / drain layer and the bottom surface of the source / drain layer is smaller than or equal to an included angle between the sidewall of the second insulating layer and the bottom surface of the second insulating layer.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The material of the first insulating layer includes silicon oxide.

8. The array substrate according to any one of claims 1 to 6, wherein: The array substrate further includes a buffer layer, which is disposed between the substrate and the active layer. The material of the portion of the buffer layer located in the light-transmitting area is silicon oxide.

9. The array substrate according to claim 8, wherein: The buffer layer includes a third insulating layer and a fourth insulating layer. The material of the third insulating layer is silicon oxide, the material of the fourth insulating layer is silicon nitride, and the fourth insulating layer is arranged in the non-light-transmitting area.

10. The array substrate according to claim 9, wherein: The array substrate further includes a light shielding layer, which is disposed between the fourth insulating layer and the substrate. The fourth insulating layer is disposed between the light shielding layer and the third insulating layer, and the fourth insulating layer covers the light shielding layer.

11. The array substrate according to claim 9, wherein: The array substrate further includes a light shielding layer, the fourth insulating layer is arranged between the light shielding layer and the substrate, and the third insulating layer is arranged on a side of the light shielding layer away from the fourth insulating layer.

12. The array substrate according to claim 11, wherein: The projection of the surface of the light-shielding layer close to the fourth insulating layer on the substrate coincides with the projection of the surface of the fourth insulating layer close to the light-shielding layer on the substrate, and the side wall of the light-shielding layer and the corresponding side wall in the fourth insulating layer are on the same plane.

13. The array substrate according to claim 8, wherein: The buffer layer includes a third insulating layer, and the array substrate also includes a light-shielding layer. One side of the third insulating layer contacts the light-shielding layer, and the other side of the third insulating layer contacts the active layer. The material of the portion of the buffer layer located in the non-light-transmitting area is silicon oxide.

14. The array substrate according to any one of claims 1 to 6, characterized in that: The array substrate further includes a source-drain electrode layer, a planarization layer, a first electrode layer, a passivation layer, and a second electrode layer, wherein the source-drain electrode layer is arranged on a side of the interlayer insulating layer away from the gate layer, the planarization layer is arranged on a side of the source-drain electrode layer away from the interlayer insulating layer, the first electrode layer is arranged on a side of the planarization layer away from the source-drain electrode layer, the passivation layer is arranged on a side of the first electrode layer away from the planarization layer, and the second electrode layer is arranged on a side of the passivation layer away from the first electrode layer; Wherein, the material of the passivation layer is silicon oxide or silicon oxynitride.

15. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 14.

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