Back contact solar cell and preparation method thereof

Abstract

According to the back contact solar cell and the preparation method thereof provided by the invention, the graphical sacrificial layer with the preset roughness is relatively conveniently prepared and obtained by adopting the technical means of'sol coating-annealing curing ', and the relative thickness of the related film layer is matched and set, so that the thickness of the back contact solar cell is greatly improved. At least enabling the tip of the graphical sacrificial layer not to be completely covered by the later formed film layer. On the basis, the subsequent etching step continues to be executed, so that the graphical sacrificial layer can be removed through etching of the exposed tip, and the target film layer covering the graphical sacrificial layer can be peeled off at the same time. Therefore, by adopting the preparation method provided by the invention, the p region (such as the first carrier collection layer) and the n region (such as the second carrier collection layer) which are arranged in an interdigital manner can be relatively conveniently prepared at low cost without executing an expensive and complicated photoetching process or laser ablation process in related technologies; and the process difficulty and the preparation cost are effectively reduced.

Description

Technical Field

[0001] The invention relates to a back contact solar cell and a preparation method thereof, belonging to the field of semiconductor materials. Background Art

[0002] The back-contact solar cell moves the emitter (i.e., p-region) located on the front side of the traditional heterojunction solar cell structure to the back side, and forms a finger-shaped back contact structure with the back field (i.e., n-region). This not only effectively improves the cell's response to the short-wave band, avoids the shading loss of the front metal electrode, and greatly increases the short-circuit current; it also greatly increases the open-circuit voltage. Therefore, this cell structure has both high open-circuit voltage and short-circuit current, which further improves the conversion efficiency and has become a research hotspot for major scientific research institutions and enterprises.

[0003] In the related art, a photolithography process or a laser ablation process is used to prepare a p-region and an n-region on the back of a back-contact solar cell. However, the above method has the defects of complex process and high production cost, which is not conducive to large-scale production. Therefore, developing a simple and low-cost method for producing back-contact solar cells has become a current research direction. Summary of the invention

[0004] The invention provides a method for preparing a back-contact solar cell, which has the characteristics of simple process and low cost.

[0005] The present invention also provides a back-contact solar cell, which has the characteristics of low production difficulty and low production cost.

[0006] In one aspect, the present invention provides a method for preparing a back-contact solar cell, comprising: providing a substrate (10), wherein the substrate (10) comprises a first surface and a second surface arranged opposite to each other; and further comprising:

[0007] forming an initial second passivation layer (50a) on the second surface of the substrate (10);

[0008] forming an initial first carrier collection layer (60a) of a first conductivity type on a side of the initial second passivation layer (50a) facing away from the substrate (10);

[0009] A patterned sacrificial layer (70) having an interdigitated opening pattern is formed on the side of the initial first carrier collection layer (60a) facing away from the substrate (10); the surface of the patterned sacrificial layer (70) is formed into a morphology including a plurality of pointed tips;

[0010] Using the patterned sacrificial layer (70) as a mask, a first type etching process is used to remove the initial first carrier collection layer (60a) and the initial second passivation layer (50a) exposed by the interdigitated opening pattern, so as to form a first carrier collection layer (60) and a second passivation layer (50) respectively, and expose a portion of the second surface of the substrate (10);

[0011] A stacked third passivation layer (80) and a second carrier collection layer (90) of a second conductivity type are sequentially formed on the patterned sacrificial layer (70) and the second surface exposed by the substrate (10); wherein at least a portion of the tip of the patterned sacrificial layer (70) is not completely covered by the third passivation layer (80) and the second carrier collection layer (90);

[0012] The patterned sacrificial layer (70) is removed by etching based on the exposed tip using a second type etching process, and a portion of the third passivation layer (80) and a portion of the second carrier collection layer (90) covering the patterned sacrificial layer (70) are also peeled off; the retained second carrier collection layer (90) is arranged crosswise with the first carrier collection layer (60).

[0013] The method for preparing a back-contact solar cell as described above, wherein the step of forming a patterned sacrificial layer (70) having an interdigitated opening pattern on the side of the initial first carrier collection layer (60a) facing away from the substrate (10) comprises:

[0014] Using silica sol to coat the side of the initial first carrier collection layer (60a) facing away from the substrate (10) to form a silica sol layer with an interdigitated pattern;

[0015] The silica sol layer is subjected to an annealing and curing treatment, so that the silica sol layer is formed into a silica layer with a preset roughness; the silica layer serves as the patterned sacrificial layer (70).

[0016] The method for preparing a back contact solar cell as described above, wherein the mass fraction of silica in the silica sol is 29-31wt%, the pH value is 9.0-10.5, and the viscosity is less than or equal to 6.5mm 2 / s.

[0017] In the method for preparing a back-contact solar cell as described above, the treatment temperature of the annealing and curing treatment is 150° C.-220° C., and the treatment time is 15 min-60 min.

[0018] The method for preparing a back-contact solar cell as described above, wherein the thickness of the patterned sacrificial layer (70) is 5 μm-50 μm;

[0019] The roughness of the patterned sacrificial layer (70) is 1 μm-50 μm.

[0020] The method for preparing a back-contact solar cell as described above, wherein the thickness of the first passivation layer (20) and / or the second passivation layer (50) is 3 nm-10 nm; and / or,

[0021] The thickness of the first carrier collection layer (60) and / or the second carrier collection layer (90) is 10 nm-30 nm.

[0022] The method for preparing a back-contact solar cell as described above, wherein the first type of etching treatment comprises: an alkali etching treatment; the first type of etching treatment lasts for 5 minutes to 10 minutes;

[0023] The second type of etching treatment includes: acid etching treatment; the duration of the second type of etching treatment is 1 min-20 min.

[0024] In the method for preparing a back-contact solar cell as described above, the ratio of the thickness of the patterned sacrificial layer (70) to the sum of the thicknesses of the third passivation layer (80) and the second carrier collection layer (90) is in the range of 200 to 10,000.

[0025] The method for preparing a back-contact solar cell as described above, wherein the method further comprises:

[0026] A transparent conductive layer (100) is formed on the first carrier collection layer (60) and the second carrier collection layer (90) on the side facing away from the substrate (10); the transparent conductive layer (100) has a plurality of isolation grooves for isolating a portion of the transparent conductive layer (100) covering the first carrier collection layer (60) from a portion of the transparent conductive layer (100) covering the second carrier collection layer (90);

[0027] A gate line electrode (M0) is formed on a side of the transparent conductive layer away from the substrate.

[0028] The method for preparing a back-contact solar cell as described above, wherein the method further comprises:

[0029] A first passivation layer (20), a first conductivity type doping layer (30) and an anti-reflection layer (40) are sequentially stacked in a direction away from the substrate (10) and formed on the first surface of the substrate (10).

[0030] The present invention also provides a back-contact solar cell, wherein the back-contact solar cell comprises a substrate (10), a first passivation layer (20), a doping layer (30), an anti-reflection layer (40), a second passivation layer (50), a first carrier collection layer (60), a third passivation layer (80), a second carrier collection layer (90), a transparent conductive layer (100), and a gate electrode (M0);

[0031] The substrate (10) has two surfaces;

[0032] A first passivation layer (20), a first conductivity type doping layer (30) and an anti-reflection layer (40) are sequentially stacked on one surface of the substrate (10) in a direction away from the substrate (10);

[0033] The other surface of the substrate (10) is provided with a second passivation layer (50) and a third passivation layer (80) in contact with each other;

[0034] A first carrier collection layer (60) is provided on the surface of the second passivation layer (50) in a direction away from the substrate (10), and the first carrier collection layer (60) and the third passivation layer (80) are separated by the third passivation layer (80) and are arranged in a cross pattern;

[0035] A transparent conductive layer (100) is provided on the side of the first carrier collection layer (60) and the second carrier collection layer (90) facing away from the substrate (10); the transparent conductive layer (100) has a plurality of isolation grooves;

[0036] A gate line electrode (M0) is provided on the side of the transparent conductive layer facing away from the substrate (10).

[0037] The method for preparing a back-contact solar cell provided by the present invention adopts the technical means of "sol-gel coating-annealing and curing" to conveniently prepare a patterned sacrificial layer with a preset roughness, and by matching the relative thickness of the relevant film layers, at least the tip of the patterned sacrificial layer is not completely covered by the film layer (such as the third passivation layer and the second carrier collection layer) formed later. Based on this, the subsequent etching steps are continued to be performed to facilitate the removal of the patterned sacrificial layer by etching the exposed tip, and the target film layer covering the patterned sacrificial layer can be peeled off. In this way, the preparation method provided by the present invention can be used without the need to perform the expensive and complicated photolithography process or laser ablation process in the related technology, and the p-region (such as the first carrier collection layer) and n-region (such as the second carrier collection layer) arranged in an interdigitated shape can be prepared relatively conveniently and at low cost, effectively reducing the process difficulty and preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A flow chart of the preparation of a back-contact solar cell provided in Example 1 of the present invention;

[0040] Figures 2 to 15 A structural diagram of the preparation process of a back-contact solar cell provided in Example 1 of the present invention.

[0041] Description of reference numerals:

[0042] 10-substrate; 20-first passivation layer; 30-doping layer; 40-anti-reflection layer; 50a-initial second passivation layer; 50-second passivation layer; 60a-initial first carrier collection layer; 60-first carrier collection layer; 70-patterned sacrificial layer; 80-third passivation layer; 90-second carrier collection layer; 100-transparent conductive layer; M0-gate line electrode. DETAILED DESCRIPTION

[0043] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0045] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0047] A first aspect of the present invention provides a method for preparing a back-contact solar cell.

[0048] In the method for preparing the back-contact solar cell provided by the present invention, each layer structure can be produced using a commonly used method in the art, such as a PECVD process, unless otherwise specified.

[0049] The first conductivity type is selected from one of the p-type and the n-type; and the second conductivity type is selected from the other of the p-type and the n-type.

[0050] Figure 1 The preparation flow chart of the back contact solar cell provided in Example 1 of the present invention is shown in FIG. Figure 1 , the process includes:

[0051] Step S10: providing a substrate 10, wherein the substrate 10 comprises a first surface and a second surface arranged opposite to each other;

[0052] Step S20: forming a first passivation layer 20, a first conductivity type doping layer 30 and an anti-reflection layer 40 stacked in sequence along a direction away from the substrate on the first surface of the substrate;

[0053] Step S30: forming an initial second passivation layer 50a on the second surface of the substrate;

[0054] Step S40: forming an initial first carrier collection layer 60a of the first conductivity type on the side of the initial second passivation layer facing away from the substrate;

[0055] Step S50: forming a patterned sacrificial layer 70 having an interdigitated opening pattern on the side of the initial first carrier collection layer 60a facing away from the substrate; the surface of the patterned sacrificial layer 70 is formed into a morphology including a plurality of sharp points;

[0056] Step S60: using the patterned sacrificial layer 70 as a mask, a first type etching process is used to remove the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the interdigitated opening pattern, so as to form the first carrier collection layer 60 and the second passivation layer 50 correspondingly, and expose a portion of the second surface of the substrate 10;

[0057] Step S70: sequentially forming a stacked third passivation layer 80 and a second carrier collection layer 90 of a second conductivity type on the patterned sacrificial layer 70 and one of the exposed surfaces of the substrate 10; wherein at least a portion of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90;

[0058] Step S80: using the second type etching process to etch and remove the patterned sacrificial layer 70 based on the exposed tip, and also peeling off a portion of the third passivation layer 80 and a portion of the second carrier collection layer 90 covering the patterned sacrificial layer 70; the retained second carrier collection layer 90 is arranged crosswise with the first carrier collection layer 60;

[0059] Step S90: forming a transparent conductive layer 100 on the first carrier collection layer 60 and the second carrier collection layer 90 on the side away from the substrate 10; the transparent conductive layer 100 has a plurality of isolation grooves for isolating the portion of the transparent conductive layer 100 covering the first carrier collection layer 60 from the portion of the transparent conductive layer 100 covering the second carrier collection layer 90;

[0060] Step S100: forming a gate line electrode M0 on a side of the transparent conductive layer away from the substrate.

[0061] The first surface may be, for example, a light incident surface of the battery, and the second surface may be, for example, a backlight surface of the battery. When the first surface is "another surface", the second surface is "one of the surfaces".

[0062] The present invention does not limit the specific conductivity types of the first conductivity type and the second conductivity type, and the first conductivity type and the second conductivity type are different. When the first conductivity type is n-type, the second conductivity type is p-type; when the first conductivity type is p-type, the second conductivity type is n-type.

[0063] The method for preparing the back-contact solar cell provided by the present invention can use relatively mature and low-cost processes (such as screen printing and PECVD processes) to prepare the back-contact solar cell without the need for photolithography or laser processes, and has the characteristics of low production difficulty and production cost.

[0064] Figures 2 to 15 The structural diagram of the preparation process of the back contact solar cell provided by the first embodiment of the present invention. The upper surface of the substrate 10 is the first surface, and the lower surface of the substrate 10 is the second surface.

[0065] refer to Figure 3 and Figure 4 , forming an initial second passivation layer 50a on the second surface of the substrate; forming an initial first carrier collection layer 60a of the first conductivity type on the side of the initial second passivation layer 50a away from the substrate. Figure 3 is a cross-sectional view, Figure 4 For Figure 3 Corresponding bottom view.

[0066] The initial second passivation layer 50 a and the first passivation layer 20 may be made of the same material.

[0067] The initial first carrier collection layer 60a of the first conductivity type is composed of amorphous silicon or microcrystalline silicon doped with phosphorus, and its main function is to collect photogenerated electrons.

[0068] refer to Figure 5 and Figure 6 A patterned sacrificial layer 70 having an interdigital opening pattern is formed on the side of the initial first carrier collection layer 60a away from the substrate; the surface of the patterned sacrificial layer 70 is formed into a morphology including multiple sharp points. Figure 5 is a cross-sectional view, Figure 6 For Figure 5 Corresponding bottom view.

[0069] The patterned sacrificial layer 70 is a temporary mask layer used to form a specific pattern in a specified area, to cover the parts that do not need to be processed, and to be etched away in the subsequent process, thereby leaving a specific structure and pattern. The present invention does not limit the specific material of the patterned sacrificial layer 70, and common materials commonly used in the art, such as silicon dioxide, can be used.

[0070] The morphology of the tip can be referenced Fig.11 .Depend on Fig.11 It can be seen that the patterned sacrificial layer 70 has six triangular structures protruding from the third passivation layer 80 and the second carrier collection layer 90, and the structure is a tip. The present invention does not limit the specific shape of the tip, and other patterns can also be used.

[0071] also, Figure 6 Take a forked finger opening pattern as an example, wherein a forked finger opening pattern is Figure 6 The structure consisting of two convex parts and one concave part formed by the patterned sacrificial layer 70. The drawings of the present invention only illustrate one interdigital opening pattern, but the present invention does not limit the number of interdigital opening patterns. Specifically, the patterned sacrificial layer 70 may include a plurality of interdigital opening patterns consisting of concave parts and convex parts, and the specific number of interdigital opening patterns may be matched and set according to actual needs.

[0072] refer to Figure 7 and Figure 8 , using the patterned sacrificial layer 70 as a mask, a first type etching process is used to remove the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the interdigitated opening pattern, so as to form the first carrier collection layer 60 and the second passivation layer 50 correspondingly, and expose a portion of the second surface of the substrate 10. Figure 7 is a cross-sectional view, Figure 8 For Figure 7 Corresponding bottom view.

[0073] During the etching process of the first type etching process, the structure covered by the patterned sacrificial layer 70 having the interdigitated opening pattern cannot be removed, while the uncovered structure is removed during the process.

[0074] Specifically, in the above process, the initial first carrier collection layer 60a and the initial second passivation layer 50a that are not covered by the graphic sacrificial layer 70 presenting a forked-finger opening pattern are removed by the first type etching process, and the initial first carrier collection layer 60a that is not removed and covered by the graphic sacrificial layer 70 forms the first carrier collection layer 60, and the initial second passivation layer 50a that is not removed and covered by the graphic sacrificial layer 70 forms the second passivation layer 50.

[0075] The present invention does not limit the specific process selected for the first type etching process, as long as the requirement of being able to remove the initial first carrier collection layer 60a and the initial second passivation layer 50a is met. For example, an alkaline etching process can be selected. In addition, by adjusting the process parameters such as the etching time, the substrate 10 can be used as an etching stop layer to ensure that the portion of the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the opening pattern are completely removed. That is, the first type etching can "OverEtch" (over-etch) a portion of the substrate 10 material.

[0076] refer to Figures 9 to 11 A stacked third passivation layer 80 and a second carrier collection layer 90 of the second conductivity type are sequentially formed on the patterned sacrificial layer 70 and the exposed second surface of the substrate 10; wherein at least part of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90.

[0077] Fig. 9 is a cross-sectional view, Fig.10 For Fig. 9 The corresponding bottom view, Fig.11 for Fig. 9 Top view of part A.

[0078] exist Figure 7 and Figure 8In the preparation process shown, after a portion of the initial first carrier collection layer 60a and the initial second passivation layer 50a are removed by a first type etching process, the patterned sacrificial layer 70 and the substrate 10 not covered by the patterned sacrificial layer 70 are exposed. At this time, a stacked third passivation layer 80 and a second carrier collection layer 90 of the second conductivity type can be sequentially formed on the second surface of the patterned sacrificial layer 70 and the substrate 10 exposed.

[0079] Among them, at least part of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90. This helps to remove the patterned sacrificial layer 70 by etching with the help of the exposed tip in the subsequent steps, and enables the related film layer structure covering the patterned sacrificial layer 70 to be successfully peeled off.

[0080] like Fig.11 As shown, at least part of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90, that is, at least part of the patterned sacrificial layer 70 can be in contact with the outside. It is worth noting that Fig.11 This is only one of the setting shapes of the tip of the patterned sacrificial layer 70. The present invention does not limit the specific setting shape of the tip of the patterned sacrificial layer 70. It can be set to other shapes as long as the requirement that at least part of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90 is met.

[0081] The material of the third passivation layer 80 is the same as that of the first passivation layer 20 .

[0082] The second carrier collecting layer 90 of the second conductivity type has a conductivity type different from the first carrier collecting layer 60 of the first conductivity type.

[0083] refer to Figure 12 to Figure 13 , the second type etching process is used to remove the patterned sacrificial layer 70 based on the exposed tip etching, and the third passivation layer 80 and the second carrier collection layer 90 covering the patterned sacrificial layer 70 are peeled off; the retained second carrier collection layer 90 and the first carrier collection layer 60 are arranged in an interdigitated shape. Fig.12 is a cross-sectional view, Fig.13 For Fig.12 Corresponding bottom view.

[0084] Specifically, at least the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90, and is etched due to contact with the etchant during the etching process using the second type etching process. The etchant enters the gap created by the etched patterned sacrificial layer 70, and continues to corrode the patterned sacrificial layer 70 covered by the third passivation layer 80 and the second carrier collection layer 90, and finally the patterned sacrificial layer 70 is completely removed, and then, part of the third passivation layer 80 and part of the second carrier collection layer 90 covering the patterned sacrificial layer 70 are also peeled off along with the patterned sacrificial layer 70 due to the loss of the attachment basis.

[0085] like Fig.13 As shown, after the etching process using the second type etching process is completed, the retained second carrier collection layer 90 and the first carrier collection layer 60 are cross-arranged and isolated by the third passivation layer 80. The cross-arrangement specifically means that the second carrier collection layer 90 has a convex portion and multiple concave portions, the first carrier collection layer 60 has a concave portion and multiple convex portions, the convex portion of the second carrier collection layer 90 is arranged opposite to the concave portion of the first carrier collection layer 60 with the third passivation layer 80, and the concave portion of the second carrier collection layer 90 is arranged opposite to the convex portion of the first carrier collection layer 60 with the third passivation layer 80.

[0086] The drawings of the present application only illustrate one cross arrangement, but the present application does not limit the number of cross arrangements. Specifically, the first carrier collection layer 60 and the second carrier collection layer 90 can both include a plurality of cross arrangements consisting of concave portions and convex portions, and the specific number of cross arrangements can be matched and set according to actual needs to achieve a cross arrangement between the first carrier collection layer 60 and the second carrier collection layer 90.

[0087] The present invention does not limit the specific process selected by the second type etching process, as long as the requirement of being able to remove the patterned sacrificial layer 70 is met. For example, an acid etching process may be selected.

[0088] refer to Figure 14 to Figure 15 , forming a transparent conductive layer 100 on the first carrier collection layer 60 and the second carrier collection layer 90 away from the substrate 10; the transparent conductive layer 100 has a plurality of isolation grooves for isolating the portion of the transparent conductive layer 100 covering the first carrier collection layer 60 from the portion of the transparent conductive layer 100 covering the second carrier collection layer 90;

[0089] A gate line electrode M0 is formed on the side of the transparent conductive layer facing away from the substrate.

[0090] The material of the transparent conductive layer 100 may include indium tin oxide ITO or indium zinc oxide IZO to ensure good conductivity and light transmittance. The present invention does not limit the method for forming the transparent conductive layer 100, and a common method in the art, such as physical vapor deposition, sputtering or electron beam evaporation, may be used.

[0091] In addition, a plurality of isolation grooves may be formed in the transparent conductive layer 100 using a graphic technique such as photolithography, laser etching or inkjet printing to isolate the transparent conductive layer portion covering the first carrier collection layer 60 from the transparent conductive layer portion covering the second carrier collection layer 90. In one embodiment, a photoresist may be coated on the surface of the transparent conductive layer 100, and a mask may be used to form a pattern of the isolation grooves by photolithography; dry etching such as plasma etching or wet etching such as acid etching solution may be used to remove the material of the patterned area in the transparent conductive layer 100 to form the isolation grooves. The width and depth of the isolation grooves are appropriately controlled to ensure complete isolation of the transparent conductive layer.

[0092] On the side of the transparent conductive layer 100 facing away from the substrate 10, a gate electrode M0 is formed for collecting and conducting current. The gate electrode M0 is usually made of silver or copper material and prepared by screen printing, inkjet printing, laser transfer or electroplating technology. In one embodiment, a screen printing method can be used to apply silver paste or copper paste on the surface of the transparent conductive layer to form a gate pattern, and the gate electrode is cured by drying and sintering. Alternatively, a photolithography electroplating method is used to form a gate pattern on the surface of the transparent conductive layer.

[0093] In a specific embodiment, the step of forming a patterned sacrificial layer 70 having an interdigitated opening pattern on the side of the initial first carrier collection layer 60a facing away from the substrate 10 includes:

[0094] A silica sol is used to coat the side of the initial first carrier collection layer 60a away from the substrate 10 to form a silica sol layer having an interdigital pattern;

[0095] The silica sol layer is subjected to an annealing and curing process, so that the silica sol layer is formed into a silicon dioxide layer with a preset roughness; the silicon dioxide layer serves as a patterned sacrificial layer 70 .

[0096] Silica sol is a mixture of silicon dioxide and solvent. The annealing and curing treatment is to heat the silica sol to volatilize the solvent contained in the sol, so that the silica sol is converted into a graphic sacrificial layer 70 composed of silicon dioxide. The present invention does not limit the specific processing temperature and processing time of the annealing and curing treatment, and it is sufficient to meet the requirement of volatilizing the solvent in the silica sol. There is a gap between the contact interface of the silicon dioxide layer with a preset roughness and the initial first carrier collection layer 60a. During the etching process using the second type etching process, the etchant can enter the gap, thereby completing the dissolution of the silicon dioxide layer. The present invention does not limit the roughness of the silicon dioxide layer, which can be preset to a suitable roughness. For example, in one embodiment, the roughness is 1μm-50μm.

[0097] In another specific embodiment, the step of forming a patterned sacrificial layer 70 having an interdigitated opening pattern on the side of the second passivation layer 50 facing away from the substrate 10 includes:

[0098] A silica sol is applied to the side of the second passivation layer 50 facing away from the substrate 10 to form a silica sol layer having an interdigital pattern;

[0099] The silica sol layer is subjected to an annealing and curing process, so that the silica sol layer is formed into a silicon dioxide layer with a preset roughness; the silicon dioxide layer serves as a patterned sacrificial layer 70 .

[0100] Silica sol is a mixture of silicon dioxide and solvent. The annealing and curing treatment is to heat the silica sol to volatilize the solvent contained in the sol, so that the silica sol is converted into a graphic sacrificial layer 70 whose component is silicon dioxide. The present invention does not limit the specific processing temperature and processing time of the annealing and curing treatment, and it is sufficient to meet the requirement of volatilizing the solvent in the silica sol. There is a gap between the contact interface of the silicon dioxide layer with a preset roughness and the second passivation layer 50. During the etching process using the second type etching process, the etchant can enter the gap, thereby completing the dissolution of the silicon dioxide layer. The present invention does not limit the roughness of the silicon dioxide layer, which can be preset to a suitable roughness. For example, in one embodiment, the roughness is 1μm-50μm.

[0101] Furthermore, in order to further facilitate the formation of a silicon dioxide layer with a preset roughness, in one embodiment, the mass fraction of silicon dioxide in the silicon dioxide sol is 29wt%-31wt%, the pH value is 9.0-10.5, and the viscosity is less than or equal to 6.5mm 2 / s.

[0102] Silica sol, also known as silica sol mSiO2·nH2O, is a dispersion of nano-sized silica particles in water. During the annealing and curing process, the water contained in the silica sol evaporates, forming a silica layer as a patterned sacrificial layer 70. The present invention does not limit the specific preparation method of the silica sol, and common preparation methods in the art can be used. For example, water glass can be used as a raw material, and sodium ions can be removed by ion exchange resin treatment and sulfuric acid neutralization to obtain silica sol. It can also be obtained by hydrolysis of silicate.

[0103] In one embodiment, the annealing and curing treatment is performed at a temperature of 150° C. to 220° C. and for a duration of 15 min to 60 min. Appropriate annealing and curing treatment conditions are conducive to the volatilization of the solvent in the silica sol, thereby forming a silica layer with a preset roughness.

[0104] In a more specific embodiment, the thickness of the patterned sacrificial layer 70 is 5 μm-50 μm, and the roughness is 1 μm-50 μm. The patterned sacrificial layer 70 with a suitable thickness can ensure that at least part of the tip included therein is not completely covered by the third passivation layer 80 or the initial first carrier collection layer 60a; the suitable roughness makes it impossible for the structure (such as the tip) deposited on the surface of the patterned sacrificial layer 70 to completely cover the silicon dioxide and produce a gap of a suitable size. In the etching process using the second type etching process, the etchant can smoothly complete the etching of the silicon dioxide layer and the smooth peeling of the structure covering its surface, thereby making the preparation method provided by the present invention more efficient.

[0105] More specifically, the thickness of the first passivation layer 20 and / or the second passivation layer 50 can be controlled to be 3nm-10nm; the thickness of the first carrier collection layer 60 and / or the second carrier collection layer 90 can be controlled to be 10nm-30nm. Appropriate thickness of the passivation layer and the carrier collection layer can make the manufactured back contact solar cell have better electrical performance.

[0106] In one embodiment, the first type of etching treatment includes: alkaline etching treatment; the duration of the first type of etching treatment includes: 5min-10min. Alkaline etching treatment is to use an alkaline substance to etch the initial first carrier collection layer 60a and the initial second passivation layer 50a, wherein the alkaline substance can be an alkaline solution. The present invention does not limit the specific selection of the alkaline solution, and at least one of a sodium hydroxide aqueous solution, a potassium hydroxide aqueous solution or an organic alkali aqueous solution with a concentration of 1-5wt% can be selected according to needs. Among them, the organic base can be tetramethylammonium hydroxide TMAH. The present invention also does not limit the time and temperature of the alkaline etching treatment, which can be selected according to actual needs. The appropriate first type etching treatment duration can meet the etching requirements while not causing excessive corrosion to the substrate 10, so that the obtained back-contact solar cell has better electrical properties.

[0107] In one embodiment, the ratio of the thickness of the patterned sacrificial layer 70 to the sum of the thickness of the third passivation layer 80 and the second carrier collection layer 90 can be controlled to be in the range of 200 to 10000. This range can ensure that at least a portion of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90.

[0108] The second type of etching treatment includes: acid etching treatment; the duration of the second type of etching treatment includes: 1min-20min. The acid etching treatment is to use an acidic substance to etch the patterned sacrificial layer 70, wherein the acidic substance can be an acidic solution. In one embodiment, the acidic solution is hydrofluoric acid with a concentration of 0.5-2% v / v, that is, in the hydrofluoric acid used for etching, the volume fraction of 20% hydrofluoric acid solution is 0.5-2%. The appropriate second type of etching treatment time can etch the patterned sacrificial layer 70 without causing damage to other components.

[0109] In one embodiment, the method for preparing a back-contact solar cell provided by the present invention also includes the following process: forming a first passivation layer 20, a first conductive type doping layer 30 and an anti-reflection layer 40 stacked in sequence along a direction away from the substrate 10 on the other surface of the substrate 10.

[0110] refer to Figure 2 On the other surface of the substrate 10, ie, the surface where the initial second passivation layer 50a is not formed, a first passivation layer 20, a first conductivity type doping layer 30 and an anti-reflection layer 40 are sequentially stacked in a direction away from the substrate.

[0111] The material of the substrate 10 includes high-purity single crystal silicon, such as n-type single crystal silicon; the material of the first passivation layer 20 includes intrinsic amorphous silicon, which helps to reduce the recombination of electrons and holes and improve the efficiency of the battery; the material of the anti-reflection layer 40 includes silicon nitride, which allows sunlight to pass through and reduces light reflection, and also helps to protect the structure below the layer.

[0112] A second aspect of the present invention provides a back contact solar cell. Fig.14 and Fig.15 As shown, the back contact solar cell includes a substrate 10, a first passivation layer 20, a doping layer 30, an anti-reflection layer 40, a second passivation layer 50, a first carrier collection layer 60, a third passivation layer 80, a second carrier collection layer 90, a transparent conductive layer 100, and a gate electrode M0;

[0113] The substrate 10 has two surfaces;

[0114] A first passivation layer 20, a first conductivity type doping layer 30 and an anti-reflection layer 40 are sequentially stacked on one surface of the substrate 10 in a direction away from the substrate 10;

[0115] The other surface of the substrate 10 is provided with a second passivation layer 50 and a third passivation layer 80 that are in contact with each other;

[0116] A first carrier collection layer 60 is disposed on the surface of the second passivation layer 50 in a direction away from the substrate 10 , and the first carrier collection layer 60 and the third passivation layer 80 are separated by the third passivation layer 80 and are arranged in a cross pattern;

[0117] A transparent conductive layer 100 is disposed on the side of the first carrier collection layer 60 and the second carrier collection layer 90 facing away from the substrate 10; the transparent conductive layer 100 has a plurality of isolation grooves;

[0118] A gate line electrode M0 is disposed on the side of the transparent conductive layer facing away from the substrate 10 .

[0119] In one embodiment, the cell can be prepared using the method for preparing a back-contact solar cell provided by the first aspect of the present invention.

[0120] Since the present invention provides a method for preparing a back-contact solar cell with the characteristics of simple process and low cost, the second aspect of the present invention provides a back-contact solar cell with the characteristics of low production difficulty and low production cost.

[0121] The back-contact solar cell provided by the present invention and its preparation method and application are described in detail below through specific embodiments.

[0122] Example 1

[0123] This embodiment uses the following method to prepare a back contact solar cell:

[0124] Step S10: providing a substrate 10, wherein the substrate 10 comprises a first surface and a second surface arranged opposite to each other;

[0125] Step S20: forming a first passivation layer 20, a first conductivity type doping layer 30 and an anti-reflection layer 40 stacked in sequence along a direction away from the substrate on the first surface of the substrate;

[0126] Step S30: forming an initial second passivation layer 50a on the second surface of the substrate;

[0127] Step S40: forming an initial first carrier collection layer 60a of the first conductivity type on the side of the initial second passivation layer facing away from the substrate;

[0128] Step S50: forming a patterned sacrificial layer 70 having an interdigitated opening pattern on the side of the initial first carrier collection layer 60a facing away from the substrate; the surface of the patterned sacrificial layer 70 is formed into a morphology including a plurality of sharp points;

[0129] Step S60: using the patterned sacrificial layer 70 as a mask, a first type etching process is used to remove the initial first carrier collection layer 60a and the initial second passivation layer 50a exposed by the interdigitated opening pattern, so as to form the first carrier collection layer 60 and the second passivation layer 50 correspondingly, and expose a portion of the second surface of the substrate 10;

[0130] Step S70: forming a stacked third passivation layer 80 and a second carrier collection layer 90 of a second conductivity type in sequence on the patterned sacrificial layer 70 and the exposed second surface of the substrate 10; wherein the ratio of the thickness of the patterned sacrificial layer 70 to the sum of the thickness of the third passivation layer 80 and the second carrier collection layer 90 is in a range of 200 to 10000, so that at least a portion of the tip of the patterned sacrificial layer 70 is not completely covered by the third passivation layer 80 and the second carrier collection layer 90;

[0131] Step S80: using the second type etching process to etch and remove the patterned sacrificial layer 70 based on the exposed tip, and also peeling off a portion of the third passivation layer 80 and a portion of the second carrier collection layer 90 covering the patterned sacrificial layer 70; the retained second carrier collection layer 90 is arranged crosswise with the first carrier collection layer 60;

[0132] Step S90: forming a transparent conductive layer 100 on the first carrier collection layer 60 and the second carrier collection layer 90 on the side away from the substrate 10; the transparent conductive layer 100 has a plurality of isolation grooves for isolating the portion of the transparent conductive layer 100 covering the first carrier collection layer 60 from the portion of the transparent conductive layer 100 covering the second carrier collection layer 90;

[0133] Step S100: forming a gate line electrode M0 on a side of the transparent conductive layer away from the substrate.

[0134] A back-contact solar cell A1 was produced.

[0135] In the above process:

[0136] The treatment temperature of annealing and curing treatment is 190°C and the treatment time is 25min;

[0137] The first type of etching treatment uses a 2% sodium hydroxide solution for alkaline etching treatment, and the treatment time is 5 minutes;

[0138] The second type of etching treatment uses a hydrofluoric acid solution with a concentration of 1% for acid etching, and the treatment time is 5 minutes.

[0139] The thickness data of each layer of the back contact solar cell A1 are as follows:

[0140] Substrate 10: 150 μm;

[0141] First passivation layer 20: 6nm;

[0142] First conductivity type doping layer 30: 10 nm;

[0143] Anti-reflection layer 40: 80nm;

[0144] Second passivation layer 50: 6nm;

[0145] First carrier collection layer 60: 20nm

[0146] The third passivation layer 80: 6nm;

[0147] Second carrier collection layer 90: 20nm;

[0148] The patterned sacrificial layer 70 has a thickness of 50 μm and a roughness of 30 μm.

[0149] Comparative Example 1

[0150] This comparative example refers to the process flow of the background technology in Chinese patent CN117577709B, and uses the following conventional process to manufacture a back-contact solar cell:

[0151] S11, double-sided polishing of silicon wafer;

[0152] S12, coating the back of the silicon wafer with a first mask layer for protection; the thickness of the first mask layer is 200 nm;

[0153] S13, cleaning the silicon wafer texture, forming a pyramid texture surface opposite to the first mask layer, and then removing the first mask layer to form a silicon wafer with a single-side texture and a single-side polishing structure;

[0154] S14, coating the back of the silicon wafer with a first semiconductor layer and a second mask layer in sequence, wherein the first semiconductor layer comprises an intrinsic amorphous or microcrystalline silicon layer and an n-type doped amorphous or microcrystalline silicon layer, and the second mask layer is generally silicon nitride; the first semiconductor layer has a thickness of 25 nm, and the second mask layer has a thickness of 200 nm;

[0155] S15, laser or etching an opening on the back side of the silicon wafer to remove the second mask layer and a portion of the first semiconductor layer to form a second semiconductor opening region; the width of the second semiconductor opening region is 700 μm;

[0156] S16, cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening region;

[0157] S17, an amorphous layer and an anti-reflection layer are sequentially formed on the front side of the silicon wafer, and a second semiconductor layer is formed on the back side, wherein the second semiconductor layer comprises an intrinsic amorphous or microcrystalline silicon layer and a p-type doped amorphous or microcrystalline silicon layer; the amorphous layer has a thickness of 10 nm, the anti-reflection layer has a thickness of 85 nm, and the second semiconductor layer has a thickness of 25 nm;

[0158] S18, laser or etching an opening on the back of the silicon wafer to form a first semiconductor opening region alternately arranged with the second semiconductor opening region; the width of the first semiconductor opening region is 300 μm;

[0159] S19, cleaning the silicon wafer to remove the second mask layer in the first semiconductor opening region;

[0160] S20, depositing a conductive film layer on the back of the silicon wafer; the thickness of the conductive film layer is 100 nm;

[0161] S21, forming an isolation groove between the first semiconductor opening region and the second semiconductor opening region by laser or etching;

[0162] S22, forming metal electrodes on the first semiconductor opening region and the second semiconductor opening region of the silicon wafer.

[0163] A back-contact solar cell B1 was produced.

[0164] Test Case

[0165] The following tests were performed using batteries A1 and B1: Under standard measurement conditions, the test temperature was 25°C and the light intensity was 1000W / m 2 , AM1.5 spectrum test. The test results are shown in Table 1.

[0166] Table 1 Test results of various battery electrical parameters

[0167]

[0168] It can be seen from Table 1 that battery A1 has similar electrical properties to battery B1 manufactured using a commonly used process in the art, which indicates that the method for preparing a back-contact solar cell provided by the present invention uses a relatively mature and low-cost process (such as screen printing and PECVD process) to prepare a back-contact solar cell without the need for photolithography or laser ablation processes, and has the characteristics of low production difficulty and production cost.

Claims

1. A method for preparing a back contact solar cell, comprising: A substrate (10) is provided, wherein the substrate (10) comprises a first surface and a second surface arranged opposite to each other; and is characterized in that it further comprises: forming an initial second passivation layer (50a) on the second surface of the substrate (10); forming an initial first carrier collection layer (60a) of a first conductivity type on a side of the initial second passivation layer (50a) facing away from the substrate (10); A patterned sacrificial layer (70) having an interdigitated opening pattern is formed on the side of the initial first carrier collection layer (60a) facing away from the substrate (10); the surface of the patterned sacrificial layer (70) is formed into a morphology including a plurality of pointed tips; Using the patterned sacrificial layer (70) as a mask, a first type etching process is used to remove the initial first carrier collection layer (60a) and the initial second passivation layer (50a) exposed by the interdigitated opening pattern, so as to form a first carrier collection layer (60) and a second passivation layer (50) respectively, and expose a portion of the second surface of the substrate (10); A stacked third passivation layer (80) and a second carrier collection layer (90) of a second conductivity type are sequentially formed on the patterned sacrificial layer (70) and the second surface exposed by the substrate (10); wherein at least a portion of the tip of the patterned sacrificial layer (70) is not completely covered by the third passivation layer (80) and the second carrier collection layer (90); The patterned sacrificial layer (70) is removed by etching based on the exposed tip using a second type etching process, and a portion of the third passivation layer (80) and a portion of the second carrier collection layer (90) covering the patterned sacrificial layer (70) are also peeled off; the retained second carrier collection layer (90) is arranged crosswise with the first carrier collection layer (60).

2. The method for preparing a back contact solar cell according to claim 1, characterized in that: The step of forming a patterned sacrificial layer (70) having an interdigitated opening pattern on the side of the initial first carrier collection layer (60a) facing away from the substrate (10) comprises: Using silica sol to coat the side of the initial first carrier collection layer (60a) facing away from the substrate (10) to form a silica sol layer with an interdigitated pattern; The silica sol layer is subjected to an annealing and curing treatment, so that the silica sol layer is formed into a silica layer with a preset roughness; the silica layer serves as the patterned sacrificial layer (70).

3. The method for preparing a back contact solar cell according to claim 2, characterized in that: The mass fraction of silicon dioxide in the silicon dioxide sol is 29wt%-31wt%, the pH value is 9.0-10.5, and the viscosity is less than or equal to 6.5mm 2 / s.

4. The method for preparing a back contact solar cell according to claim 3, characterized in that: The annealing and curing treatment has a treatment temperature of 150° C. to 220° C. and a treatment time of 15 min to 60 min; and / or, The thickness of the patterned sacrificial layer (70) is 5 μm-50 μm; The roughness of the patterned sacrificial layer (70) is 1 μm-50 μm.

5. The method for preparing a back contact solar cell according to claim 4, characterized in that: The thickness of the first passivation layer (20) and / or the second passivation layer (50) is 3 nm-10 nm; The thickness of the first carrier collection layer (60) and / or the second carrier collection layer (90) is 10 nm-30 nm.

6. The method for preparing a back contact solar cell according to claim 5, characterized in that: The first type of etching treatment includes: alkaline etching treatment; the first type of etching treatment lasts for 5 minutes to 10 minutes; The second type of etching treatment includes: acid etching treatment; the duration of the second type of etching treatment is 1 min-20 min.

7. The method for preparing a back contact solar cell according to claim 6, characterized in that: The ratio of the thickness of the patterned sacrificial layer (70) to the sum of the thicknesses of the third passivation layer (80) and the second carrier collection layer (90) is in the range of 200 to 10,000.

8. The method for preparing a back contact solar cell according to claim 7, characterized in that: The method further comprises: A transparent conductive layer (100) is formed on the first carrier collection layer (60) and the second carrier collection layer (90) on the side facing away from the substrate (10); the transparent conductive layer (100) has a plurality of isolation grooves for isolating a portion of the transparent conductive layer (100) covering the first carrier collection layer (60) from a portion of the transparent conductive layer (100) covering the second carrier collection layer (90); A gate line electrode (M0) is formed on a side of the transparent conductive layer away from the substrate.

9. The method for preparing a back-contact solar cell according to any one of claims 1 to 8, characterized in that: The method further comprises: A first passivation layer (20), a first conductivity type doping layer (30) and an anti-reflection layer (40) are formed on the first surface of the substrate (10) and are stacked in sequence in a direction away from the substrate (10).

10. A back contact solar cell, characterized in that: The back-contact solar cell comprises a substrate (10), a first passivation layer (20), a doping layer (30), an anti-reflection layer (40), a second passivation layer (50), a first carrier collection layer (60), a third passivation layer (80), a second carrier collection layer (90), a transparent conductive layer (100), and a gate electrode (M0); The substrate (10) has two surfaces; A first passivation layer (20), a first conductivity type doping layer (30) and an anti-reflection layer (40) are sequentially stacked on one surface of the substrate (10) in a direction away from the substrate (10); The other surface of the substrate (10) is provided with a second passivation layer (50) and a third passivation layer (80) in contact with each other; A first carrier collection layer (60) is provided on the surface of the second passivation layer (50) in a direction away from the substrate (10), and the first carrier collection layer (60) and the third passivation layer (80) are separated by the third passivation layer (80) and are arranged in a cross pattern; A transparent conductive layer (100) is provided on the side of the first carrier collection layer (60) and the second carrier collection layer (90) facing away from the substrate (10); the transparent conductive layer (100) has a plurality of isolation grooves; A gate line electrode (M0) is provided on the side of the transparent conductive layer facing away from the substrate (10).

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