Preparation method of heterojunction battery and heterojunction battery

Abstract

The invention relates to the technical field of crystalline silicon cells, in particular to a preparation method of a heterojunction cell and the heterojunction cell. The preparation method of the heterojunction cell comprises the following steps of performing texturing and cleaning, depositing each photovoltaic power generation functional film layer, preparing a metal electrode, removing a transparent conductive film layer in an edge region, performing smooth etching on the edge region, and preparing a passivation layer in the edge region of a silicon wafer. The heterojunction cell comprises a silicon wafer, the silicon wafer is divided into an edge area and a middle area, the surface of the edge area of the silicon wafer is a smooth surface covered with a passivation layer or a smooth textured surface, and the front face and the back face of the middle area of the silicon wafer are textured surfaces covered with photovoltaic power generation functional film layers. And the outermost layer of each photovoltaic power generation functional film layer in the middle area is a transparent conductive film layer. The transparent conductive film layer in the edge area is etched and removed, and the edge area is smoothly etched by using the reserved transparent conductive film layer as a mask, so that the preparation process of the heterojunction cell is simple and easy to realize.

Description

Technical Field

[0001] The present invention relates to the technical field of crystalline silicon cells, and in particular to a method for preparing a heterojunction cell and a heterojunction cell. Background Art

[0002] Crystalline silicon solar cells are the most widely used solar cells in today's society and can be seen everywhere in daily life. In addition to the large-scale application of conventional solar cells in ground photovoltaic power stations and distributed photovoltaics, flexible solar cells also have huge development space in the fields of wearable electronics, mobile communications, mobile energy for vehicles, photovoltaic building integration, aerospace, etc. However, the limitations of conventional crystalline silicon solar cells, such as their inability to be bent and their high brittleness, have greatly restricted the flexible application scenarios of crystalline silicon solar cells.

[0003] A certain degree of bendability can be achieved by reducing the thickness of silicon wafers. However, since crystalline silicon is an indirect bandgap semiconductor, reducing the thickness of silicon wafers will cause the current density of the battery to be significantly reduced, thereby greatly reducing the photoelectric conversion efficiency. Among the existing crystalline silicon cells, PERC cells and TOPCon cells are prone to silicon wafer warping in high-temperature processes, which limits the thinning of silicon wafers. Compared with cells and TOPCon cells, heterojunction cells (HJT cells) have the lowest preparation process temperature. HJT cells are suitable for silicon wafer thinning in low-temperature processes. A certain degree of flexibility can be achieved by using HJT cells combined with thin silicon wafers. However, for conventional thin HJT cells, they are still prone to breakage under mechanical shock and vibration conditions, especially in areas of stress concentration.

[0004] Therefore, it is necessary to increase the bending strength, improve the flexibility of HJT batteries, and expand the application scope of thin HJT batteries.

[0005] The Chinese patent application with publication number CN116435403A proposes: stacking textured silicon wafers, performing plasma edge etching of silicon, achieving smooth textured surfaces in the edge area, and then performing subsequent photovoltaic cell preparation processes on the silicon wafers to obtain photovoltaic cells with smooth edges. The technical problem with this method is that in the process of etching the pyramids at the edge of the silicon wafer, new surface undulations are easily generated, introducing new stress concentration points, resulting in a decrease in the bending strength of the silicon wafer instead of an increase.

[0006] The Chinese patent application with publication number CN116230787A proposes: using polished silicon wafers to coat the edges with glue, drying them as a protective mask, making texture in the middle of the silicon wafer, and then removing the glue to form a silicon wafer with polished edges and texture in the middle. The technical problems of this method are: the preparation process is complicated, the coating cost of the glue film and the treatment cost of organic wastewater are high, and it is not suitable for mass production. Summary of the invention

[0007] The technical problem to be solved by the present invention is that the existing preparation method of photovoltaic cells with smooth edge velvet surface has a complex preparation process and is not suitable for mass production; in addition, the bending strength of the prepared photovoltaic cells cannot meet the requirements.

[0008] The technical solution adopted by the present invention is:

[0009] A method for preparing a heterojunction battery comprises the following steps:

[0010] Step S1, performing texturing and cleaning on the silicon wafer;

[0011] Step S2, depositing various photovoltaic power generation functional film layers on the front and back sides of the silicon wafer;

[0012] Step S3, preparing metal electrodes, forming a first metal electrode on the front side of the middle area of ​​the silicon wafer, and forming a second metal electrode on the back side of the middle area of ​​the silicon wafer;

[0013] Step S4, removing the transparent conductive film layer in the edge area;

[0014] Step S5, smooth etching of the edge region: using the transparent conductive film layer as a mask, smoothly etching the edge region of the silicon wafer, and smoothing the suede surface of the edge region to obtain a smooth surface or a smoothed suede surface;

[0015] Step S6, preparing a passivation layer in the edge area of ​​the silicon wafer;

[0016] Alternatively, step S3 is located after step S6.

[0017] Furthermore, in step S4, plasma etching is used to remove the transparent conductive film layer in the edge area. Specifically, multiple silicon wafers are stacked and placed in an inductively coupled plasma etching chamber for plasma edge etching to remove the transparent conductive film layer in the edge area.

[0018] Furthermore, in step S5, a wet etching method is used to smoothly etch the edge area.

[0019] A method for preparing a heterojunction battery comprises the following steps:

[0020] Step S1, preparing a heterojunction battery with a velvet surface on the edge;

[0021] Step S2, removing the transparent conductive film layer in the edge area;

[0022] Step S3, smooth etching of the edge region: using the transparent conductive film layer as a mask, smoothly etching the edge region of the silicon wafer, and smoothing the suede surface of the edge region to obtain a smooth surface or a smoothed suede surface;

[0023] S4. Prepare a passivation layer in the edge area of ​​the silicon wafer.

[0024] Furthermore, in step S4, plasma etching is used to remove the transparent conductive film layer in the edge area. Specifically, multiple silicon wafers are stacked and placed in an inductively coupled plasma etching chamber for plasma edge etching to remove the transparent conductive film layer in the edge area.

[0025] Furthermore, in step S5, a wet etching method is used to smoothly etch the edge area.

[0026] A heterojunction battery is prepared by the above-mentioned heterojunction battery preparation method, comprising a silicon wafer, which is divided into an edge region and a middle region. The surface of the edge region of the silicon wafer is a smooth surface covered with a passivation layer or a smoothed velvet surface, and the front and back sides of the middle region of the silicon wafer are velvet surfaces covered with various layers of photovoltaic power generation functional film layers, and the outermost layers of the various layers of photovoltaic power generation functional film layers in the middle region are transparent conductive film layers.

[0027] Furthermore, the silicon wafer is a single crystal silicon wafer, and the photovoltaic power generation functional film layers on the front side of the middle region of the silicon wafer are, from the inside to the outside, respectively a first intrinsic amorphous silicon film layer, a first doped amorphous silicon film layer, and a first transparent conductive film layer, and a first metal electrode is also arranged on the outside of the first transparent conductive film layer; the photovoltaic power generation functional film layers on the back side of the middle region of the silicon wafer are, from the inside to the outside, respectively a second intrinsic amorphous silicon film layer, a second doped amorphous silicon film layer, and a second transparent conductive film layer, and a second metal electrode is also arranged on the outside of the second transparent conductive film layer.

[0028] Furthermore, the thickness of the edge region is smaller than that of the middle region, and the difference in thickness between the edge region and the middle region is 0.5-5 μm, and the width of the edge region is 0.5-5 mm.

[0029] Compared with the prior art, the present invention has the following advantages: by etching away the transparent conductive film layer in the edge area and using the retained transparent conductive film layer as a mask to smoothly etch the edge area, the preparation process of the heterojunction battery is simple and easy to implement.

[0030] The edge area of ​​the heterojunction battery prepared by the present invention is a smooth surface or a smoothed velvet surface, which can prevent the stress from concentrating on the bottom of the velvet surface at the edge when the silicon wafer is bent, causing the silicon wafer to break, greatly improving the bending strength of the silicon wafer, and most of the middle area is still velvet, which does not affect the overall reflectivity of the heterojunction battery. In addition, the edge area is protected by a passivation layer to avoid increased recombination and reduced efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the heterojunction battery structure of the present invention;

[0032] Figure 2 It is a schematic diagram of the process of preparing a heterojunction battery of the present invention;

[0033] Figure 3 It is a schematic diagram of the structure of a comparative heterojunction battery;

[0034] Figure 4 It is a schematic diagram of the process of preparing a heterojunction battery of a comparative example.

[0035] Numbers in the figure: 1. Silicon wafer; 1-1. Middle area; 1-2. Edge area; 2. First intrinsic amorphous silicon film layer; 3. First doped amorphous silicon film layer; 4. First transparent conductive film layer; 5. First metal electrode; 6. Second intrinsic amorphous silicon film layer; 7. Second doped amorphous silicon film layer; 8. Second transparent conductive film layer; 9. Second metal electrode; 10. Passivation layer. DETAILED DESCRIPTION

[0036] The embodiments of the present invention are described in detail below. The embodiments are implemented on the premise of the technical solution of the present invention, and detailed implementation methods and specific operation processes are given, but the protection scope of the present invention is not limited to the following embodiments.

[0037] Example 1

[0038] like Figure 1 As shown, a heterojunction battery includes a silicon wafer 1, which is divided into an edge region 1-2 and a middle region 1-1. The surface of the edge region 1-2 of the silicon wafer 1 is a smooth surface covered with a passivation layer or a smoothed velvet surface, and the front and back sides of the middle region 1-1 of the silicon wafer 1 are velvet surfaces covered with various layers of photovoltaic power generation functional film layers, and the outermost layers of the various layers of photovoltaic power generation functional film layers in the middle region 1-1 are transparent conductive film layers.

[0039] The silicon wafer 1 is a single crystal silicon wafer. The photovoltaic power generation functional film layers on the front side of the middle region 1-1 of the silicon wafer 1 are, from the inside to the outside, a first intrinsic amorphous silicon film layer 2, a first doped amorphous silicon film layer 3 and a first transparent conductive film layer 4, and a first metal electrode 5 is also arranged on the outside of the first transparent conductive film layer 4; the photovoltaic power generation functional film layers on the back side of the middle region 1-1 of the silicon wafer 1 are, from the inside to the outside, a second intrinsic amorphous silicon film layer 6, a second doped amorphous silicon film layer 7 and a second transparent conductive film layer 8, and a second metal electrode 9 is also arranged on the outside of the second transparent conductive film layer 8.

[0040] The thickness of the edge region 1-2 is less than that of the middle region 1-1, and the difference in thickness between the edge region 1-2 and the middle region 1-1 is 0.5-5 μm. The width of the edge region 1-2 is 0.5-5 mm.

[0041] The thickness of the silicon wafer 1 is ≤100 μm.

[0042] The silicon wafer 1 is an n-type doped single crystal silicon wafer or a p-type doped single crystal silicon wafer with a thickness of 50-100 μm; wherein the single crystal is a Czochralski single crystal or a cast single crystal.

[0043] The first intrinsic amorphous silicon film layer 2 and the second intrinsic amorphous silicon film layer 6 are made of one material selected from undoped amorphous silicon, amorphous silicon oxide, and amorphous silicon carbide semiconductor films, or a composite film layer of a combination of several materials, with a thickness of 4-10nm; the first intrinsic amorphous silicon film layer 2 and the second intrinsic amorphous silicon film layer 6 are made of the same or different materials, and have the same or different thicknesses.

[0044] The first doped amorphous silicon film layer 3 and the second doped amorphous silicon film layer 7 are n-type doped amorphous silicon film layers or p-type doped amorphous silicon film layers, and are composite film layers made of one material or a combination of several materials selected from amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, microcrystalline silicon, microcrystalline silicon oxide, and microcrystalline silicon carbide semiconductor thin films, with a thickness of 5-30nm; the first doped amorphous silicon film layer 3 and the second doped amorphous silicon film layer 7 have the same or different materials and the same or different thicknesses, and the first doped amorphous silicon film layer 3 and the second doped amorphous silicon film layer 7 have opposite conductivity types.

[0045] The first transparent conductive film layer 4 and the second transparent conductive film layer 8 are made of one material selected from doped indium oxide, zinc oxide or tin oxide or a composite film layer of a combination of several materials, with a thickness of 60-120 nm; the first transparent conductive film layer 4 and the second transparent conductive film layer 8 may be made of the same or different materials and have the same or different thicknesses.

[0046] The first metal electrode 5 and the second metal electrode 9 are made of a composite material of one or a combination of Ag, Cu, Al, and Ni, with a thickness of 10-50um and a width of 5-50um; the first metal electrode 5 and the second metal electrode 9 are made of the same or different materials, have the same or different thicknesses, and have the same or different widths.

[0047] The material of the passivation layer 10 is one or more combinations of SiOx, AlOx, SiNx, SiOxNy, and SiCx, and the thickness is 20-150 nm.

[0048] More specifically, the first intrinsic amorphous silicon film layer 2 of the heterojunction cell of this embodiment 1 is an n-type doped amorphous silicon film layer, the second intrinsic amorphous silicon film layer 6 is a p-type doped amorphous silicon film layer, and the first transparent conductive film layer is 80nm ITO (3wt% SnO 2 ) transparent conductive film layer, the second transparent conductive film layer 8 is 65nm ITO (10wt% SnO 2 ) transparent conductive film layer, the velvet surface of the middle area 1-1 of the silicon wafer 1 is a pyramid velvet surface, the surface of the edge area 1-2 is a smooth surface, and the passivation layer 10 is an AlOx dielectric film passivation layer.

[0049] like Figure 2 As shown, the method for preparing the heterojunction battery of this embodiment 1 includes the following steps:

[0050] Step S1, performing texturing and cleaning on the silicon wafer 1: using 2wt% KOH alkaline solution and 0.5vol% texturing additive, the solution temperature is controlled at 75-80°C, anisotropically etching the silicon wafer 1, forming a pyramid velvet surface on the surface of the silicon wafer 1, and then using an acid-base chemical solution to clean the surface of the silicon wafer 1 to provide a clean surface;

[0051] Step S2, depositing various photovoltaic power generation functional film layers on the front and back sides of the silicon wafer 1, specifically:

[0052] Step S2.1, depositing an amorphous silicon film layer: using a PECVD deposition method, forming a first intrinsic amorphous silicon film layer 2 with a thickness of 4-6 nm and an n-type doped amorphous silicon film layer with a thickness of 5-10 nm on the front side of the silicon wafer 1, and forming a second intrinsic amorphous silicon film layer 6 with a thickness of 5-7 nm and a p-type doped amorphous silicon film layer with a thickness of 8-15 nm on the back side of the silicon wafer 1;

[0053] Step S2.2, depositing a transparent conductive film layer: using magnetron sputtering deposition, deposit 80nm ITO (3wt% SnO 2 ) transparent conductive film layer, as the first transparent conductive film layer 4, 65nm ITO (10wt% SnO 2 ) a transparent conductive film layer, serving as a second transparent conductive film layer 8;

[0054] Step S3, preparing metal electrodes: using screen printing, printing low-temperature conductive Ag paste on the front side of the silicon wafer 1, printing low-temperature conductive Ag@Cu paste on the back side of the silicon wafer 1, and drying and curing, forming a first metal electrode 5 on the front side of the middle area 1-1 of the silicon wafer 1, and forming a second metal electrode 9 on the back side of the middle area 1-1 of the silicon wafer 1, or using laser transfer to prepare metal electrodes;

[0055] Step S4, removing the transparent conductive film layer in the edge region 1-2: using plasma etching to remove the transparent conductive film layer in the edge region 1-2, specifically: firstly stacking a plurality of silicon wafers 1, placing them in an inductively coupled plasma etching chamber with Cl 2 , C 2 H 4 , using Ar as a reaction gas to perform plasma edge etching to remove the transparent conductive film layer in the edge region 1-2. In addition to the plasma etching method, other methods may be used to remove the transparent conductive film layer in the edge region 1-2;

[0056] Step S5, smoothing the edge region 1-2: using a wet etching method to smoothly etch the edge region 1-2 to obtain a smooth surface or a smoothed velvet surface, for example, by using an alkaline polishing solution to smoothly etch the edge region 1-2;

[0057] Step S6, preparing a passivation layer 10 on the edge region 1-2 of the silicon wafer 1: using an ALD deposition method, stacking the silicon wafers 1 in a reaction chamber, and depositing them with TMA and O 3 The reactive gas is used to deposit an AlOx dielectric film with a thickness of 20 nm on the edge region after the smooth etching process to form a passivation layer 10.

[0058] Comparative Example 1

[0059] like Figure 3 and Figure 4 As shown, a method for preparing a heterojunction battery comprises the following steps:

[0060] Step S1, performing texturing and cleaning on the silicon wafer 1: using 2wt% KOH alkaline solution and 0.5vol% texturing additive, the solution temperature is controlled at 75-80°C, anisotropically etching the silicon wafer 1, forming a pyramid velvet surface on the surface of the silicon wafer 1, and then using an acid-base chemical solution to clean the surface of the silicon wafer 1 to provide a clean surface;

[0061] Step S2, depositing an amorphous silicon film layer: using a PECVD deposition method, a first intrinsic amorphous silicon film layer 2 with a thickness of 4-6 nm and an n-type doped amorphous silicon film layer with a thickness of 5-10 nm are formed on the front side of the silicon wafer 1, and a second intrinsic amorphous silicon film layer 6 with a thickness of 5-7 nm and a p-type doped amorphous silicon film layer with a thickness of 8-15 nm are formed on the back side of the silicon wafer 1;

[0062] Step S3, depositing a transparent conductive film layer: using magnetron sputtering deposition, deposit 80nm ITO (3wt% SnO 2 ) transparent conductive film layer, as the first transparent conductive film layer 4, 65nm ITO (10wt% SnO 2 ) a transparent conductive film layer, serving as a second transparent conductive film layer 8;

[0063] Step S4, preparing metal electrodes: using screen printing, printing low-temperature conductive Ag paste on the front side of the silicon wafer 1, printing low-temperature conductive Ag@Cu paste on the back side of the silicon wafer 1, and drying and curing, forming a first metal electrode 5 on the front side of the middle area 1-1 of the silicon wafer 1, and forming a second metal electrode 9 on the back side of the middle area 1-1 of the silicon wafer 1.

[0064] The batteries obtained in Example 1 and Comparative Example 1 were subjected to performance tests. The parameters of the obtained battery cells were measured using an IV tester. The bending strength was tested using a three-point test method. The results are shown in Table 1.

[0065] Table 1 Performance parameters of heterojunction batteries obtained in Example 1 and Comparative Example 1

[0066]

[0067]

[0068] It can be seen from the above data that the flexible heterojunction battery prepared by the technical solution of the present application, by etching away the transparent conductive film layer in the edge area of ​​the heterojunction battery, and using the retained transparent conductive film layer as a mask to smoothly etch the edge area, and depositing a passivation layer in the edge area for protection, makes the edge of the silicon wafer become a smooth surface, which consumes more energy during the fracture process, avoids the stress concentration at the bottom of the pyramid velvet surface at the edge when the silicon wafer is bent, causing the silicon wafer to break, and greatly improves the bending strength of the silicon wafer. Since the smooth etching process is only implemented at the edge of the silicon wafer, it significantly improves the bending strength of the solar cell while basically not affecting the photoelectric conversion efficiency of the solar cell.

[0069] Steps S1 to S4 of the method for preparing a heterojunction battery in this embodiment 1 are the same as the method for preparing an existing heterojunction battery, i.e., comparative example 1. The existing heterojunction battery can be prepared by steps S1 to S4 of the method for preparing a heterojunction battery in this embodiment 1. That is, steps S1 to S4 can be omitted, and the heterojunction battery of the present invention can be prepared by directly using the existing finished heterojunction battery and then using steps S5 to S6 of embodiment 1. Specifically, the heterojunction battery of the present invention is as follows:

[0070] Example 2

[0071] A method for preparing a heterojunction battery and a heterojunction battery are basically the same as those in Example 1, except that: a method for preparing a heterojunction battery comprises the following steps:

[0072] Step S1, preparing a heterojunction battery with a velvet surface at the edge, such as the heterojunction battery prepared in Comparative Example 1;

[0073] Step S2, removing the transparent conductive film layer in the edge area 1-2;

[0074] Step S3, performing smooth etching on the edge area 1-2;

[0075] Step S4 , preparing a passivation layer 10 in the edge region 1 - 2 of the silicon wafer 1 .

[0076] Example 3

[0077] A method for preparing a heterojunction battery and a heterojunction battery are basically the same as those in Example 1, except that in the method for preparing the heterojunction battery, step S3 is located after step S6.

[0078] The method for preparing the heterojunction battery of this embodiment 3 comprises the following steps:

[0079] Step S1, performing texturing and cleaning on the silicon wafer 1;

[0080] Step S2, depositing various photovoltaic power generation functional film layers on the front and back of the silicon wafer 1; Step S3, removing the transparent conductive film layer in the edge area 1-2;

[0081] Step S4, performing smooth etching on the edge area 1-2;

[0082] Step S5 , preparing a passivation layer 10 in the edge region 1 - 2 of the silicon wafer 1 .

[0083] Step S6: preparing metal electrodes.

Claims

1. A method for preparing a heterojunction battery, characterized in that: The following steps are involved: Step S1, performing texturing and cleaning on the silicon wafer (1); Step S2, depositing various photovoltaic power generation functional film layers on the front and back sides of the silicon wafer (1); Step S3, preparing metal electrodes, forming a first metal electrode (5) on the front side of the middle region (1-1) of the silicon wafer (1), and forming a second metal electrode (9) on the back side of the middle region (1-1) of the silicon wafer (1); Step S4, removing the transparent conductive film layer in the edge area (1-2); Step S5, smoothing the edge region (1-2): using the transparent conductive film layer as a mask, smoothly etching the edge region (1-2) of the silicon wafer (1), and smoothing the velvet surface of the edge region (1-2) to obtain a smooth surface or a smoothed velvet surface; Step S6, preparing a passivation layer (10) on the edge region (1-2) of the silicon wafer (1); Alternatively, step S3 is located after step S6.

2. The method for preparing a heterojunction battery according to claim 1, characterized in that: In step S4, a plasma etching method is used to remove the transparent conductive film layer in the edge area (1-2), specifically: firstly, a plurality of silicon wafers (1) are stacked and placed in an inductively coupled plasma etching chamber for plasma edge etching to remove the transparent conductive film layer in the edge area (1-2).

3. The method for preparing a heterojunction battery according to claim 1, characterized in that: In step S5, a wet etching method is used to smoothly etch the edge region (1-2).

4. A method for preparing a heterojunction battery, characterized in that: The following steps are involved: Step S1, preparing a heterojunction battery with a velvet surface on the edge; Step S2, removing the transparent conductive film layer in the edge area (1-2); Step S3, smoothing the edge region (1-2): using the transparent conductive film layer as a mask, smoothly etching the edge region (1-2) of the silicon wafer (1), and smoothing the velvet surface of the edge region (1-2) to obtain a smooth surface or a smoothed velvet surface; S4. Prepare a passivation layer (10) in the edge region (1-2) of the silicon wafer (1).

5. The method for preparing a heterojunction battery according to claim 4, characterized in that: In step S4, a plasma etching method is used to remove the transparent conductive film layer in the edge area (1-2), specifically: firstly, a plurality of silicon wafers (1) are stacked and placed in an inductively coupled plasma etching chamber for plasma edge etching to remove the transparent conductive film layer in the edge area (1-2).

6. The method for preparing a heterojunction battery according to claim 4, characterized in that: In step S5, a wet etching method is used to smoothly etch the edge region (1-2).

7. A heterojunction battery, characterized in that: The heterojunction battery is prepared by the preparation method of any one of claims 1 to 6, comprising a silicon wafer (1), wherein the silicon wafer (1) is divided into an edge region (1-2) and a middle region (1-1), wherein the surface of the edge region (1-2) of the silicon wafer (1) is a smooth surface covered with a passivation layer or a smoothed velvet surface, and the front and back sides of the middle region (1-1) of the silicon wafer (1) are velvet surfaces covered with various layers of photovoltaic power generation functional film layers, and the outermost layers of the various layers of photovoltaic power generation functional film layers in the middle region (1-1) are transparent conductive film layers.

8. The heterojunction battery according to claim 7, characterized in that: The silicon wafer (1) is a single crystal silicon wafer, and the photovoltaic power generation functional film layers on the front side of the middle region (1-1) of the silicon wafer (1) are, from the inside to the outside, a first intrinsic amorphous silicon film layer (2), a first doped amorphous silicon film layer (3) and a first transparent conductive film layer (4), and a first metal electrode (5) is also provided on the outside of the first transparent conductive film layer (4); the photovoltaic power generation functional film layers on the back side of the middle region (1-1) of the silicon wafer (1) are, from the inside to the outside, a second intrinsic amorphous silicon film layer (6), a second doped amorphous silicon film layer (7) and a second transparent conductive film layer (8), and a second metal electrode (9) is also provided on the outside of the second transparent conductive film layer (8).

9. The heterojunction battery according to claim 7, characterized in that: The thickness of the edge region (1-2) is smaller than that of the middle region (1-1), and the difference in thickness between the edge region (1-2) and the middle region (1-1) is 0.5-5 μm. The width of the edge region (1-2) is 0.5-5 mm.

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