Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel includes: a substrate; the driving circuit layer is positioned on one side of the substrate; the metal layer is at least partially located on the side, away from the substrate, of the driving circuit layer; the first conductive layer is located on the side, away from the substrate, of the metal layer in the non-display area, and at least part of the first conductive layer is electrically connected with the metal layer in the non-display area; the second conductive layer is located on the side, away from the substrate, of the first conductive layer in the non-display area, and at least part of the second conductive layer is electrically connected with the first conductive layer in the non-display area; the orthographic projection of the electric connection area of the second conducting layer and the first conducting layer on the substrate is at least partially located in the orthographic projection of the driving circuit layer on the substrate; therefore, on the premise of realizing lap joint of the cathode layer, the frame of the AMOLED display device is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] An active matrix organic light emitting diode (AMOLED) display device is a self-luminous display device, which generally includes a plurality of pixels arranged in an effective display area. The plurality of pixels use a common cathode (ie, cathode layer) covering the entire effective display area.

[0003] In the related art, in order to form a current loop, a cathode overlap region is provided on the frame outside the cathode layer, and current is conducted between the pixel and the back cover of the AMOLED display device through the cathode overlap region. However, the existence of the cathode overlap region will make the frame of the AMOLED display device larger, affecting the user experience. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device that can reduce the frame of an AMOLED display device while achieving cathode layer overlap in order to solve the above technical problems.

[0005] In a first aspect, the present application provides a display panel, the display panel comprising a display area and a non-display area at least partially surrounding the display area, the display panel comprising:

[0006] substrate;

[0007] A driving circuit layer, located on one side of the substrate, and comprising a plurality of driving sub-circuit layers arranged at intervals;

[0008] a metal layer, at least partially located on a side of the driving circuit layer away from the substrate;

[0009] a first conductive layer, located at a side of the metal layer away from the substrate in the non-display area, and at least a portion of the first conductive layer is electrically connected to the metal layer in the non-display area;

[0010] a second conductive layer, located at a side of the first conductive layer away from the substrate in the non-display area, and in the non-display area, at least a portion of the second conductive layer is electrically connected to the first conductive layer;

[0011] The orthographic projection of the region where the second conductive layer is electrically connected to the first conductive layer on the substrate is at least partially located within the orthographic projection of the driving circuit layer on the substrate, and / or the orthographic projection of the region where the second conductive layer is electrically connected to the first conductive layer on the substrate is at least partially located between the orthographic projections of two driving sub-circuit layers in the non-display area on the substrate; the two driving sub-circuit layers are adjacent in a direction from the display area to the non-display area.

[0012] In one embodiment, the display panel further includes:

[0013] A first planarization layer, located between the driving circuit layer and the metal layer, and covering a side of each driving sub-circuit layer away from the substrate;

[0014] Preferably, along the direction from the display area to the non-display area, there is a first gap between two adjacent driving sub-circuit layers in the non-display area that are covered by the first planarization layer;

[0015] Part of the first planarization layer is located in the first interval, and part of the metal layer is located in the first interval on a side of the first planarization layer away from the substrate, wherein a thickness of the first planarization layer covering the first interval is less than or equal to a thickness of the first planarization layer covering the driving sub-circuit layer; or, an orthographic projection of the first planarization layer on the substrate is staggered from an orthographic projection of the first interval on the substrate, and part of the metal layer is located in the first interval;

[0016] Preferably, part of the first planarization layer is located in the first interval, and the thickness of the first planarization layer covering the first interval is less than the thickness of the first planarization layer covering the driving sub-circuit layer;

[0017] Preferably, at least part of the first conductive layer contacts the metal layer in the first space;

[0018] Preferably, at least a portion of the first conductive layer covers a side of the metal layer in the first space away from the substrate.

[0019] In one embodiment, the display panel further includes:

[0020] a second planarization layer, at least partially located on a side of the metal layer away from the substrate, and comprising a plurality of first protrusion structures in the non-display area; wherein a second interval exists between two adjacent first protrusion structures in a direction from the display area to the non-display area;

[0021] The second spaces expose the metal layer, and at least a portion of the first conductive layer contacts the metal layer exposed by the second spaces.

[0022] In one embodiment, at least a portion of the second conductive layer contacts the first conductive layer.

[0023] In one embodiment, the display panel further includes:

[0024] A pixel definition layer, located on a side of the first conductive layer away from the substrate;

[0025] A support column layer, located on a side of the pixel definition layer away from the substrate;

[0026] Preferably, the pixel definition layer includes at least one second protruding structure in the non-display area, and the second protruding structure is located on a side of the first conductive layer away from the substrate; and / or the support column layer includes at least one third protruding structure in the non-display area, and the third protruding structure is located on a side of the first conductive layer away from the substrate;

[0027] Preferably, the second protruding structure is arranged corresponding to the first protruding structure, and the second conductive layer is in contact with at least a portion of the exposed first conductive layer;

[0028] Preferably, the orthographic projection of the second protruding structure on the substrate is staggered from the orthographic projection of the first interval on the substrate;

[0029] Preferably, the third protruding structure is arranged corresponding to the first protruding structure, and the second conductive layer is in contact with at least a portion of the exposed first conductive layer;

[0030] Preferably, an orthographic projection of the third protruding structure on the substrate is staggered from an orthographic projection of the first gap on the substrate.

[0031] In one embodiment, the second conductive layer contacts the first conductive layer in a third interval;

[0032] The third interval is at least one of the following intervals: an interval between the second convex structure and an adjacent third convex structure, an interval between the second convex structure and an adjacent second convex structure, and an interval between the third convex structure and an adjacent third convex structure.

[0033] In one embodiment, the display panel further includes:

[0034] a first inorganic encapsulation layer, located on a side of the second conductive layer away from the substrate and covering the second conductive layer, wherein a side of the first inorganic encapsulation layer away from the substrate in the first gap forms a groove, and an orthographic projection of the groove on the substrate is located within an orthographic projection of the first gap on the substrate;

[0035] an organic encapsulation layer, located on a side of the first inorganic encapsulation layer away from the substrate and covering the first inorganic encapsulation layer, and a portion of the organic encapsulation layer is located in the groove;

[0036] The second inorganic encapsulation layer is located on a side of the organic encapsulation layer away from the substrate and covers the organic encapsulation layer.

[0037] In one of the embodiments, the driving circuit layer includes two driving sub-circuit layers located in the non-display area;

[0038] In the direction from the display area to the non-display area, the two driving sub-circuit layers are a scanning circuit and a light-emitting control circuit in sequence; the first interval is located between the scanning circuit and the light-emitting control circuit;

[0039] Preferably, in the non-display area, the orthographic projection of one end of the organic encapsulation layer away from the display area on the substrate is located between the orthographic projection of one end of the scanning circuit away from the display area on the substrate and the orthographic projection of one end of the light emitting control circuit away from the display area on the substrate.

[0040] In one embodiment, the display panel further includes:

[0041] an anode layer, located in the display area and on a side of the metal layer away from the substrate; the material of the first conductive layer is the same as that of the anode layer;

[0042] a cathode layer, located in the display area and on a side of the anode layer away from the substrate; the cathode layer extends from the display area to the non-display area and is electrically connected to the second conductive layer;

[0043] Preferably, the material of the second conductive layer is the same as that of the cathode layer.

[0044] In a second aspect, the present application further provides a display device, comprising a display panel as described in any of the above embodiments.

[0045] The above-mentioned display panel and display device, under the premise of realizing the overlap of the cathode layer in the non-display area, move the cathode overlap area to above the driving circuit layer in the non-display area, and / or move it to between the orthographic projections of two driving sub-circuit layers in the non-display area on the substrate, thereby removing the cathode overlap area between the inner side of the dam and the driving circuit layer in the non-display area in the related art, thereby reducing the size of the non-display area of ​​the display panel, and further reducing the border of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 is a schematic diagram of a cross-sectional structure of a display panel in the related art;

[0048] Figure 2 is a schematic top view of a display panel in one embodiment;

[0049] Figure 3 for Figure 2 One of the cross-sectional structural diagrams along line CC';

[0050] Figure 4 The second cross-sectional view of the display panel along line CC' in one embodiment;

[0051] Figure 5 The third cross-sectional view of the display panel along line CC' in one embodiment;

[0052] Figure 6 The fourth cross-sectional view of the display panel along the CC' line in one embodiment;

[0053] Figure 7 A fifth cross-sectional view of a display panel along line CC' in one embodiment;

[0054] Figure 8 is a sixth cross-sectional view of a display panel along line CC' in one embodiment;

[0055] Fig. 9 FIG7 is a seventh cross-sectional view of a display panel along line CC' in one embodiment;

[0056] Fig.10 An eighth cross-sectional view of a display panel along line CC' in one embodiment;

[0057] Fig.11A ninth cross-sectional view of a display panel along line CC' in one embodiment;

[0058] Fig.12 is a tenth cross-sectional view of a display panel along line CC' in one embodiment;

[0059] Fig.13 The eleventh cross-sectional view of the display panel along the CC' line in one embodiment;

[0060] Fig.14 is a twelfth cross-sectional view of a display panel along line CC' in one embodiment;

[0061] Fig.15 is a thirteenth cross-sectional view of a display panel along line CC' in one embodiment;

[0062] Fig.16 is a fourteenth cross-sectional view of a display panel along line CC' in one embodiment;

[0063] Fig.17 The fifteenth cross-sectional view of the display panel along the CC' line in one embodiment;

[0064] Fig.18 Schematic diagram of a metal layer window in a non-display area in an embodiment.

[0065] Description of reference numerals:

[0066] Reference numerals in the related art: AA-display area, NAA-non-display area, 110-substrate, 120-driving circuit layer, 130-planarization layer, 140-dam, BB-cathode overlapping area.

[0067] The figure marks in the present application are: AA-display area, NAA-non-display area, 210-substrate, 220-driving circuit layer, 2210-driving sub-circuit layer, 22101-first driving sub-circuit layer, 22102-second driving sub-circuit layer, 230-metal layer, 231-window, 240-first conductive layer, 250-second conductive layer, 260-first planarization layer, 270-second planarization layer, 271-first convex structure, 280-pixel definition layer, 281-second convex structure, 290-support column layer, 291-third convex structure, N1-first interval, N2-second interval, N3-third interval, D-groove, 310-anode layer, 320-cathode layer, 410-first inorganic encapsulation layer, 430-organic encapsulation layer, 420-second inorganic encapsulation layer. DETAILED DESCRIPTION

[0068] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0070] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0071] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0072] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0073] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0074] As mentioned in the background technology, in the related art, the existence of the cathode overlap region makes the frame of the AMOLED display device larger. Figure 1 , an exemplary supplementary explanation is given:

[0075] The AMOLED display device includes a display panel, the display panel includes a display area AA and a non-display area NAA at least partially surrounding the display area AA, and a plurality of pixels are arranged in the display area AA. In the cross-sectional structure of the display panel, the display panel may include a substrate 110, a driving circuit layer 120, a planarization layer 130 and a dam 140. The driving circuit layer 120 is located on one side of the substrate 110 and is distributed in the display area AA and the non-display area NAA. The driving circuit layer 120 is used to provide signals required to drive the pixels. For example, the driving circuit layer 120 in the non-display area NAA may include a SCAN circuit and an EM circuit. The SCAN circuit is used to provide a scanning signal, and the EM circuit is used to provide a light-emitting control signal. The planarization layer 130 is located on the side of the driving circuit layer 120 away from the substrate 110, and can planarize the side of the driving circuit layer 120 away from the substrate 110.

[0076] like Figure 1 As shown, the dam 140 is located in the non-display area NAA, and the driving circuit layer 120 in the non-display area NAA is located on a side away from the display area AA. One of the functions of the dam 140 is to prevent the organic encapsulation material from overflowing to the outside of the dam 140 during the process of preparing the organic encapsulation layer of the display panel, and the area between the inner side of the dam 140 and the driving circuit layer 120 in the non-display area NAA is used as the cathode overlapping area BB, and the cathode layer is overlapped in the cathode overlapping area BB. Figure 1 It can be seen that the existence of the cathode overlapping area BB makes the size of the non-display area NAA of the display panel very large, thereby resulting in a larger frame of the AMOLED display device.

[0077] In view of this, the embodiments of the present application provide a display panel and a display device, so as to reduce the frame of the AMOLED display device while achieving cathode layer overlap.

[0078] In an exemplary embodiment, in combination Figure 2 and Figure 3 A display panel is provided, the display panel includes a display area AA and a non-display area NAA at least partially surrounding the display area AA, wherein the display area AA can be used to set a plurality of pixels, and the pixels are, for example, OLED devices. In the cross-sectional structure of the display panel, the display panel may include a substrate, a driving circuit layer 220, a metal layer 230, a first conductive layer 240, and a second conductive layer 250.

[0079] The substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be made of glass, quartz, etc. The flexible substrate may be made of an organic polymer material, which may include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0080] The driving circuit layer 220 is located on one side of the substrate and includes a plurality of driving sub-circuit layers 2210 arranged at intervals. The driving circuit layer 220 is used to provide signals required to drive pixels. Among the plurality of driving sub-circuit layers 2210 arranged at intervals, some driving sub-circuit layers 2210 are located in the display area AA, and some driving sub-circuit layers 2210 are located in the non-display area NAA. For example, the driving sub-circuit layer 2210 in the display area AA is a pixel circuit layer in the display area AA, and the pixel circuit layer may include a plurality of pixel circuits, and the pixel circuit is used to drive the connected pixels. The driving sub-circuit layer 2210 in the non-display area NAA is a GIP circuit layer in the non-display area NAA, and each GIP circuit layer is used to provide different signals required to drive pixels.

[0081] In the display area AA, the display panel may include a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 stacked in sequence on the substrate. The gate electrode, source electrode, drain electrode of the thin film transistor (TFT) in the pixel circuit and the plate of the storage capacitor in the pixel circuit are composed of metals of the first metal layer M1, the second metal layer M2 and the third metal layer M3. The data signal line for transmitting the data signal Vdata and other metal traces connected to the pixel circuit are composed of metals of the fourth metal layer M4.

[0082] The metal layer 230 in the embodiment of the present application is distributed in the display area AA and the non-display area NAA, and at least part of the metal layer 230 is located on the side of the driving circuit layer 220 away from the substrate. The metal layer 230 in the display area AA and the metal layer 230 in the non-display area NAA are arranged at intervals, and the metal layer 230 in the display area AA can be the fourth metal layer M4 in the display area AA; the metal layer 230 in the non-display area NAA can be a metal layer prepared in the non-display area NAA in the same process as the fourth metal layer M4 in the display area AA, and accordingly, the metal layer 230 in the non-display area NAA can be referred to as the fourth metal layer M4 in the non-display area NAA.

[0083] The first conductive layer 240 is located on the side of the metal layer 230 in the non-display area NAA away from the substrate, and in the non-display area NAA, at least part of the first conductive layer 240 is electrically connected to the metal layer 230. The first conductive layer 240 can be prepared and formed in the same process as other metal layers or other conductive layers in the display panel; after the first conductive layer 240 is electrically connected to the metal layer 230 in the non-display area NAA, other conductive layers that are subsequently electrically connected to the first conductive layer 240 also form an electrical connection relationship with the metal layer 230 in the non-display area NAA.

[0084] The second conductive layer 250 is a cathode layer in the non-display area NAA. The second conductive layer 250 is made of the same material as the cathode layer in the display area AA. The second conductive layer 250 can be electrically connected to the cathode layer in the display area AA. The second conductive layer 250 is located on a side of the first conductive layer 240 in the non-display area NAA away from the substrate, and in the non-display area NAA, at least a portion of the second conductive layer 250 is electrically connected to the first conductive layer 240, so that the cathode layer is overlapped in the non-display area NAA.

[0085] Based on this, in the embodiments of this application, reference Figure 3 , the orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located within the orthographic projection of the driving circuit layer 220 on the substrate. In this way, under the premise of realizing the overlap of the cathode layer 320 in the non-display area NAA, the cathode overlap area is moved to above the driving circuit layer 220 in the non-display area NAA, thereby removing the cathode overlap area BB between the inner side of the dam 140 and the driving circuit layer 120 in the non-display area NAA in the related art, thereby reducing the size of the non-display area NAA of the display panel, and further reducing the frame of the display device; and, in the overlap, not only the metal layer 230 in the non-display area NAA is used, but also the first conductive layer 240, that is, the metal layer 230 and the first conductive layer 240 in the non-display area NAA are used together for the cathode layer overlap, which reduces the resistance of the cathode layer overlap and improves the reliability of the cathode layer overlap.

[0086] Alternatively, refer to Figure 4 The orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located between the orthographic projections of the two driving sub-circuit layers 2210 in the non-display area NAA on the substrate, wherein the two driving sub-circuit layers 2210 are adjacent in the direction from the display area AA to the non-display area NAA. In this way, under the premise of realizing the overlap of the cathode layer in the non-display area NAA, the cathode overlap area is moved to between the orthographic projections of the two driving sub-circuit layers 2210 in the non-display area NAA on the substrate, thereby removing the cathode overlap area BB between the inner side of the dam 140 and the driving circuit layer 120 in the non-display area NAA in the related art, thereby reducing the size of the non-display area NAA of the display panel, and further reducing the border of the display device.

[0087] Alternatively, refer to Figure 5The orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located within the orthographic projection of the driving circuit layer 220 on the substrate, and the orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located between the orthographic projections of the two driving sub-circuit layers 2210 in the non-display area NAA on the substrate, wherein the two driving sub-circuit layers 2210 are adjacent in the direction from the display area AA to the non-display area NAA. In this way, under the premise of realizing the overlap of the cathode layer 320 in the non-display area NAA, the cathode overlap area is no longer the area between the inner side of the dam 140 and the driving circuit layer 120 in the non-display area NAA in the related art, thereby reducing the size of the non-display area NAA of the display panel, and thereby reducing the frame of the display device; and the more electrically connected areas between the second conductive layer 250 and the first conductive layer 240, the more conducive it is to reducing the overlap resistance of the cathode layer 320 and improving the reliability of the overlap of the cathode layer 320.

[0088] In an exemplary embodiment, referring to Figure 5 The display panel further includes a first planarization layer 260. The first planarization layer 260 is located between the driving circuit layer 220 and the metal layer 230, and covers the side of each driving sub-circuit layer 2210 away from the substrate. Thus, the side of the driving circuit layer 220 away from the substrate is planarized by the first planarization layer 260, so as to facilitate the arrangement of subsequent film layers, and the first planarization layer 260 can protect the driving circuit layer 220.

[0089] In an exemplary embodiment, referring to Figure 5 , in the direction from the display area AA to the non-display area NAA, the first planarization layer 260 between the driving sub-circuit layer 2210 in the display area AA and the driving sub-circuit layer 2210 in the adjacent non-display area NAA is continuously arranged.

[0090] In an exemplary embodiment, referring to Figure 5 , along the direction from the display area AA to the non-display area NAA, there is a first gap N1 between two adjacent driving sub-circuit layers 2210 covered by the first planarization layer 260 in the non-display area NAA, and the first gap N1 is filled by the first planarization layer 260 .

[0091] refer to Figure 6, part of the first planarization layer 260 is located in the first interval N1, wherein the thickness of the first planarization layer 260 covering the first interval N1 is less than or equal to the thickness of the first planarization layer 260 covering the driving sub-circuit layer 2210, so that the first planarization layer 260 located in the first interval N1 does not fill the first interval N1, but covers the sidewalls of the two driving sub-circuits 2210 in the first interval N1 facing the first interval N1 and covers the substrate 210 exposed in the first interval N1; based on this, part of the metal layer 230 is located on the side of the first planarization layer 260 in the first interval N1 away from the substrate. In this way, the first planarization layer 260 in the first interval N1 can play an isolating and protective role for the two adjacent driving sub-circuit layers 2210, ensure the insulation between the two adjacent driving sub-circuit layers 2210, and ensure that the packaging protection reliability of each driving sub-circuit layer 2210 is good.

[0092] Can Figure 6 and Figure 3 For comparison, Figure 6 The diagram is a schematic diagram in which part of the first planarization layer 260 is located in the first interval N1, the thickness of the first planarization layer 260 covering the first interval N1 is less than or equal to the thickness of the first planarization layer 260 covering the driving sub-circuit layer 2210, and the orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located within the orthographic projection of the driving circuit layer 220 on the substrate.

[0093] Figure 7 Can be used with Figure 4 For comparison, Figure 7 The diagram shows that part of the first planarization layer 260 is located in the first interval N1, and the thickness of the first planarization layer 260 covering the first interval N1 is less than or equal to the thickness of the first planarization layer 260 covering the driving sub-circuit layer 2210, so that the first planarization layer 260 located in the first interval N1 does not fill the first interval N1, but covers the side walls of the two driving sub-circuits 2210 in the first interval N1 facing the first interval N1 and covers the substrate 210 exposed in the first interval N1, and the orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located between the orthographic projections of the two driving sub-circuit layers 2210 in the non-display area NAA on the substrate.

[0094] Figure 8 Can be used with Figure 5 For comparison, Figure 8The schematic diagram shows that part of the first planarization layer 260 is located in the first interval N1, and the thickness of the first planarization layer 260 covering the first interval N1 is less than or equal to the thickness of the first planarization layer 260 covering the driving sub-circuit layer 2210, so that the first planarization layer 260 located in the first interval N1 does not fill the first interval N1, but covers the side walls of the two driving sub-circuits 2210 in the first interval N1 facing the first interval N1 and covers the substrate 210 exposed in the first interval N1, and the orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located within the orthographic projection of the driving circuit layer 220 on the substrate, and the orthographic projection of the electrically connected area between the second conductive layer 250 and the first conductive layer 240 on the substrate is at least partially located between the orthographic projections of the two driving sub-circuit layers 2210 in the non-display area NAA on the substrate.

[0095] Alternatively, refer to Fig. 9 , the orthographic projection of the first planarization layer 260 on the substrate is staggered with the orthographic projection of the first interval N1 on the substrate, and part of the metal layer 230 is located in the first interval N1. In the process of preparing the film layers such as the driving sub-circuit layer 2210 in the display area AA, and / or in the process of preparing the film layers such as the driving sub-circuit layer 2210 in the non-display area NAA, packaging materials and / or insulating materials, such as inorganic materials, will be deposited in the first interval N1. When the deposited packaging materials and / or insulating materials are sufficient to isolate and protect the two adjacent driving sub-circuit layers 2210 and insulate them, the first planarization layer 260 may not be located in the first interval N1, that is, the first planarization layer 260 may not be set in the first interval N1. Not setting the first planarization layer 260 in the first interval N1 is conducive to setting more metal layers 230 in the first interval N1, and is conducive to the reliable overlap of the subsequent cathode layer 320.

[0096] In an exemplary embodiment, referring to Figure 6 , Figure 7 or Figure 8 , part of the first planarization layer 260 is located in the first interval N1, and the thickness of the first planarization layer 260 covering the first interval N1 is less than or equal to the thickness of the first planarization layer 260 covering the driving sub-circuit layer 2210. Part of the first planarization layer 260 is located in the first interval N1, which can play a role of isolating, protecting and insulating two adjacent driving sub-circuit layers 2210. Figure 6 , Figure 7 or Figure 8When the thickness of the first planarization layer 260 in the first interval N1 is small, that is, the thickness of the first planarization layer 260 in the first interval N1 is less than the thickness of the first planarization layer 260 covering the driving sub-circuit layer 2210, it is beneficial to set more metal layers 230 in the first interval N1, thereby facilitating reliable overlapping of the subsequent cathode layer 320.

[0097] In an exemplary embodiment, referring to Fig.10 , at least part of the first conductive layer 240 covers the side of the metal layer 230 in the first interval N1 away from the substrate; in this way, while realizing the electrical connection between the first conductive layer 240 and the metal layer 230, the first conductive layer 240 and the metal layer 230 have a larger contact area, which is not only conducive to the reliable overlapping of the subsequent cathode layer 320, but also conducive to reducing the overlapping resistance.

[0098] In an exemplary embodiment, referring to Fig.10 , at least a portion of the first conductive layer 240 contacts the metal layer 230 in the first interval N1; thus, the first conductive layer 240 is electrically connected to the metal layer 230.

[0099] In an exemplary embodiment, the material of the first planarization layer 260 is an organic material, such as an organic glue.

[0100] In an exemplary embodiment, referring to Fig.11 , the display panel further includes a second planarization layer 270. At least part of the second planarization layer 270 is located on the side of the metal layer 230 away from the substrate, and includes a plurality of first protrusion structures 271 in the non-display area NAA; wherein, in the direction from the display area AA to the non-display area NAA, there is a second gap N2 between two adjacent first protrusion structures 271; the second gap N2 exposes the metal layer 230, and at least part of the first conductive layer 240 contacts the metal layer 230 exposed by the second gap N2; thus, the electrical connection between the first conductive layer 240 and the metal layer 230 is achieved.

[0101] In this embodiment, the first protrusion structure 271 is provided to prevent the organic encapsulation material from overflowing to the frame and edge of the display panel during the preparation of the organic encapsulation layer 430 of the display panel, thereby ensuring the encapsulation performance of the display panel. In addition, after the first protrusion structure 271 is provided, the dam 140 in the related art can be removed, thereby further reducing the size of the non-display area NAA of the display panel, thereby further reducing the frame of the display device.

[0102] In an exemplary embodiment, the material of the second planarization layer 270 is an organic material, such as an organic glue.

[0103] In an exemplary embodiment, at least a portion of the second conductive layer 250 contacts the first conductive layer 240 ; thus, the second conductive layer 250 is electrically connected to the first conductive layer 240 .

[0104] In an exemplary embodiment, referring to Fig.12 The display panel further includes a pixel definition layer 280 and a support column layer 290. The pixel definition layer 280 is located on the side of the first conductive layer 240 away from the substrate. The support column layer 290 is located on the side of the pixel definition layer 280 away from the substrate. The pixel definition layer 280 is used to define the area of ​​the pixel, and the support column layer 290 is used to support the evaporation mask when preparing the pixel, so as to realize the preparation of the sub-pixel.

[0105] In an exemplary embodiment, referring to Fig.13 The pixel definition layer 280 includes at least one second protruding structure 281 in the non-display area NAA, and the second protruding structure 281 is located on a side of the first conductive layer 240 away from the substrate.

[0106] In this embodiment, a second protruding structure 281 is provided to combine with the first protruding structure 271 during the process of preparing the organic encapsulation layer 430 of the display panel to further prevent the organic encapsulation material from overflowing to the frame and edge of the display panel, thereby ensuring the encapsulation performance of the display panel.

[0107] In an exemplary embodiment, the second protruding structure 281 is arranged corresponding to the first protruding structure 271, and the second conductive layer 250 is in contact with the at least partially exposed first conductive layer 240; in this way, the electrical connection between the second conductive layer 250 and the first conductive layer 240 is achieved, and in this case, the first conductive layer 240 is exposed by the third interval N3 between the second protruding structure 281 and the adjacent second protruding structure 281, and the second conductive layer 250 is in contact with the at least partially exposed first conductive layer 240.

[0108] In an exemplary embodiment, the orthographic projection of the second protruding structure 281 on the substrate is staggered from the orthographic projection of the first interval N1 on the substrate; thus, the second protruding structure 281 does not block the first conductive layer 240 , ensuring that the subsequent second conductive layer 250 overlaps the first conductive layer 240 .

[0109] In an exemplary embodiment, referring to Fig.14 The support column layer 290 includes at least one third protruding structure 291 in the non-display area NAA, and the third protruding structure 291 is located on a side of the first conductive layer 240 away from the substrate.

[0110] In this embodiment, a third protruding structure 291 is provided to combine with the first protruding structure 271 during the process of preparing the organic encapsulation layer 430 of the display panel to further prevent the organic encapsulation material from overflowing to the frame and edge of the display panel, thereby ensuring the performance of the display panel.

[0111] In an exemplary embodiment, the third protruding structure 291 is arranged corresponding to the first protruding structure 271, and the second conductive layer 250 is in contact with the at least partially exposed first conductive layer 240; in this way, the electrical connection between the second conductive layer 250 and the first conductive layer 240 is achieved, and in this case, the first conductive layer 240 is exposed by the third interval N3 between the third protruding structure 291 and the adjacent third protruding structure 291, and the second conductive layer 250 is in contact with the at least partially exposed first conductive layer 240.

[0112] In an exemplary embodiment, the orthographic projection of the third protruding structure 291 on the substrate is staggered from the orthographic projection of the first gap on the substrate; thus, the third protruding structure 291 does not block the first conductive layer 240 , ensuring that the subsequent second conductive layer 250 overlaps the first conductive layer 240 .

[0113] In an exemplary embodiment, referring to Fig.15 , the pixel definition layer 280 includes at least one second protruding structure 281 in the non-display area NAA, the second protruding structure 281 is located on the side of the first conductive layer 240 away from the substrate, and the support column layer 290 includes at least one third protruding structure 291 in the non-display area NAA, the third protruding structure 291 is located on the side of the first conductive layer 240 away from the substrate, and the second conductive layer 250 is in contact with the at least partially exposed first conductive layer 240. In this way, the electrical connection between the second conductive layer 250 and the first conductive layer 240 is achieved, and in this case, the third interval N3 between the third protruding structure 291 and the adjacent second protruding structure 281 will also expose the first conductive layer 240, and the second conductive layer 250 is in contact with the at least partially exposed first conductive layer 240.

[0114] In an exemplary embodiment, the second conductive layer 250 contacts the first conductive layer 240 in the third interval N3; the third interval N3 is at least one of the following intervals: the interval between the second protruding structure 281 and the adjacent third protruding structure 291, the interval between the second protruding structure 281 and the adjacent second protruding structure 281, and the interval between the third protruding structure 291 and the adjacent third protruding structure 291.

[0115] In the embodiments of the present application, there are various specific overlapping positions of the second conductive layer 250 and the first conductive layer 240. The above embodiments are only examples. As long as the second conductive layer 250 and the first conductive layer 240 can be reliably electrically connected and reliably overlapped, they all fall within the protection scope of the present invention. Similarly, there are various specific overlapping positions of the first conductive layer 240 and the metal layer 230 in the non-display area NAA. The above embodiments are only examples. As long as the first conductive layer 240 and the metal layer 230 in the non-display area NAA can be reliably electrically connected and reliably overlapped, they all fall within the protection scope of the present invention.

[0116] In an exemplary embodiment, referring to Fig.16 The display panel further includes an anode layer 310 and a cathode layer 320 .

[0117] The anode layer 310 is located in the display area AA and on the side of the metal layer 230 away from the substrate; the material of the first conductive layer 240 is the same as that of the anode layer 310. The material of the anode layer 310 is generally a material with a higher work function to improve the hole injection efficiency, and can be gold (Au), platinum (Pt), titanium (Ti), silver (Ag), indium tin oxide (ITO), zinc tin oxide (IZO) or a transparent conductive polymer (such as polyaniline).

[0118] The cathode layer 320 is located in the display area AA and on the side of the anode layer 310 away from the substrate; the cathode layer 320 extends from the display area AA to the non-display area NAA and is electrically connected to the second conductive layer 250. The material of the cathode layer 320 generally uses a material with a low work function to facilitate electron injection. The material of the cathode can be one of the metal materials such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), ytterbium (Yb), calcium (Ca) or indium (In), and can also be an alloy of the aforementioned metal materials, such as magnesium silver alloy (Mg / Ag) and lithium aluminum alloy (Li / Al).

[0119] Usually, in a display panel, a plurality of pixels are provided in the display area AA, and the anode layer 310 in the display area AA is used to make the anodes of the plurality of pixels, and the plurality of pixels use a common cathode (i.e., cathode layer 320) covering the entire display area AA. The first conductive layer 240 can be formed in the non-display area AA while the anode layer 310 in the display area AA is formed, so as to save process and reduce the cost of the display panel. The first conductive layer 240 and the metal layer 230 in the non-display area NAA are used together for overlapping the cathode layer 320. Compared with only using a single layer of metal such as the metal layer 230 in the non-display area NAA to overlap the cathode layer 320, the resistance of the cathode layer 320 overlap can be reduced, thereby achieving better overlap of the cathode layer 320.

[0120] In an exemplary embodiment, the material of the second conductive layer 250 is the same as that of the cathode layer 320. The second conductive layer 250 can be formed in the non-display area NAA while the cathode layer 320 in the display area AA is formed, so as to save process and reduce the cost of the display panel.

[0121] In an exemplary embodiment, referring to Fig.17 The display panel further includes a first inorganic encapsulation layer 410, an organic encapsulation layer 430 and a second inorganic encapsulation layer 420 to encapsulate and protect the display panel.

[0122] The first inorganic encapsulation layer 410 is located on the side of the second conductive layer 250 away from the substrate and covers the second conductive layer 250 , and the side of the first inorganic encapsulation layer 410 away from the substrate in the first gap N1 forms a groove D, and the orthographic projection of the groove D on the substrate 210 is located within the orthographic projection of the first gap N1 on the substrate 210 .

[0123] The organic encapsulation layer 430 is located on the side of the first inorganic encapsulation layer 410 away from the substrate and covers the first inorganic encapsulation layer 410 , and part of the organic encapsulation layer 430 is located in the groove D; the second inorganic encapsulation layer 420 is located on the side of the organic encapsulation layer 430 away from the substrate and covers the organic encapsulation layer 430 .

[0124] Among them, the groove D can accommodate a portion of the overflow of the raw material of the organic encapsulation layer 430, thereby blocking the overflow of the raw material of the organic encapsulation layer 430, so that the overflow area of ​​the raw material of the organic encapsulation layer 430 is reduced, thereby reducing the range of the boundary extension of the organic encapsulation layer 430, thereby reducing the size of the non-display area of ​​the display panel, and further reducing the border of the display device.

[0125] In addition, the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 420 can extend along the direction from the display area AA to the non-display area NAA, onto the substrate 210 of the non-display area NAA, and directly contact the substrate 210, which is conducive to ensuring the packaging reliability of the display panel.

[0126] In the embodiment of the present application, due to the provision of the first convex structure 271 , the second convex structure 281 and the third convex structure 291 , during the preparation of the organic encapsulation layer 430 , overflow of the organic encapsulation material can be prevented, thereby improving encapsulation reliability.

[0127] In an exemplary embodiment, the driving circuit layer 220 includes two driving sub-circuit layers 2210 located in the non-display area NAA; in the direction from the display area AA to the non-display area NAA, the two driving sub-circuit layers 2210 are respectively the first driving sub-circuit layer 22101 and the second driving sub-circuit layer 22102.

[0128] In an embodiment of an embodiment, along the direction from the display area AA to the non-display area NAA, the first driving sub-circuit layer 22101 and the second driving sub-circuit layer 22102 are distributed as a scanning circuit (SCAN circuit) and a light-emitting control circuit (EM circuit) in sequence, and the first interval N1 is located between the scanning circuit and the light-emitting control circuit.

[0129] In an exemplary embodiment, in the non-display area, the orthographic projection of one end of the organic encapsulation layer 430 away from the display area AA on the substrate 210 is located between the orthographic projection of one end of the scanning circuit away from the display area AA on the substrate 210 and the orthographic projection of one end of the light emitting control circuit away from the display area AA on the substrate 210.

[0130] In the embodiment of the present application, due to the arrangement of the first protruding structure 271, the second protruding structure 281 and the third protruding structure 281, the overflow of the raw material of the organic encapsulation layer 430 is blocked, so that the overflow area of ​​the raw material of the organic encapsulation layer 430 is reduced, thereby reducing the range of the boundary extension of the organic encapsulation layer 430, and the range of the boundary extension of the organic encapsulation layer 430 is located between the positive projection of the end of the scanning circuit away from the display area AA on the substrate 210 and the positive projection of the end of the light emitting control circuit away from the display area AA on the substrate 210, thereby reducing the size of the non-display area of ​​the display panel, and further reducing the frame of the display device. In addition, due to the arrangement of the first protruding structure 271, the second protruding structure 281 and the third protruding structure 281, the overflow of the raw material of the organic encapsulation layer 430 is sufficiently blocked, so that the dam 140 in the related art can be removed, further reducing the size of the non-display area of ​​the display panel, and further reducing the frame of the display device.

[0131] In an exemplary embodiment, referring to Fig.18 In the case where the material of the first planarization layer 260 is an organic glue, in order to prevent bubbles in the first planarization layer 260 from remaining in the display panel, a window 231 may be provided on the metal layer 230 to exhaust the gas. Among them, since the driving sub-circuit layer 2210 in the non-display area NAA is covered with a large amount of the first planarization layer 260, a plurality of windows 231 may be provided on the metal layer 230 above the driving sub-circuit layer 2210 in the non-display area NAA to improve the exhaust efficiency. Similarly, in the case where the material of the second planarization layer 270 is an organic glue, a plurality of windows 231 may be provided on the first conductive layer 240 above the first protruding structure 271 to exhaust the gas generated from the second planarization layer 270.

[0132] In an exemplary embodiment, a display device is provided, which may be an OLED display device. The display device may be a mobile phone, a tablet computer, a television, a wearable electronic product, etc. The display device includes a display panel provided in any of the above embodiments.

[0133] The display device and display panel provided in the embodiments of the present application belong to the same inventive concept, can solve the same technical problems, and achieve the same technical effects, and repeated contents will not be repeated.

[0134] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0135] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area at least partially surrounding the display area, and the display panel includes: substrate; A driving circuit layer, located on one side of the substrate, and comprising a plurality of driving sub-circuit layers arranged at intervals; a metal layer, at least partially located on a side of the driving circuit layer away from the substrate; a first conductive layer, located at a side of the metal layer away from the substrate in the non-display area, and at least a portion of the first conductive layer is electrically connected to the metal layer in the non-display area; a second conductive layer, located at a side of the first conductive layer away from the substrate in the non-display area, and in the non-display area, at least a portion of the second conductive layer is electrically connected to the first conductive layer; The orthographic projection of the region where the second conductive layer is electrically connected to the first conductive layer on the substrate is at least partially located within the orthographic projection of the driving circuit layer on the substrate, and / or the orthographic projection of the region where the second conductive layer is electrically connected to the first conductive layer on the substrate is at least partially located between the orthographic projections of two driving sub-circuit layers in the non-display area on the substrate; the two driving sub-circuit layers are adjacent in a direction from the display area to the non-display area.

2. The display panel according to claim 1, characterized in that: The display panel further includes: A first planarization layer, located between the driving circuit layer and the metal layer, and covering a side of each driving sub-circuit layer away from the substrate; Preferably, along the direction from the display area to the non-display area, there is a first gap between two adjacent driving sub-circuit layers in the non-display area that are covered by the first planarization layer; Part of the first planarization layer is located in the first interval, and part of the metal layer is located in the first interval on a side of the first planarization layer away from the substrate, wherein a thickness of the first planarization layer covering the first interval is less than or equal to a thickness of the first planarization layer covering the driving sub-circuit layer; or, an orthographic projection of the first planarization layer on the substrate is staggered from an orthographic projection of the first interval on the substrate, and part of the metal layer is located in the first interval; Preferably, part of the first planarization layer is located in the first interval, and the thickness of the first planarization layer covering the first interval is less than the thickness of the first planarization layer covering the driving sub-circuit layer; Preferably, at least part of the first conductive layer contacts the metal layer in the first space; Preferably, at least a portion of the first conductive layer covers a side of the metal layer in the first space away from the substrate.

3. The display panel according to claim 2, characterized in that: The display panel further includes: a second planarization layer, at least partially located on a side of the metal layer away from the substrate, and comprising a plurality of first protrusion structures in the non-display area; wherein a second interval exists between two adjacent first protrusion structures in a direction from the display area to the non-display area; The second spaces expose the metal layer, and at least a portion of the first conductive layer contacts the metal layer exposed by the second spaces.

4. The display panel according to any one of claims 1 to 3, characterized in that: At least a portion of the second conductive layer contacts the first conductive layer.

5. The display panel according to claim 3, characterized in that: The display panel further includes: A pixel definition layer, located on a side of the first conductive layer away from the substrate; A support column layer, located on a side of the pixel definition layer away from the substrate; Preferably, the pixel definition layer includes at least one second protruding structure in the non-display area, and the second protruding structure is located on a side of the first conductive layer away from the substrate; and / or the support column layer includes at least one third protruding structure in the non-display area, and the third protruding structure is located on a side of the first conductive layer away from the substrate; Preferably, the second protruding structure is arranged corresponding to the first protruding structure, and the second conductive layer is in contact with at least a portion of the exposed first conductive layer; Preferably, the orthographic projection of the second protruding structure on the substrate is staggered from the orthographic projection of the first interval on the substrate; Preferably, the third protruding structure is arranged corresponding to the first protruding structure, and the second conductive layer is in contact with at least a portion of the exposed first conductive layer; Preferably, an orthographic projection of the third protruding structure on the substrate is staggered from an orthographic projection of the first gap on the substrate.

6. The display panel according to claim 5, characterized in that: The second conductive layer contacts the first conductive layer in a third interval; The third interval is at least one of the following intervals: an interval between the second convex structure and an adjacent third convex structure, an interval between the second convex structure and an adjacent second convex structure, and an interval between the third convex structure and an adjacent third convex structure.

7. The display panel according to claim 6, characterized in that: The display panel further includes: a first inorganic encapsulation layer, located on a side of the second conductive layer away from the substrate and covering the second conductive layer, wherein a side of the first inorganic encapsulation layer away from the substrate in the first gap forms a groove, and an orthographic projection of the groove on the substrate is located within an orthographic projection of the first gap on the substrate; an organic encapsulation layer, located on a side of the first inorganic encapsulation layer away from the substrate and covering the first inorganic encapsulation layer, and a portion of the organic encapsulation layer is located in the groove; The second inorganic encapsulation layer is located on a side of the organic encapsulation layer away from the substrate and covers the organic encapsulation layer.

8. The display panel according to claim 7, characterized in that: The driving circuit layer includes two driving sub-circuit layers located in the non-display area; In the direction from the display area to the non-display area, the two driving sub-circuit layers are a scanning circuit and a light-emitting control circuit in sequence; the first interval is located between the scanning circuit and the light-emitting control circuit; Preferably, in the non-display area, the orthographic projection of one end of the organic encapsulation layer away from the display area on the substrate is located between the orthographic projection of one end of the scanning circuit away from the display area on the substrate and the orthographic projection of one end of the light emitting control circuit away from the display area on the substrate.

9. The display panel according to any one of claims 1 to 3, characterized in that: The display panel further includes: an anode layer, located in the display area and on a side of the metal layer away from the substrate; the material of the first conductive layer is the same as that of the anode layer; a cathode layer, located in the display area and on a side of the anode layer away from the substrate; the cathode layer extends from the display area to the non-display area and is electrically connected to the second conductive layer; Preferably, the material of the second conductive layer is the same as that of the cathode layer.

10. A display device, characterized in that: Comprising the display panel as described in any one of claims 1-9.

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