Overlay mark

Abstract

The invention provides an overlay mark. The overlay mark comprises a previous layer mark and a current layer mark. The front layer mark comprises a plurality of first working areas, each first working area comprises a first cell and a second cell, and the first cell is closer to the center point of the front layer mark than the second cell. The front layer mark comprises a first mark and an auxiliary mark, the first mark is arranged in the first cell of each first working area, and the auxiliary mark is arranged in the second cell of each first working area. The current layer mark comprises a plurality of second working areas, and each second working area comprises the first cell and the second cell. The current layer mark comprises a second mark which is arranged in the second cell of each second working area. The overlay mark can be applied to a process for manufacturing a 3D NAND flash memory with high capacity and high performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to an overlay mark. Background Art

[0002] Photolithography is a patterning technology widely used in semiconductor processes. Photolithography usually calculates the overlay error through overlay marks. However, if the overlay mark is a trench, the conductor material filled in the trench may suffer from a loading effect when polishing. In addition, the surface profile of the conductor layer filled in the trench is uneven or asymmetric, which may also make it difficult to calculate the correct overlay error. Summary of the invention

[0003] The embodiment of the present invention provides an overlay mark, which can reduce or avoid the load effect and calculate the correct overlay error.

[0004] An overlay mark according to an embodiment of the present invention includes a previous layer mark and a current layer mark. The previous layer mark includes a plurality of first working areas, each of which includes a first small area and a second small area, wherein the first small area is closer to the center point of the previous layer mark than the second small area. The previous layer mark includes a first mark and an auxiliary mark, wherein the first mark is set in the first small area of ​​each first working area, and the auxiliary mark is set in the second small area of ​​each first working area. The current layer mark includes a plurality of second working areas, each of which includes a first small area and a second small area, wherein the first small area of ​​the current layer mark overlaps with the first small area of ​​the previous layer mark, and the second small area of ​​the current layer mark overlaps with the second small area of ​​the previous layer mark, and the current layer mark includes a second mark set in the second small area of ​​each second working area.

[0005] Based on the above, the overlay mark of the embodiment of the present invention can reduce or avoid the load effect and calculate the correct overlay error. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A FIG. 4 is a top view of a front layer mark of an overlay mark according to an embodiment of the present invention.

[0007] Figure 1B FIG. 4 is a top view of a current layer mark of an overlay mark according to an embodiment of the present invention.

[0008] Figure 1C FIG. 4 is a top view of an overlay mark according to an embodiment of the present invention.

[0009] Figure 2 FIG. 4 is a schematic diagram of a local area of ​​an overlay mark and a signal wave during measurement according to an embodiment of the present invention.

[0010] FIG. 3A to FIG. 3E FIG. 4 is an enlarged schematic diagram of a local area of ​​a first overlay pattern according to various embodiments of the present invention.

[0011] FIG. 4A to FIG. 4B Schematic diagram of an enlarged local area of ​​an auxiliary mark according to various embodiments of the present invention.

[0012] Figure 5 FIG. 4 is an enlarged schematic diagram of a local area of ​​a second overlay pattern according to an embodiment of the present invention.

[0013] Fig. 6A FIG. 4 is a top view of a front layer mark of an overlay mark according to another embodiment of the present invention.

[0014] Figure 6B FIG. 4 is a top view of a current layer mark of an overlay mark according to another embodiment of the present invention.

[0015] Figure 6C FIG. 4 is a top view of an overlay mark according to another embodiment of the present invention.

[0016] Figure 7 FIG. 4 is a schematic diagram of a local area of ​​an overlay mark and a signal wave during measurement according to another embodiment of the present invention.

[0017] FIG. 8A to FIG. 8F is a cross-sectional schematic diagram of a manufacturing process of a memory device according to an embodiment of the present invention.

[0018] Fig.9A and Fig. 9B They are Figure 1C Schematic cross-sectional view of line II′ and line II-II′.

[0019] Description of Reference Numerals

[0020] 10: First working area

[0021] 10A, 20A: First District

[0022] 10B, 20B: Second cell

[0023] 10C, 20C: Center point

[0024] 20: Second work area

[0025] 100: First Mark

[0026] 100W, 200W: signal wave

[0027] 100a: First overlay pattern

[0028] 100s: First sub-pattern

[0029] 102, 102′: Auxiliary marking

[0030] 102a, 102a′: auxiliary pattern

[0031] 110, 120, 120′, 220: local area

[0032] 200: Second Mark

[0033] 200a: Second overlay pattern

[0034] 200s: Second sub-pattern

[0035] 300: Complete memory element

[0036] 302: Insulation layer

[0037] 304: Spacer layer

[0038] 308: Charge storage structure

[0039] 310: Base

[0040] 320: Component layer

[0041] 326, 348, ML4: Conductor layer

[0042] 330, 362: Metal interconnect structure

[0043] 332, 334, 364: Dielectric layer

[0044] 336: Stop layer

[0045] 340, 342, 354, 356: Channel

[0046] 344: Barrier layer

[0047] 346: Metal layer

[0048] 348: Conductor layer

[0049] 350: Top cover dielectric layer

[0050] 366: Plug

[0051] 368: Wire

[0052] 370: Protective layer

[0053] 1000A, 1000A′: Overlap mark

[0054] 1000C, 1000C′: when the layer is marked

[0055] 1000P, 1000P′: front layer mark

[0056] AR: Array of Memory

[0057] B1, B2: Block

[0058] BL: Bit Line

[0059] C1, C2, TAC: Contact window

[0060] CP: Vertical Channel Column

[0061] D1: First direction

[0062] D2, D2′: Second direction

[0063] D3: Third direction

[0064] D4, D4′: The fourth direction

[0065] DR: Chip area

[0066] H1: Holes

[0067] L0: Slanted lines

[0068] L0′: Line

[0069] L1, L1′ first line

[0070] l0, l0′, l1, l1′, l2: length

[0071] L2: Second Line

[0072] MC: Memory Cell

[0073] MD: Memory Element

[0074] OP31: Via Window

[0075] P1: First gap width

[0076] P2: Second gap width

[0077] PR: Photoresist layer

[0078] R1: Storage array area

[0079] R2: Step Area

[0080] R3: Peripheral area

[0081] SC: Ladder structure

[0082] SK1, SK2: stacked structure

[0083] SR: Cutting Road Area

[0084] V31: Interlayer Window

[0085] W1: First width

[0086] W2: Second width

[0087] w0, w0′, w1, w1′, w2, w4: width

[0088] WL: Word Line

[0089] d1: diameter

[0090] p0, p0′: gap width

[0091] p1, p1′, p1″, p2: inner gap width

[0092] ΔX, ΔY: Overlay error

[0093] θ, θ′: Angle

[0094] II′, II-II′: line DETAILED DESCRIPTION

[0095] Figure 1A FIG. 1 is a top view of a front layer mark 1000P of an overlay mark 1000A according to an embodiment of the present invention. Figure 1B FIG. 1 is a top view of a current layer mark 1000C of an overlay mark 1000A according to an embodiment of the present invention. Figure 1C FIG. 1 is a top view of an overlay mark 1000A according to an embodiment of the present invention.

[0096] Reference Figures 1A to 1C , an overlay mark 1000A of an embodiment of the present invention includes a front layer mark 1000P and a current layer mark 1000C. Referring to FIG. 1A , the front layer mark 1000P includes a plurality of first working areas 10. Figure 1A In the embodiment, the front layer mark 1000P includes four first working areas 10, but the present invention is not limited thereto. The four first working areas 10 are adjacent to each other, and each first working area 10 includes a first small area 10A and a second small area 10B, wherein the first small area 10A is closer to the center point 10C of the front layer mark 1000P than the second small area 10B. In other words, the multiple first small areas 10A of the front layer mark 1000P are adjacent to each other and arranged in a windmill shape; the multiple second small areas 10B of the front layer mark 1000P are separated from each other by the multiple first small areas 10A.

[0097] Reference Figure 1A The front layer mark 1000P includes a plurality of first marks 100, each of which is respectively arranged in the first area 10A of each first working area 10. In this embodiment, the front layer mark 1000P includes four first marks 100, which are adjacent to each other. The first mark 100 of the front layer mark 1000P is used to communicate with the second mark 200 (shown in FIG. 200 ) of the current layer mark 1000C. Figure 1B ) is used to calculate the overlay error. Each first mark 100 includes a plurality of first overlay patterns 100a extending along the first direction D1. Figure 1A In the embodiment, each first mark 100 includes 6 first overlay patterns 100a. However, the embodiment of the present invention is not limited thereto. Each first mark 100 may include more first overlay patterns 100a.

[0098] FIG. 3A to FIG. 3E FIG. 1 is an enlarged schematic diagram of a local area 110 of a first overlay pattern 100 a according to various embodiments of the present invention.

[0099] Reference Figure 1A as well as FIG. 3A to FIG. 3E The first overlay patterns 100a extend along the first direction D1 and are arranged along the third direction D3. The first widths W1 of the first overlay patterns 100a are substantially equal. The first gap widths P1 of the first overlay patterns 100a are substantially equal. The ratio (P1 / W1) of the first gap width P1 to the first width W1 is in the range of 0.8 to 2.

[0100] Each first stacked pattern 100a includes at least one first sub-pattern 100s. Figure 1A , Figure 3A Each first overlay pattern 100a may include three first sub-patterns 100s. However, the present invention is not limited thereto. Each first overlay pattern 100a may include two first sub-patterns 100s or a single first sub-pattern 100s, respectively. Figure 3B and Figure 3C In other embodiments of the present application, each first stacked pattern 100a may include more than 10 or more first sub-patterns 100s, such as Figure 3D and Figure 3E shown.

[0101] Reference FIG. 3A to FIG. 3C , the first sub-pattern 100s may be a first line (or first channel) L1 extending along the first direction D1. The first line L1 has a width w1 and a length ￡1. Figure 3A and Figure 3B In an embodiment where the first overlay pattern 100a includes a plurality of first sub-patterns 100s, the first lines L1 of the first sub-patterns 100s may extend along the first direction D1 and be arranged along the third direction D3. The widths w1 of the plurality of first lines L1 are substantially equal, and the lengths l1 are substantially equal. The inner gap widths p1 between the plurality of first sub-patterns 100s (first lines L1) of each first overlay pattern 100a are substantially equal. The ratio (p1 / w1) of the inner gap width p1 to the width w1 is, for example, in the range of 0.8 to 1.2.

[0102] Reference Figure 3D , the first sub-pattern 100s may be a first line (or first channel) L1′ extending along the third direction D3. In some embodiments, the first overlay pattern 100a includes a plurality of first sub-patterns 100s, and the first lines L1′ of the first sub-patterns 100s may extend along the third direction D3 and be arranged along the first direction D1. The widths w1′ of the plurality of first lines L1′ are substantially equal, and the lengths l1′ are substantially equal. The inner gap widths p1′ between the plurality of first sub-patterns 100s (first lines L1′) of each first overlay pattern 100a are substantially equal. The first gap widths P1 between the first overlay patterns 100a are substantially equal.

[0103] Reference Figure 3E , the first sub-pattern 100s may include a hole H1. In some embodiments, the first overlay pattern 100a may include a plurality of first sub-patterns 100s, and the holes H1 of the first sub-pattern 100s may be arranged along the first direction D1. The diameters d1 of the holes H1 are substantially equal. The inner gap widths p1″ between the plurality of first sub-patterns 100s (holes H1) of each first overlay pattern 100a are substantially equal. The first gap widths P1 between the first overlay patterns 100a are substantially equal.

[0104] Reference Figure 1A , the front layer mark 1000P further includes a plurality of auxiliary marks 102. The plurality of auxiliary marks 102 are respectively arranged in the second area 10B of each first working area 10. In this embodiment, the front layer mark 1000P includes four auxiliary marks 102, and they are separated by four first marks 100.

[0105] Reference Figure 1A The auxiliary pattern 102a of the auxiliary mark 102 has a function different from the first overlay pattern 100a of the first mark 100 and is not used to calculate the overlay error. The auxiliary pattern 102a is an auxiliary pattern used to reduce the load effect. Therefore, the auxiliary pattern 102a can also be called a load effect auxiliary pattern.

[0106] exist Figure 1A In the embodiment, the first mark 100 in the first cell 10A includes a plurality of first sub-patterns (or first pattern units) 100s, for example, more than 20 or more. In each first working area 10, the first mark 100 in the first cell 10A includes 18 first sub-patterns 100s; the auxiliary mark 102 in the second cell 10B includes more than 20 auxiliary patterns 102a.

[0107] The pattern density of the auxiliary mark 102 in the second cell 10B of the front layer mark 1000P is greater than the pattern density of the first mark 100 in the first cell 10A of the front layer mark 1000P. More specifically, the number of auxiliary patterns 102a is greater than the number of first sub-patterns 100s, and the total area of ​​the auxiliary patterns 102a is greater than the total area of ​​the first sub-patterns 100s. The pattern density of the auxiliary patterns 102a of the auxiliary mark 102 in the second cell 10B is greater than the pattern density of the first overlay pattern 100a of the first mark 100 in the first cell 10A.

[0108] Figure 4A FIG. 1 is an enlarged schematic diagram of the auxiliary mark 102 in the local area 120 according to an embodiment of the present invention.

[0109] Reference Figure 4A In this embodiment, the auxiliary pattern 102a includes inclined lines L0. The inclined lines L0 extend along the second direction D2 and are arranged along the fourth direction D4. The second direction D2 is different from the first direction D1, and the fourth direction D4 is also different from the first direction D1. The second direction D2 has an angle θ with the first direction D1, and the range of the angle θ is, for example, 0<θ<90° or 90°<θ<180°. The widths w0 of the multiple inclined lines L0 are approximately equal, and the lengths l0 can have various variations to cover the second area 10B. The gap widths p0 between the inclined lines L0 are approximately equal. The ratio of the width w0 to the gap width p0 is, for example, in the range of 0.8 to 1.2.

[0110] Reference FIG. 3A to FIG. 3E as well as Figure 4A , the width w0 of the inclined line L0 may be less than, equal to, or greater than the width w1 or w1′ of the first line L1 or L1′. The length l0 of the inclined line L0 may be less than, equal to, or greater than the length l1 or l1′ of the first line L1 or L1′. The gap width p0 of the inclined line L0 may be less than, equal to, or greater than the inner gap width p1, p1′, or p1″ of the first lines L1, L1′, or the hole H1. The gap width p0 of the inclined line L0 may be less than the first gap width P1 between the first lines L1, L1′, or the hole H1.

[0111] The auxiliary mark 102 in the embodiment of the present invention is arranged outside the first mark 100, which can reduce the influence of the load effect on the first mark 100.

[0112] The plurality of first working areas 10 of the front layer mark 1000P may have the same plurality of first marks 100 and the same plurality of auxiliary marks 102. The first marks 100 and the auxiliary marks 102 of the first working area 10 may be rotated 90 degrees to form the first marks 100 and the auxiliary marks 102 of the adjacent first working areas 10. Therefore, the plurality of first marks 100 of the front layer mark 1000P may be arranged in a windmill shape. The plurality of auxiliary marks 102 are formed on the periphery of the windmill-shaped first marks 100.

[0113] Reference Figure 1B , when the layer mark 1000C includes a plurality of second working areas 20. Figure 1B In the embodiment, the layer mark 1000C includes four second working areas 20, but the present invention is not limited thereto. The four second working areas 20 are adjacent to each other, and each second working area 20 includes a first small area 20A and a second small area 20B, wherein the first small area 20A is closer to the center point 20C of the layer mark 1000C than the second small area 20B. In other words, the multiple first small areas 20A of the layer mark 1000C are adjacent to each other; and the multiple second small areas 20B of the layer mark 1000C are separated from each other by the multiple first small areas 20A.

[0114] Reference Figure 1B , when the first cell 20A of the layer mark 1000C may not be set with any pattern, but a blank area may be formed. When the second cell 20B of the layer mark 1000C may be set with a second mark 200. When the multiple second working areas 20 of the layer mark 1000C may have the same multiple blank areas and the same multiple second marks 200. The blank areas and multiple second marks 200 of the second working area 20 may be rotated 90 degrees to form the blank areas and multiple second marks 200 of the adjacent second working areas 20. Therefore, when the multiple first cells 20A of the layer mark 1000C may form a windmill-shaped blank area. Multiple second marks 200 may be formed on the periphery of the windmill-shaped blank area.

[0115] Reference Figure 1B , when the second mark 200 of the layer mark 1000C is used with the first mark 100 of the previous layer mark 1000P (shown in Figure 1A ) is used to calculate the overlay error. Each second mark 200 includes a plurality of second overlay patterns 200a extending along the first direction D1. Each second mark 200 includes 6 second overlay patterns 200a. However, the embodiment of the present invention is not limited thereto. Each second mark 200 may include more second overlay patterns 200a.

[0116] Figure 5 FIG. 2 is an enlarged schematic diagram of a local area 220 of a second overlay pattern 200 a according to an embodiment of the present invention.

[0117] Reference Figure 1B and Figure 5 The second overlay patterns 200a extend along the first direction D1 and are arranged along the third direction D3. Each second overlay pattern 200a includes at least one second sub-pattern 200s. Figure 1B In the embodiment of the present invention, each second overlay pattern 200a may include three second sub-patterns 200s. However, the embodiment of the invention is not limited thereto. Each second overlay pattern 200a may include two or a single second sub-pattern 200s (not shown). In other embodiments of the present application, each second overlay pattern 200a may include more than 10 or more second sub-patterns 200s (not shown).

[0118] Reference Figure 5 , the second sub-pattern 200s may be a second line (or second channel) L2 extending along the first direction D1. In some embodiments, the second overlay pattern 200a includes a plurality of second sub-patterns 200s, and the second lines L2 of the second sub-patterns 200s may extend along the first direction D1 and be arranged along the third direction D3. The widths w2 of the plurality of second lines L2 are substantially equal, and the lengths L2 are substantially equal. The inner gap widths p2 between the plurality of second sub-patterns 200s (second lines L2) of each second overlay pattern 200a are substantially equal. The second gap widths P2 between the second overlay patterns 200a are substantially equal.

[0119] Reference Figure 4A and Figure 5 , the width w0 of the inclined line L0 may be less than, equal to, or greater than the second width W2 of the second line L2. The length ￡0 of the inclined line L0 may be less than, equal to, or greater than the length ￡2 of the second line L2. The gap width p0 of the inclined line L0 may be less than, equal to, or greater than the inner gap width p2 of the second line L2. The gap width p0 of the inclined line L0 may be less than the first gap width P2 between the second lines L2.

[0120] Reference Figure 1A and Figure 1B Similarly, the pattern density of the auxiliary mark 102 in the second small area 10B of the front layer mark 1000P is greater than the pattern density of the second mark 200 in the second small area 20B of the current layer mark 1000C. More specifically, the number of auxiliary patterns 102a is greater than the number of second sub-patterns 200s, and the total area of ​​the auxiliary patterns 102a is greater than the total area of ​​the second sub-patterns 200s. The pattern density of the auxiliary pattern 102a of the auxiliary mark 102 in the second small area 10B is greater than the pattern density of the second overlay pattern 200a of the second mark 200 in the second small area 20B.

[0121] Reference Figure 1C, the current layer mark 1000C overlaps with the previous layer mark 1000P to form an overlay mark 1000A. In the corresponding first working area 10 and second working area 20, the first cell 20A of the current layer mark 1000C overlaps with the first cell 10A of the previous layer mark 1000P; the second cell 20B of the current layer mark 1000C overlaps with the second cell 10B of the previous layer mark 1000P. The overlay error can be calculated by the second mark 200 in the second cell 20B and the first mark 100 in the first cell 10A.

[0122] Figure 2 FIG. 4 is a schematic diagram of a local area of ​​an overlay mark 1000A and a signal wave during measurement according to an embodiment of the present invention.

[0123] Reference Figure 2 The overlay error can be obtained by comparing the peak value of the signal wave 200W of the multiple second overlay patterns 200a of the current layer mark 1000C with the peak value of the signal wave 100W of the multiple first overlay patterns 100a of the front layer mark 1000P to obtain the overlay errors ΔX and ΔY in the X direction and the Y direction.

[0124] Fig. 6A FIG. 1 is a top view of a front layer mark 1000P′ of an overlay mark 1000A′ according to an embodiment of the present invention. Figure 6B FIG. 1 is a top view of a current layer mark 1000C′ of an overlay mark 1000A′ according to an embodiment of the present invention. Figure 6C FIG. 1 is a top view of an overlay mark 1000A′ according to an embodiment of the present invention.

[0125] Reference FIG. 6A to FIG. 6C An overlay mark 1000A′ according to an embodiment of the present invention includes a front layer mark 1000P′ and a current layer mark 1000C′.

[0126] Reference Figure 1A and Fig. 6A The front layer mark 1000P′ is similar to the front layer mark 1000P. The multiple first marks 100 of the front layer mark 1000P′ are the same as the multiple first marks 100 of the front layer mark 1000P, but the multiple auxiliary marks 102′ of the front layer mark 1000P′ are different from the multiple auxiliary marks 102 of the front layer mark 1000P.

[0127] Figure 4B is an enlarged schematic diagram of an auxiliary mark 102 ′ in a local area 120 ′ according to an embodiment of the present invention.

[0128] Reference Figure 4B and Fig. 6A, multiple auxiliary marks 102' are located in multiple second small areas 10B. Each auxiliary mark 102' includes multiple auxiliary patterns 102a'. In this embodiment, the auxiliary pattern 102a' is a line L0', which extends along the second direction D2' and is arranged along the fourth direction D4'. The second direction D2' is perpendicular to the first direction D1, and the fourth direction D4' is parallel to the first direction D1.

[0129] The second direction D2′ has an angle θ′ with the first direction D1, and the angle θ′ is 90 degrees. The widths w0′ of the multiple lines L0′ are substantially equal, and the lengths ￡0′ of the multiple lines L0′ are substantially equal. The gap widths p0′ between the multiple lines L0′ are substantially equal. The ratio of the width w0′ to the gap width p0′ is, for example, in the range of 0.8 to 1.2.

[0130] Reference FIG. 3A to FIG. 3E as well as Figure 4B , the width w0′ of the line L0′ may be less than, equal to, or greater than the width w1 or w1′ of the first line L1 or L1′. The length l0′ of the line L0′ may be greater than the length l1 or l1′ of the first line L1 or L1′. The gap width p0′ of the line L0′ may be less than, equal to, or greater than the inner gap width p1, p1′, or p1″ of the first lines L1, L1′, or the hole H1. The gap width p0′ of the line L0′ may be less than the first gap width P1 between the first lines L1, L1′, or the hole H1.

[0131] The pattern density of the auxiliary mark 102' in the second small area 10B of the front layer mark 1000P' is greater than the pattern density of the first mark 100 in the first small area 10A.

[0132] Likewise, the auxiliary mark 102 ′ of the embodiment of the present invention is disposed outside the first mark 100 , which can reduce the influence of the load effect on the first mark 100 .

[0133] Reference Figure 6B , the current layer mark 1000C' is similar to the current layer mark 1000C. Similarly, the pattern density of the auxiliary mark 102' in the second small area 10B of the front layer mark 1000P' is greater than the pattern density of the second mark 200 in the second small area 20B of the current layer mark 1000C'.

[0134] Reference Figure 6C , when the layer mark 1000C' overlaps with the previous layer mark 1000P' to form an overlay mark 1000A', an overlay error can be calculated by the second mark 200 in the second area 20B and the first mark 100 in the first area 10A.

[0135] Figure 7FIG. 4 is a schematic diagram of a local area of ​​an overlay mark 1000A′ and a signal wave during measurement according to another embodiment of the present invention.

[0136] Reference Figure 7 The overlay error can be obtained by measuring the peak value of the signal wave 200W of the multiple second overlay patterns 200a in the multiple second working areas 20 of the current layer mark 1000C′ and the peak value of the signal wave 100W of the multiple first overlay patterns 100a in the multiple first working areas 10 of the front layer mark 1000P′, and then calculating the overlay errors ΔX and ΔY in the X direction and the Y direction.

[0137] Reference Figure 1C and Figure 6C The above-mentioned overlay marks 1000A and 1000A′ can be applied to the manufacturing process of semiconductor devices, such as memory devices. The following takes the overlay mark 1000A applied to the manufacturing process of NAND flash memory devices as an example for explanation, but the present invention is not limited thereto. FIG. 8A to FIG. 8F is a cross-sectional schematic diagram of a manufacturing process of a memory device MD according to an embodiment of the present invention. Fig.9A and Fig. 9B They are Figure 1C Schematic cross-sectional view of line II′ and line II-II′.

[0138] Reference Fig. 8A and Fig.9A , providing a substrate 310. The substrate 310 includes a chip region DR and a scribe line region SR. The chip region DR includes a memory array region R1, a step region R2, and a peripheral region R3. The substrate 310 may be a semiconductor substrate, such as a silicon-containing substrate. The substrate 310 may also be divided into blocks B1 and B2. The step region R2 and the peripheral region R3 are cross-sectional schematic diagrams along the same direction, and the memory array region R1 is a cross-sectional schematic diagram along another direction.

[0139] A device layer 320 is formed on the substrate 310 of the chip region DR. The device layer 320 may include active devices or passive devices. Active devices are, for example, transistors, diodes, etc. Passive devices are, for example, capacitors, inductors, etc. Transistors may be N-type metal oxide semiconductor (NMOS) transistors, P-type metal oxide semiconductor (PMOS) transistors, or complementary metal oxide semiconductor devices (CMOS).

[0140] A metal interconnect structure 330 is formed on the substrate 310. The metal interconnect structure 330 covers the device layer 320. The metal interconnect structure 330 may include multiple dielectric layers and metal interconnects formed in the multiple dielectric layers. The metal interconnects may be electrically connected to active devices or passive devices of the device layer 320.

[0141] A stacked structure SK1 is formed on the metal interconnect structure 330. A portion of the stacked structure SK1 includes a plurality of insulating layers and a plurality of conductive layers stacked alternately. In one embodiment, the insulating layer is made of silicon oxide, and the conductive layer is made of doped polysilicon. Another portion of the stacked structure SK1 includes a plurality of conductive layers connected to each other, which can be used as a common source line.

[0142] A stacked structure SK2 has been formed on the stacked structure SK1. The stacked structure SK2 in the peripheral region R3 includes a plurality of insulating layers 302 and a plurality of spacer layers 304 stacked alternately. The stacked structure SK2 in the storage array region R1 and the step region R2 includes a plurality of insulating layers 302 and a plurality of conductor layers 326 stacked alternately. The conductor layer 326 can be used as a word line WL. The plurality of insulating layers 302 and the plurality of conductor layers 326 in the step region R2 can form a step structure SC. The material of the insulating layer 302 includes silicon oxide. The material of the spacer layer 304 includes silicon nitride. The conductor layer 326, for example, includes a barrier layer and a metal layer. The material of the barrier layer includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer includes tungsten (W).

[0143] A plurality of vertical channel pillars CP and a plurality of charge storage structures 308 are formed in the stacked structure SK2. The vertical channel pillar CP includes a polysilicon layer, and the polysilicon layer can be coated on the periphery of the insulating pillar. The vertical channel pillar CP can be electrically connected to the conductor layer in the stacked structure SK1. The charge storage structure 308 is between the vertical channel pillar CP and the plurality of conductor layers 326. The charge storage structure 308 is, for example, an oxide / nitride / oxide (ONO) composite layer. The conductor layer 326, the vertical channel pillar CP and the charge storage structure 308 can together form a memory cell MC. Therefore, the stacked structure SK2 can include a memory array AR composed of a plurality of memory cells MC. Since the device layer 320 can include, for example, a complementary metal oxide semiconductor device (CMOS), and since the complementary metal oxide semiconductor device is formed below the memory array, this architecture can also be referred to as a complementary metal oxide semiconductor device below the memory array (CMOS-Under-Array, CUA) structure.

[0144] A dielectric layer 332 has been formed on the stacked structure SK2. The dielectric layer 332 may include a single layer or multiple layers. The dielectric layer 332 may include silicon oxide, silicon nitride, or a combination thereof. In addition, contact windows C1, C2, and TAC have been formed in the dielectric layer 332, the stacked structures SK2, and SK1. The contact window C1 lands on the vertical channel column CP and is electrically connected thereto. The contact window C2 is electrically connected to the conductor layer 326 of the step structure SC. The contact window TAC may also be referred to as a through array contact. The contact window TAC is electrically connected to the metal interconnect structure 330.

[0145] Reference Figure 8B and Fig.9A , a dielectric layer 334 and a stop layer 336 are formed on the dielectric layer 332. The dielectric layer 334 can be a single layer or multiple layers. The dielectric layer 334 includes, for example, silicon oxide. The stop layer 336 includes, for example, silicon nitride. Next, a plurality of via windows V31 are formed in the stop layer 336 and the dielectric layer 334 in the chip region DR, such as Figure 8B In addition, a plurality of first overlay patterns 100a of the first mark 100 and a plurality of auxiliary patterns 102a of the auxiliary mark 102 are formed in the stop layer 336 and the dielectric layer 334 of the scribe line region SR, respectively as shown in FIG. Fig.9A and Fig. 9B shown.

[0146] The method for forming the via window V31, the plurality of first overlay patterns 100a, and the plurality of auxiliary patterns 102a is, for example, to form a plurality of via window holes OP31, and a plurality of trenches 340 and 342 in the stop layer 336 and the dielectric layer 334. Then, a conductor material (not shown) is formed in the plurality of via window holes OP31, the plurality of trenches 340 and 342, and on the stop layer 336, and then a polishing process such as chemical mechanical polishing is performed to remove the conductor material on the stop layer 336, thereby forming a conductor layer 348 in the plurality of via window holes OP31, the plurality of trenches 340 and 342. The conductor layer 348 may include a barrier layer 344 and a metal layer 346. The barrier layer 344 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The metal layer 346 may include, for example, tungsten. The plurality of via holes OP31 and the conductive layer 348 in the plurality of trenches 340 and 342 serve as the vias V31 , the plurality of first overlay patterns 100 a and the plurality of auxiliary patterns 102 a , respectively.

[0147] In some embodiments, the width w4 of the via hole OP31 is less than or equal to 100 nm, and the width w1 of the channel 340 and the width w0 of the channel 342 are less than 0.8 μm. In the embodiment of the present invention, the widths w4, w1 and w0 of the plurality of via holes OP31 and the plurality of channels 340 and 342 are less than or equal to twice the thickness of the conductor material, so that the conductor layer 348 can fill the via hole OP31, the channels 340 and 342 without leaving a dish-shaped groove in the via hole OP31, the channels 340 and 342. If the dish-shaped groove is left in the channel 340 without filling the conductor layer 348, the conductor layer 348 in the channel 340 may be asymmetric, thereby causing interference with subsequent overlay measurement. Since the channel 340 of the present invention can be filled with the conductor layer 348, the interference problem caused by not filling the conductor layer 348 can be avoided.

[0148] Reference Figure 8C and Fig.9A A cap dielectric layer 350 is formed on the stop layer 336 and the conductor layer 348. The cap dielectric layer 350 is, for example, a silicon oxide layer. Then, a photoresist material is formed on the cap dielectric layer 350. Then, a photolithography process is performed to form a patterned photoresist layer PR. The patterned photoresist layer PR of the chip region DR has a plurality of trenches 352, such as Figure 8C There are a plurality of channels 354 in the patterned photoresist layer PR of the cutting road region SR, as shown in FIG. Fig. 9B As shown. Multiple channels 354 can be used as multiple second overlay patterns 200a. Afterwards, by measuring multiple first overlay patterns 100a and second overlay patterns 200a for overlay measurement and calculation, the overlay errors ΔX and ΔY can be obtained, and then the alignment of the photolithography process can be determined. If the alignment error range is exceeded, a rework process is performed to remove the photoresist layer PR, re-form another photoresist layer, and then another photolithography process is performed. If it is within the alignment error range, the subsequent process is continued.

[0149] Reference Fig.8D , the top cover dielectric layer 350 is etched using the patterned photoresist layer PR as a mask to form a channel 356 in the chip region DR, and a channel (not shown) is formed in the top cover dielectric layer 350 in the scribe region SR. For simplicity, the scribe region SR will not be discussed later.

[0150] Reference Fig. 8E, a conductor material (not shown) is formed in the channel 356, and then a polishing process such as chemical mechanical polishing is performed to remove the conductor material on the stop layer 336, thereby forming a conductor layer ML4 in the plurality of channels 356. The conductor layer ML4 may include a barrier layer and a metal layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof. The metal layer may include copper, for example. The conductor layer ML4 connected to the contact window C1 may be used as a bit line BL.

[0151] Reference Figure 8F , forming a metal interconnect structure 362 and a protective layer 370. The metal interconnect structure 362 may include a plurality of dielectric layers 364, a plurality of plugs 366, and a plurality of conductive lines 368. The dielectric layer 364 may include silicon oxide, for example. The protective layer 370 may include silicon nitride, for example. Thus, the manufacturing of the memory element 300 is completed.

[0152] In the embodiment of the present invention, the front layer mark of the overlay mark is designed with a line segment (channel) or a hole with a smaller width to design the first overlay pattern, so that the conductor layer can completely fill the line segment (channel) or the hole, thereby avoiding interference in overlay measurement caused by incomplete filling of the conductor layer.

[0153] Furthermore, the front layer mark of the overlay mark of the embodiment of the present invention is set close to the center (such as the center point) of the overlay mark, and the auxiliary mark is set at the periphery of the front layer mark. The auxiliary mark set at the periphery of the front layer mark can reduce the load effect of the polishing process, and reduce or avoid the first overlay pattern from being affected by the load effect.

Claims

1. An overlay mark, comprising: A front-layer mark includes a plurality of first working areas, each of which includes a first small area and a second small area, wherein the first small area is closer to a center point of the front-layer mark than the second small area, and the front-layer mark includes: A first mark is set in the first small area of ​​each first working area; and an auxiliary mark, disposed in the second small area of ​​each first working area; and The current layer mark includes a plurality of second working areas, each second working area includes a first cell and a second cell, the first cell of the current layer mark overlaps with the first cell of the previous layer mark, the second cell of the current layer mark overlaps with the second cell of the previous layer mark, and the current layer mark includes: A second mark is set in the second small area of ​​each second working area.

2. The overlay mark according to claim 1, wherein a pattern density of the auxiliary mark in the second small area of ​​the front layer mark is greater than a pattern density of the first mark in the first small area of ​​the front layer mark.

3. The overlay mark according to claim 2, wherein the pattern density of the auxiliary mark in the second small area of ​​the front layer mark is greater than the pattern density of the second mark in the second small area of ​​the current layer mark. 4 . The overlay mark according to claim 1 , wherein the auxiliary mark comprises a plurality of auxiliary patterns, and the plurality of auxiliary patterns comprises a plurality of inclined lines. 5 . The overlay mark according to claim 4 , wherein the first mark comprises a plurality of first overlay patterns extending in a first direction, and the plurality of inclined lines of the plurality of auxiliary patterns extend in a second direction, the second direction being different from the first direction. 6 . The overlay mark according to claim 5 , wherein the plurality of first overlay patterns have a first gap, and a gap between the plurality of inclined lines of the plurality of auxiliary patterns is smaller than the first gap. 7 . The overlay mark according to claim 5 , wherein the second mark comprises a plurality of second overlay patterns extending in the first direction. 8 . The overlay mark according to claim 7 , wherein each first overlay pattern comprises a plurality of first sub-patterns. 9 . The overlay mark according to claim 8 , wherein the plurality of first sub-patterns comprises a plurality of first lines, and the plurality of first lines are arranged along the first direction.

10. The overlay mark according to claim 1, wherein the first mark comprises a plurality of first overlay patterns extending in a first direction, the auxiliary mark comprises a plurality of auxiliary patterns, the plurality of auxiliary patterns comprises a plurality of lines extending in a second direction, and the second direction is perpendicular to the first direction.

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