Power management unit redundancy reset system, automobile chip and automobile

Abstract

The invention relates to a power management unit redundancy reset system, an automobile chip and an automobile. The reset system comprises a voltage stabilization module, a native power-on reset module, an internal redundancy power-on reset module, a reset mode configuration module and a reset signal output module. Digital voltage is accessed through the voltage stabilizing module, and the digital voltage is converted into analog voltage to be input to the original power-on reset module and the internal redundancy power-on reset module. In the boosting process, the original power-on reset module continuously detects the climbing of the digital voltage and the analog voltage, and can output a reset signal to the chip function system after the digital voltage reaches a first threshold value and the analog voltage reaches a second threshold value. In addition, the internal redundant power-on reset module can also continuously detect the climbing of the analog voltage and output the reset signal to the chip function system when the analog voltage reaches the third threshold value, so that the reset signal can be provided when the original power-on reset module fails, and the operation stability and reliability of the chip can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip startup stability, and in particular to a power management unit redundant reset system, an automobile chip and an automobile. Background Art

[0002] During the startup process of automotive industry chips, in order to ensure that the chip has a good operating state after power-on, the chip must go through three stages: power-on, reset and normal working state. Reset is the basis for normal operation. The reset process includes reset, clock initialization to ensure the normal operation of the chip's clock system, memory initialization to clear the data in the chip memory, peripheral initialization of various peripherals on the chip (such as serial port, network port, etc.), and the operating system starts to enter the application execution stage. Reset is a key action for chip power-on, mainly including power reset, hardware reset and software reset. The corresponding reset sequence is that when the power management unit (Power Management Unit, PMU) receives the external initial voltage signal, the VDD voltage rises to the set power-on reset (Power On Reset, POR) threshold, executes reset, and outputs a hardware reset signal to each hardware functional module of the chip. Each hardware functional module of the chip executes reset. After the hardware reset is successful, the software is loaded to execute the corresponding function.

[0003] As a chip system reset front-end module, the reset accuracy and success rate of the power management unit are directly related to whether a chip can start and run normally. Therefore, the reset capability of the power management unit is the core capability of the chip function, especially for automotive-grade chips. The failure rate of the chip is based on the failure probability of a single transistor at a certain process node, which is used to deduce the failure probability of the on-chip logic or memory. The larger the area and the more transistors, the greater the corresponding failure rate.

[0004] The power management unit is equipped with a clock oscillation module, a POR detection module, and a reset module. The POR module detects that the VCC access voltage has increased. Once the voltage reaches the threshold, the clock oscillation module starts to oscillate. At the same time, the reset module controls the PMU reset. The POR detection module may have stability problems due to process factors during the power-on process, such as Figure 1 As shown, Figure 1 It is a schematic diagram of the abnormal reset trigger voltage of the PMU (where Vpor represents the normal reset signal output, Vpor1 represents the reset signal output when the input voltage does not reach the target threshold, and Vpor2 represents the reset signal output when the input voltage exceeds the threshold). Specifically, the input voltage (for example, 1.8V) has exceeded the target threshold (for example, 1.2V+100mV) but the reset signal still cannot be output, the input voltage does not reach the target threshold and the reset signal is output in advance, and PMU failure, voltage fluctuation exceeding the upper limit and negative voltage shock will also lead to the inability to output the reset signal, affecting the overall functional operation of the chip system.

[0005] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0006] One of the purposes of the present invention is to provide a redundant reset system for a power management unit to solve the problem in the prior art that the power-on reset detection module of the PMU cannot output a reset signal due to process factors, thereby affecting the overall functional operation of the chip system; the second purpose is to provide an automotive chip; and the third purpose is to provide an automobile.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] A power management unit redundant reset system is connected to a chip function system, comprising: a voltage stabilizing module, a native power-on reset module, an internal redundant power-on reset module, a reset mode configuration module and a reset signal output module; wherein the voltage stabilizing module is connected to a digital voltage and is respectively connected to the native power-on reset module and the internal redundant power-on reset module, for converting the digital voltage into an analog voltage and inputting the analog voltage into the native power-on reset module and the internal redundant power-on reset module respectively;

[0009] The native power-on reset module is connected to the digital voltage and the analog voltage, and is connected to the reset mode configuration module, and is used to output a reset signal to the reset mode configuration module after the digital voltage reaches a first threshold and after the analog voltage reaches a second threshold;

[0010] The internal redundant power-on reset module is connected to the analog voltage and is respectively connected to the voltage stabilization module and the reset mode configuration module, and is used for outputting a reset signal to the reset mode configuration module when the analog voltage reaches a third threshold;

[0011] The reset mode configuration module is respectively connected to the native power-on reset module, the internal redundant power-on reset module, the external redundant power-on reset module and the reset signal output module, and is used to output a reset signal to the reset signal output module;

[0012] The reset signal output module is connected to the reset mode configuration module and the chip function system respectively, and is used to output a reset signal to the chip function system.

[0013] According to the above technical solution, the digital voltage is connected through the voltage stabilizing module and converted into an analog voltage and input into the native power-on reset module and the internal redundant power-on reset module. During the voltage boosting process, the native power-on reset module continuously detects the rise of the digital voltage and the analog voltage. After the digital voltage reaches the first threshold value and the analog voltage reaches the second threshold value, a reset signal can be output to the reset mode configuration module, and then the reset signal is output to the reset signal output module through the reset mode configuration module, and the reset signal is output to the chip functional system through the reset signal output module. The internal redundant power-on reset module can also continuously detect the rise of the analog voltage, and output the reset signal to the reset mode configuration module when the analog voltage reaches the third threshold value, and then output it to the reset signal output module through the reset mode configuration module, and output the reset signal to the chip functional system through the reset signal output module, so that a reset signal can be provided when the native power-on reset module fails, thereby improving the operational stability and reliability of the chip, and avoiding the impact of the overall function of the chip system on the operation due to the failure of the PMU.

[0014] Furthermore, the internal redundant power-on module includes: a current generating unit and a first comparison unit; wherein, the current generating unit is connected to the analog voltage and is connected to the first comparison unit, and is used to output a reference current to the first comparison unit according to the analog voltage; the first comparison unit is respectively connected to the current generating unit and the reset mode configuration module, and is used to convert the reference current into a reference voltage, and compare the reference voltage with a third threshold voltage, and when the reference voltage reaches the third threshold voltage, output a reset signal to the reset mode configuration module.

[0015] According to the above technical solution, the current generating unit obtains the analog voltage from the voltage stabilizing module, and then generates a high-precision reference current, and inputs the high-precision current to the first comparing unit. After receiving the reference current, the first comparing unit converts the reference current into a voltage signal, i.e., a reference voltage, and compares the reference voltage with a third threshold value. When the reference voltage exceeds the third threshold value, a reset signal is output to the reset mode configuration module, so that a reset signal can be output to the chip functional system when the native power-on reset module fails.

[0016] Further, the current generating unit includes: a PMOS tube, an operational amplifier, a reference voltage source, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor; wherein the source of the PMOS tube is connected to the analog voltage, the drain of the PMOS tube is connected to the output end of the current generating unit, and the gate of the PMOS tube is connected to the output end of the operational amplifier; the in-phase input end of the operational amplifier is connected to one end of the first resistor and one end of the second resistor, and the inverting input end of the operational amplifier is connected to the positive electrode of the reference voltage source; the other end of the first resistor is connected to the output end of the current generating unit, and the other end of the second resistor is grounded; one end of the third resistor is connected to the output end of the current generating unit, and the other end of the third resistor is grounded; the negative electrode of the reference voltage source is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded; the first capacitor is connected in parallel with the third resistor; and the first comparison unit is a Schmitt trigger.

[0017] According to the above technical solution, when the source of the PMOS tube is connected to the analog voltage provided by the voltage stabilizing module, the initial voltage of the common terminal of the first resistor and the second resistor is 0. At this time, the output of the operational amplifier causes the gate potential of the PMOS tube to decrease. Since the source voltage of the PMOS tube remains unchanged, the output voltage of the current generating unit rises to the reference voltage output by the reference voltage source, thereby obtaining a stable reference current.

[0018] In addition, the first comparison unit adopts a Schmitt trigger, which has a hysteresis characteristic, and can ensure that a slight change in the power supply voltage after power-on is completed will not cause an erroneous flip of the reset signal.

[0019] Furthermore, the power management unit redundant reset system also includes: an external redundant power-on reset module; the external redundant power-on reset module is connected to the analog voltage, and is used to output a reset signal to the reset mode configuration module when the output terminal voltage of the external redundant power-on reset module reaches a fourth threshold.

[0020] According to the above technical solution, the connected analog voltage is detected by an external redundant power-on reset module. When the output voltage of the external redundant power-on reset module reaches the fourth threshold, a reset signal can be output to the reset mode configuration module, so that when the native power-on reset module and the internal redundant power-on reset module fail, a reset signal can still be output to the chip functional system, further improving the startup stability and reliability of the chip.

[0021] Furthermore, the external redundant power-on reset module includes: a fifth resistor, a second capacitor and a diode; wherein one end of the fifth resistor is connected to the analog voltage, and the other end of the fifth resistor is connected to one end of the second capacitor; the cathode of the diode is connected to the analog voltage, and the anode of the diode is connected to one end of the second capacitor; the other end of the second capacitor is grounded; and the common end of the diode, the fifth resistor and the second capacitor is connected to the reset mode configuration module.

[0022] According to the above technical solution, the external redundant power-on reset module is composed of the fifth resistor, the second capacitor and the diode. Since it is an independent separation device, it has stronger anti-interference ability and is less affected by temperature and voltage fluctuations. One end of the fifth resistor connected to the voltage stabilizing module is the power supply end, which can obtain the analog voltage output by the voltage stabilizing module in real time. When the power supply is powered off, the diode discharges the second capacitor. According to the zero-state response characteristics of the circuit, when the voltage stabilizing module is powered on, the external redundant power-on reset module is also powered on. The power supply end of the external redundant power-on reset module immediately reaches a stable value, and the voltage across the capacitor is 0V. Thereafter, the fifth resistor charges the second capacitor, and the voltage of the second capacitor gradually rises. When the voltage rises to the reset threshold voltage, that is, the fourth threshold, the external redundant power-on reset module can output a reset signal to the reset mode configuration module to improve the operational stability and reliability of the chip.

[0023] Furthermore, the native power-on reset module includes: an input unit, a reference voltage generating unit, a second comparison unit and a reset signal generating unit; wherein the input unit is connected to the digital voltage and the analog voltage, and is connected to the second comparison unit, for inputting the digital voltage and the analog voltage into the second comparison unit; the reference voltage generating unit is connected to the second comparison unit, for setting the reset voltage threshold of the digital voltage, and setting the reset voltage threshold of the analog voltage; the second comparison unit is respectively connected to the input unit, the reference voltage generating unit and the reset signal generating unit, for outputting a control signal to the reset signal generating unit after the digital voltage reaches a first threshold and after the analog voltage reaches a second threshold; the reset signal generating unit is respectively connected to the second comparison unit and the reset mode configuration module, for outputting a reset signal to the reset signal output module after receiving the control signal.

[0024] According to the above technical solution, the input unit receives the external digital voltage and the analog voltage output by the voltage regulator module. During the boost process, the input unit continuously detects the rise of the input digital voltage and analog voltage, and transmits the rise voltage signal to the second comparison unit. The reference voltage generation unit can set the reset voltage threshold of the digital voltage, and can set the reset voltage threshold of the analog voltage, allowing the millivolt level to float up and down. Thereafter, the second comparison unit continuously compares the digital voltage input by the input unit, and when the digital voltage exceeds the reset voltage threshold set by a certain threshold, the reset signal generation unit is notified to output the reset signal; at the same time, the second comparison unit continuously compares the analog voltage input by the input module, and when the analog voltage exceeds the reset voltage threshold by a certain threshold, the reset signal generation unit is notified to output the reset signal. The above two conditions must be met at the same time, and the reset signal generation unit then outputs the reset signal to the chip functional system to complete the normal startup reset of the chip.

[0025] Further, the reset mode configuration module includes a first input pin and a second input pin; when the first input pin and the second input pin are configured to a low level, the reset signal output by the native power-on reset module is a valid reset signal; when the first input pin is configured to a high level and the second input pin is configured to a low level, the reset signal output by the internal redundant power-on reset module is a valid reset signal; when the first input pin is configured to a low level and the second input pin is configured to a high level, the reset signal output by the external redundant power-on reset module is a valid reset signal; when the first input pin and the second input pin are configured to a high level, the reset signals output by the native power-on reset module, the internal redundant power-on reset module and the external redundant power-on reset module are all valid reset signals.

[0026] According to the above technical solution, when the first input pin is configured as a high level and the second input pin is configured as a low level, the reset signal output by the internal redundant power-on reset module is a valid reset signal; when the first input pin is configured as a low level and the second input pin is configured as a high level, the reset signal output by the external redundant power-on reset module is a valid reset signal; when the first input pin and the second input pin are configured as a high level, the reset signals output by the native power-on reset module, the internal redundant power-on reset module and the external redundant power-on reset module are all valid reset signals. It can be seen that the present application can select the reset mode by configuring the high and low levels of the two input pins of the reset mode configuration module to achieve full coverage of the reset signal.

[0027] Furthermore, the chip functional system includes: a core functional module, a clock and reset functional module, a power functional module, a storage functional module, a peripheral functional module and a bus functional module, and the core functional module, the clock functional module, the power functional module, the reset functional module, the storage functional module, and the peripheral functional module are connected through the bus functional module.

[0028] In the above technical solution, the power supply function module can provide digital voltage, the clock and reset function module can provide clock signal, and obtain the reset signal output by the reset signal output module. After the reset signal is stable for a period of time, the clock module reset is released, and the reset function module controls the chip system reset. After all clock modules are stable, the core function module reads the first instruction from the storage function module through the bus function module, runs the user software, and uses the peripherals for signal processing or communication through the peripheral function module.

[0029] An automobile chip comprises the power management unit redundant reset system mentioned above.

[0030] According to the above technical solution, the digital voltage is connected through the voltage stabilizing module and the digital power supply is converted into an analog voltage and input to the native power-on reset module and the internal redundant power-on reset module. During the voltage boosting process, the native power-on reset module continuously detects the rise of the digital voltage and the analog voltage. After the digital voltage reaches the first threshold and the analog voltage reaches the second threshold, a reset signal can be output to the reset mode configuration module, and then the reset signal is output to the reset signal output module through the reset mode configuration module, and the reset signal is output to the chip function system through the reset signal output module. The internal redundant power-on reset module can also continuously detect the rise of the analog voltage, and output the reset signal to the reset mode configuration module when the analog voltage reaches the third threshold, and then output it to the reset signal output module through the reset mode configuration module, and output the reset signal to the chip function system through the reset signal output module, so that a reset signal can be provided when the native power-on reset module fails, thereby improving the operation stability and reliability of the chip, avoiding the impact of the overall function of the chip system on the operation of the PMU after the failure, ensuring that the single point failure rate of the chip system meets the requirements of ISO26262, and ensuring personal safety.

[0031] A car comprising the above-mentioned car chip.

[0032] Beneficial effects of the present invention:

[0033] (1) By adding an internal redundant power-on reset module, the rise of the analog voltage is continuously detected. When the analog voltage reaches the third threshold, a reset signal is output to the reset mode configuration module, and then the reset signal is output to the reset signal output module through the reset mode configuration module. The reset signal is output to the chip functional system through the reset signal output module, so that a reset signal can be provided even when the native power-on reset module fails, thereby improving the operation stability and reliability of the chip, avoiding the impact of the overall function of the chip system on the operation due to the failure of the PMU, ensuring that the single point failure rate of the chip system meets the requirements of ISO26262 and ensuring personal safety;

[0034] (2) By adding an external redundant power-on reset module, when the voltage rises to the reset threshold voltage, that is, the fourth threshold, the external redundant power-on reset module can output a reset signal to the reset mode configuration module, which can further improve the operating stability and reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the abnormal trigger voltage for resetting the PMU;

[0036] Figure 2 A principle block diagram of a redundant reset system for a power management unit according to the present invention;

[0037] Figure 3 Schematic diagram of the native power-on reset module outputting the reset signal;

[0038] Figure 4 This is the principle block diagram of the native power-on reset module;

[0039] Figure 5 It is the circuit schematic diagram of the external redundant power-on reset module;

[0040] Figure 6 is a circuit schematic diagram of a current generating unit;

[0041] Figure 7 It is the schematic diagram of the chip functional module.

[0042] Among them, 100, voltage stabilization module; 200, native power-on reset module; 210, input unit; 220, reference voltage generating unit; 230, second comparison unit; 240, reset signal generating unit; 300, internal redundant power-on reset module; 310, current generating unit; 320, first comparison unit; 400, reset mode configuration module; 500, reset signal output module; 600, chip function system; 700, external redundant power-on reset module. DETAILED DESCRIPTION

[0043] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0044] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] This embodiment proposes a power management unit redundant reset system, such as Figure 2 As shown, it is connected to the chip functional system 600, which includes: a voltage stabilizing module 100, a native power-on reset module 200, an internal redundant power-on reset module 300, a reset mode configuration module 400 and a reset signal output module 500. Among them, the voltage stabilizing module 100 is connected to the digital voltage VDD, and is respectively connected to the native power-on reset module 200 and the internal redundant power-on reset module 300, for converting the digital voltage VDD into an analog voltage VCC and inputting it to the native power-on reset module 200 and the internal redundant power-on reset module 300 respectively; the native power-on reset module 200 is connected to the digital voltage and the analog voltage, and is connected to the reset mode configuration module 400, for outputting a reset signal to the reset mode configuration module 400 after the digital voltage reaches a first threshold value and after the analog voltage reaches a second threshold value; the internal redundant power-on reset module 300 is connected to the The analog voltage is respectively connected to the voltage stabilizing module 100 and the reset mode configuration module 400, and is used to output a reset signal to the reset mode configuration module 400 when the analog voltage reaches a third threshold; the reset mode configuration module 400 is respectively connected to the native power-on reset module 200, the internal redundant power-on reset module 300, the external redundant power-on reset module 700 and the reset signal output module 500, and is used to output a reset signal to the reset signal output module 500; the reset signal output module 500 is respectively connected to the reset mode configuration module 400 and the chip functional system 600, and is used to output a reset signal to the chip functional system 600.

[0046] ISO26262 divides safety levels into ASIL-B and ASIL-D. ASIL-B requires chips to cover 90% of single-point failure scenarios, while ASIL-D requires 99%. Although the failure probability of a transistor is low, a complex chip is usually composed of hundreds of millions of transistors. If no measures are taken, any error may cause functional failure, and the failure rate is very high.

[0047] In this embodiment, the voltage stabilizing module 100 may be an LDO chip, which receives an external 3.3V digital voltage and converts it into a 1.8V analog voltage.

[0048] During the voltage boosting process, the native power-on reset module 200 continuously detects the rise of the digital voltage and the analog voltage, and can output a reset signal to the reset mode configuration module 400 after the digital voltage reaches the first threshold and the analog voltage reaches the second threshold, and then outputs the reset signal to the reset signal output module 500 through the reset mode configuration module 400, and outputs the reset signal to the chip function system 600 through the reset signal output module 500. In this process, the internal redundant power-on reset module 300 can also continuously detect the rise of the analog voltage, and output a reset signal to the reset mode configuration module 400 when the analog voltage reaches the third threshold, and then outputs it to the reset signal output module 500 through the reset mode configuration module 400, and outputs the reset signal to the chip function system 600 through the reset signal output module 500, so that a reset signal can be provided when the native power-on reset module 200 fails, thereby improving the operational stability and reliability of the chip, and avoiding the impact of the overall function of the chip system on the operation due to the failure of the PMU. In addition, the present invention can prevent the operation of the overall function of the chip system from being affected by a PMU failure, ensure that the single point failure rate of the chip system meets the requirements of ISO26262, and ensure personal safety.

[0049] It should be noted that the purpose of power-on reset is to ensure that the analog and digital modules are initialized to a known state after power is applied. The power-on reset module generates an internal reset pulse to keep the device static and prevent the internal circuit from operating in an unordered and erroneous state until the power supply voltage reaches a threshold that can ensure normal operation, and then releases this reset signal to restore the chip to normal operation.

[0050] like Figure 3 As shown, Figure 3This is a schematic diagram of the native power-on reset module outputting a reset signal. Before the digital voltage VDD rises from low to high and crosses the specified voltage threshold (the stable operating voltage of the chip functional system, which can be 100mV, where min = 1.8, typ = 1.88, max = 1.96), the chip is kept reset. After a short period of time after crossing this voltage threshold ( Figure 3 The reset hysteresis is 100mV), the reset ends and the reset vector is taken to start executing instructions.

[0051] In some embodiments, Figure 2 As shown, the power management unit redundant reset system further includes: an external redundant power-on reset module 700. The external redundant power-on reset module 700 is connected to the analog voltage, and is respectively connected to the voltage stabilizing module 100 and the reset mode configuration module 400, and is used to output a reset signal to the reset mode configuration module 400 when the output terminal voltage of the external redundant power-on reset module 700 reaches a fourth threshold.

[0052] In this embodiment, the external redundant power-on reset module 700 is an external circuit module, and the connected analog voltage is detected by the external redundant power-on reset module 700. When the output voltage of the external redundant power-on reset module 700 reaches the fourth threshold, a reset signal can be output to the reset mode configuration module 400, so that when the native power-on reset module 200 and the internal redundant power-on reset module 300 fail, a reset signal can still be output to the chip function system 600, further improving the startup stability and reliability of the chip.

[0053] In some embodiments, Figure 2 As shown, the internal redundant power-on reset module 300 includes: a current generating unit 310 and a first comparing unit 320. The current generating unit 310 is connected to the analog voltage and connected to the first comparing unit 320, and is used to output a reference current to the first comparing unit 320 according to the analog voltage; the first comparing unit 320 is connected to the current generating unit 310 and the reset mode configuration module 400 respectively, and is used to convert the reference current into a reference voltage, and compare the reference voltage with a third threshold voltage, and when the reference voltage reaches the third threshold voltage, output a reset signal to the reset mode configuration module 400.

[0054] In this embodiment, the current generating unit 310 obtains an analog voltage of 1.8V from the voltage stabilizing module 100, and then generates a high-precision reference current through an internal resistor-capacitor circuit, and inputs the high-precision current to the first comparing unit 320. After receiving the reference current, the first comparing unit 320 converts the reference current into a voltage signal, i.e., a reference voltage, and compares the reference voltage with a third threshold value. When the reference voltage exceeds the third threshold value, a reset signal is output to the reset mode configuration module 400, so that a reset signal can also be output to the chip functional system 600 when the native power-on reset module 200 fails.

[0055] In some embodiments, Figure 2 and Figure 6 As shown, the current generating unit 310 includes: a PMOS tube PMOS, an operational amplifier OP, a reference voltage source Vref, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a first capacitor C1; wherein the source of the PMOS tube PMOOS is connected to the analog voltage VCC, the drain of the PMOS tube PMOS is connected to the output end of the current generating unit 310, and the gate of the PMOS tube PMOS is connected to the output end of the operational amplifier OP; the in-phase input end of the operational amplifier OP is connected to one end of the first resistor R1 with and one end of the second resistor R2, the inverting input end of the operational amplifier OP is connected to the positive electrode of the reference voltage source Vref; the other end of the first resistor R1 is connected to the output end of the current generating unit 310, and the other end of the second resistor R2 is grounded; one end of the third resistor R3 is connected to the output end of the current generating unit 310, and the other end of the third resistor R3 is grounded; the negative electrode of the reference voltage source Vref is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded; the first capacitor C1 is connected in parallel with the third resistor R3.

[0056] In this embodiment, the first capacitor C1 is a filter capacitor, the first resistor R1 and the second resistor R2 are voltage-dividing resistors, and the third resistor R3 is a current-limiting resistor. When the source of the PMOS tube PMOS is connected to the analog voltage VCC provided by the voltage stabilizing module 100, the initial voltage of the common terminal A of the first resistor R1 and the second resistor R2 is 0, and at this time, the output of the operational amplifier OP causes the gate potential of the PMOS tube PMOS to decrease. Since the source voltage Vs of the PMOS tube PMOS remains unchanged, the output terminal voltage Vout of the current generating unit 310 rises to the reference voltage output by the reference voltage source Vref, so that a stable reference current Iout can be obtained and output to the first comparing unit 320.

[0057] In some embodiments, the first comparison unit 320 is a Schmitt trigger. The first comparison unit 320 uses a Schmitt trigger. Since the Schmitt trigger has a hysteresis characteristic, it can ensure that a slight change in the power supply voltage after power-on is completed will not cause an erroneous flip of the reset signal.

[0058] In some embodiments, Figure 2 and Figure 5 As shown, the external redundant power-on reset module 700 includes: a fifth resistor R5, a second capacitor C2 and a diode D1. One end of the fifth resistor R5 is connected to the analog voltage VCC, and the other end of the fifth resistor R5 is connected to one end of the second capacitor C2; the cathode of the diode D1 is connected to the analog voltage VCC, and the anode of the diode D1 is connected to one end of the second capacitor C2; the other end of the second capacitor C2 is grounded; and the common terminal VRST of the diode D1, the fifth resistor R5 and the second capacitor C2 is connected to the reset mode configuration module 400.

[0059] In this embodiment, the external redundant power-on reset module 700 is composed of a fifth resistor R5, a second capacitor C2 and a diode D1. Since it is an independent separation device, it has stronger anti-interference ability and is less affected by temperature and voltage fluctuations. One end of the fifth resistor R5 connected to the voltage stabilizing module 100 is a power supply end, which can obtain the analog voltage VCC output by the voltage stabilizing module 100 in real time. When the power supply is powered off, the diode D1 discharges the second capacitor C2. According to the zero-state response characteristics of the circuit, when the voltage stabilizing module 100 is powered on, the external redundant power-on reset module 700 is also powered on. The power supply end of the external redundant power-on reset module 700 immediately reaches a stable value, and the voltage across the second capacitor C2 is 0V. Thereafter, the fifth resistor R5 charges the second capacitor C2, and the voltage of the second capacitor C2 gradually rises. When the voltage rises to the reset threshold voltage, that is, the fourth threshold, the external redundant power-on reset module 700 can output a reset signal to the reset mode configuration module 400 to improve the operational stability and reliability of the chip.

[0060] In some embodiments, Figure 2 and Figure 4As shown, the native power-on reset module 200 includes: an input unit 210, a reference voltage generating unit 220, a second comparison unit 230 and a reset signal generating unit 240. The input unit 210 is connected to the digital voltage and the analog voltage, and is connected to the second comparison unit 230, for inputting the digital voltage and the analog voltage into the second comparison unit 230; the reference voltage generating unit 220 is connected to the second comparison unit 230, for setting the reset voltage threshold of the digital voltage and the reset voltage threshold of the analog voltage; the second comparison unit 230 is respectively connected to the input unit 210, the reference voltage generating unit 220 and the reset signal generating unit 240, for outputting a control signal to the reset signal generating unit 240 after the digital voltage reaches a first threshold and the analog voltage reaches a second threshold; the reset signal generating unit 240 is respectively connected to the second comparison unit 230 and the reset mode configuration module 400, for outputting a reset signal to the reset signal output module 500 after receiving the control signal.

[0061] In this embodiment, the input unit 210 receives an external 3.3V digital voltage and a 1.8V analog voltage output by the voltage stabilizing module 100. During the voltage boosting process, the input unit 210 continuously detects the rise of the input digital voltage and analog voltage, and transmits the rise voltage signal to the second comparison unit 230. The reference voltage generating unit 220 can set the reset voltage threshold of the digital voltage, for example, setting the reset voltage threshold of the digital voltage to 1.8V, and can set the reset voltage threshold of the analog voltage, for example, setting the reset voltage threshold of the analog voltage to 0.9V, allowing the millivolt level to fluctuate up and down. Thereafter, the second comparison unit 230 continuously compares the digital voltage input by the input unit 210, and when the digital voltage exceeds the reset voltage threshold set by a certain threshold, that is, reaches the first threshold, the reset signal generating unit 240 is notified to output a reset signal. At the same time, the second comparison unit 230 continuously compares the analog voltage input by the input module. When the analog voltage exceeds the reset voltage threshold by a certain threshold, the reset signal generating unit 240 is notified to output a reset signal. The above two conditions must be met at the same time. The reset signal generating unit 240 then outputs a reset signal to the chip functional system 600 to complete the normal startup reset of the chip.

[0062] In some embodiments, Figure 7As shown, the chip function system 600 includes: a core function module, a clock function module, a power function module, a reset function module, a storage function module, a peripheral function module and a bus function module. The core function module, the clock function module, the power function module, the reset function module, the storage function module and the peripheral function module are connected through the bus function module.

[0063] In this embodiment, the core function module (CORE), the clock and reset function module (RCMU), the power function module, the storage function module (SRAM and ROM), and the peripheral function module are connected through the bus function module, wherein the bus function module includes an AHB bus and an APB bus (such as Figure 7 APB1 and APB2 in the bus), the peripheral function modules are connected to the bus APB1, APB2 or the bus AHB, for example, TIM, GPIO, PMU, etc. When the power management unit is powered on, the power function module starts to work, and the power function module can provide a 3.3V digital voltage. The resistor-capacitor circuit inside the clock and reset function module also starts to work, and can provide a clock signal to obtain the reset signal output by the reset signal output module. After the reset signal is stable for a period of time, the reset of the clock module is released, and the reset function module controls the chip system to reset. After all the clock modules are stable, the core function module reads the first instruction from the storage function module through the bus function module, runs the user software, and uses the peripherals for signal processing or communication through the peripheral function module. It should be noted that the specific component modules of the chip function system 600 are prior art, and therefore will not be repeated here.

[0064] In some implementations, such as Figure 2 As shown, the reset mode configuration module 400 includes a first input pin set1 and a second input pin set2. When the first input pin set1 and the second input pin set2 are configured to a low level, the reset signal output by the native power-on reset module 200 is a valid reset signal; when the first input pin set1 is configured to a high level and the second input pin set2 is configured to a low level, the reset signal output by the internal redundant power-on reset module 300 is a valid reset signal; when the first input pin set1 is configured to a low level and the second input pin set2 is configured to a high level, the reset signal output by the external redundant power-on reset module 700 is a valid reset signal; when the first input pin set1 and the second input pin set2 are configured to a high level, the reset signals output by the native power-on reset module 200, the internal redundant power-on reset module 300 and the external redundant power-on reset module 700 are all valid reset signals.

[0065] In this embodiment, when the first input pin set1 is configured as a high level and the second input pin set2 is configured as a low level, the reset signal output by the internal redundant power-on reset module 300 is a valid reset signal; when the first input pin set1 is configured as a low level and the second input pin set2 is configured as a high level, the reset signal output by the external redundant power-on reset module 700 is a valid reset signal; when the first input pin set1 and the second input pin set2 are configured as high levels, the reset signals output by the native power-on reset module 200, the internal redundant power-on reset module 300 and the external redundant power-on reset module 700 are all valid reset signals. It can be seen that the present application can select the reset mode by configuring the high and low levels of the two input pins of the reset mode configuration module 400, thereby achieving full coverage of the reset signal.

[0066] Taking the internal redundant power-on reset module 300 as an example, the first input pin set1 and the second input pin set2 are configured as a high level and a low level respectively, so that the reset signal output by the internal redundant power-on reset module 300 is used as a valid reset signal.

[0067] First, the voltage regulator module 100 converts the 3.3V digital voltage into an analog voltage of 1.8V and inputs it into the internal redundant power-on reset module 300. The input end of the reset mode configuration module 400 obtains the external digital power-on power supply from the input end of the native power-on reset module 200. The input end of the current generating unit 310 obtains the analog voltage of 1.8V from the voltage regulator module 100, and generates a high-precision reference current through a circuit composed of internal resistors / capacitors. The first comparison unit 320 converts the reference current into a voltage signal and compares the voltage threshold. When the threshold is exceeded, a reset signal is output. The reset mode configuration module 400 uses the reset signal output by the internal redundant power-on reset module 300 as a valid reset signal according to the first input pin set1 / the second input pin set2 and outputs it to the reset signal output module 500. The reset signal output module 500 outputs it to each module, completing the power-on reset of the chip and allowing the chip to enter a normal working state.

[0068] Taking the external redundant power-on reset module 700 as an example, the first input pin set1 and the second input pin set2 are configured as a low level and a high level respectively, so that the reset signal output by the external redundant power-on reset module 700 is used as a valid reset signal.

[0069] The voltage regulator module 100 converts the 3.3V digital voltage into an analog voltage of 1.8V, and outputs it to the external redundant power-on reset module 700 through the PAD pin of the chip. At the moment of power-on, the second capacitor C2 is charged, and the voltage formed by the charging current on the fifth resistor R5 is a high level. After a few milliseconds, the second capacitor C2 is fully charged, the current is 0, and the voltage on the fifth resistor R5 is also a low level. The output end changes from a high level to a low level, which is expressed as a low-level reset signal. At this time, the external redundant power-on reset module 700 outputs a reset signal, and the reset mode configuration module 400 uses the reset signal output by the external redundant power-on reset module 700 as a valid reset signal according to the first input pin set1 and the second input pin set2, and outputs it to the reset signal output module 500. The reset signal output module 500 outputs the reset signal to each module, completes the chip POR reset, and puts the chip into a normal working state.

[0070] In some embodiments, the present invention further provides an automotive chip, which includes the power management unit redundant reset system described above.

[0071] In some embodiments, the present invention provides a car comprising the above-mentioned car chip.

[0072] The present invention adds an internal redundant power-on reset module, continuously detects the rise of the analog voltage, outputs a reset signal to the reset mode configuration module when the analog voltage reaches the third threshold, and then outputs it to the reset signal output module through the reset mode configuration module, and outputs the reset signal to the chip function system through the reset signal output module, so that a reset signal can be provided when the native power-on reset module fails, thereby improving the operation stability and reliability of the chip, avoiding the impact of the operation of the overall function of the chip system after the PMU fails, ensuring that the single point failure rate of the chip system meets the requirements of ISO26262, and ensuring personal safety. In addition, the present invention further adds an external redundant power-on reset module. When the voltage rises to the reset threshold voltage, that is, the fourth threshold, the external redundant power-on reset module can output a reset signal to the reset mode configuration module, which can further improve the operation stability and reliability of the chip.

[0073] The above embodiments are only preferred embodiments for fully illustrating the present invention, and the protection scope of the present invention is not limited thereto. Any equivalent substitution or change made by a person skilled in the art based on the present invention is within the protection scope of the present invention.

Claims

1. A power management unit redundant reset system, connected to a chip function system, characterized in that: include: A voltage stabilizing module, a native power-on reset module, an internal redundant power-on reset module, a reset mode configuration module and a reset signal output module; wherein the voltage stabilizing module is connected to a digital voltage and is respectively connected to the native power-on reset module and the internal redundant power-on reset module, for converting the digital voltage into an analog voltage and inputting it into the native power-on reset module and the internal redundant power-on reset module respectively; The native power-on reset module is connected to the digital voltage and the analog voltage, and is connected to the reset mode configuration module, and is used to output a reset signal to the reset mode configuration module after the digital voltage reaches a first threshold and after the analog voltage reaches a second threshold; The internal redundant power-on reset module is connected to the analog voltage and is respectively connected to the voltage stabilization module and the reset mode configuration module, and is used for outputting a reset signal to the reset mode configuration module when the analog voltage reaches a third threshold; The reset mode configuration module is respectively connected to the native power-on reset module, the internal redundant power-on reset module, the external redundant power-on reset module and the reset signal output module, and is used to output a reset signal to the reset signal output module; The reset signal output module is connected to the reset mode configuration module and the chip function system respectively, and is used to output a reset signal to the chip function system.

2. The power management unit redundant reset system according to claim 1, characterized in that: The internal redundant power-on module comprises: a current generating unit and a first comparing unit; wherein, The current generating unit is connected to the analog voltage and is connected to the first comparing unit, and is used to output a reference current to the first comparing unit according to the analog voltage; The first comparison unit is connected to the current generating unit and the reset mode configuration module respectively, and is used to convert the reference current into a reference voltage and compare the reference voltage with a third threshold voltage. When the reference voltage reaches the third threshold voltage, a reset signal is output to the reset mode configuration module.

3. The power management unit redundant reset system according to claim 2, characterized in that: The current generating unit includes: a PMOS tube, an operational amplifier, a reference voltage source, a first resistor, a second resistor, a third resistor, a fourth resistor and a first capacitor; wherein, The source of the PMOS tube is connected to the analog voltage, the drain of the PMOS tube is connected to the output end of the current generating unit, and the gate of the PMOS tube is connected to the output end of the operational amplifier; The non-inverting input terminal of the operational amplifier is connected to one end of the first resistor and one end of the second resistor, and the inverting input terminal of the operational amplifier is connected to the positive electrode of the reference voltage source; The other end of the first resistor is connected to the output end of the current generating unit, and the other end of the second resistor is grounded; One end of the third resistor is connected to the output end of the current generating unit, and the other end of the third resistor is grounded; The negative electrode of the reference voltage source is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded; The first capacitor is connected in parallel with the third resistor; The first comparison unit is a Schmitt trigger.

4. The power management unit redundant reset system according to claim 1, characterized in that: Also includes: External redundant power-on reset module; The external redundant power-on reset module is connected to the analog voltage, and is used to output a reset signal to the reset mode configuration module when the output terminal voltage of the external redundant power-on reset module reaches a fourth threshold.

5. The power management unit redundant reset system according to claim 4, characterized in that: The external redundant power-on reset module includes: a fifth resistor, a second capacitor and a diode; wherein, One end of the fifth resistor is connected to the analog voltage, and the other end of the fifth resistor is connected to one end of the second capacitor; the cathode of the diode is connected to the analog voltage, and the anode of the diode is connected to one end of the second capacitor; The other end of the second capacitor is grounded; A common terminal of the diode, the fifth resistor and the second capacitor is connected to the reset mode configuration module.

6. The power management unit redundant reset system according to claim 1, characterized in that: The native power-on reset module includes: an input unit, a reference voltage generating unit, a second comparison unit and a reset signal generating unit; wherein, The input unit is connected to the digital voltage and the analog voltage, and is connected to the second comparing unit, and is used to input the digital voltage and the analog voltage into the second comparing unit; The reference voltage generating unit is connected to the second comparing unit and is used to set a reset voltage threshold of the digital voltage and a reset voltage threshold of the analog voltage; The second comparison unit is connected to the input unit, the reference voltage generating unit and the reset signal generating unit respectively, and is used to output a control signal to the reset signal generating unit after the digital voltage reaches a first threshold value and after the analog voltage reaches a second threshold value; The reset signal generating unit is connected to the second comparing unit and the reset mode configuration module respectively, and is used for outputting a reset signal to the reset signal output module after receiving the control signal.

7. The power management unit redundant reset system according to claim 4, characterized in that: The reset mode configuration module includes a first input pin and a second input pin; When the first input pin and the second input pin are configured to be at a low level, the reset signal output by the native power-on reset module is a valid reset signal; When the first input pin is configured as a high level and the second input pin is configured as a low level, the reset signal output by the internal redundant power-on reset module is a valid reset signal; When the first input pin is configured as a low level and the second input pin is configured as a high level, the reset signal output by the external redundant power-on reset module is a valid reset signal; When the first input pin and the second input pin are configured to be at a high level, the reset signals output by the native power-on reset module, the internal redundant power-on reset module, and the external redundant power-on reset module are all valid reset signals.

8. The power management unit redundant reset system according to claim 1, characterized in that: The chip functional system includes: a core functional module, a clock and reset functional module, a power functional module, a storage functional module, a peripheral functional module and a bus functional module. The core functional module, the clock and reset functional module, the power functional module, the storage functional module and the peripheral functional module are connected through the bus functional module.

9. An automotive chip, characterized in that: It comprises a power management unit redundant reset system as described in any one of claims 1 to 8.

10. An automobile, characterized in that: The automotive chip as claimed in claim 9.

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