Multi-core heterogeneous chip task scheduling method and system for intelligent power distribution terminal

Abstract

The invention discloses a power distribution intelligent terminal-oriented multi-core heterogeneous chip task scheduling method and system, and belongs to the technical field of computers, the method comprises the following steps: receiving calculation tasks, storing the calculation tasks in a scheduling task queue, and obtaining task importance levels, task arrival time, task deadline and core resources required by the tasks of the calculation tasks; performing priority evaluation on the calculation task according to the data to obtain a priority value; performing scheduling arrangement on the scheduling task queue according to the task importance level and the priority value to obtain a current scheduling queue; in each scheduling period, performing task scheduling on each slave core in combination with the shared memory according to the current scheduling queue and the core resources required by the task; according to the method, index basis can be provided for scheduling of calculation tasks, the problem of chip-level task scheduling caused by different task importance and different calculation resources of the power distribution intelligent terminal is solved, the edge self-adaptive calculation capability of the power distribution terminal is improved, and the multi-service low-delay requirement of the power distribution intelligent terminal can be met.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a multi-core heterogeneous chip task scheduling method and system for power distribution intelligent terminals. Background Art

[0002] The data processing of power distribution intelligent terminals has the characteristics of high real-time requirements, large amount of collected data, and high data accuracy requirements, which puts forward high requirements on the data processing capabilities and computing efficiency of terminal chips. At the same time, power distribution intelligent terminals have multiple business functions such as data collection, data preprocessing, data packaging, data encryption, data transmission, and remote control, which requires the terminal chip to have good concurrency performance.

[0003] Although the multi-core heterogeneous chips in the existing chip architecture have their advantages, they are oriented to general scenarios and focus on factors such as waiting time, arrival time, and end time of various services. However, the importance of various services at the distribution terminal varies and the amount of data varies. Scheduling based solely on general scenario factors cannot meet the personalized business needs of the distribution scenario. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a multi-core heterogeneous chip task scheduling method and system for power distribution intelligent terminals, aiming to achieve reasonable scheduling and allocation of the importance of power distribution intelligent terminal tasks and chip computing resources, as well as low-latency transmission between multi-core data.

[0005] To achieve the above objectives, an embodiment of the present application provides a multi-core heterogeneous chip task scheduling method for a power distribution intelligent terminal, the method comprising:

[0006] Receive computing tasks and store them in the scheduling task queue, and obtain the task importance level, task arrival time, task deadline and core resources required for the computing tasks;

[0007] Performing a priority evaluation on the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value;

[0008] Scheduling the scheduling task queue according to the task importance level and the priority value to obtain a current scheduling queue;

[0009] In each scheduling cycle, tasks are scheduled for each slave core according to the current scheduling queue and the core resources required for the task in combination with the shared memory; wherein the shared memory is a memory area used jointly by the master core and all slave cores.

[0010] In some embodiments, the step of performing priority evaluation on the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value comprises the following steps:

[0011] Configure importance level weight, waiting time weight, and remaining time weight;

[0012] Calculate a first difference between the current time and the task arrival time to obtain the task waiting time;

[0013] Calculate a second difference between the current time and the task deadline to obtain the remaining time of the task;

[0014] The importance level of the task is weighted by using the importance level weight to obtain a weighted task level;

[0015] The waiting time weight is used to perform weighted processing on the task waiting time to obtain a weighted waiting time;

[0016] The remaining time of the task is processed by using a negative logarithmic function, and the processing result is weighted by using the remaining time weight to obtain a weighted remaining time;

[0017] A weighted sum of the weighted task level, the weighted waiting time and the weighted remaining time is calculated to obtain a priority value.

[0018] In some embodiments, scheduling the scheduling task queue according to the task importance level and the priority value to obtain the current scheduling queue includes the following steps:

[0019] sorting the computing tasks in the scheduling task queue according to the priority value;

[0020] When there is only one computing task with the highest task importance level in the scheduling task queue, the computing task is moved to the front of the scheduling task queue;

[0021] When there are multiple computing tasks with the highest task importance level in the scheduling task queue, all the computing tasks are brought to the front of the scheduling task queue, and all the computing tasks brought to the front are sorted according to the priority value.

[0022] In some embodiments, the sorting of computing tasks in the scheduling task queue according to the priority value comprises the following steps:

[0023] When a number of computing tasks are compared and only the priority values ​​are the same, the computing tasks are sorted in such a way that the higher the task importance, the earlier it is scheduled;

[0024] When a plurality of computing tasks are compared and only the priority value and the task importance level are the same, the computing tasks are sorted in such a way that the earlier the task ends, the earlier it is scheduled;

[0025] When several computing tasks are compared and the priority values, the task importance levels and the task end times are all the same, the computing tasks are sorted in a random order.

[0026] In some embodiments, the step of scheduling tasks on each slave core in combination with a shared memory according to the current scheduling queue and the core resources required for the task includes the following steps:

[0027] Take out the computing task at the front of the queue from the current scheduling queue;

[0028] When the task importance level of the computing task is the highest level, preemptive scheduling is performed according to the core resources required by the task and in combination with the shared memory;

[0029] When the task importance level of the computing task is not the highest level, polling waiting scheduling is performed according to the core resources required by the task in combination with the shared memory.

[0030] In some embodiments, the method further includes the step of configuring a multi-core heterogeneous chip for a power distribution intelligent terminal, specifically including the following steps:

[0031] Configure the main core for task scheduling, communication control, shared memory control, and task distribution processing;

[0032] Configure several slave cores to perform various task executions;

[0033] Configure shared memory to store the data required to perform computing tasks.

[0034] In some embodiments, the method further includes the step of initializing the master core and each slave core of the multi-core heterogeneous chip for the intelligent power distribution terminal, specifically including the following steps:

[0035] Establish inter-core communication channels;

[0036] Create shared memory;

[0037] Initialize the scheduling task queue.

[0038] To achieve the above purpose, another aspect of the embodiment of the present application proposes a multi-core heterogeneous chip task scheduling system for power distribution intelligent terminals, the system comprising:

[0039] The first module is used to receive computing tasks and store them in the scheduling task queue, and obtain the task importance level, task arrival time, task deadline and core resources required for the computing tasks;

[0040] The second module is used to evaluate the priority of the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value;

[0041] The third module is used to schedule the scheduling task queue according to the task importance level and the priority value to obtain the current scheduling queue;

[0042] The fourth module is used to schedule tasks for each slave core in each scheduling cycle according to the current scheduling queue and the core resources required for the task in combination with the shared memory; wherein the shared memory is a memory area used jointly by the master core and all slave cores.

[0043] In some embodiments, the system further comprises:

[0044] The fifth module is used to configure multi-core heterogeneous chips for power distribution intelligent terminals, specifically for: configuring the master core for task scheduling, communication control, shared memory control and task distribution processing; configuring several slave cores for various task execution processing; configuring shared memory for storing data required to perform computing tasks.

[0045] In some embodiments, the system further comprises:

[0046] The sixth module is used to initialize the master core and each slave core of the multi-core heterogeneous chip for the intelligent power distribution terminal, specifically for: establishing an inter-core communication channel; establishing a shared memory; and initializing the scheduling task queue.

[0047] To achieve the above-mentioned purpose, another aspect of an embodiment of the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above-mentioned method when executing the computer program.

[0048] To achieve the above objective, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described above is implemented.

[0049] The embodiments of the present application include at least the following beneficial effects: The present application provides a multi-core heterogeneous chip task scheduling method and system for power distribution intelligent terminals. The scheme evaluates the priority by integrating the importance of tasks, task arrival time, task deadline, etc., obtains the priority value, and schedules the scheduling task queue according to the task importance level and priority value, combined with the core resources required for the task, which can provide an indicator basis for the scheduling of computing tasks, solve the chip-level task scheduling problems caused by the different importance of tasks and computing resources of power distribution intelligent terminals, and improve the edge adaptive computing capabilities of power distribution terminals and the intelligent level of power grid operation and maintenance. In addition, low-latency transmission between multi-core data in a shared memory manner can also meet the low-latency requirements of multiple services of power distribution intelligent terminals. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0051] Figure 1 It is a flow chart of a multi-core heterogeneous chip task scheduling method for power distribution intelligent terminals provided in an embodiment of the present application;

[0052] Figure 2 It is a module structure diagram of a multi-core heterogeneous distribution network intelligent terminal chip provided in an embodiment of the present application;

[0053] Figure 3 It is a module schematic diagram of a multi-core heterogeneous chip task scheduling system for power distribution intelligent terminals provided in an embodiment of the present application;

[0054] Figure 4 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0056] Although the functional modules are divided in the system schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the system or the order in the flowchart. The terms "first / S100", "second / S200", etc. in the specification, claims and the above drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0057] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0058] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0059] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0061] In related technologies, chip architectures are divided into single-core, multi-core homogeneous, and multi-core heterogeneous. Among them, multi-core heterogeneous chips customize various functions according to actual business, which can not only meet diverse business requirements, but also ensure the high real-time of important business through task scheduling and multi-core parallelism. The existing task scheduling methods of multi-core heterogeneous chips are oriented to general scenarios, focusing on factors such as waiting time, arrival time, and end time in various industries. However, the importance of various businesses in the distribution terminal is different, and scheduling based solely on general scenarios cannot well meet the personalized business needs of distribution terminals.

[0062] In view of this, a multi-core heterogeneous chip task scheduling method and system for power distribution intelligent terminals are provided in this embodiment. In view of the demand for low latency of multiple services of power distribution intelligent terminals, a distribution network intelligent terminal chip based on multi-core heterogeneity is proposed to realize low-latency transmission between multi-core data in a shared memory manner. In view of the needs of priority processing and queue-jumping processing of important tasks in the distribution network, a preemptive important task priority scheduling method is designed, which not only guarantees the basic requirements for realizing multi-task scheduling, but also meets the needs of timely processing of important tasks in the distribution network. A task priority evaluation method integrating multiple factors such as priority, waiting time, and remaining time is proposed to provide an indicator basis for preemptive and sequential scheduling. The purpose of the present invention is to solve the chip-level task scheduling problem caused by the different importance of tasks and computing resources of distribution intelligent terminals, in order to improve the adaptive computing capabilities of the edge of distribution intelligent terminals and enhance the intelligent level of distribution network operation and maintenance.

[0063] Figure 1 is an optional flowchart of a multi-core heterogeneous chip task scheduling method for a power distribution intelligent terminal provided in an embodiment of the present application. Figure 1 The method may include but is not limited to steps S100 to S400.

[0064] Step S100, receiving a computing task and storing it in a scheduling task queue, and obtaining the task importance level, task arrival time, task deadline and core resources required for the computing task.

[0065] Step S200 , performing a priority evaluation on the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value.

[0066] Step S300, scheduling the scheduling task queue according to the task importance level and the priority value to obtain a current scheduling queue.

[0067] Step S400, in each scheduling cycle, tasks are scheduled for each slave core according to the current scheduling queue and the core resources required for the task.

[0068] Steps S100 to S400 shown in the embodiment of the present application are evaluated by integrating the importance of tasks, task arrival time, task deadline, etc. to obtain priority values, and scheduling the scheduling task queue according to the task importance level and priority value, combined with the core resources required for the task, which can provide an indicator basis for the scheduling of computing tasks, solve the chip-level task scheduling problems caused by different task importances and computing resources of distribution intelligent terminals, and improve the edge adaptive computing capabilities of distribution terminals and the intelligent level of power grid operation and maintenance. In addition, low-latency transmission between multi-core data in a shared memory manner can also meet the low-latency requirements of multiple services of distribution intelligent terminals.

[0069] In some embodiments, step S200 includes but is not limited to the following steps S210 to S270:

[0070] Step S210, configuring importance level weight, waiting time weight, and remaining time weight.

[0071] Step S220, calculating a first difference between the current time and the task arrival time to obtain the task waiting time.

[0072] Step S230, calculating a second difference between the current time and the task deadline to obtain the remaining time of the task.

[0073] Step S240: weighting the task importance level using the importance level weight to obtain a weighted task level.

[0074] Step S250: weighting the task waiting time using the waiting time weight to obtain a weighted waiting time.

[0075] Step S260, using a negative logarithmic function to process the task remaining time, and using the remaining time weight to weight the processing result to obtain a weighted remaining time.

[0076] Step S270, calculating the weighted sum of the weighted task level, the weighted waiting time and the weighted remaining time to obtain a priority value.

[0077] In some embodiments, step S300 includes but is not limited to the following steps S310 to S330:

[0078] Step S310: sort the computing tasks in the scheduling task queue according to the priority value.

[0079] Step S320: When there is only one computing task with the highest task importance level in the scheduling task queue, the computing task is moved to the front of the scheduling task queue.

[0080] Step S330, when there are multiple computing tasks with the highest task importance level in the scheduling task queue, all the computing tasks are moved to the front of the scheduling task queue, and all the computing tasks moved to the front are sorted according to the priority value.

[0081] In some embodiments, step S320 includes but is not limited to the following steps S321 to S323:

[0082] Step S321: When a number of computing tasks are compared and only the priority values ​​are the same, the computing tasks are sorted in such a way that the higher the task importance level, the earlier it is scheduled.

[0083] Step S322: When a plurality of computing tasks are compared and only the priority value and the task importance level are the same, the computing tasks are sorted in such a way that the earlier the task ends, the earlier it is scheduled.

[0084] Step S323: When several computing tasks are compared and the priority values, the task importance levels and the task end times are all the same, the computing tasks are sorted in a random order.

[0085] In some embodiments, step S400 includes but is not limited to the following steps S410 to S430:

[0086] Step S410, taking out the computing task at the front of the queue from the current scheduling queue.

[0087] Step S420, when the task importance level of the computing task is the highest level, preemptive scheduling is performed based on the core resources required for the task and in combination with the shared memory.

[0088] Step S430, when the task importance level of the computing task is not the highest level, polling waiting scheduling is performed according to the core resources required by the task in combination with the shared memory.

[0089] In some embodiments, the method further includes a step of configuring a multi-core heterogeneous chip for a power distribution intelligent terminal, specifically including the following steps S510 to S530:

[0090] Step S510: configure the main core for task scheduling, communication control, shared memory control and task distribution processing

[0091] Step S520, configuring a number of slave cores for performing various task execution processes.

[0092] Step S530, configuring a shared memory for storing data required to execute the computing task.

[0093] In some embodiments, the method further includes the step of initializing the master core and each slave core of the multi-core heterogeneous chip for the intelligent power distribution terminal, specifically including the following steps S610 to S630:

[0094] Step S610, establishing an inter-core communication channel.

[0095] Step S620, establishing a shared memory.

[0096] Step S630, initializing the scheduling task queue.

[0097] Below, in conjunction with a specific scenario application example of multi-core heterogeneous chip task scheduling for a power distribution intelligent terminal, the solution of the embodiment of the present application is described in detail and explained:

[0098] In an embodiment of the present application, a multi-core heterogeneous chip task scheduling method for power distribution intelligent terminals is provided, and the method can be applied to multi-core heterogeneous chip task scheduling for power distribution intelligent terminals.

[0099] Specifically, refer to Figure 2 The chip adopts a master-slave multi-core heterogeneous structure, in which the master core is the management core for task scheduling, and various slave cores are the execution cores for computing tasks. Through the task scheduling method proposed in the present invention, the master core is responsible for the scheduling, distribution, communication and other management of various computing tasks received by the chip, and the data interaction between each core is managed by controlling the shared memory. The method of the present invention can realize chip-level task scheduling that meets the priority processing requirements of important tasks in the distribution network. Reduce latency,

[0100] Shared memory refers to a memory space that is divided in the memory space, except for the exclusive space of each core, and all cores have access and read and write permissions. In the present invention, the shared memory space is divided into a management information area, an input data area, an output data area, and a reserved area. Among them, the management information area stores information data used to initialize the master core and each slave core, and the input data area stores the data required to be loaded before the calculation task is executed, the output data area stores the result data generated after the calculation task is completed, and the reserved area is used for future function expansion.

[0101] Based on the above-mentioned chip, the preemptive important task scheduling method based on multi-core heterogeneous chips in the embodiment of the present application is mainly based on the task priority evaluation method proposed in the embodiment of the present application, which evaluates the priority of the currently arriving tasks, sorts the various computing tasks from high to low according to the priority, and prioritizes the resource allocation for tasks with high priority. At the same time, when an urgent and important task occurs, preemptive scheduling is implemented, that is, the existing executing tasks are interrupted to release resources for the urgent and important tasks, so as to meet the scheduling needs of the power distribution intelligent terminal for important tasks.

[0102] Furthermore, the specific steps include the following steps 1 to 3:

[0103] Step 1: After the chip is powered on, the master core and each slave core execute an initialization program, including but not limited to establishing an inter-core mailbox communication channel, establishing a shared memory, and initializing a scheduling task queue operation. Specifically, the initialization scheduling task queue operation sets the scheduling task queue ToDoList to an empty list.

[0104] Step 2: The main core loop waits and receives computing tasks sent by the application. When the main core receives the computing task, it starts the task scheduling process. The input of the task scheduling process includes the importance level of each task, the task arrival time, the task deadline, and the core resources required for the task. The task scheduling process calculates the importance and urgency of each task, obtains the scheduling priority of each task, and then arranges the scheduling task queue ToDoList according to the scheduling priority of each task. The specific steps are as follows:

[0105] Step 2.1: The main core calculates the importance and urgency of each task in the waiting queue according to the task priority evaluation method for power distribution intelligent terminal measurement and control services proposed in the embodiment of the present application, and obtains the scheduling priority value Prior of each task.

[0106] Specifically, the input of the task priority evaluation method includes the importance level Imp of each task, the task arrival time Start, and the task deadline End. Among them, the importance level of the task is an integer from 1 to 10 (including 1 and 10), 1 represents the lowest importance level, 10 represents the highest importance level, and in the task scheduling method of the embodiment of the present application, preemptive scheduling is implemented for tasks with an importance level of 10; the task arrival time is the time when the high-level application initiates a computing task request to the chip; the task deadline is the time when the high-level application expects the task to end execution.

[0107] The formula for calculating the priority value of a task is as follows:

[0108] Prior=a*Imp+b*(Now-Start)+c*e -(End-Now) ;

[0109] Among them, Now is the current time, a, b, c are the weights of importance level, waiting time, and remaining time respectively, and e is the natural logarithm. The formula uses a linear weighted method to calculate the three factors that affect the priority of task scheduling, among which the remaining time is processed by a negative logarithmic function to satisfy the logic that the smaller the remaining time, the earlier it is scheduled. According to the priority value calculated by the formula, if the method of scheduling first is followed according to the principle of scheduling first with a larger priority value, the more important the task, the longer the waiting time, and the smaller the remaining time, the earlier it will be scheduled.

[0110] The weights a, b, and c can be selected according to preference. In view of the important and timely characteristics of the power distribution intelligent terminal, the weights a and c can be appropriately increased to make important and urgent tasks easier to be scheduled, so as to ensure that important tasks such as uploading and issuing control instructions and collecting important sensor data in the power distribution intelligent terminal can be completed in time.

[0111] Step 2.2: Arrange the order of each task from high to low according to the Prior value of each task. When the Prior values ​​of two tasks are the same, compare the task importance levels Imp. The higher the importance level, the earlier it will be scheduled. When the Imp values ​​of the two tasks are the same, compare the task deadlines End. The earlier the deadline, the earlier it will be scheduled. When the End values ​​of the two tasks are the same, arrange the order of the two tasks randomly.

[0112] Step 2.3: If there is a task with the highest priority level of 10 in the waiting queue, move it to the front of the scheduling task queue ToDoList. If there are multiple tasks with the priority level of 10, move all of them to the front of ToDoList and arrange the order of these tasks according to their Prior values.

[0113] Step 3: In each scheduling cycle, the main core schedules tasks according to the task queue in ToDoList. The specific steps are as follows:

[0114] Step 3.1: The main core takes the task at the front of the queue from ToDoList. If the task's importance level is 10, execute step 3.2 to perform preemptive scheduling; if the task's importance level is less than 10, execute step 3.3 to perform round-robin scheduling.

[0115] Step 3.2: Preemptively schedule the task with an importance level of 10. According to the required core resources of the task and the current operation status of each slave core, determine whether the current remaining resources can meet the execution resource requirements of the task. If it can be met, the data required by the task is loaded into the input data area of ​​the shared memory, and an execution command is sent to the core required by the task. If the requirements cannot be met, an interrupt instruction is sent to the task currently occupying these resources, instructing it to protect the scene and add it to the front of the ToDoList. After all the required resources are released, the data required by the task is loaded into the input data area of ​​the shared memory, and an execution command is sent to the core required by the task. After the preemptive scheduling is completed, jump to step 3.4.

[0116] Step 3.3: Perform polling and waiting scheduling for tasks with an importance level less than 10. According to the required core resources of the task and the current operation status of each slave core, determine whether the current remaining resources can meet the execution resource requirements of the task. If it can be met, the data required for the task is loaded into the input data area of ​​the shared memory, and an execution command is sent to the core required by the task. If the requirements cannot be met, wait and continue to inquire about the required resources until the resource requirements are met or the maximum waiting time is reached. If it still cannot be scheduled after the maximum waiting time is reached, put the task at the front position of ToDoList. After the polling and waiting scheduling is completed, jump to step 3.4.

[0117] Step 3.4: The loop jumps back to step 3.1.

[0118] The method of the embodiment of the present application includes at least the following beneficial effects:

[0119] 1. Low-latency transmission between multi-core data is achieved by sharing memory, which can meet the low-latency requirements of multiple services of power distribution intelligent terminals;

[0120] 2. Through the preemptive priority scheduling method of important tasks, it can not only meet the basic requirements of multi-task scheduling, but also meet the needs of timely processing of important tasks in the distribution network. It integrates multiple factors such as priority, waiting time, and remaining time for priority evaluation, and provides indicators for preemptive and sequential scheduling. It can solve the chip-level task scheduling problems caused by different task importance and computing resources of distribution intelligent terminals, improve the adaptive computing capabilities of the edge of distribution terminals, and enhance the intelligent level of operation and maintenance of power grids.

[0121] See also Figure 3 The embodiment of the present application also provides a multi-core heterogeneous chip task scheduling system for power distribution intelligent terminals, which can implement the multi-core heterogeneous chip task scheduling method for power distribution intelligent terminals. The system includes:

[0122] The first module 101 is used to receive a computing task and store it in a scheduling task queue, and obtain the task importance level, task arrival time, task deadline and core resources required for the computing task;

[0123] The second module 102 is used to evaluate the priority of the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value;

[0124] The third module 103 is used to schedule the scheduling task queue according to the task importance level and the priority value to obtain the current scheduling queue;

[0125] The fourth module 104 is used to schedule tasks for each slave core in each scheduling cycle according to the current scheduling queue and the core resources required for the task in combination with the shared memory; wherein the shared memory is a memory area used jointly by the master core and all slave cores.

[0126] In some embodiments, the system further comprises:

[0127] The fifth module is used to configure multi-core heterogeneous chips for power distribution intelligent terminals, specifically for: configuring the master core for task scheduling, communication control, shared memory control and task distribution processing; configuring several slave cores for various task execution processing; configuring shared memory for storing data required to perform computing tasks.

[0128] In some embodiments, the system further comprises:

[0129] The sixth module is used to initialize the master core and each slave core of the multi-core heterogeneous chip for the intelligent power distribution terminal, specifically for: establishing an inter-core communication channel; establishing a shared memory; and initializing the scheduling task queue.

[0130] It can be understood that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0131] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the multi-core heterogeneous chip task scheduling method for power distribution intelligent terminals when executing the computer program. The electronic device can be any intelligent terminal including a tablet computer, a car computer, etc.

[0132] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0133] See also Figure 4 , Figure 4 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0134] The processor 201 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0135] The memory 202 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 202 can store an operating system and other applications. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 202, and the processor 201 calls and executes the multi-core heterogeneous chip task scheduling method for power distribution intelligent terminals in the embodiment of this application;

[0136] Input / output interface 203, used to implement information input and output;

[0137] The communication interface 204 is used to realize the communication interaction between the device and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WIFI, Bluetooth, etc.);

[0138] Bus 205 , which transmits information between various components of the device (e.g., processor 201 , memory 202 , input / output interface 203 , and communication interface 204 );

[0139] The processor 201 , the memory 202 , the input / output interface 203 and the communication interface 204 are connected to each other in communication within the device via the bus 205 .

[0140] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the above-mentioned multi-core heterogeneous chip task scheduling method for power distribution intelligent terminals.

[0141] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiments, the functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0142] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0143] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0144] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0145] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0146] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0147] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0148] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0149] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0150] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0151] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0152] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0153] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A multi-core heterogeneous chip task scheduling method for power distribution intelligent terminals, characterized in that: The following steps are involved: Receive computing tasks and store them in the scheduling task queue, and obtain the task importance level, task arrival time, task deadline and core resources required for the computing tasks; Performing a priority evaluation on the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value; Scheduling the scheduling task queue according to the task importance level and the priority value to obtain a current scheduling queue; In each scheduling cycle, tasks are scheduled for each slave core according to the current scheduling queue and the core resources required for the task in combination with the shared memory; wherein the shared memory is a memory area used jointly by the master core and all slave cores.

2. The method according to claim 1, characterized in that The step of performing a priority evaluation on the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value comprises the following steps: Configure importance level weight, waiting time weight, and remaining time weight; Calculate a first difference between the current time and the task arrival time to obtain the task waiting time; Calculate a second difference between the current time and the task deadline to obtain the remaining time of the task; The importance level of the task is weighted by using the importance level weight to obtain a weighted task level; The waiting time weight is used to perform weighted processing on the task waiting time to obtain a weighted waiting time; The remaining time of the task is processed by using a negative logarithmic function, and the processing result is weighted by using the remaining time weight to obtain a weighted remaining time; A weighted sum of the weighted task level, the weighted waiting time and the weighted remaining time is calculated to obtain a priority value.

3. The method according to claim 1, characterized in that The step of scheduling the scheduling task queue according to the task importance level and the priority value to obtain the current scheduling queue includes the following steps: sorting the computing tasks in the scheduling task queue according to the priority value; When there is only one computing task with the highest task importance level in the scheduling task queue, the computing task is moved to the front of the scheduling task queue; When there are multiple computing tasks with the highest task importance level in the scheduling task queue, all the computing tasks are brought to the front of the scheduling task queue, and all the computing tasks brought to the front are sorted according to the priority value.

4. The method according to claim 3, characterized in that The step of sorting the computing tasks in the scheduling task queue according to the priority value comprises the following steps: When several computing tasks are compared and only the priority values ​​are the same, the computing tasks are sorted in such a way that the higher the task importance, the earlier it is scheduled; When a plurality of computing tasks are compared and only the priority value and the task importance level are the same, the computing tasks are sorted in such a way that the earlier the task ends, the earlier it is scheduled; When several computing tasks are compared and the priority values, the task importance levels and the task end times are all the same, the computing tasks are sorted in a random order.

5. The method according to claim 1, characterized in that The step of scheduling tasks on each slave core in combination with shared memory according to the current scheduling queue and the core resources required for the task includes the following steps: Take out the computing task at the front of the queue from the current scheduling queue; When the task importance level of the computing task is the highest level, preemptive scheduling is performed according to the core resources required by the task and in combination with the shared memory; When the task importance level of the computing task is not the highest level, polling waiting scheduling is performed according to the core resources required by the task in combination with the shared memory.

6. The method according to claim 1, characterized in that The method also includes the step of configuring a multi-core heterogeneous chip for a power distribution intelligent terminal, specifically including the following steps: Configure the main core for task scheduling, communication control, shared memory control, and task distribution processing; Configure several slave cores to perform various task executions; Configure shared memory to store the data required to perform computing tasks.

7. The method according to claim 1, characterized in that The method further includes the step of initializing the master core and each slave core of the multi-core heterogeneous chip for the intelligent power distribution terminal, specifically including the following steps: Establish inter-core communication channels; Create shared memory; Initialize the scheduling task queue.

8. A multi-core heterogeneous chip task scheduling system for power distribution intelligent terminals, characterized in that: include: The first module is used to receive computing tasks and store them in the scheduling task queue, and obtain the task importance level, task arrival time, task deadline and core resources required for the computing tasks; The second module is used to evaluate the priority of the computing task according to the task importance level, the task arrival time, and the task deadline to obtain a priority value; The third module is used to schedule the scheduling task queue according to the task importance level and the priority value to obtain the current scheduling queue; The fourth module is used to schedule tasks for each slave core in each scheduling cycle according to the current scheduling queue and the core resources required for the task in combination with the shared memory; wherein the shared memory is a memory area used jointly by the master core and all slave cores.

9. An electronic device, characterized in that: including a processor and a memory; The memory is used to store programs; The processor executes the program to implement the method according to any one of claims 1 to 7.

10. A computer storage medium storing a program executable by a processor, characterized in that: The program executable by the processor is used to implement the method according to any one of claims 1 to 7 when executed by the processor.

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