Multi-HS mode eMMC main controller based on FPGA

Abstract

The invention discloses a multi-HS mode eMMC master controller based on an FPGA. The eMMC master controller comprises a system control module, a function processing module, a data stream arbitration module, a read-write FIFO module, a CMD module, a data sending and receiving module, a clock management module and a reset management module. The system is good in stability, high in system integration, high in adaptability, high in transportability and applicable to various architectures, and only occupies user IO of an FPGA and a very small part of resources; and meanwhile, the high-speed eMMC main controller can release resources of a CPU on the FPGA, so that the CPU focuses on data transmission, and power-on automatic ID detection, hard reset enabling and SLC mode setting are realized.

Description

Technical Field

[0001] The invention relates to the field of electronic information technology, and in particular to a multi-HS mode eMMC main controller based on FPGA. Background Art

[0002] With the rapid development of electronic information technology, people's demand for electronic products has grown rapidly, which has led to an increasing demand for high-speed and large-capacity data storage, so electronic products and equipment have higher and higher requirements for data storage. However, the NAND FLASH chips traditionally used in electronic devices have the disadvantages of poor compatibility, high operational complexity, high management difficulty, and slow transmission speed. As an embedded storage chip, eMMC has the advantages of simple interface, large storage capacity, fast transmission speed and high integration, making it widely used in the electronics field.

[0003] The existing eMMC main controller is generally controlled by a CPU or a single-chip microcomputer, and the eMMC reading and writing are controlled by calling the IP or functions packaged by the chip manufacturer. The disadvantage of this implementation method is the low reading and writing speed and poor adaptability.

[0004] Currently, most eMMC master controllers implemented on FPGA only support low-speed mode and are not compatible with high-speed mode, making them inconvenient to use. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a multi-HS mode eMMC master controller based on FPGA, which is characterized by comprising a system control module, a function processing module, a data flow arbitration module, a read-write FIFO module, a CMD module, a data sending and receiving module, a clock management module and a reset management module, wherein the system control module is used to parse the user command word, identify the corresponding content of the command word, and issue the operation command to the function processing module; the function processing module is used to execute different operation commands issued by the system control module, output the operation result as CMD content and transmit it to the data flow arbitration module, the data flow arbitration module is bidirectionally electrically connected to the function processing module, the function processing module is bidirectionally electrically connected to the read-write FIFO module, and the read-write FIFO module is used to perform cross-clock domain processing and cache processing, bidirectional data interaction between the read and written data and the functional processing module; the data stream arbitration module is bidirectionally electrically connected to the CMD module and the data sending and receiving module respectively, and the CMD module is used to perform CRC calculation according to the CMD content output by the data stream arbitration module and send it to the eMMC device to determine whether this CMD needs a response to receive the CMD response content; the data sending and receiving module is used to select different data sending and receiving paths according to different working modes of the eMMC main controller; the clock management module is used to generate a clock lower than 400kHz when the eMMC main controller is initialized, and switch to a normal working clock after the initialization is completed; the reset management module is used to generate a reset signal according to the timing required by the eMMC protocol when the eMMC main controller is initialized and powered on and hard reset.

[0006] Preferably, the functional processing module includes an initialization module, a bus mode switching module, a bus test module, an erase control module, a write control module and a read control module. The initialization module is used to initialize the eMMC master controller chip according to the internal process; the bus mode switching module is used to switch between the HS mode, the HS200 mode and the HS400 mode according to the enablement of the system control module; the bus test module is used to perform a read and write test on the data bus in the HS mode according to the test enablement of the system control module, and perform a bus read test when the HS mode is switched to the HS200 mode, so that the eMMC master controller finds the best sampling point; the erase control module is used to perform a read and write test on the data bus in the HS mode according to the test enablement of the system control module, and perform a bus read test when the HS mode is switched to the HS200 mode, so that the eMMC master controller finds the best sampling point; the erase control module is used to perform a read and write test on the data bus in the HS mode according to the test enablement of the system control module. The eMMC main controller is erased according to the erase enable and erase address of the system control module; the write control module writes data to the eMMC main controller according to the single / multi-block write enable and operation address of the system control module, and uses corresponding write operation states according to different modes; the read control module reads data from the eMMC main controller according to the single / multi-block read enable and operation address of the system control module, and uses corresponding read operation states according to different modes; the output end of the read-write FIFO module is electrically connected to the write control module, and the output end of the read control module is electrically connected to the input end of the read-write FIFO module.

[0007] Preferably, the data flow arbitration module arbitrates the CMD content input by the CMD module and distributes it to the functional processing module, and the CMD content arbitration output by each functional module of the functional processing module is distributed to the CMD module through the data flow arbitration module; the data flow arbitration module arbitrates the data input by the data sending and receiving module and distributes it to the read control module or the bus test module, and the data flow arbitration module distributes the data arbitration of the system control module or the bus test module to the data sending and receiving module.

[0008] Preferably, in the HS mode or HS200 mode, the data sending and receiving module operates in an SDR mode for data sending and receiving, and in the HS400 mode, the data sending and receiving module operates in a DDR mode.

[0009] Preferably, in the HS400 mode, the DDR data outputted from the data sending and receiving module passes through ODDR, the ODD byte is sent at the rising edge of the internal clock, and the EVEN byte is sent at the falling edge; the data returned by the eMMC main controller passes through IDDR, the ODD byte is decoded at the rising edge of the DS clock, and the EVEN byte is released at the falling edge of the DS clock.

[0010] Preferably, when the data sending and receiving module is in HS mode or HS200 mode, the DDR data output from the data sending and receiving module passes through ODDR, and the data at the rising edge and the falling edge are the same byte of data, while the data input from the data sending and receiving module will not enter IDDR after logical judgment, but will be directly input into the data stream arbitration module.

[0011] Preferably, the internal process of initializing the eMMC master controller chip in the initialization module includes the following steps:

[0012] S1.1. After power-on or hard reset, send CMD0 to perform soft reset on the device.

[0013] S1.2. Send CMD1 to confirm the device capacity;

[0014] S1.3. Send CMD2 to confirm the device ID;

[0015] S1.4. Send CMD3 to set the RCA address;

[0016] S1.5, send CMD7 to instruct the device to enter the Stanby state and wait for the busy signal to be pulled high;

[0017] S1.6, send CMD6 to write HS_TIMING register to set it to HS mode, and wait for the busy signal to be pulled high;

[0018] S1.7, send CMD6 to write BUS_WIDTH register to set bus width to 8 bits, and wait for busy signal to be pulled high;

[0019] S1.8, send CMD8 to obtain the EXT_CSD register, release the bidirectional data bus, wait for the data lines to be fully pulled low, then receive the EXT_CSD register and store it;

[0020] S1.9. Confirm whether hard reset needs to be enabled based on the parameters. If yes, proceed to step S1.10. Otherwise, proceed to step S1.12.

[0021] S1.10, confirm whether the current hard reset is enabled according to the data of the 162nd byte of EXT_CSD. If it is not enabled, go to step S1.11, otherwise go to step S1.12;

[0022] S1.11, send CMD6 to write RST_n_FUNCTION register to enable hard reset, wait for busy signal to be pulled high and then enter S1.8;

[0023] S1.12, confirm whether it is necessary to enable the SLC mode of the user data area. If it is necessary to enable it, proceed to step S1.13, otherwise proceed to step S1.20;

[0024] S1.13, obtain the maximum enhanced area size of the current eMMC device from bytes 157 to 159 in the EXT_CSD register obtained in step S1.8;

[0025] S1.14, send CMD6 to write ERASE_GROUP_DEF register to enable the setting, and wait for the busy signal to be pulled high;

[0026] S1.15, send CMD6 three times to write the 140th to 142th bytes of EXT_CSD to set the size of the enhanced area, and wait for the busy signal to be pulled high;

[0027] S1.16, send CMD6 to write EXT_CSD bytes 136 to 139 to set the start address of the enhance area, and wait for the busy signal to go high;

[0028] S1.17, send CMD6 to write the PARTITIONS_ATTRIBUTE register to set the User Data area to enhanced mode, and wait for the busy signal to be pulled high;

[0029] S1.18, send CMD6 to write the PARTITION_SETTING_COMPLETED register to indicate that all write setting operations of the device have been completed, and wait for the busy signal to be pulled high;

[0030] S1.19, send CMD13 to obtain device status;

[0031] S1.20. If the device status is Tran and there is no error, the initialization is completed. Otherwise, repeat steps S1.14 to S1.19.

[0032] Preferably, the switching process of the bus mode switching module for HS mode, HS200 mode and HS400 mode is as follows:

[0033] S2.1. After the device is initialized, send CMD8 to obtain the EXT_CSD register.

[0034] S2.2, query whether the DEVICE_TYPE register supports the HS200 mode and HS400 mode that need to be set. If it does, go to step 3. If it does not, directly jump out of the state machine and report to the system control module that the mode switching failed;

[0035] S2.3. Send CMD6 to write the HS_TIMING register to HS200 mode and wait for the busy signal to go high.

[0036] S2.4, send CMD13 to obtain the device status. If the device is in Tran status and there is no error, proceed to step S2.5. Otherwise, continue the operation of step S2.3.

[0037] S2.5, the device enters HS200 mode and sends CMD21 to start the bus test in HS200 mode;

[0038] S2.6, compare the received data with the test sequence number stored in RAM in advance, if the comparison is consistent, proceed to step S2.7, otherwise continue the operation of step S2.5;

[0039] S2.7, if the comparison is successful, it means that the HS200 switch is successful. If the final set mode is HS400 mode, then go to step S2.8. Otherwise, it proves that the mode switch is completed;

[0040] S2.8, send CMD6 to write HS_TIMING register to enter HS mode first, and wait for the busy signal to be pulled high;

[0041] S2.9, send CMD6 to write the BUS_WIDTH register to set the data width to 8-bit DDR data bus, and wait for the busy signal to be pulled high;

[0042] S2.10, send CMD6 to write HS_TIMING register to enter HS400 mode, and wait for the busy signal to be pulled high;

[0043] S2.11, send CMD13 to obtain the device status. If the device is in Tran status and there is no error, proceed to step S2.12. Otherwise, proceed to step S2.8.

[0044] S2.12, HS400 mode setting is successful.

[0045] Preferably, the write control module uses corresponding write operation states according to different modes, including that the data of the write control module is in SDR mode in HS / HS200 mode and the data of the write control module is in DDR mode in HS400 mode.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] (1) The multi-HS mode eMMC master controller provided by the present invention has good stability, high system integration, strong adaptability, and strong portability. It can be applied to various architectures and only occupies the user IO and a very small part of the resources of the FPGA. At the same time, the high-speed eMMC master controller implemented on the FPGA can release the resources of the CPU, allowing the CPU to focus on data transmission, and realizes automatic power-on detection of ID, hard reset enablement, and SLC mode setting. The user can set whether to set the hard reset and SLC mode according to needs, and can switch the HS mode online without recompiling the project setting mode. The function processing module is more flexible to use and transplant. The interface provided to the user is simple, allowing the user to focus on data transmission, saving the time spent on CMD control in the conventional technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is the overall framework diagram of the present invention.

[0049] Figure 2 This is an internal flow chart of initializing the eMMC main controller chip in the initialization module of the present invention.

[0050] Figure 3 This is a flow chart of the switching of the bus mode switching module of the present invention to the HS mode, HS200 mode and HS400 mode.

[0051] Figure 4 This is a processing block diagram of the data stream arbitration module of the present invention.

[0052] Figure 5 This is a block diagram of the data sending and receiving module IO compatible with DDR and SDR modes of the present invention. DETAILED DESCRIPTION

[0053] The present invention is further described below in conjunction with specific implementation methods.

[0054] In the description of the present invention, unless otherwise specified, "plurality" means two or more than two; the orientations or positional relationships indicated by the terms "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0055] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] The FPGA-based multi-HS mode eMMC master controller includes a system control module, a function processing module, a data flow arbitration module, a read-write FIFO module, a CMD module, a data sending and receiving module, a clock management module and a reset management module. The system control module is used to parse the user command word, identify the corresponding content of the command word, and send the operation command to the function processing module; the function processing module is used to execute different operation commands sent by the system control module, output the operation result into CMD content and transmit it to the data flow arbitration module, the data flow arbitration module is bidirectionally electrically connected to the function processing module, the function processing module is bidirectionally electrically connected to the read-write FIFO module, the read-write FIFO module is used to perform cross-clock domain processing and cache processing on the read-write data, and read and write to The data of the eMMC main controller is used to select different data sending and receiving paths according to different working modes of the eMMC main controller; the clock management module is used to generate a clock lower than 400kHz when the eMMC main controller is initialized, and switch to a normal working clock after the initialization is completed; the reset management module is used to generate a reset signal according to the timing required by the eMMC protocol when the eMMC main controller is initialized and powered on and hard reset.

[0057] The functional processing module includes an initialization module, a bus mode switching module, a bus test module, an erase control module, a write control module and a read control module. The initialization module is used to initialize the eMMC master controller chip according to the internal process; the bus mode switching module is used to switch between HS mode, HS200 mode and HS400 mode according to the enablement of the system control module; the bus test module is used to perform read and write tests on the data bus in the HS mode according to the test enablement of the system control module, and perform bus read tests when the HS mode is switched to the HS200 mode, so that the eMMC master controller can find the best sampling point;

[0058] The erase control module is used to perform an erase operation on the eMMC main controller according to the erase enable and erase address of the system control module;

[0059] The write control module performs write data operation on the eMMC main controller according to the single / multi-block write enable and operation address of the system control module, and also uses the corresponding write operation state according to different modes; the read control module performs read data operation on the eMMC main controller according to the single / multi-block read enable and operation address of the system control module, and also uses the corresponding read operation state according to different modes; the output end of the read-write FIFO module is electrically connected to the write control module, and the output end of the read control module is electrically connected to the input end of the read-write FIFO module. Specifically, the write control module uses the corresponding write operation state according to different modes, including that the data of the write control module is SDR mode in HS / HS200 mode, and the data of the write control module is DDR mode in HS400 mode. The read control module is the same as the write control module, and selects different state machines according to different HS working modes.

[0060] like Figure 4 As shown, the data flow arbitration module arbitrates the CMD content input by the CMD module and distributes it to the functional processing module. The arbitration of the CMD content output by each functional module of the functional processing module is distributed to the CMD module through the data flow arbitration module; the data flow arbitration module arbitrates the data input by the data sending and receiving module and distributes it to the read control module or the bus test module. The data flow arbitration module distributes the data arbitration of the system control module or the bus test module to the data sending and receiving module. Each submodule in the functional processing module that needs to send CMD data and DATA data will be assigned a module ID, which is the module_N_flag signal in the figure. When this module needs to send and receive CMD or DATA data, this signal will be pulled high, and the data flow arbitration module will process the data flowing to the IO or internal module at this time according to the assigned priority order.

[0061] like Figure 5 As shown, in the HS mode or HS200 mode, the data transmission and reception of the data transmission and reception module is in the SDR operation mode, and in the HS400 mode, the data transmission and reception is in the DDR mode. Module 1 to module N represent submodules of the replaceable functional processing module.

[0062] In the HS400 mode, the DDR data output from the data sending and receiving module passes through ODDR, the ODD byte is sent at the rising edge of the internal clock, and the EVEN byte is sent at the falling edge. The data returned by the eMMC host controller passes through IDDR, the ODD byte is decoded at the rising edge of the DS clock, and the EVEN byte is released at the falling edge of the DS clock.

[0063] In the HS mode or HS200 mode, the DDR data output from the data sending and receiving module passes through ODDR, and the rising and falling edges are the same byte of data, while the data input from the data sending and receiving module will not enter IDDR after logical judgment, but will be directly input into the data stream arbitration module.

[0064] The internal process of initializing the eMMC master controller chip in the initialization module includes the following steps:

[0065] S1.1. After power-on or hard reset, send CMD0 to perform soft reset on the device.

[0066] S1.2. Send CMD1 to confirm the device capacity;

[0067] S1.3. Send CMD2 to confirm the device ID;

[0068] S1.4. Send CMD3 to set the RCA address;

[0069] S1.5, send CMD7 to instruct the device to enter the Stanby state and wait for the busy signal to be pulled high;

[0070] S1.6, send CMD6 to write HS_TIMING register to set it to HS mode, and wait for the busy signal to be pulled high;

[0071] S1.7, send CMD6 to write BUS_WIDTH register to set bus width to 8 bits, and wait for busy signal to be pulled high;

[0072] S1.8, send CMD8 to obtain the EXT_CSD register, release the bidirectional data bus, wait for the data lines to be fully pulled low, then receive the EXT_CSD register and store it;

[0073] S1.9. Confirm whether hard reset needs to be enabled based on the parameters. If yes, proceed to step S1.10. Otherwise, proceed to step S1.12.

[0074] S1.10. According to the data of the 162th byte of EXT_CSD (RST_n_FUNCTION register), confirm whether the current hard reset is enabled. If not, proceed to step S1.11. Otherwise, proceed to step S1.12.

[0075] S1.11, send CMD6 to write RST_n_FUNCTION register to enable hard reset, wait for busy signal to be pulled high and then enter S1.8;

[0076] S1.12, confirm whether it is necessary to enable the SLC mode of the user data area. If it is necessary to enable it, proceed to step S1.13, otherwise proceed to step S1.20;

[0077] S1.13, obtain the maximum enhanced area size of the current eMMC device from bytes 157 to 159 (MAX_ENH_SIZE_MULT register) in the EXT_CSD register obtained in step S1.8;

[0078] S1.14, send CMD6 to write ERASE_GROUP_DEF register to enable the setting, and wait for the busy signal to be pulled high;

[0079] S1.15, send CMD6 three times to write the 140th to 142th bytes of EXT_CSD (ENH_SIZE_MULT register) to set the size of the enhanced area, and wait for the busy signal to be pulled high;

[0080] S1.16, send CMD6 to write 136th to 139th bytes (ENH_START_ADDR) of EXT_CSD to set the start address of the enhance area, and wait for the busy signal to be pulled high;

[0081] S1.17, send CMD6 to write the PARTITIONS_ATTRIBUTE register to set the User Data area to enhanced mode, and wait for the busy signal to be pulled high;

[0082] S1.18, send CMD6 to write the PARTITION_SETTING_COMPLETED register to indicate that all write setting operations of the device have been completed, and wait for the busy signal to be pulled high;

[0083] S1.19, send CMD13 to obtain device status;

[0084] S1.20. If the device status is Tran and there is no error, the initialization is completed. Otherwise, repeat steps S1.14 to S1.19.

[0085] The switching process of the bus mode switching module for HS mode, HS200 mode and HS400 mode is as follows:

[0086] S2.1. After the device is initialized, send CMD8 to obtain the EXT_CSD register.

[0087] S2.2, query whether the DEVICE_TYPE register supports the HS200 mode and HS400 mode that need to be set. If it does, go to step 3. If it does not, directly jump out of the state machine and report to the system control module that the mode switching failed;

[0088] S2.3. Send CMD6 to write the HS_TIMING register to HS200 mode and wait for the busy signal to go high.

[0089] S2.4, send CMD13 to obtain the device status. If the device is in Tran status and there is no error, proceed to step S2.5. Otherwise, continue the operation of step S2.3.

[0090] S2.5, the device enters HS200 mode and sends CMD21 to start the bus test in HS200 mode;

[0091] S2.6, compare the received data with the test sequence number stored in RAM in advance, if the comparison is consistent, proceed to step S2.7, otherwise continue the operation of step S2.5;

[0092] S2.7, if the comparison is successful, it means that the HS200 switch is successful. If the final set mode is HS400 mode, then go to step S2.8. Otherwise, it proves that the mode switch is completed;

[0093] S2.8, send CMD6 to write HS_TIMING register to enter HS mode first, and wait for the busy signal to be pulled high;

[0094] S2.9, send CMD6 to write the BUS_WIDTH register to set the data width to 8-bit DDR data bus, and wait for the busy signal to be pulled high;

[0095] S2.10, send CMD6 to write HS_TIMING register to enter HS400 mode, and wait for the busy signal to be pulled high;

[0096] S2.11, send CMD13 to obtain the device status. If the device is in Tran status and there is no error, proceed to step S2.12. Otherwise, proceed to step S2.8.

[0097] S2.12, HS400 mode setting is successful.

[0098] In actual use, if you want to switch from HS400 mode back to HS mode, use hard reset to return directly to HS mode.

[0099] In this embodiment, the FPGA used is the A7 platform of Xilinx, and is encoded according to the eMMC 5.1 protocol standard.

[0100] The present invention has good stability, high system integration, strong adaptability, and strong portability, and is applicable to a variety of architectures, occupying only the user IO and a very small part of the resources of the FPGA; at the same time, realizing a high-speed eMMC main controller on the FPGA can release the resources of the CPU, allowing the CPU to focus on data transmission, and realizing automatic power-on detection of ID, hard reset enablement, and SLC mode setting. The user can set whether to set the hard reset and SLC mode according to needs, and can switch the HS mode online without recompiling the engineering setting mode, and the function processing module is more flexible in use and transplantation; the interface provided to the user is simple, allowing the user to focus on data transmission, saving the time spent on CMD control in conventional telephone charges in the prior art.

[0101] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of rights of the present invention. Therefore, modifications, equivalent changes, improvements, etc. made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A multi-HS mode eMMC master controller based on FPGA, characterized in that: It includes a system control module, a function processing module, a data flow arbitration module, a read-write FIFO module, a CMD module, a data sending and receiving module, a clock management module and a reset management module. The system control module is used to parse the user command word, identify the corresponding content of the command word, and issue the operation command to the function processing module; The function processing module is used to execute different operation commands issued by the system control module, output the operation results as CMD content and transmit them to the data flow arbitration module, the data flow arbitration module is bidirectionally electrically connected to the function processing module, the function processing module is bidirectionally electrically connected to the read-write FIFO module, the read-write FIFO module is used to perform cross-clock domain processing and cache processing on the read and write data, and bidirectional data interaction between the read and written data and the function processing module; the data flow arbitration module is bidirectionally electrically connected to the CMD module and the data sending and receiving module respectively, the CMD module is used to perform CRC calculation according to the CMD content output by the data flow arbitration module and send it to the eMMC device, and determine whether this CMD needs to respond to receive the CMD response content; the data sending and receiving module is used to select different data sending and receiving paths according to different working modes of the eMMC main controller; the clock management module is used to generate a clock lower than 400kHz when the eMMC main controller is initialized, and switch to a normal working clock after the initialization is completed; the reset management module is used to generate a reset signal according to the timing required by the eMMC protocol when the eMMC main controller is initialized and powered on and hard reset.

2. A multi-HS mode eMMC master controller based on FPGA according to claim 1, characterized in that: The functional processing module includes an initialization module, a bus mode switching module, a bus test module, an erase control module, a write control module and a read control module. The initialization module is used to initialize the eMMC master controller chip according to the internal process; the bus mode switching module is used to switch between HS mode, HS200 mode and HS400 mode according to the enablement of the system control module; the bus test module is used to perform a read and write test on the data bus in the HS mode according to the test enablement of the system control module, and perform a bus read test when the HS mode is switched to the HS200 mode, so that the eMMC master controller can find the best sampling point; The erase control module is used to perform an erase operation on the eMMC main controller according to the erase enable and erase address of the system control module; the write control module performs a write data operation on the eMMC main controller according to the single / multi-block write enable and operation address of the system control module, and uses the corresponding write operation state according to different modes; the read control module performs a read data operation on the eMMC main controller according to the single / multi-block read enable and operation address of the system control module, and uses the corresponding read operation state according to different modes; the output end of the read-write FIFO module is electrically connected to the write control module, and the output end of the read control module is electrically connected to the input end of the read-write FIFO module.

3. The FPGA-based multi-HS mode eMMC master controller according to claim 2, characterized in that: The data flow arbitration module arbitrates the CMD content input by the CMD module and distributes it to the functional processing module, and the CMD content arbitration output by each functional module of the functional processing module is distributed to the CMD module through the data flow arbitration module; The data flow arbitration module arbitrates and distributes the data input by the data sending and receiving module to the read control module or the bus test module, and the data flow arbitration module distributes the data of the system control module or the bus test module to the data sending and receiving module.

4. The FPGA-based multi-HS mode eMMC master controller according to claim 3, characterized in that: The data sending and receiving module operates in SDR mode for data sending and receiving in HS mode or HS200 mode, and in DDR mode for data sending and receiving in HS400 mode.

5. The FPGA-based multi-HS mode eMMC master controller according to claim 4, characterized in that: In the HS400 mode, the DDR data outputted from the data sending and receiving module passes through ODDR, the ODD byte is sent at the rising edge of the internal clock, and the EVEN byte is sent at the falling edge. The data returned by the eMMC master controller passes through IDDR, the ODD byte is decoded at the rising edge of the DS clock, and the EVEN byte is released at the falling edge of the DS clock.

6. The FPGA-based multi-HS mode eMMC master controller according to claim 5, characterized in that: When the data sending and receiving module is in HS mode or HS200 mode, the DDR data output from the data sending and receiving module passes through ODDR, and the data of the same byte is received at the rising edge and the falling edge, while the data input from the data sending and receiving module will not enter IDDR after logical judgment, but will be directly input into the data stream arbitration module.

7. The FPGA-based multi-HS mode eMMC master controller according to claim 3 or 4, characterized in that: The internal process of initializing the eMMC master controller chip in the initialization module includes the following steps: S1.

1. After power-on or hard reset, send CMD0 to perform soft reset on the device. S1.

2. Send CMD1 to confirm the device capacity; S1.

3. Send CMD2 to confirm the device ID; S1.

4. Send CMD3 to set the RCA address; S1.5, send CMD7 to instruct the device to enter the Stanby state and wait for the busy signal to be pulled high; S1.6, send CMD6 to write HS_TIMING register to set it to HS mode, and wait for the busy signal to be pulled high; S1.7, send CMD6 to write BUS_WIDTH register to set bus width to 8 bits, and wait for busy signal to be pulled high; S1.8, send CMD8 to obtain the EXT_CSD register, release the bidirectional data bus, wait for the data lines to be fully pulled low, then receive the EXT_CSD register and store it; S1.

9. Confirm whether hard reset needs to be enabled based on the parameters. If yes, proceed to step S1.

10. Otherwise, proceed to step S1.

12. S1.10, confirm whether the current hard reset is enabled according to the data of the 162nd byte of EXT_CSD. If it is not enabled, go to step S1.11, otherwise go to step S1.12; S1.11, send CMD6 to write RST_n_FUNCTION register to enable hard reset, wait for busy signal to be pulled high and then enter S1.8; S1.12, confirm whether it is necessary to enable the SLC mode of the user data area. If it is necessary to enable it, proceed to step S1.13, otherwise proceed to step S1.20; S1.13, obtain the maximum enhanced area size of the current eMMC device from bytes 157 to 159 in the EXT_CSD register obtained in step S1.8; S1.14, send CMD6 to write ERASE_GROUP_DEF register to enable the setting, and wait for the busy signal to be pulled high; S1.15, send CMD6 three times to write the 140th to 142th bytes of EXT_CSD to set the size of the enhanced area, and wait for the busy signal to be pulled high; S1.16, send CMD6 to write EXT_CSD bytes 136 to 139 to set the start address of the enhance area, and wait for the busy signal to go high; S1.17, send CMD6 to write the PARTITIONS_ATTRIBUTE register to set the User Data area to enhanced mode, and wait for the busy signal to be pulled high; S1.18, send CMD6 to write the PARTITION_SETTING_COMPLETED register to indicate that all write setting operations of the device have been completed, and wait for the busy signal to be pulled high; S1.19, send CMD13 to obtain device status; S1.

20. If the device status is Tran and there is no error, the initialization is completed. Otherwise, repeat steps S1.14 to S1.

19.

8. The FPGA-based multi-HS mode eMMC master controller according to claim 7, characterized in that: The switching process of the bus mode switching module for HS mode, HS200 mode and HS400 mode is as follows: S2.

1. After the device is initialized, send CMD8 to obtain the EXT_CSD register. S2.2, query whether the DEVICE_TYPE register supports the HS200 mode and HS400 mode that need to be set. If it does, go to step 3. If it does not, directly jump out of the state machine and report to the system control module that the mode switching failed; S2.

3. Send CMD6 to write the HS_TIMING register to HS200 mode and wait for the busy signal to go high. S2.4, send CMD13 to obtain the device status. If the device is in Tran status and there is no error, proceed to step S2.

5. Otherwise, continue the operation of step S2.

3. S2.5, the device enters HS200 mode, and sends CMD21 to start the bus test in HS200 mode; S2.6, compare the received data with the test sequence number stored in RAM in advance, if the comparison is consistent, proceed to step S2.7, otherwise continue the operation of step S2.5; S2.7, if the comparison is successful, it means that the HS200 switch is successful. If the final set mode is HS400 mode, then go to step S2.

8. Otherwise, it proves that the mode switch is completed; S2.8, send CMD6 to write HS_TIMING register to enter HS mode first, and wait for the busy signal to be pulled high; S2.9, send CMD6 to write the BUS_WIDTH register to set the data width to 8-bit DDR data bus, and wait for the busy signal to be pulled high; S2.10, send CMD6 to write HS_TIMING register to enter HS400 mode, and wait for the busy signal to be pulled high; S2.11, send CMD13 to obtain the device status. If the device is in Tran status and there is no error, proceed to step S2.

12. Otherwise, proceed to step S2.

8. S2.12, HS400 mode setting is successful.

9. The FPGA-based multi-HS mode eMMC master controller according to claim 8, characterized in that: The write control module uses corresponding write operation states according to different modes, including that the data of the write control module is SDR mode in HS / HS200 mode and the data of the write control module is DDR mode in HS400 mode.

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