Method for estimating packaging size of system-in-package circuit
Through systematic steps and rules, the accuracy of system-level packaging circuit packaging size estimates is improved, and the problem of low packaging size estimate accuracy in the prior art is solved, the risk of packaging size changes is reduced, and the estimated efficiency and design reliability are improved.
Patent Information
- Application Number
- CN202411725190.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-28
- Publication Date
- 2025-03-21
AI Technical Summary
The existing system-level packaging circuit packaging size estimate method has low accuracy, resulting in frequent changes in packaging size, affecting client design and system solutions.
Through the steps of chip layout size calculation, effective packaging area adjustment, device layout and packaging appearance dimension determination, unified and determined rules are used to estimate, reduce engineering experience dependence, and approximate the optimal packaging design size through multiple iterations.
Improve the accuracy of system-level packaging circuit packaging size estimates, reduce the risk of package size changes, and improve the estimated efficiency and design reliability.
Smart Images
Figure CN119670665A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of hybrid integrated circuit design and manufacturing, and in particular to a method for estimating the package size of a system-level packaged circuit. Background Art
[0002] The rapid development of the integrated circuit industry towards miniaturization, multi-function, high performance and high reliability has led to a sharp increase in the demand for hybrid integrated circuit products containing multiple specifications and multiple bare chips. Hybrid integrated circuits include a variety of advanced packaging forms such as multi-chip packages (MCP), multi-chip modules (MCM) and system-in-package (SIP). Among them, the system-in-package circuit is generally the core control and computing processing unit of the client subsystem or complete equipment, and its development process is generally carried out simultaneously with the development of the client equipment. In the feasibility analysis and demonstration process of the system-level package circuit development, it is necessary to give the expected package size of the product as early as possible and feedback to the customer to evaluate whether the package size meets the conditions of the customer's application scenario. During the development process, changes in the package size often cause design changes on the client side, and even overturn the client's existing system solution, leading to solution iteration.
[0003] The design and development of system-level packaging circuits include electrical aspects and packaging structure aspects. The packaging structure design is generally completed by the integrated circuit packaging factory. However, the integrated circuit packaging factory is generally unable to provide a reliable estimated package size during the system-level packaging circuit demonstration stage, that is, before the actual design work is carried out. At the same time, the electrical design unit of the SIP circuit generally arranges circuit designers to make a preliminary layout of the main internal components according to engineering experience, and provide an estimated package size. The estimated package size generally has a large deviation, and the size can only be expanded a second time to reduce the risk of later package size changes. Therefore, there are two problems with the existing system-level packaging circuit package size estimation method: first, the estimation is based on engineering experience rather than established methods, and the degree of deviation of the estimated value cannot be controlled; second, the final estimated package size is generally significantly larger than the actual demand, and it is impossible to maximize the miniaturization integration advantages of hybrid integrated circuits.
[0004] In summary, the problem with the prior art is that the estimation accuracy of the package size of the system-level package circuit is low. Summary of the invention
[0005] The object of the present invention is to provide a method for estimating the package size of a system-in-package circuit with high accuracy.
[0006] The technical solution to achieve the purpose of the present invention is:
[0007] A method for estimating the package size of a system-level package circuit comprises the following steps:
[0008] Die layout size calculation: Determine the total die layout size based on the die size and soldering type and margin control requirements;
[0009] Adjustment of effective package area: According to the expected package shape and the package forbidden area, the effective package area is obtained. According to the rationality judgment rules of the effective package area, the expected package shape size is adjusted to obtain the available effective package area;
[0010] Device layout: Place bare chips and resistor and capacitor devices in the available effective packaging area in descending order and using the remaining maximum rectangular area method;
[0011] Determine the package size: divide the remaining area after device layout by the available effective package area to get the blank ratio. Based on the blank ratio and the package size judgment rules, evaluate and adjust the expected package size to get the estimated value of the system-level package circuit package size.
[0012] Preferably, the effective packaging area adjustment step includes:
[0013] Determine the effective package area: subtract the package forbidden area from the expected package shape to obtain the rectangular effective package area;
[0014] Reasonableness judgment of effective encapsulation area: judge whether the reasonableness judgment rules of effective encapsulation area are met at the same time according to the area, first and second side lengths of the effective encapsulation area;
[0015] Obtaining the available effective packaging area: when any of the area, the first and the second side lengths of the effective packaging area do not meet the reasonableness judgment rules of the effective packaging area, adjust the corresponding dimensions of the expected packaging shape to obtain a new expected packaging shape, and jump to the step of determining the effective packaging area; when the area, the first and the second side lengths of the effective packaging area simultaneously meet the reasonableness judgment rules of the effective packaging area, determine the effective packaging area as the available effective packaging area.
[0016] Preferably, the device layout step comprises:
[0017] Select target device: select the device with the largest size from the devices that have not been placed as the target device;
[0018] Determine the area to be placed: calculate the maximum rectangular position of the remaining area of the available effective packaging area to obtain the area to be placed;
[0019] Calculate the remaining area of the placement method: Place the target device in different postures along the four corners of the area to be placed, and calculate the remaining area and side length of various placement methods;
[0020] Selected placement method: The placement method with the largest remaining area is selected as the selected placement method. If the areas of the largest remaining areas of two placement methods are the same, the placement method with the largest remaining area closer to a square is selected as the selected placement method. If the areas of the largest remaining areas of two placement methods are the same and have the same shape, the placement method with the second largest remaining area is selected as the selected placement method.
[0021] Place the target device: place the target device in the to-be-placed area according to the selected placement method; if the target device is not the last device, jump to the step of selecting the target device; otherwise, end the device layout.
[0022] Preferably, the step of adjusting the package size includes:
[0023] Blank ratio calculation: Calculate the blank ratio as follows:
[0024] P space =S space / S valid
[0025] Where P space is the blank ratio, S valid is the available effective packaging area, S space It is the remaining area after finishing the device layout;
[0026] Package size acquisition: When the blank ratio is less than 10%, the expected package size is too small, increase the expected package size, and jump to the effective package area adjustment step; when the blank ratio is greater than 20%, the expected package size is too large, reduce the expected package size, and jump to the effective package area adjustment step; when the blank ratio is between 10% and 20%, the expected package size is moderate, take this expected package size as the estimated value of the system-level packaging circuit package size.
[0027] Compared with the prior art, the present invention has the following significant advantages:
[0028] 1. High estimation accuracy: The method of the present invention adopts a unified and definite rule in the process of layout of internal devices of the system-level packaging circuit. Under the same packaging requirements, different solutions will not be generated due to different estimation executors, thus avoiding the dependence on engineering experience of using traditional methods. Moreover, the method of the present invention can perform multiple iterations to enlarge or reduce the previous estimated size to gradually approach the optimal packaging design size, thus avoiding the situation where the traditional estimation method is used to artificially expand the packaging size to reduce the risk of change. The estimated size has high accuracy.
[0029] 2. High estimation efficiency: This method allows the use of programming means or simulation tools to automate the calculation method, judgment and layout process, thereby improving the efficiency of package size estimation.
[0030] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 It is the main flow chart of the system-level packaging circuit package size estimation method of the present invention.
[0032] Figure 2 yes Figure 1 Flowchart of the steps for adjusting the effective package area.
[0033] Figure 3 yes Figure 1 Flowchart of the device layout steps in .
[0034] Figure 4 is a schematic diagram of calculating different placement methods during device layout. Figure 4a Indicates that the target device is placed in a vertical position at the lower left corner of the remaining area; Figure 4b Indicates that the target device is placed in a vertical position at the lower right corner of the remaining area; Figure 4c Indicates that the target device is placed in a vertical position at the upper left corner of the remaining area; Figure 4d Indicates that the target device is placed in a vertical position at the upper left and right corners of the remaining area; Figure 4e Indicates that the target device is placed in the lower left corner of the remaining area in a lying position; Figure 4f Indicates that the target device is placed in the lower right corner of the remaining area in a lying position; Figure 4g Indicates that the target device is placed in the upper left corner of the remaining area in a lying position; Figure 4h Indicates that the target device is placed in the upper left and right corners of the remaining area in a lying position.
[0035] Figure 5 yes Figure 1 Flowchart of the steps for determining package dimensions. DETAILED DESCRIPTION
[0036] like Figure 1 As shown, the method for estimating the package size of a system-level package circuit of the present invention comprises the following steps:
[0037] S10, bare die layout size calculation: according to the bare die size and welding type, based on the margin control requirements, determine the total bare die layout size;
[0038] For example, for a flip-chip bare chip, a 0.5mm spacing should be reserved around the perimeter for bottom filling; for a wire-bonded bare chip, a 0.7mm gold wire bonding area should be reserved around the perimeter. The layout dimensions of all bare chips need to be calculated based on the size of each bare chip and the type of welding. For example, for a flip-chip bare chip with a size of L×W, the bare chip layout dimensions are determined as:
[0039] A layout=(L+(0.5×2))×(W+(0.5×2))
[0040] In the formula, A layout is the die layout size, L is the die length, and W is the die width.
[0041] S20, effective package area adjustment: according to the expected package shape and the package forbidden area, the effective package area is obtained, and according to the reasonableness judgment rule of the effective package area, the expected package shape size is adjusted to obtain the available effective package area;
[0042] like Figure 2 As shown, the effective packaging area adjustment step S20 includes:
[0043] S21. Determine the effective packaging area: subtract the forbidden packaging area from the expected packaging shape to obtain a rectangular effective packaging area.
[0044] For example, for a circuit with an expected package size of L×W, if the cover requires a keep-out area with a width of D to be set around the substrate, then the area of the rectangular effective package area is:
[0045] A valid =(L-(D×2))×(W-(D×2))
[0046] In the formula, A valid is the effective package area, L is the expected package outline length, W is the expected package outline width, and D is the forbidden width.
[0047] The first side length of the rectangular effective packaging area is: L-(D×2);
[0048] The second side length of the rectangular effective packaging area is: W-(D×2).
[0049] S22, judging the rationality of the effective encapsulation area: judging whether the rationality judgment rule of the effective encapsulation area is satisfied at the same time according to the area, the first side length and the second side length of the effective encapsulation area;
[0050] The rationality judgment rules of the effective packaging area include:
[0051] 221. Total area judgment rule: The effective packaging area must be larger than the sum of all bare chip layout areas;
[0052] 222. The first side length judgment rule: one of the sides of the effective packaging area must be greater than the larger side length of the maximum bare chip layout size;
[0053] 223. Second side length judgment rule: The other side length of the effective packaging area must be greater than the sum of the smaller side lengths of the largest bare chip layout and the second largest bare chip layout.
[0054] S23, obtaining the available effective package area: when any of the area, the first side length, and the second side length of the effective package area does not meet the reasonableness judgment rule of the effective package area, adjusting the corresponding size of the expected package shape to obtain a new expected package shape, and jumping to S21, determining the effective package area step;
[0055] When the area, the first side length and the second side length of the effective packaging area simultaneously satisfy the effective packaging area rationality judgment rule, the effective packaging area is determined as an available effective packaging area.
[0056] S30, device layout: Place bare chips and resistor and capacitor devices in the available effective packaging area in the order from large to small and according to the method of the remaining maximum rectangular area;
[0057] like Figure 3 As shown, the step S30, device layout step includes:
[0058] S31, selecting a target device: selecting a device with the largest size from the devices that have not been placed as the target device;
[0059] S32, determining the area to be placed: calculating the maximum rectangular position of the remaining area of the available effective packaging area to obtain the area to be placed;
[0060] S33, calculating the remaining area of the placement method: placing the target device in different postures along the four corners of the area to be placed, and calculating the remaining area and side length of each placement method;
[0061] The principle of calculating different placement methods is shown in FIG4 . The eight methods of the target device are shown in the dotted box, the maximum remaining area of different placement methods is shown in the shaded diagonal area, and the second largest remaining area is shown in the shaded grid area.
[0062] in, Figure 4a Indicates that the target device is placed in a vertical position at the lower left corner of the remaining area;
[0063] Figure 4b Indicates that the target device is placed in a vertical position at the lower right corner of the remaining area;
[0064] Figure 4c Indicates that the target device is placed in a vertical position at the upper left corner of the remaining area;
[0065] Figure 4d Indicates that the target device is placed in a vertical position at the upper left and right corners of the remaining area;
[0066] Figure 4e Indicates that the target device is placed in the lower left corner of the remaining area in a lying position;
[0067] Figure 4f Indicates that the target device is placed in the lower right corner of the remaining area in a lying position;
[0068] Figure 4g Indicates that the target device is placed in the upper left corner of the remaining area in a lying position;
[0069] Figure 4h Indicates that the target device is placed in the upper left and right corners of the remaining area in a lying position. Figure 4a , 4b , Figure 4c , Figure 4d , Figure 4e , Figure 4f , Figure 4g and Figure 4h It can be seen that Figure 4e and Figure 4f The largest remaining area in the Figure 4e The middle and second largest residual areas are larger.
[0070] S34, selecting a placement method: selecting the placement method with the largest remaining area as the selected placement method; if the areas of the largest remaining areas of two placement methods are the same, selecting the placement method with the largest remaining area closer to a square as the selected placement method; if the areas of the largest remaining areas of two placement methods are the same and have the same shape, selecting the placement method with the second largest remaining area as the selected placement method;
[0071] S35, placing the target device: placing the target device in the to-be-placed area according to the selected placement method; if the target device is not the last device, jump to S31, select the target device step; otherwise, end the device layout.
[0072] S40, package size determination: divide the remaining area after device layout by the available effective package area to obtain a blank ratio, and evaluate and adjust the expected package size based on the blank ratio and package size judgment rules to obtain an estimated value of the system-level package circuit package size.
[0073] If the evaluation result shows that the expected package size is too small or too large, the expected package size is increased or decreased accordingly, and the process jumps to S20, the effective package area adjustment step;
[0074] If the evaluation result shows that the expected package size is moderate, then the expected package size is taken as the estimated value of the required SIP circuit package size.
[0075] The package size judgment rules and corresponding adjustment strategies include:
[0076] 41. The blank ratio is less than 10%, the package size is too small, increase the package size;
[0077] 42. The blank ratio is between 10% and 20%, and the package size is moderate. This package size is taken as the estimated value of the SIP circuit package size;
[0078] 43. The blank ratio is greater than 20%, and the package dimensions are too large. Reduce the package dimensions.
[0079] like Figure 5 As shown, the step of adjusting the package dimensions in S40 includes:
[0080] S41. Blank ratio calculation: Calculate the blank ratio as follows:
[0081] P space =S space / S valid
[0082] Where P space is the blank ratio, S valid is the available effective packaging area, S space It is the remaining area after finishing the device layout;
[0083] S42, package dimensions acquisition:
[0084] When the blank ratio is less than 10%, the expected package size is too small, the expected package size is increased, and the process jumps to S20, the effective package area adjustment step;
[0085] When the blank ratio is greater than 20%, the expected package size is too large, and the expected package size is reduced, and the process jumps to S20, the effective package area adjustment step;
[0086] When the blank ratio is between 10% and 20%, the expected package size is moderate, and this expected package size is taken as the estimated value of the system-level package circuit package size.
Claims
1. A method for estimating the package size of a system-level package circuit, characterized in that: The steps include: Die layout size calculation: Determine the total die layout size based on the die size and soldering type and margin control requirements; Adjustment of effective package area: According to the expected package shape and the package forbidden area, the effective package area is obtained. According to the rationality judgment rules of the effective package area, the expected package shape size is adjusted to obtain the available effective package area; Device layout: Place bare chips and resistor and capacitor devices in the available effective packaging area in descending order and using the remaining maximum rectangular area method; Determine the package size: divide the remaining area after device layout by the available effective package area to get the blank ratio. Based on the blank ratio and the package size judgment rules, evaluate and adjust the expected package size to get the estimated value of the system-level package circuit package size.
2. The package size estimation method according to claim 1, characterized in that: The effective packaging area adjustment step comprises: Determine the effective package area: subtract the package forbidden area from the expected package shape to obtain the rectangular effective package area; Reasonableness judgment of effective encapsulation area: judge whether the reasonableness judgment rules of effective encapsulation area are met at the same time according to the area, first and second side lengths of the effective encapsulation area; Obtaining the available effective packaging area: when any of the area, the first and the second side lengths of the effective packaging area do not meet the reasonableness judgment rules of the effective packaging area, adjust the corresponding dimensions of the expected packaging shape to obtain a new expected packaging shape, and jump to the step of determining the effective packaging area; when the area, the first and the second side lengths of the effective packaging area simultaneously meet the reasonableness judgment rules of the effective packaging area, determine the effective packaging area as the available effective packaging area.
3. The package size estimation method according to claim 2, characterized in that: The rationality judgment rules of the effective packaging area include: Total area judgment rule: The effective package area must be larger than the sum of all bare chip layout areas; The first side length judgment rule: one of the sides of the effective packaging area must be greater than the larger side length of the maximum bare chip layout size; Second side length judgment rule: the other side length of the effective packaging area must be greater than the sum of the smaller side lengths of the largest bare chip layout and the second largest bare chip layout.
4. The package size estimation method according to claim 1, characterized in that: The device layout step comprises: Select target device: select the device with the largest size from the devices that have not been placed as the target device; Determine the area to be placed: calculate the maximum rectangular position of the remaining area of the available effective packaging area to obtain the area to be placed; Calculate the remaining area of the placement method: Place the target device in different postures along the four corners of the area to be placed, and calculate the remaining area and side length of various placement methods; Selected placement method: The placement method with the largest remaining area is selected as the selected placement method. If the areas of the largest remaining areas of two placement methods are the same, the placement method with the largest remaining area closer to a square is selected as the selected placement method. If the areas of the largest remaining areas of two placement methods are the same and have the same shape, the placement method with the second largest remaining area is selected as the selected placement method. Place the target device: place the target device in the to-be-placed area according to the selected placement method; if the target device is not the last device, jump to the step of selecting the target device; otherwise, end the device layout.
5. The package size estimation method according to claim 1, characterized in that: The step of adjusting the package size comprises: Blank ratio calculation: Calculate the blank ratio as follows: P space =S space / S valid Where P space is the blank ratio, S valid is the available effective packaging area, S space It is the remaining area after finishing the device layout; Package size acquisition: When the blank ratio is less than 10%, the expected package size is too small, increase the expected package size, and jump to the effective package area adjustment step; when the blank ratio is greater than 20%, the expected package size is too large, reduce the expected package size, and jump to the effective package area adjustment step; when the blank ratio is between 10% and 20%, the expected package size is moderate, take this expected package size as the estimated value of the system-level packaging circuit package size.