Low redundancy rate image segmentation method and system based on FPGA

Abstract

The invention relates to the technical field of remote sensing image on-orbit real-time processing, in particular to a low-redundancy-rate image segmentation method and system based on an FPGA, and the method comprises the steps: determining the maximum physical size of a target object; calculating a first maximum pixel value occupied by the target type object in the remote sensing image according to the maximum physical size of the target type object; performing correction calculation on the maximum physical size according to the side-sway angle during satellite imaging to obtain the maximum physical size of the target object after side-sway distortion is considered; calculating a second maximum pixel value occupied by the target type object in the remote sensing image according to the maximum physical size of the target type object after side-sway distortion is considered; taking the maximum value from the first maximum pixel value and the second maximum pixel value as an overlapping region setting value; setting an overlapping region setting value as a sliding window segmentation step length; and carrying out sliding window segmentation on the segmented sub-graphs according to the sliding window segmentation step length. According to the method and the device, the minimization of the overlapped region of the segmented sub-images is realized, the segmentation redundancy rate is reduced, and the data storage and transmission quantity is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of on-orbit real-time processing of remote sensing images, and in particular to a low-redundancy image segmentation method and system based on FPGA. Background Art

[0002] With the development of remote sensing technology, the resolution of optical remote sensing images is constantly improving, and the amount of satellite remote sensing image data is also constantly expanding. The traditional remote sensing data processing process "satellite data acquisition-ground image reception-professional processing" has poor timeliness, takes a long time, and has a high pressure on data transmission. On-orbit processing can effectively alleviate these problems and can be used as an important development direction for future remote sensing data processing. However, the ultra-large format and high resolution characteristics of remote sensing images bring huge challenges to the processing on the satellite platform. A single image may contain hundreds of millions of pixels. Direct processing will bring a huge burden on the computing resources and storage space of the satellite platform. Therefore, it is necessary to segment it and then perform relevant processing based on the segmented sub-images. However, this process involves a lot of data handling and memory access work, which puts higher requirements on the management of computing resources and storage bandwidth. When traditional satellite-borne processing units (such as CPUs) carry out large-scale data handling, they are often limited by bus bandwidth and storage bottlenecks, resulting in low data processing efficiency and unable to meet the real-time requirements of efficient segmentation. Therefore, when performing image segmentation tasks on the satellite, there is an urgent need for a hardware solution that can provide both high data processing efficiency and low storage latency. FPGA (Field Programmable Gate Array) has become an ideal choice due to its low power consumption, high parallelism, and reconfigurability. FPGA can realize rapid processing of large amounts of image data through hardware-level parallel computing, and can flexibly configure hardware circuits according to specific application requirements, and efficiently implement complex image segmentation operations on the satellite platform. Therefore, applying FPGA to the segmentation task of satellite remote sensing images can significantly improve segmentation efficiency and data processing capabilities under limited hardware resources and strict power consumption constraints.

[0003] The segmentation process of remote sensing images refers to the process of segmenting remote sensing images into sub-images of the same size and resolution according to certain standards. However, during the segmentation process, since some target objects in the image are located on the segmentation grid line, they are easily segmented into two or even multiple parts, which affects the subsequent image processing. In order to solve this problem, a certain overlapping area is usually introduced between adjacent sub-images so that the target object can exist completely in at least one sub-image. However, the setting of the overlapping area directly determines the redundancy rate, which is obtained by dividing the total area of ​​the sub-image by the area of ​​the original remote sensing image. A high redundancy rate will increase the amount of data storage and calculation, thereby reducing the overall segmentation and processing efficiency; but simply pursuing a low redundancy rate to reduce the overlapping area may cause the target to be cut off during segmentation, which violates the original intention of setting the overlapping area. Most of the existing processing solutions set the overlapping area to 25%~30% of the sub-image size. Although setting the overlapping area in a fixed range can simplify the problem of area setting, the lack of specificity will lead to excessive redundancy or missed detection, thereby affecting the processing rate and effect. Therefore, there is an urgent need to provide an innovative remote sensing image segmentation method so as to minimize the redundancy rate while ensuring that no target is missed, thereby ensuring the optimal efficiency of the overall operation. Summary of the invention

[0004] This application aims to solve the problem in the prior art that the overlapping area setting in the large-format remote sensing image segmentation process lacks pertinence, which makes the redundancy rate unable to be optimized. At the same time, it adapts to the application technology scenarios of on-board image processing and proposes a low-redundancy image segmentation method based on FPGA.

[0005] On the other hand, the present application provides a low-redundancy image segmentation system based on FPGA.

[0006] The implementation process of this application method is as follows: A low redundancy rate image segmentation method based on FPGA, the method comprising: Determine the maximum physical size of the target class object; Calculate a first maximum pixel value occupied by the target object in the remote sensing image according to the maximum physical size of the target object, wherein the first maximum pixel value includes a maximum pixel value in length and a maximum pixel value in width; The maximum physical size is corrected and calculated according to the roll angle during satellite imaging, and the maximum physical size of the target object after considering the roll distortion is obtained; Calculate a second maximum pixel value occupied by the target object in the remote sensing image according to the maximum physical size of the target object after considering the roll distortion, wherein the second maximum pixel value includes a maximum pixel value in length and a maximum pixel value in width; Taking the maximum value from the first maximum pixel value and the second maximum pixel value as the overlapping area setting value; Set the overlapping area setting value to the sliding window segmentation step size; The remote sensing image is divided into a plurality of square segmentation sub-images of the same size arranged in a row and column array; An FPGA module is used to perform sliding window segmentation on the segmented sub-images according to the sliding window segmentation step size. The sliding window segmentation includes: horizontal segmentation and vertical segmentation. Two groups of RAM modules are used to alternately store the intermediate results of each row of segmented sub-images in the sliding window segmentation process. The number of RAM modules in each group of RAM modules is the same as the number of segmented sub-images in each row. The segmented sub-image data in the same row are stored using one group of RAM modules, and the segmented sub-image data of two adjacent rows are stored using different groups of RAM modules.

[0007] Furthermore, before dividing the remote sensing image into multiple square segmentation sub-images of the same size arranged in a row and column array, the remote sensing image to be segmented is padded so that the size of the segmentation sub-images is consistent, ensuring that the segmentation sub-image data in each row during horizontal segmentation is allocated to multiple RAM modules arranged in storage order in each group of RAM modules.

[0008] Furthermore, when sliding window segmentation is performed on a remote sensing image, horizontal segmentation is first performed, starting from the segmentation sub-image of the first row of the remote sensing image, and the segmentation sub-images in the same row are segmented according to pixel rows. The segmentation sub-image data in the same row are written sequentially into each RAM module in a group of RAM modules, and the data corresponding to the overlapping area between two adjacent segmentation sub-images in the same pixel row are simultaneously written into the two RAM modules corresponding to the two segmentation sub-images.

[0009] Furthermore, when a group of RAM modules completes the storage of a row of segmented sub-image data, data is read from the RAM modules and a write operation is performed to store data in the DDR module. After the write operation is completed, the current group of RAM modules is cleared.

[0010] Furthermore, in the horizontal segmentation, the segmentation sub-image of a row is not completely segmented, and when the pixel rows of the overlapping area are segmented, the segmentation sub-image data in each pixel row of the overlapping area are written into a group of RAM modules corresponding to the segmentation sub-image of the current row, and at the same time, are written into another group of RAM modules corresponding to the segmentation sub-image of the next adjacent row, and so on, to complete the vertical segmentation.

[0011] Furthermore, the first maximum pixel value is calculated as: , , Where: and are the pixel values ​​of the maximum physical length and maximum physical width of the target object in the remote sensing image, and They are the maximum physical length and maximum physical width of the target object, respectively. GSD represents the imaging payload resolution. The maximum physical size of the target object after considering the sway distortion is calculated as: , , in and are the maximum physical length and maximum physical width of the target object after sway distortion, It represents the side swing angle of satellite imaging; The second largest pixel value is calculated as: , , in and They are the pixel values ​​of the maximum physical length and maximum physical width of the target object in the remote sensing image after side-sway distortion.

[0012] Further, taking the maximum value from the first maximum pixel value and the second maximum pixel value as the overlapping area setting value includes: , in It represents the overlapping area setting value, and max[ ] represents the maximum value operation.

[0013] A low redundancy rate image segmentation system based on FPGA includes an FPGA module, a RAM module and a DDR module, wherein: The FPGA module is used to receive remote sensing image data and store the remote sensing image data in the DDR module. When the remote sensing image needs to be processed, the image data is read out from the DDR module, and the segmentation sub-image is segmented according to the set sliding window segmentation step size and the size of the segmentation sub-image; the segmentation sub-image data obtained during the segmentation process is temporarily stored in the RAM module, and is stored again in the DDR module after the segmentation is completed; The RAM module includes two groups of RAM modules, which alternately store the intermediate results of each row of segmented sub-images in the sliding window segmentation process. The number of RAM modules in each group of RAM modules is the same as the number of segmented sub-images in each row. The segmented sub-image data in the same row are stored using one group of RAM modules, and the segmented sub-image data of two adjacent rows are stored using different groups of RAM modules respectively. When a group of RAM modules completes the storage of a row of segmented sub-image data, the data is read from the RAM modules and stored in the DDR module for write operation. After the write operation is completed, the current group of RAM modules is cleared.

[0014] Compared with the prior art, the present application has the following beneficial effects: the present application determines the step size parameter of the sliding window segmentation by calculating the pixel value occupied by the detection target object in the remote sensing image, thereby minimizing the image segmentation overlap area while ensuring the detection accuracy. Compared with the method of retaining 20% ​​overlap area without considering the purpose of the task, the redundancy rate can be effectively reduced; compared with the method of obtaining a reasonable overlap area by statistically analyzing the target detection frame after marking the detection target, the present application is more robust and simpler.

[0015] The method of the present application achieves minimization of the overlapping area of ​​the segmented sub-images by precisely controlling the size of the sliding window overlapping area, effectively reducing the segmentation redundancy rate and significantly reducing the amount of data storage and transmission. At the same time, the hardware architecture of dual-group RAM alternating storage based on FPGA can realize efficient segmentation sub-image storage and real-time processing in the process of low-redundancy image segmentation, and realize dynamic management and synchronous writing of overlapping area data, thereby avoiding the data bandwidth bottleneck and resource waste caused by repeated storage in the method based on CPU architecture. Under the premise of ensuring segmentation accuracy, this method realizes more efficient satellite image segmentation, has the advantages of low redundancy, high energy efficiency and strong real-time performance, and is very suitable for real-time remote sensing image processing tasks in satellite environments.

[0016] The FPGA of this application will write the data of the overlapping area in parallel to ensure the data consistency of the overlapping area between adjacent sub-images in the same row. Similarly, when sliding the window vertically, two sets of RAM modules are used for alternating storage, so that the overlapping areas of different sub-images can be managed simultaneously, avoiding repeated calculation and storage of redundant data. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present application will become easy to understand. In the accompanying drawings, several embodiments of the present application are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein: Figure 1 A flow chart of a low-redundancy image segmentation method based on FPGA provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0019] In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more than two.

[0020] First, let me explain the technical terms: (1) FPGA: Field Programmable Gate Array; (2) RAM: Random-access memory; (3) DDR: Double Data Rate, specifically DDR Synchronous Dynamic Random Access Memory, such as DDR3 (or DDR4) SDRAM.

[0021] The specific embodiment of the present application takes a wide-format original remote sensing image as an example, whose size is 16290 pixel rows × 2528 pixel columns, the resolution is 5m, the imaging side swing range is ±25°, the size of the segmented sub-image is 640 pixel rows × 640 pixel columns, and the detection target is selected as a military ship.

[0022] Figure 1 This is a flow chart of a low-redundancy image segmentation method based on FPGA provided in an embodiment of the present application. It includes: The first step is to determine the maximum physical size of the target class object. This application can be directly applied to subsequent image processing tasks such as image classification and target detection. The target to be processed can be one or more types of objects in related tasks, such as ships, vehicles, aircraft, etc. The key is to determine the maximum physical size of the target class. For example, taking military ships as an example of the detection target, aircraft carriers are the largest military ships. The Ford-class aircraft carrier, the largest aircraft carrier in the world, is 337 meters long and 78 meters wide. Its length value is used as the maximum value of the actual size referenced by the sliding window step length parameter.

[0023] The first maximum pixel value occupied by the target object in the remote sensing image is calculated according to the maximum physical size of the target object. After calculation, the number of pixels occupied by the object used as an example in this embodiment is rounded up to 68.

[0024] Consider the image deformation caused by the attitude changes (such as yaw, pitch and roll) of the satellite during the shooting process, and calculate the pixel changes caused by these situations. Determine the maximum side swing angle that may occur in the sensor during the imaging process, and calculate the second maximum pixel value of the target object in the remote sensing image based on the maximum physical size of the target object after considering the side swing distortion. The second maximum pixel value includes the maximum pixel value in length and the maximum pixel value in width. Take the maximum value from the first maximum pixel value and the second maximum pixel value as the overlapping area setting value; set the overlapping area setting value as the sliding window segmentation step size to ensure low redundancy image segmentation at the FPGA hardware level. The step size will be written into the FPGA configuration file by burning, and is used to control the sliding window operation of the subsequent image segmentation process.

[0025] The calculation of the first maximum pixel value is: , , Where: and are the pixel values ​​of the maximum physical length and maximum physical width of the target object in the remote sensing image, and They are the maximum physical length and maximum physical width of the target object, respectively. GSD represents the imaging payload resolution. The maximum physical size of the target object after considering the sway distortion is calculated as: , , in and are the maximum physical length and maximum physical width of the target object after sway distortion, It represents the side swing angle of satellite imaging; The second largest pixel value is calculated as: , , in and They are the pixel values ​​of the maximum physical length and maximum physical width of the target object in the remote sensing image after side-sway distortion.

[0026] Taking a maximum value from the first maximum pixel value and the second maximum pixel value as the overlap area setting value includes: , in It represents the overlapping area setting value, and max[ ] represents the maximum value operation.

[0027] For example, considering the side swing angle of 25°, it can be seen that the length after distortion is 338.39m and the width is 213.11m. The maximum value is still the length value, so the length value is still used as the maximum scale. The number of pixels occupied after calculation is rounded up to 68, which is the same as the number of pixels occupied before distortion, so 68 pixels is used as the sliding window segmentation step.

[0028] The remote sensing image is divided into a plurality of square segmentation sub-images of the same size arranged in a row and column array; An FPGA module is used to perform sliding window segmentation on the segmented sub-images according to the sliding window segmentation step size. The sliding window segmentation includes: horizontal segmentation and vertical segmentation. Two groups of RAM modules are used to alternately store the intermediate results of each row of segmented sub-images in the sliding window segmentation process. The number of RAM modules in each group of RAM modules is the same as the number of segmented sub-images in each row. The segmented sub-image data in the same row are stored using one group of RAM modules, and the segmented sub-image data of two adjacent rows are stored using different groups of RAM modules.

[0029] Before dividing the remote sensing image into multiple square segmentation sub-images of the same size arranged in a row and column array, the remote sensing image to be segmented is filled to make the segmentation sub-images of the same size, ensuring that the segmentation sub-image data in each row during horizontal segmentation is allocated to multiple RAM modules arranged in a storage order in each group of RAM modules.

[0030] For example, during the segmentation process, 5×2 RAM modules are used to jointly complete the horizontal segmentation and vertical segmentation processes. The RAM modules are divided into two groups. The first group of RAM modules is represented by the RAM_0 group. The RAM modules in the first group of RAM modules are marked as RAM_0.0 to RAM_0.5 respectively. The second group of RAM modules is represented by the RAM_1 group. The RAM modules in the second group of RAM modules are marked as RAM_1.0 to RAM_1.5 respectively. The two groups of RAM modules are stored alternately to jointly complete the storage process.

[0031] The first is horizontal segmentation, starting from the segmentation sub-image of the first row of the remote sensing image, and segmenting the segmentation sub-image in the same row according to pixel rows. The segmentation sub-image data in the same row are written into each RAM module in a group of RAM modules in sequence, and the data corresponding to the overlapping area between two adjacent segmentation sub-images in the same pixel row are written into the two RAM modules corresponding to the two segmentation sub-images at the same time.

[0032] For example, starting from the upper left corner of the original remote sensing image, that is, the first row, it can be understood that there is no limitation on the selection of the diagonal corner. The row here refers to the row formed by the segmentation sub-image after the remote sensing image is divided into rows and columns, that is, the row where the picture is located. The segmentation sub-image is represented by (x, y), where x represents the row number of the segmentation sub-image and y represents the column number. The segmented sub-image data obtained after the first segmentation is written into the RAM_0 group, that is, the first row of segmented sub-image data. For example, the first row of segmented sub-images performs data processing of 640 pixel rows in sequence. In the first pixel row, the data of pixels (1,1) to pixels (1,572) are written into RAM_0.0 in sequence as the pixels of the first segmented sub-image in the first pixel row. Pixels (1,573) to pixels (1,640) are the overlapping areas of the (1,1) segmented sub-image and the (1,2) segmented sub-image in the first pixel row in the horizontal window sliding process of the first pixel row. These 68 pixel data are written into RAM_0.0 at the same time as they are written into RAM_0.1 in parallel. RAM_0.1 corresponds to the (1,2) segmented sub-image. The parallel processing of the overlapping data of the horizontal sliding window is realized; the sliding window segmentation continues to the right, and the data of pixels (1,641) to pixels (1,1212) are written to RAM_0.1. The overlapping area pixels (1,1213) to pixels (1,1280) are operated in the same way as in the previous step, and are written to RAM_0.1 and RAM_0.2 at the same time, and so on, until the horizontal overlapping sliding window segmentation of all pixels in the first pixel row is completed. The horizontal segmentation of each pixel row is performed in the same way, and the results are stored in the RAM module data. After completing the cutting and storage of 640 pixel rows, the first group of RAM modules completes the storage of the first row of segmented sub-images, and will start the read operation from RAM and the write operation to DDR storage. After the write operation is completed, the RAM_0 group is cleared.

[0033] The second is vertical segmentation. In horizontal segmentation, if the segmentation sub-image of a row is not completed, and when the pixel rows of the overlapping area are segmented, the segmentation sub-image data in each pixel row of the overlapping area is written into a group of RAM modules corresponding to the segmentation sub-image of the current row, and is also written into another group of RAM modules corresponding to the segmentation sub-image of the next adjacent row in parallel, and so on, the vertical segmentation is completed; For example, when the first row of segmented sub-images is not segmented, when the horizontal segmentation reaches the 573rd pixel row, that is, when the overlapping area begins, the segmented sub-image data is written into the RAM_0 group and written into the RAM_1 group in parallel, as the data of the first 68 pixels of the next row of segmented sub-images, completing the overlapping part of the vertical segmentation. When the horizontal segmentation reaches the 1145th pixel row, the segmented sub-image data is written into the RAM_0 group in parallel. After the segmentation of the first row of segmented sub-images is completed, the RAM_0 group has cleared the data to zero, as the first 68 pixel data of the third row of segmented sub-images. The vertical segmentation is completed by analogy. When the sliding window is cut to the bottom of the remote sensing image, if the data is not enough, the corresponding address data in the RAM module is set to 0. By analogy, the horizontal segmentation and vertical segmentation sliding window operation processes are repeated until the sliding window segmentation of the entire original remote sensing image is completed and written to the external DDR module for storage; so far, all processes of low-redundancy overlapping sliding window segmentation of 16290 rows × 2528 columns of original remote sensing images based on FPGA are realized.

[0034] The present application provides a low-redundancy image segmentation system based on FPGA, including an FPGA module, a RAM module and a DDR module, wherein: The FPGA module is used to receive remote sensing image data and store the remote sensing image data in the DDR module. When the remote sensing image needs to be processed, the image data is read out from the DDR module, and the segmentation sub-image is segmented according to the set sliding window segmentation step size and the size of the segmentation sub-image; the segmentation sub-image data obtained during the segmentation process is temporarily stored in the RAM module, and is stored again in the DDR module after the segmentation is completed; The RAM module includes two groups of RAM modules, which alternately store the intermediate results of each row of segmented sub-images in the sliding window segmentation process. The number of RAM modules in each group of RAM modules is the same as the number of segmented sub-images in each row. The segmented sub-image data in the same row are stored using one group of RAM modules, and the segmented sub-image data of two adjacent rows are stored using different groups of RAM modules respectively. When a group of RAM modules completes the storage of a row of segmented sub-image data, the data is read from the RAM modules and stored in the DDR module for write operation. After the write operation is completed, the current group of RAM modules is cleared.

[0035] FPGA-based image segmentation can achieve low-redundancy and efficient remote sensing image segmentation tasks on satellite-borne platforms.

[0036] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present application in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits and programmable logic controllers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present application can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

Claims

1. A low redundancy image segmentation method based on FPGA, characterized in that: The method includes: Determine the maximum physical size of the target class object; Calculate a first maximum pixel value occupied by the target object in the remote sensing image according to the maximum physical size of the target object, wherein the first maximum pixel value includes a maximum pixel value in length and a maximum pixel value in width; The maximum physical size is corrected and calculated according to the roll angle during satellite imaging, and the maximum physical size of the target object after considering the roll distortion is obtained; Calculate a second maximum pixel value occupied by the target object in the remote sensing image according to the maximum physical size of the target object after considering the roll distortion, wherein the second maximum pixel value includes a maximum pixel value in length and a maximum pixel value in width; Taking the maximum value from the first maximum pixel value and the second maximum pixel value as the overlapping area setting value; Set the overlapping area setting value to the sliding window segmentation step size; The remote sensing image is divided into a plurality of square segmentation sub-images of the same size arranged in a row and column array; An FPGA module is used to perform sliding window segmentation on the segmented sub-images according to the sliding window segmentation step size. The sliding window segmentation includes: horizontal segmentation and vertical segmentation. Two groups of RAM modules are used to alternately store the intermediate results of each row of segmented sub-images in the sliding window segmentation process. The number of RAM modules in each group of RAM modules is the same as the number of segmented sub-images in each row. The segmented sub-image data in the same row are stored using one group of RAM modules, and the segmented sub-image data of two adjacent rows are stored using different groups of RAM modules.

2. The low redundancy rate image segmentation method based on FPGA according to claim 1, characterized in that: Before dividing the remote sensing image into multiple square segmentation sub-images of the same size arranged in a row and column array, the remote sensing image to be segmented is filled to make the segmentation sub-images of the same size, ensuring that the segmentation sub-image data in each row during horizontal segmentation is allocated to multiple RAM modules arranged in a storage order in each group of RAM modules.

3. The low redundancy rate image segmentation method based on FPGA according to claim 1, characterized in that: When performing sliding window segmentation on a remote sensing image, horizontal segmentation is performed first, starting from the segmentation sub-image of the first row of the remote sensing image, and the segmentation sub-images in the same row are segmented according to pixel rows. The segmentation sub-image data in the same row are written sequentially into each RAM module in a group of RAM modules, and the data corresponding to the overlapping area between two adjacent segmentation sub-images in the same pixel row are simultaneously written into the two RAM modules corresponding to the two segmentation sub-images.

4. The low redundancy rate image segmentation method based on FPGA according to claim 3, characterized in that: When a group of RAM modules completes the storage of a row of segmented sub-image data, the data is read from the RAM modules and stored in the DDR module for write operation. After the write operation is completed, the current group of RAM modules is cleared.

5. The low redundancy rate image segmentation method based on FPGA according to claim 3, characterized in that: In horizontal segmentation, if the segmentation sub-image of a row is not completed, and when segmenting the pixel rows of the overlapping area, the segmentation sub-image data in each pixel row of the overlapping area is written into a group of RAM modules corresponding to the segmentation sub-image of the current row, and at the same time, it is written into another group of RAM modules corresponding to the segmentation sub-image of the next adjacent row in parallel, and so on, to complete the vertical segmentation.

6. The low redundancy rate image segmentation method based on FPGA according to claim 1, characterized in that: The calculation of the first maximum pixel value is: ， ， Where: and are the pixel values ​​of the maximum physical length and maximum physical width of the target object in the remote sensing image, and They are the maximum physical length and maximum physical width of the target object, respectively. GSD represents the imaging payload resolution. The maximum physical size of the target object after considering the sway distortion is calculated as: ， ， in and are the maximum physical length and maximum physical width of the target object after sway distortion, It represents the side swing angle of satellite imaging; The second largest pixel value is calculated as: ， ， in and They are the pixel values ​​of the maximum physical length and maximum physical width of the target object in the remote sensing image after side-sway distortion.

7. The low redundancy rate image segmentation method based on FPGA according to claim 6, characterized in that: Taking a maximum value from the first maximum pixel value and the second maximum pixel value as the overlap area setting value includes: ， in It represents the overlapping area setting value, and max[ ] represents the maximum value operation.

8. A low redundancy rate image segmentation system based on FPGA, used to implement the low redundancy rate image segmentation method according to any one of claims 1 to 7, characterized in that: It includes FPGA module, RAM module and DDR module, among which: The FPGA module is used to receive remote sensing image data and store the remote sensing image data in the DDR module. When the remote sensing image needs to be processed, the image data is read out from the DDR module, and the segmentation sub-image is segmented according to the set sliding window segmentation step size and the size of the segmentation sub-image; the segmentation sub-image data obtained during the segmentation process is temporarily stored in the RAM module, and is stored again in the DDR module after the segmentation is completed; The RAM module includes two groups of RAM modules, which alternately store the intermediate results of each row of segmented sub-images in the sliding window segmentation process. The number of RAM modules in each group of RAM modules is the same as the number of segmented sub-images in each row. The segmented sub-image data in the same row are stored using one group of RAM modules, and the segmented sub-image data of two adjacent rows are stored using different groups of RAM modules respectively. When a group of RAM modules completes the storage of a row of segmented sub-image data, the data is read from the RAM modules and stored in the DDR module for write operation. After the write operation is completed, the current group of RAM modules is cleared.

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