Slew rate enhancement at source amplifier input

Abstract

A display driver includes a plurality of gamma bus lines and a driving branch configured to receive pixel data. The drive branch includes a decoder having a first output and a second output, a source amplifier having a set of inputs, and a source interpolation selector. A decoder electrically connects a first output to a first one of the gamma bus lines and a second output to a second one of the gamma bus lines based on pixel data. The source amplifier provides a data voltage to the display panel based on a set of input voltages at the input set. The source interpolation selector provides an electrical connection between the first and second outputs of the decoder and the input set of the source amplifier based on the pixel data, and electrically connects the first and second outputs of the decoder during a first period of the horizontal synchronization period.

Description

Technical Field

[0001] The present disclosure relates generally to apparatus and methods for driving display panels, and more particularly to slew rate improvement at a source amplifier input. Background Art

[0002] A display driver of a panel display device (such as a liquid crystal display (LCD) device, an organic light emitting diode (OLED) display device, and a micro light emitting diode (μLED) display device) can use a source amplifier to drive a source line of a display panel. In a typical implementation, the source amplifiers can each be configured to receive one or more gamma voltages selected by a decoder based on pixel data and generate a data voltage corresponding to the pixel data from the received one or more gamma voltages. The data voltage generated by the source amplifier can be output to a source line of the display panel and then provided to a selected pixel of the display panel to update or program the pixel.

[0003] Due to the recent increase in display resolution and frame rate of panel display devices, reduced settling time may be an issue with respect to source amplifiers. The settling time referred to herein is the time required for the output to reach and remain within a given error band after a certain input stimulus. Reducing the settling time of the source amplifier may increase the operating speed of the display driver, and thus the source amplifier may be designed to shorten the settling time. Summary of the invention

[0004] This summary is provided to introduce a selection of concepts that are further described below in a simplified form. This summary is not intended to necessarily identify key features or essential features of the present disclosure. The present disclosure may include the following various aspects and embodiments.

[0005] In an exemplary embodiment, the present disclosure provides a display driver, which includes: a plurality of gamma bus lines, on which a plurality of gamma voltages are generated; and a driving branch configured to receive first pixel data and a plurality of gamma voltages. The driving branch includes a decoder, a source amplifier, and a source interpolation selector. The decoder has a first output and a second output and is configured to: electrically connect the first output to a first gamma bus line among a plurality of gamma bus lines based on the first pixel data; and electrically connect the second output to a second gamma bus line among a plurality of gamma bus lines based on the first pixel data. The source amplifier has an input set and is configured to provide a data voltage to a display panel based on an input voltage set at the input set. The source interpolation selector is configured to provide an electrical connection between the first output and the second output of the decoder and the input set of the source amplifier based on the first pixel data. The source interpolation selector is further configured to electrically connect the first output and the second output of the decoder during the first cycle of the horizontal synchronization cycle.

[0006] In another exemplary embodiment, the present disclosure provides a display device, which includes a display panel and a display driver. The display driver includes: a plurality of gamma bus lines, on which a plurality of gamma voltages are generated respectively; and a driving branch, which is configured to receive first pixel data and a plurality of gamma voltages. The driving branch includes a decoder, a source amplifier, and a source interpolation selector. The decoder has a first output and a second output and is configured to: electrically connect the first output to a first gamma bus line among a plurality of gamma bus lines based on the first pixel data; and electrically connect the second output to a second gamma bus line among a plurality of gamma bus lines based on the first pixel data. The source amplifier has an input set and is configured to provide a data voltage to the display panel based on an input voltage set at the input set. The source interpolation selector is configured to provide an electrical connection between the first output and the second output of the decoder and the input set of the source amplifier based on the first pixel data. The source interpolation selector is further configured to electrically connect the first output and the second output of the decoder during the first cycle of the horizontal synchronization cycle.

[0007] In another exemplary embodiment, the present disclosure provides a method. The method includes generating multiple gamma voltages on multiple gamma bus lines, respectively. The method also includes: electrically connecting a first output of the decoder to a first gamma bus line among multiple gamma bus lines based on first pixel data provided to the decoder; and electrically connecting a second output of the decoder to a second gamma bus line among multiple gamma bus lines based on the first pixel data. The method also includes electrically connecting the first output and the second output of the decoder during a first cycle of a horizontal synchronization cycle. The method also includes electrically connecting the first output and the second output of the decoder to an input set of a source amplifier based on the first pixel data during a second cycle of the horizontal synchronization cycle, the second cycle being after the first cycle. The method also includes providing a data voltage to a display panel by a source amplifier based on an input voltage set at the input set during the first cycle and the second cycle.

[0008] Additional features and aspects are described in more detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example partial configuration of a display driver including a source amplifier is shown.

[0010] Figure 2 An example configuration of a panel display device according to one or more embodiments is shown.

[0011] Figure 3A An example partial configuration of a display driver according to one or more embodiments is shown.

[0012] Figure 3BAn example configuration of a gamma voltage generator according to one or more embodiments is shown.

[0013] Figure 4 An example configuration of a driver branch according to one or more embodiments is shown.

[0014] Figure 5 Example operations of a driver circuit according to one or more embodiments are shown.

[0015] Figure 6 is a schematic diagram illustrating an example operation of a driver circuit according to one or more embodiments.

[0016] Figure 7 is an equivalent circuit diagram of selected gamma bus lines according to one or more embodiments.

[0017] Figure 8 is a schematic diagram illustrating an example operation of a driver circuit according to one or more embodiments.

[0018] Fig. 9 An example configuration of a display driver according to other embodiments is shown.

[0019] Fig.10 is a flow chart of an exemplary process for driving a display panel according to one or more embodiments.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific narration. Suffixes may be appended to reference numerals to distinguish identical elements from one another. Unless specifically noted, the drawings mentioned herein should not be understood to be drawn to scale. Likewise, drawings are usually simplified and details or components are omitted for clarity of presentation and explanation. The drawings and discussion are used to explain the principles discussed below, wherein the same names refer to the same elements. DETAILED DESCRIPTION

[0021] The following specific embodiments are exemplary in nature and are not intended to limit the present disclosure or the application and use of the present disclosure. In addition, it is not intended to be bound by any express or implied theory presented in the above background technology, invention content and accompanying drawings or the following specific embodiments.

[0022] In the following detailed description, many specific details are set forth to provide a more thorough understanding of the disclosed technology. However, it will be apparent to one of ordinary skill in the art that the disclosed technology can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating this description.

[0023] As used herein, the term "coupled" means directly connected to or connected through one or more intermediate components or circuits. In addition, throughout this application, ordinal numbers (e.g., first, second, third, etc.) can be used as adjectives of elements (i.e., any noun in this application). Unless (such as by using the terms "before", "after", "single" and other such terms) explicitly disclosed, the use of ordinal numbers is not intended to imply or create any specific ordering of elements, nor is it intended to limit any element to only a single element. On the contrary, the use of ordinal numbers is to be distinguished between elements. By way of example, the first element is distinct from the second element, and the first element can include more than one element and be after (or before) the second element in the ordering of the element.

[0024] As discussed above, due to the recent increase in display resolution and frame rate of panel display devices, the reduction in stabilization time may be an issue with respect to source amplifiers. Shortening the stabilization time of the source amplifier may increase the operating speed of the display driver, and thus the source amplifier may be designed to reduce the stabilization time.

[0025] The present disclosure recognizes that one way to shorten the settling time of a source amplifier is to improve or increase the slew rate at one or more inputs of the source amplifier. The slew rate referred to herein is the rate of voltage change per unit time. With a high slew rate at the input of the source amplifier, the voltage at the input of the source amplifier will quickly reach the desired voltage level when driven to the desired voltage level, resulting in a shortened settling time of the source amplifier. In the following, a description of the slew rate at the input of the source amplifier is first given.

[0026] Figure 1 FIG. 1 shows an example partial configuration of a display driver 100 including a source amplifier 120. Figure 1 In the configuration shown in , the decoder 110 is configured to select a gamma voltage from the gamma voltages generated by the gamma voltage generator 130 based on the pixel data and provide the selected gamma voltage to the source amplifier 120. The source amplifier 120 is configured to generate a data voltage from the selected gamma voltage and output the data voltage to a source output S[i] coupled to a pixel to be programmed.

[0027] The slew rate at the input of source amplifier 120 depends on the RC time constant of the input of source amplifier 120. Figure 1 In the configuration shown in , the RC time constant is the product of the input capacitance C_IN of the source amplifier 120 and the resistance of the path across which the selected gamma voltage from the gamma voltage generator 130 is provided to the input of the source amplifier 120. The path includes the gamma bus line 135, which provides the selected gamma voltage from the gamma voltage generator 130 to the decoder 110 and the switches coupled in series in the decoder 110. The resistance across the path is the sum of the resistance R_gamma across the gamma bus line 135 and the on-resistance R_ON of the decoder 110, where the on-resistance R_ON may be the sum of the on-resistances of the switches coupled in series of the decoder 110. The slew rate at the input of the source amplifier 120 can be increased by reducing the effective resistance of the path across which the selected gamma voltage is provided to the input of the source amplifier 120.

[0028] Based on this knowledge, the present disclosure provides various techniques for reducing the effective resistance across the path providing selected gamma voltages from a gamma voltage generator to the input of a source amplifier in a display driver. Various embodiments for improving or increasing the slew rate at the input of a source amplifier are described below.

[0029] Figure 2 An example configuration of a display device 500 according to one or more embodiments is shown. In the illustrated embodiment, the display device 500 is configured as a panel display device including a display panel 200 and a display driver 300. The display driver 300 is configured to drive the display panel 200 under the control of a host 400. Examples of the host 400 include an application processor, a central processing unit (CPU), and other processors and controllers suitable for controlling the display device 500. In one implementation, the display driver 300 is configured to generate data voltages based on pixel data received from the host 400 and output the data voltages from source outputs S[1] to S[n] to the display panel 200. The data voltages are provided to pixels of the display panel 200 to program the pixels.

[0030] Figure 3A An example partial configuration of a display driver 300 according to one or more embodiments is shown. In the illustrated embodiment, the display driver 300 includes a set of driving branches 310-1 to 310-n (where n is a natural number greater than two), a gamma voltage generator 320, and a control circuit 370. When not distinguished from each other, the driving branches 310-1 to 310-n may be collectively referred to as driving branches 310 for short.

[0031] The driving branches 310-1 to 310-n are respectively configured to generate data voltages based on the pixel data D[1] to D[n] and output the data voltages to the source outputs S[1] to S[n]. The pixel data D[1] to D[n] respectively specify the grayscale of the pixel to be programmed using the data voltages output from the source outputs S[1] to S[n]. The data voltages output from the source outputs S[1] to S[n] respectively have voltage levels corresponding to the grayscale of the pixel data D[1] to D[n]. In some implementations, the pixel data D[1] to D[n] can be processed by applying the desired image processing (e.g., color adjustment, scaling, demura, overshoot driving, contrast enhancement, gamma conversion, and other image processing) to the pixel data from the host 400 (in Figure 2 310-1 to 310-n are configured to generate data voltages using a gamma voltage set Vg[0] to Vg[m] received from a gamma voltage generator 320, wherein m is a natural number greater than two. The gamma voltage generator 320 is configured to generate gamma voltages Vg[0] to Vg[m] and provide gamma voltages Vg[0] to Vg[m] to each of the drive branches 310-1 to 310-n via a gamma bus 330 including a gamma bus line set GL[0] to GL[m]. The gamma voltages Vg[0] to Vg[m] are generated on gamma bus lines GL[0] to GL[m], respectively.

[0032] Figure 3B An example configuration of a gamma voltage generator 320 according to one or more embodiments is shown. In the illustrated embodiment, the gamma voltage generator 320 includes a gamma resistor string 322, a gamma top amplifier 324, a gamma bottom amplifier 326, and a gamma tap amplifier set 328-1 to 328-r (two are shown), where r is a natural number greater than one. The gamma top amplifier 324 is configured to provide a gamma top voltage V to a first end 322a of the gamma resistor string 322. TOP , and the gamma bottom amplifier 326 is configured to provide a gamma bottom voltage V to the second end 322 b of the gamma resistor string 322 BOTTOM The gamma tap amplifiers 328 - 1 to 328 - r are configured to provide tap voltages V to the corresponding intermediate taps of the gamma resistor string 322 , respectively. TAP1 To V TAPr The gamma bus line GL[0] is coupled to the first end 322a of the gamma resistor string 322, and thus the gamma voltage Vg[0] is equal to the gamma top voltage V TOPThe gamma bus line GL[m] is coupled to the second end 322b of the gamma resistor string 322, and thus the gamma voltage Vg[m] is equal to the gamma bottom voltage V BOTTOM The gamma bus lines GL[1] to GL[m−1] are coupled to the middle positions of the gamma resistor string 322 to generate gamma voltages Vg[1] to Vg[m−1] on the gamma bus lines GL[1] to GL[m−1] by using voltage division of the gamma resistor string 322 .

[0033] Return to reference Figure 3A , the driving branches 310 each include a decoder (DEC) 340, a source interpolation selector 350, and a source amplifier 360. The decoder 340 of each driving branch 310 has an input set coupled to the gamma bus lines GL[0] to GL[m] respectively and two outputs coupled to the source interpolation selector 350. The source amplifier 360 has an input set coupled to the source interpolation selector 350. In the illustrated embodiment, the source amplifier 360 has three inputs. In other embodiments, the number of inputs of the source amplifier 360 can be two, four or more. The source interpolation selector 350 is configured to provide an electrical connection between the output of the decoder 340 and the input of the source amplifier 360.

[0034] The display driver 300 also includes a control circuit 370 configured to generate a shunt control signal and provide the shunt control signal to the source interpolation selectors 350 of the corresponding drive branches 310. As discussed in detail later, the shunt control signal is used to instruct each source interpolation selector 350 to electrically connect the two outputs of the corresponding decoder 340 to thereby shunt (or short-circuit) the two outputs. The control circuit 370 may include a register 375 that stores a register value for controlling the shunt control signal. The register value stored in the register 375 may indicate the duration of a time period during which: each time the shunt control signal is asserted, the shunt control signal remains asserted. In one implementation, the register 375 is configured to be controllable by an entity external to the display driver 300 (such as Figure 1 In such an implementation, an external entity (such as host 400) may be configured to program register values ​​stored in register 375.

[0035] Figure 4An example configuration of each drive branch 310-i according to one or more embodiments is shown. In the illustrated embodiment, the decoder 340 of the drive branch 310-i includes a switch array 342, a first output 344, and a second output 346. The switch array 342 is configured to select two gamma bus lines among the gamma bus lines GL[0] to GL[m] based on the most significant p bits (or higher p bits) of the pixel data D[i] and couple the selected two gamma bus lines to the first output 344 and the second output 346, respectively, wherein the pixel data D[i] is (p+q)-bit data. In an embodiment in which the pixel data D[i] is 10-bit data, for example, p can be eight and q can be two.

[0036] Source amplifier 360 has a set of inputs and is configured to drive source output S[i] based on an input voltage at the input. In one implementation, source amplifier 360 can be configured to drive source output S[i] to a voltage that is a weighted average of the voltages at the inputs of source amplifier 360. In the illustrated embodiment, source amplifier 360 has three inputs 362-1, 362-2, and 362-3. In one implementation, the weights assigned to inputs 362-1, 362-2, and 362-3 can be 1 / 4, 2 / 4, and 1 / 4, respectively. In this case, the voltage V at source output S[i] OUT It is expressed by the following expression (1): (1) V OUT = (1 / 4) V IN1 + (2 / 4) V IN2 + (1 / 4) V IN3 , Where V IN1 、V IN2 and V IN3 are the voltages at inputs 362-1, 362-2, and 362-3, respectively. The voltage generated at source output S[i] serves as the data voltage for programming the selected pixel coupled to source output S[i].

[0037] The source interpolation selector 350 is configured to respond to the least significant q bits (or lower q bits) of the (p+q)-bit pixel data D[i] and the slave control circuit 370 (in Figure 3AThe source interpolation selector 350 is configured to operate based on a shunt control signal received by the decoder 340 (shown in FIG). The source interpolation selector 350 is configured to provide an electrical connection between the output of the decoder 340 and the input of the source amplifier 360 based on the least significant q bits of the (p+q)-bit pixel data D[i]. As discussed in detail later, the electrical connection within the source interpolation selector 350 is controlled based on the least significant q bits of the (p+q)-bit pixel data D[i] to allow the source amplifier 360 to provide a data voltage corresponding to the pixel data D[i] to the source output S[i]. In addition, the source interpolation selector 350 is configured to electrically connect the first output 344 and the second output 346 of the decoder 340 in response to the shunt control signal so that the first output 344 and the second output 346 are shunted or short-circuited.

[0038] In the illustrated embodiment, the source interpolation selector 350 includes a first set of switches 352-1, 352-2, and 352-3 and a second set of switches 354-1, 354-2, and 354-3. The switches 352-1, 352-2, and 352-3 of the first set are coupled between the first output 344 and the inputs 362-1, 362-2, and 362-3 of the decoder 340, respectively. The switches 354-1, 354-2, and 354-3 of the second set are coupled between the second output 346 of the decoder 340 and the inputs 362-1, 362-2, and 362-3, respectively.

[0039] In one implementation, the source interpolation selector 350 has two modes: a selection mode and a shunt mode. In the selection mode in which the shunt control signal is deasserted, the source interpolation selector 350 is configured to electrically connect one of the first output 344 and the second output 346 of the decoder 340 to the corresponding inputs 362-1, 362-2, and 362-3 based on the least significant q bit of the pixel data D[i]. More specifically, the source interpolation selector 350 is configured to close (or turn on) one of the switches 352-1 and 354-1 based on the least significant q bit of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-1 of the source amplifier 360. The source interpolation selector 350 is further configured to close one of the switches 352-2 and 354-2 based on the least significant q bit of the pixel data D[i] to electrically connect a corresponding one of the first output 344 and the second output 346 to the input 362-2 of the source amplifier 360. The source interpolation selector 350 is further configured to close one of the switches 352-3 and 354-3 based on the least significant q bit of the pixel data D[i] to electrically connect a corresponding one of the first output 344 and the second output 346 to the input 362-3 of the source amplifier 360. Note that in the selection mode, the source interpolation selector 350 electrically disconnects the first output 344 and the second output 346 of the decoder 340 from each other.

[0040] In the shunt mode in which the shunt control signal is asserted, the source interpolation selector 350 closes (or turns on) all of the switches 352-1, 352-2, 352-3, 354-1, 354-2, and 354-3 to shunt or short the first output 344 and the second output 346 of the decoder 340, and further electrically connects both the first output 344 and the second output 346 to each of the inputs 362-1, 362-2, and 362-3 of the source amplifier 360. As will be discussed in detail later, shunting (or shorting) the first output 344 and the second output 346 by the source interpolation selector 350 effectively reduces the effective resistance of the path that provides the selected gamma voltage from the gamma voltage generator 320 to the inputs 362-1, 362-2, and 362-3 of the source amplifier 360, thereby improving the slew rate at the inputs 362-1, 362-2, and 362-3.

[0041] Figure 5 5. The following diagram shows the timing of the horizontal synchronization period 502 and 504 during the horizontal synchronization period 502 and 504 according to one or more embodiments. Figure 4. At time t0, the horizontal synchronization signal used in the display driver 300 is asserted to start the horizontal synchronization cycle 502. At the beginning of the horizontal synchronization cycle 502, the pixel data D[i] of the driving branch 310-i is data [T-1], and the source output S[i] is set to the voltage level V corresponding to data [T-1]. Si [T-1].

[0042] At time t1 in horizontal synchronization period 502, pixel data D[i] changes from data[T-1] to data[T]. The change in pixel data D[i] causes the decoder 340 to change the selection of gamma bus lines GL[0] to GL[m] (i.e., the selection of gamma voltages Vg[0] to Vg[m]), which causes the voltage at source output S[i] to begin to move toward the voltage level V corresponding to data[T] as indicated by solid line 510. Si [T] changes. In addition, at time t1, the shunt control signal is asserted in synchronization with the change of pixel data D[i]. By asserting the shunt control signal at time t1, the source interpolation selector 350 is set to the shunt mode during the initial stage of the voltage change at the source output S[i].

[0043] Figure 6 is a schematic diagram illustrating example operations of a drive branch 310-i during a period between time t1 and time t2 in a horizontal synchronization period 502 according to one or more embodiments. The decoder 340 selects two adjacent gamma bus lines GL[N] and GL[N-1] from the gamma bus 330 based on the most significant p bits of the pixel data D[i], the pixel data D[i] being data [T] during a period between time t1 and time t2, where N is a natural number from one to m. In addition, the decoder 340 electrically connects the gamma bus line GL[N] to the first output 344 and electrically connects the gamma bus line GL[N-1] to the second output 346. Note that the gamma bus lines GL[N] and GL[N-1] are used as also described in Figure 7 As shown in FIG. 1 , the gamma voltages Vg[N] and Vg[N-1] are respectively provided from the gamma voltage generator 320 to the decoder 340 of each driving branch 310. The decoder 340 selects two gamma bus lines GL[N] and GL[N-1] so that the voltage level V corresponding to the data [T] Si [T] falls inclusively within a voltage range between the gamma voltage Vg[N−1] and the gamma voltage Vg[N]. The decoder 340 further electrically couples the selected gamma bus line GL[N] to a first output 344 and the selected gamma bus line GL[N−1] to a second output 346.

[0044] The source interpolation selector 350 is set to the shunt mode in response to the shunt control signal being asserted at time t1. In the shunt mode, the source interpolation selector 350 closes (or turns on) all switches 352-1 to 352-3 and 354-1 to 354-3. By closing switches 352-1 to 352-3 and 354-1 to 354-3, the source interpolation selector 350 electrically connects both the first output 344 and the second output 346 of the decoder 340 to each of the inputs 362-1, 362-2 and 362-3 of the source amplifier 360. As a result, each of the inputs 362-1, 362-2 and 362-3 of the source amplifier 360 is driven toward a voltage between the gamma voltage Vg[N] and Vg[N-1], so that the source amplifier 360 drives the source output S[i] toward the voltage.

[0045] At the same time, the turning on of switches 352-1 to 352-3 and 354-1 to 354-3 electrically connects and short-circuits the first output 344 and the second output 346 of the decoder 340. The electrical connection of the first output 344 and the second output 346 causes the gamma bus line GL[N] and the gamma bus line GL[N-1] to be electrically connected in parallel. More specifically, when the first output 344 and the second output 346 are electrically connected, a first path formed by the gamma bus line GL[N] and a first set of switches connected in series in the decoder 340 between the first output 344 and the gamma bus line GL[N] and a second path formed by the gamma bus line GL[N-1] and a second set of switches connected in series in the decoder 340 between the second output 345 and the gamma bus line GL[N-1] are electrically connected in parallel. Despite the resistance across the gamma bus line GL[N] and the gamma bus line GL[N-1] (at Figure 7 The on-resistance of the switches connected in series (indicated by "R-gamma" in the figure) and in decoder 340 can be quite large, but the parallel connection of the first path and the second path reduces the effective resistance of the path providing the gamma voltage to each input of source amplifier 360, thereby reducing the RC time constant at each input of source amplifier 360. The reduction of the RC time constant at each input of source amplifier 360 effectively increases the slew rate at each input of source amplifier 360.

[0046] Return to reference Figure 5 , the shunt control signal remains asserted during the time period from time t1 to time t2. Figure 5 In the example, the assertion duration of the shunt control signal (i.e., the duration of the cycle between time t1 and time t2) is determined by “T SH "Instruction. The assertion duration of the shunt control signal is T SH(i.e., the time interval between time t1 and time t2) can be adjusted based on the characteristics of the display panel 200 and the display driver 300 (such as the capacitance and / or resistance of the source line of the display panel 200 and the driving capability of the source amplifier 360). In some embodiments, the display driver 300 can be configured so that the assertion duration T of the shunt control signal is 100%. SH In some embodiments, the register 375 (in Figure 3A The register value in FIG. 1 indicates the assertion duration T of the shunt control signal. SH In such an embodiment, the assertion duration T SH This can be adjusted by programming the register value.

[0047] At time t2, the shunt control signal is de-asserted to set the source interpolation selector 350 to the selection mode. In the illustrated embodiment, the shunt control signal remains de-asserted until time t4 in the next horizontal synchronization period 504 beginning at time t3.

[0048] Figure 8 is a schematic diagram illustrating an example operation of a driving branch 310-i during a time period between time t2 and time t4 according to one or more embodiments. When the source interpolation selector 350 is in the selection mode, the source interpolation selector 350 electrically disconnects the first output 344 and the second output 346 of the decoder 340 from each other. Accordingly, the first output 344 is driven to the gamma voltage Vg[N] provided by the gamma bus line GL[N], and the second output 346 is driven to the gamma voltage Vg[N-1] provided by the gamma bus line GL[N-1].

[0049] In addition, the source interpolation selector 350 electrically connects a selected one of the first output 344 and the second output 346 of the decoder 340 to each of the inputs 362-1, 362-2, and 362-3 of the source amplifier 360 based on the least significant q bit of the pixel data D[i], which is data [T] during a time period from time t2 to time t3. As a result, a gamma voltage Vg[N] or Vg[N-1] is provided to each of the inputs 362-1, 362-2, and 362-3 of the source amplifier 360 based on the least significant q bit of the pixel data D[i]. More specifically, the source interpolation selector 350 closes (or turns on) one of the switches 352-1 and 354-1 based on the least significant q bit of the pixel data D[i] to electrically connect a corresponding one of the first output 344 and the second output 346 to the input 362-1 of the source amplifier 360. As a result, the gamma voltage Vg[N] or Vg[N-1] is provided to the input 362-1 based on the least significant q bit of the pixel data D[i]. The source interpolation selector 350 further closes one of the switches 352-2 and 354-2 based on the least significant q bit of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-2 of the source amplifier 360. As a result, the gamma voltage Vg[N] or Vg[N-1] is provided to the input 362-2 based on the least significant q bit of the pixel data D[i]. The source interpolation selector 350 further closes one of the switches 352-3 and 354-3 based on the least significant q bit of the pixel data D[i] to electrically connect the corresponding one of the first output 344 and the second output 346 to the input 362-3 of the source amplifier 360. As a result, the gamma voltage Vg[N] or Vg[N-1] is provided to the input 362-3 based on the least significant q bits of the pixel data D[i].

[0050] Source amplifier 360 drives source output S[i] in response to the voltages at inputs 362-1, 362-2, and 362-3. In one implementation, source amplifier 360 drives source output S[i] to a voltage level that is a weighted average of the voltages at inputs 362-1, 362-2, and 362-3. In an embodiment where the weights assigned to inputs 362-1, 362-2, and 362-3 are 1 / 4, 2 / 4, and 1 / 4, respectively, for example, the voltage V generated at source output S[i] is OUT It is expressed by the following expression (2): (2) V OUT = (1 / 4) V IN1 + (2 / 4) V IN2 + (1 / 4) V IN3, Where V IN1 、V IN2 and V IN3 The voltages at the inputs 362-1, 362-2, and 362-3 are respectively. The voltage generated at the source output S[i] is used as the data voltage for programming the selected pixel coupled to the source output S[i]. The combination of gamma voltages (Vg[N] or Vg[N-1]) provided to the corresponding inputs 362-1, 362-2, and 362-3 is determined so that the voltage at the source output S[i] is driven to the voltage level V corresponding to the data [T]. Si [T].

[0051] Return to reference Figure 5 , the drive branch 310-i can operate in a similar manner during the next horizontal synchronization period 504 starting at time t3. In the illustrated embodiment, the pixel data D[i] changes from data[T] to data[T+1] at time t4 in the horizontal synchronization period 504, and the shunt control signal is asserted synchronously with the change of the pixel data D[i] at time t4. After time t4, in addition to the change of the pixel data D[i] from data[T] to data[T+1], the drive branch 310-i performs the same operation as with respect to Figures 6 to 8 More specifically, the change in pixel data D[i] causes the decoder 340 to change the selection of gamma bus lines GL[0] to GL[m] (i.e., the selection of gamma voltages Vg[0] to Vg[m]), thereby causing the voltage at the source output S[i] to begin to move toward the voltage level V corresponding to data [T+1] as indicated by the solid line 510. Si [T+1] changes. In addition, assertion of the shunt control signal sets the source interpolation selector 350 to a shunt mode to electrically couple the first output 344 and the second output 346 of the decoder 340. The shunt control signal remains asserted until time t5. The shunt control signal is then deasserted at time t5 to set the source interpolation selector 350 to a selection mode. In the selection mode, the source interpolation selector 350 provides one of the two selected gamma voltages to each of the inputs 362-1, 362-2, and 362-3 of the source amplifier 360. The source amplifier 360 drives the source output S[i] to a voltage level V corresponding to the data [T+1] in response to the voltages at the inputs 362-1, 362-2, and 362-3. Si [T+1].

[0052] Note that although Figure 5It is shown that the pixel data D[i] is changed once during each of the horizontal synchronization periods, but the pixel data D[i] may be changed a plurality of times during each of the horizontal synchronization periods.

[0053] In the above article about Figures 5 to 8 The described operation effectively increases the slew rate at the input of the source amplifier 360 during the initial stage of the change in voltage at the source output S[i], thereby achieving a reduction in the settling time of the source amplifier 360. Figure 5 An example of shortening the stabilization time is shown in FIG. 5 , where a solid line 510 indicates an example change in voltage at the source output S[i] when the first output 344 and the second output 346 of the decoder 340 are electrically connected during the initial stage, and dashed lines 520 and 525 indicate an example change in voltage at the source output S[i] when the first output 344 and the second output 346 are not electrically connected during the initial stage.

[0054] Fig. 9 900 according to other embodiments. Figure 3A 300 is configured in a manner similar to that of the display driver 300 shown in FIG. Figure 5 One difference is that each driver branch 380-i includes a control circuit 390 configured to provide a shunt control signal to the source interpolation selector 350. The control circuit 390 is configured to control the assertion duration ( Figure 5 The “T SH ”). The control circuit 390 of the driving branch 380-i is configured to generate a shunt control signal based on the pixel data D[i] and provide the shunt control signal to the source interpolation selector 350. In one or more embodiments, the control circuit 390 of the driving branch 380-i is configured to adjust the assertion duration T of the shunt control signal based on the pixel data D[i]. SH Use pixel data D[i] to adjust the assertion duration T of the shunt control signal SH This allows the assertion duration T to be appropriately determined for changes in the voltage at the input of the source amplifier 360. SH .

[0055] In various embodiments, the control circuit 390 of each driving branch 380-i can be configured to adjust the assertion duration T of the shunt control signal based on data [T-1] and data [T] when the pixel data D[i] changes from data [T-1] to data [T]. SH (exist Figure 5). Note that data [T-1] is the previous pixel data provided to the decoder 340 before data [T] is provided to the decoder 340. In some embodiments, the control circuit 390 of each driving branch 380-i can be configured to adjust the assertion duration T of the shunt control signal based on the difference between data [T-1] and data [T] (more specifically, between the gray level specified by data [T-1] and the gray level specified by data [T]) when the pixel data D[i] changes from data [T-1] to data [T]. SH In one implementation, the assertion duration T of the shunt control signal is adjusted SH , so that the assertion duration T SH It increases as the difference between the data [T-1] and the data [T] (or the difference between the gray level specified by the data [T-1] and the gray level specified by the data [T]) increases.

[0056] In some implementations, the control circuit 390 of each driving branch 380-i can be configured to adjust the assertion duration T of the shunt control signal based on one or more most significant bits of data [T-1] and data [T] when the pixel data D[i] changes from data [T-1] to data [T]. SH In the embodiment where data [T-1] and data [T] are (p+q)-bit data, the assertion duration T of the shunt control signal SH The control circuit 390 can be adjusted based on the most significant r bits of data [T-1] and data [T], where r is an integer less than p+q. By using only one or more most significant bits of data [T-1] and data [T], the circuit size of the control circuit 390 can be advantageously reduced. The control circuit 390 of each driving branch 380-i can be configured to adjust the assertion duration T of the shunt control based on the difference between one or more most significant bits of data [T-1] and data [T]. SH In one implementation, the control circuit 390 of each driving branch 380-i may be configured to adjust the assertion duration T of the shunt control based on the difference between the most significant bit (MSB) of data [T-1] and the MSB of data [T]. SH .

[0057] Fig.10 is a flow chart of an exemplary process for driving a display panel according to one or more examples of the present disclosure. Process 1000 may be performed by Figure 3A or Fig. 9 However, it will be appreciated that the display driver 300 shown in FIG. Figure 3A or Fig. 9A display driver with additional and / or fewer components as shown in FIG. 100 may be used to perform process 1000 , any of the following steps may be performed in any suitable order, and process 1000 may be performed in any suitable environment.

[0058] Process 1000 includes generating a plurality of gamma voltages (eg, gamma bus lines GL[0] to GL[m]) at step 1002, respectively, on a plurality of gamma bus lines (eg, gamma bus lines GL[0] to GL[m]). Figure 3A and Fig. 9 The gamma voltages Vg[0] to Vg[m] shown in FIG.

[0059] Process 1000 also includes, at step 1004, providing the decoder with first pixel data (eg, Figure 3A , Figure 6 and Fig. 9 ) to convert the first output (eg, pixel data D[i]) of the decoder (eg, decoder 340) into Figure 4 ) is electrically connected to a first gamma bus line (eg, Figure 6 ). Process 1000 also includes, at step 1006, converting a second output of the decoder (eg, Figure 4 ) is electrically connected to a second gamma bus line (eg, Figure 6 The gamma bus line GL[N-1] shown in FIG.

[0060] Process 1000 also includes, at step 1008, performing a horizontal synchronization cycle (e.g., Figure 5 502) shown in FIG. Figure 5 The first output and the second output of the decoder are electrically connected during the period between time t1 and time t2 shown in FIG.

[0061] Process 1000 also includes, at step 1010, performing a second period of the horizontal synchronization period (eg, Figure 5 The first output and the second output of the decoder are provided based on the first pixel data and the source amplifier (eg, Figure 3A and Fig. 9 The electrical connection between the input sets of the source amplifier 360) shown in , the second cycle follows the first cycle.

[0062] Process 1000 also includes, at step 1012, providing a display panel (eg, Figure 2The display panel 200 shown in FIG. 1 provides a data voltage.

[0063] Unless otherwise indicated herein or clearly contradicted by the context, the use of the terms "a and an" and "the" and "at least one" and similar referents in the context of describing the present invention (especially in the context of the following claims) is to be interpreted as covering both the singular and the plural. Unless otherwise indicated herein or clearly contradicted by the context, the use of the term "at least one" followed by a list of one or more items (e.g., "at least one of A and B") is to be interpreted as meaning one item (A or B) selected from the listed items or any combination of two or more items in the listed items (A and B). Unless otherwise indicated, the terms "comprising", "having", "including" and "containing" are to be interpreted as open terms (i.e., meaning "including but not limited to"). Unless otherwise indicated herein, the description of the range of values ​​herein is intended only to serve as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as it is individually described herein. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. Unless otherwise required, the use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the invention and will not limit the scope of the invention. Language in this specification should not be construed as indicating any non-claimed element as essential to the practice of the invention.

[0064] Exemplary embodiments are described herein. When reading the foregoing description, variations of those exemplary embodiments may become apparent to those of ordinary skill in the art. The inventor expects that the skilled person will adopt such variations when appropriate, and the inventor intends to practice the present invention in a manner other than as specifically described herein. Accordingly, the present invention includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. In addition, unless otherwise indicated herein or otherwise clearly contradictory to the context, the present invention includes any combination of the elements described above in all possible variations thereof.

Claims

1. A display driver, comprising: a plurality of gamma bus lines, on which a plurality of gamma voltages are generated respectively; as well as A driving branch, configured to receive the first pixel data and the plurality of gamma voltages, the driving branch comprising: A decoder comprising a first output and a second output, wherein the decoder is configured to: electrically connecting the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data, and electrically connecting the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; a source amplifier comprising a set of inputs and configured to provide a data voltage to a display panel based on a set of input voltages at the set of inputs; and Source interpolation selector configured to: providing electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier based on the first pixel data, and The first output and the second output of the decoder are electrically connected during a first period of a horizontal synchronization period.

2. The display driver of claim 1 , wherein the source interpolation selector is further configured to electrically connect the corresponding input of the source amplifier to the first output or the second output during a second cycle of the horizontal synchronization cycle, the second cycle being subsequent to the first cycle.

3. The display driver according to claim 1, wherein the source interpolation selector comprises: a first set of switches coupled between the first output of the decoder and the set of inputs of the source amplifier, respectively; as well as A second set of switches are respectively coupled between the second output of the decoder and the set of inputs of the source amplifier. 4 . The display driver of claim 3 , wherein electrically connecting the first output and the second output of the decoder during the first period comprises closing all of the first set of switches and all of the second set of switches during the first period.

5. The display driver according to claim 1, wherein the source interpolation selector is further configured to receive a shunt control signal, wherein electrically connecting the first output and the second output of the decoder during the first period of the horizontal synchronization period is responsive to the shunt control signal. The display driver according to claim 1 , wherein the duration of the first period is programmable.

7. The display driver of claim 1, further comprising a control circuit configured to adjust a duration of the first period.

8. The display driver of claim 7, wherein adjusting the duration of the first cycle is based on the first pixel data and second pixel data provided to the decoder before providing the first pixel data to the decoder.

9. The display driver of claim 7, wherein adjusting the duration of the first cycle is based on a difference between the first pixel data and second pixel data provided to the decoder before providing the first pixel data to the decoder.

10. The display driver of claim 7, wherein adjusting the duration of the first cycle is based on the first pixel data and one or more most significant bits of second pixel data provided to the decoder before providing the first pixel data to the decoder.

11. A display device, comprising: Display panel; as well as The display driver comprises: a plurality of gamma bus lines, on which a plurality of gamma voltages are generated respectively; and A driving branch, configured to receive the first pixel data and the plurality of gamma voltages, the driving branch comprising: A decoder comprising a first output and a second output, wherein the decoder is configured to: electrically connecting the first output to a first gamma bus line of the plurality of gamma bus lines based on the first pixel data, and electrically connecting the second output to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; a source amplifier comprising a set of inputs and configured to provide a data voltage to the display panel based on a set of input voltages at the set of inputs; and Source interpolation selector configured to: providing electrical connections between the first and second outputs of the decoder and the set of inputs of the source amplifier based on the first pixel data, and The first output and the second output of the decoder are electrically connected during a first period of a horizontal synchronization period.

12. The display device of claim 11, wherein the source interpolation selector is further configured to electrically connect the corresponding input of the source amplifier to the first output or the second output during a second cycle of the horizontal synchronization cycle, the second cycle being subsequent to the first cycle.

13. The display device according to claim 11, wherein the source interpolation selector comprises: a first set of switches coupled between the first output of the decoder and the set of inputs of the source amplifier, respectively; as well as A second set of switches are respectively coupled between the second output of the decoder and the set of inputs of the source amplifier.

14. The display device of claim 13, wherein electrically connecting the first output and the second output of the decoder during the first period comprises closing all of the first set of switches and all of the second set of switches during the first period.

15. The display device according to claim 11, wherein the source interpolation selector is further configured to receive a current splitting control signal, wherein electrically connecting the first output and the second output of the decoder during the first period of the horizontal synchronization period is responsive to the shunt control signal.

16. The display driver of claim 11, further comprising a control circuit configured to adjust a duration of the first period.

17. The display driver of claim 16, wherein adjusting the duration of the first cycle is based on the first pixel data and second pixel data provided to the decoder before providing the first pixel data to the decoder.

18. A method comprising: generating a plurality of gamma voltages on a plurality of gamma bus lines respectively; electrically connecting a first output of the decoder to a first gamma bus line of the plurality of gamma bus lines based on first pixel data provided to the decoder; electrically connecting a second output of the decoder to a second gamma bus line of the plurality of gamma bus lines based on the first pixel data; electrically connecting the first output and the second output of the decoder during a first period of a horizontal synchronization period; electrically connecting the first and second outputs of the decoder to a set of inputs of a source amplifier based on the first pixel data during a second cycle of the horizontal synchronization cycle, the second cycle following the first cycle; as well as A data voltage is provided to a display panel by the source amplifier based on a set of input voltages at the set of inputs during the first period and the second period.

19. The method of claim 18, wherein a first set of switches are coupled between the first output of the decoder and the set of inputs of the source amplifier, respectively, wherein a second set of switches are respectively coupled between the second output of the decoder and the input set of the source amplifier, Wherein electrically connecting the first output and the second output of the decoder comprises closing all of the first set of switches and all of the second set of switches during the first period.

20. The method of claim 18, further comprising adjusting a duration of the first cycle based on the first pixel data and second pixel data provided to the decoder prior to providing the first pixel data to the decoder.

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