Pixel circuit, display panel and display device

Abstract

The invention discloses a pixel circuit, a display panel and a display device, and belongs to the technical field of display. The pixel circuit comprises a driving module; the threshold compensation module is arranged in a first branch connected between the control end and the second end of the driving module, and the threshold compensation module is used for being switched on or switched off according to the first scanning signal; the first initialization module is arranged in a second branch connected with the control end of the driving module, and the first initialization module is used for being switched on or switched off according to a second scanning signal; the frequency control module is respectively connected with the first branch circuit and the second branch circuit, and accesses a frequency control signal and a first scanning signal; and the frequency control module is used for controlling the on-off of the first branch according to the frequency control signal and the first scanning signal, and controlling the on-off of the second branch according to the frequency control signal so as to control the refresh frequency of the pixel circuit. According to the embodiment of the invention, pixel-level refresh frequency control can be realized, so that the display panel supports a flexible partition frequency division display function.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] Organic light emitting diode (OLED) and flat display devices based on light emitting diode (LED) technologies have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream of display devices. However, the display panel in the related art cannot realize flexible partition and frequency display. Summary of the invention

[0003] The present invention provides a pixel circuit, a display panel and a display device to realize refresh frequency control at the pixel level, so that the display panel supports a flexible partitioned frequency display function.

[0004] In a first aspect, an embodiment of the present invention provides a pixel circuit, including:

[0005] Driver module;

[0006] A threshold compensation module is provided in a first branch connected between the control end and the second end of the driving module, and the threshold compensation module is used to be turned on or off according to a first scanning signal;

[0007] A first initialization module, disposed in a second branch connected to the control end of the driving module, the first initialization module being used to be turned on or off according to a second scanning signal;

[0008] A frequency control module is connected to the first branch and the second branch respectively, and is connected to a frequency control signal and the first scanning signal; the frequency control module is used to control the on-off of the first branch according to the frequency control signal and the first scanning signal, and to control the on-off of the second branch according to the frequency control signal, so as to control the refresh frequency of the pixel circuit.

[0009] Optionally, the frequency control module includes:

[0010] A first switch unit is connected in series with the threshold compensation module in the first branch; the first switch unit is used to be turned on or off according to the voltage of its control terminal;

[0011] A second switch unit is connected in series with the first initialization module in the second branch, and a control end of the second switch unit is connected to the frequency control signal; the second switch unit is used to be turned on or off according to the frequency control signal;

[0012] a voltage control unit connected to the control end of the first switch unit and connected to the frequency control signal and the first scanning signal; the voltage control unit is used to control whether the frequency control signal is transmitted to the control end of the first switch unit according to the first scanning signal;

[0013] Preferably, one end of the second branch is connected to the control end of the driving module, and the other end of the second branch is connected to the initialization signal;

[0014] Preferably, the on-voltage of the first switch unit is the same as the on-voltage of the second switch unit; when the first scanning signal is the cut-off voltage of the threshold compensation module, the voltage control unit is controlled to transmit the frequency control signal to the control end of the first switch unit.

[0015] Optionally, in any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase that occur successively; in the first initialization phase, the second scanning signal is a turn-on voltage of the first initialization module; in the data writing phase, the first scanning signal is a turn-on voltage of the threshold compensation module;

[0016] In a display frame in which the pixel circuit performs data refresh, a period during which the frequency control signal maintains the on-voltage of the second switch unit at least covers the start time of the first initialization phase and the data writing phase;

[0017] In a display frame in which the pixel circuit performs data retention, a period in which the frequency control signal maintains the cut-off voltage of the second switch unit at least covers the start time of the first initialization phase and the data writing phase;

[0018] Preferably, in a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains the on-voltage of the second switch unit at least during a period from the start of the first initialization phase to the start of the data writing phase;

[0019] In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the second switch unit at least during a period from when the first initialization phase starts to after the data writing phase starts.

[0020] Optionally, the first switch unit includes: a first transistor, connected in series with the threshold compensation module in the first branch, and a gate of the first transistor is connected to a control terminal of the first switch unit;

[0021] The second switch unit comprises: a second transistor connected in series with the first initialization module in the second branch, and a gate of the second transistor is connected to the frequency control signal;

[0022] The voltage control unit comprises: a third transistor, a gate of the third transistor is connected to the first scanning signal, a first electrode of the third transistor is connected to the frequency control signal, and a second electrode of the third transistor is connected to the control end of the first switch unit;

[0023] Preferably, the voltage control unit further includes: a first capacitor, a first end of the first capacitor is connected to the control end of the first switch unit, and a second end of the first capacitor is connected to a fixed voltage signal;

[0024] Preferably, the threshold compensation module comprises: a fourth transistor connected in series with the first switch unit in the first branch, and a gate of the fourth transistor is connected to the first scanning signal;

[0025] The first initialization module includes: a fifth transistor connected in series with the second switch unit in the second branch, and a gate of the fifth transistor is connected to the second scanning signal;

[0026] Preferably, the first transistor and the second transistor have the same channel type, and the third transistor and the fourth transistor have different channel types;

[0027] Preferably, the channel types of the first transistor, the second transistor, the fourth transistor and the fifth transistor are all the same;

[0028] Preferably, the first transistor, the second transistor, the fourth transistor and the fifth transistor are all N-type transistors, and the third transistor is a P-type transistor.

[0029] Optionally, the driving module comprises: a driving transistor, a gate of the driving transistor is connected to a control terminal of the driving module, a first electrode of the driving transistor is connected to a first terminal of the driving module, and a second electrode of the driving transistor is connected to a second terminal of the driving module;

[0030] Preferably, the pixel circuit further includes:

[0031] The data writing module comprises a sixth transistor; the gate of the sixth transistor is connected to the third scanning signal, the first electrode of the sixth transistor is connected to the data signal, and the second electrode of the sixth transistor is connected to the first end of the driving module;

[0032] A light-emitting control module, comprising a seventh transistor and an eighth transistor; the gate of the seventh transistor and the gate of the eighth transistor are both connected to a light-emitting control signal, the first electrode of the seventh transistor is connected to a first power supply signal, the second electrode of the seventh transistor is connected to a first end of the driving module, the first electrode of the eighth transistor is connected to a second end of the driving module, the second electrode of the eighth transistor is connected to an anode of a light-emitting device, and the cathode of the light-emitting device is connected to a second power supply signal;

[0033] A second initialization module includes a ninth transistor; a gate of the ninth transistor is connected to a fourth scanning signal, a first electrode of the ninth transistor is connected to an initialization signal, and a second electrode of the ninth transistor is connected to an anode of the light-emitting device;

[0034] A storage module, comprising a storage capacitor; a first end of the storage capacitor is connected to the first power signal, and a second end of the storage capacitor is connected to a control end of the driving module;

[0035] Preferably, the frequency control module includes a first capacitor, and a second end of the first capacitor is connected to a fixed voltage signal; wherein the initialization signal, the first power signal or the second power signal is multiplexed into the fixed voltage signal.

[0036] In a second aspect, an embodiment of the present invention provides a display panel, including: a pixel circuit provided by any embodiment of the present invention;

[0037] Preferably, the frequency control module comprises a first switch unit, a second switch unit and a voltage control unit; the display panel comprises a plurality of pixel circuits arranged in an array; at least two pixel circuits in the same row share the same voltage control unit;

[0038] Preferably, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit share the same voltage control unit;

[0039] Preferably, the display panel further comprises: at least one frequency control signal line, at least one column of the pixel circuits is connected to the same frequency control signal line, and the frequency control signal line is used to provide the frequency control signal to the connected pixel circuits;

[0040] Preferably, at least two pixel circuits in the same row are connected to the same frequency control signal line;

[0041] Preferably, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines;

[0042] Preferably, the display panel further comprises: a plurality of data lines connected to the pixel circuits of each column in a one-to-one correspondence; the data lines and the frequency control signal lines extend in the same direction.

[0043] In a third aspect, an embodiment of the present invention provides a display device, including:

[0044] A display panel, comprising a plurality of pixel circuits and at least one frequency control signal line; the pixel circuit comprises: a driving module, a threshold compensation module, a first initialization module and a frequency control module; the threshold compensation module is arranged in a first branch connected between a control end and a second end of the driving module; the first initialization module is arranged in a second branch connected to the control end of the driving module; the frequency control module is connected to the frequency control signal line corresponding to the pixel circuit, and the frequency control module is used to control the on and off of the first branch and the second branch according to the frequency control signal transmitted by the connected frequency control signal line, so as to control the refresh frequency of the pixel circuit;

[0045] A driving component is connected to each of the frequency control signal lines and is used to control the voltage of the frequency control signal transmitted by each of the frequency control signal lines according to the partition frequency information.

[0046] Optionally, the driving assembly comprises:

[0047] A timing controller, used for analyzing the partition frequency information and generating a display control signal;

[0048] A driving chip connected to the timing controller;

[0049] level conversion circuits having the same number as the frequency control signal lines, each of the level conversion circuits being connected to each of the frequency control signal lines in a one-to-one correspondence; each of the level conversion circuits being connected to a first level signal and a second level signal, and being connected to the driving chip; the driving chip being used to control each of the level conversion circuits to output the first level signal or the second level signal according to the display control signal;

[0050] Preferably, the display panel includes a plurality of pixel circuits arranged in an array; the display panel also includes: a gate driving circuit connected to the timing controller and each pixel circuit respectively; the timing controller is further used to control the output of the gate driving circuit so that each row of the pixel circuits enters the scanning stage row by row;

[0051] The driving chip is used to control the voltage of the frequency control signal received by each pixel circuit in a row according to the display control signal during the scanning phase of each row of pixel circuits;

[0052] Preferably, the display panel includes a plurality of frequency control signal lines, one of which is connected to at least one column of pixel circuits; the display control signal includes refresh control signals of the pixel circuits in each row, and the timing controller serially outputs the refresh control signals of the pixel circuits in each row to the driver chip; in a scanning phase of any row of pixel circuits, the driver chip controls the level conversion circuits to transmit frequency control signals to the frequency control signal lines in parallel according to the refresh control signals of the pixel circuits in that row;

[0053] Preferably, the display panel further comprises: a plurality of data lines, connected to each column of pixel circuits one by one; the driving chip is also connected to each of the data lines; the timing controller is also used to control the driving chip to transmit a corresponding data signal to each of the data lines;

[0054] Preferably, the data line and the frequency control signal line extend in the same direction;

[0055] Preferably, at least two pixel circuits in the same row are connected to the same frequency control signal line;

[0056] Preferably, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines;

[0057] Preferably, the display device further comprises: a host connected to the driving component and configured to provide the partition frequency information;

[0058] Preferably, the partition frequency information includes: the number, position and refresh frequency of each display partition in the display area of ​​the display panel;

[0059] Preferably, the display panel comprises a lower frame area and a display area which are sequentially away from the driving chip, the level conversion circuit is arranged in the lower frame area, and the pixel circuit is arranged in the display area;

[0060] Alternatively, the level conversion circuit is integrated into the driver chip;

[0061] Alternatively, the level conversion circuit is arranged in a circuit board for carrying the timing controller.

[0062] Optionally, the pixel circuit is the pixel circuit provided by any embodiment of the first aspect.

[0063] Optionally, the frequency control module includes:

[0064] A third switch unit is connected in series with the threshold compensation module in the first branch, and a control end of the third switch unit is connected to the frequency control signal;

[0065] a fourth switch unit, connected in series with the first initialization module in the second branch, and a control end of the second switch unit is connected to the frequency control signal;

[0066] Preferably, the on-voltage of the third switch unit is the same as the on-voltage of the fourth switch unit;

[0067] Preferably, in any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase which occur successively; in the first initialization phase, the first initialization module is turned on; in the data writing phase, the threshold compensation module is turned on;

[0068] In a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains a turn-on voltage of the third switch unit at least in the first initialization phase and the data writing phase;

[0069] In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switch unit at least in the first initialization phase and the data writing phase;

[0070] Preferably, in a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains a turn-on voltage of the third switch unit in the scanning phase;

[0071] In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switch unit in the scanning phase;

[0072] Preferably, the third switch unit comprises: a tenth transistor, connected in series with the threshold compensation module in the first branch, and a gate of the tenth transistor is connected to the frequency control signal;

[0073] The fourth switch unit comprises: an eleventh transistor, connected in series with the first initialization module in the second branch, and a gate of the eleventh transistor is connected to the frequency control signal;

[0074] Preferably, the tenth transistor and the eleventh transistor have the same channel type.

[0075] In the pixel circuit provided by the embodiment of the present invention, a frequency control module is set to control the on and off of the first branch and the second branch. In the holding frame, the frequency control module controls the first branch and the second branch to be disconnected, so that the threshold compensation module and the first initialization module can be turned on. Then, the first scanning signal and the second scanning signal can maintain the same waveform in the holding frame as in the display frame. Therefore, the embodiment of the present invention does not need to redesign the gate drive circuit for providing the scanning signal. In addition, by setting the frequency control module, the refresh frequency adjustment at the pixel level can be realized, so that the partition position of the display partition with different refresh frequencies in the display panel can be arbitrarily adjusted according to the demand, so that the display panel supports flexible partition and frequency display function.

[0076] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0078] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0079] Figure 2 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0080] Figure 3 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0081] Figure 4 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0082] Figure 5 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0083] Figure 6 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0084] Figure 7 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0085] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0086] Fig. 9 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0087] Fig.10 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0088] Fig.11 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0089] Fig.12 It is a schematic diagram of a display partition structure of a display panel provided by an embodiment of the present invention;

[0090] Fig.13 It is a schematic diagram of the refresh state of each display frame of a display panel in a display cycle provided by an embodiment of the present invention;

[0091] Fig.14 is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0092] Fig.15 is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0093] Fig.16 is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0094] Fig.17 is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0095] Fig.18 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0096] Fig.19 is a structural schematic diagram of another display panel provided by an embodiment of the present invention;

[0097] Fig. 20 It is a schematic structural diagram of a voltage control unit shared by two pixel circuits provided by an embodiment of the present invention;

[0098] Fig.21is a structural schematic diagram of a display device provided by an embodiment of the present invention;

[0099] Fig. 22 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0100] Fig.23 is a schematic structural diagram of another display device provided by an embodiment of the present invention;

[0101] Fig.24 is a structural schematic diagram of another display device provided by an embodiment of the present invention;

[0102] Fig.25 is a structural schematic diagram of another display device provided by an embodiment of the present invention;

[0103] Fig.26 is a schematic diagram of control signals of a display panel in different time periods in a frame provided by an embodiment of the present invention;

[0104] Fig. 27 is a schematic diagram of control signals of another display panel in different time periods in a frame provided by an embodiment of the present invention;

[0105] Fig.28 This is another schematic diagram of control signals of a display panel in different time periods in a frame provided by an embodiment of the present invention;

[0106] Fig.29 is a timing diagram of a frequency control signal provided by an embodiment of the present invention;

[0107] Fig.30 It is a structural schematic diagram of another pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0108] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0109] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0110] As pointed out in the background technology, the display panel in the related art cannot achieve flexible partitioned frequency display, mainly for the following reasons: in the display panel, pixels are arranged in an array, and the display screen usually adopts a refresh mode of row-by-row scanning. In the related art, in order to realize the display of multiple display areas of the display panel at different refresh frequencies, the gate drive circuit (GIP) is usually improved, specifically: the signals transmitted row by row between each GIP are transmitted normally and are not controlled by the partition signal; but a control switch is added to the output stage of each row of GIP, and the control switch is controlled by the partition signal, thereby controlling the frequency of the gate drive signal of each row to achieve partitioned multi-frequency. Since the pixels in the same row of the display panel are controlled by the same gate drive signal, the above scheme can only realize the frequency division display by row partition, and cannot realize the partition by column or other more flexible partitioned frequency division display.

[0111] To solve the above problem, an embodiment of the present invention provides a pixel circuit. Figure 1 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 1 The pixel circuit includes: a driving module 10, a threshold compensation module 20, a first initialization module 30 and a frequency control module 40.

[0112] Among them, the threshold compensation module 20 is arranged in the first branch connected between the control terminal G and the second terminal D of the driving module 10, and the control terminal of the threshold compensation module 20 is connected to the first scanning signal S1; the threshold compensation module 20 is used to turn on or off according to the first scanning signal S1. The first initialization module 30 is arranged in the second branch connected to the control terminal G of the driving module 10, and the control terminal of the first initialization module 30 is connected to the second scanning signal S2; the first initialization module 30 is used to turn on or off according to the second scanning signal S2. The frequency control module 40 is connected to the first branch and the second branch respectively, and is connected to the frequency control signal CCL and the first scanning signal S1; the frequency control module 40 is used to control the on and off of the first branch according to the frequency control signal CCL and the first scanning signal S1, and control the on and off of the second branch according to the frequency control signal CCL, so as to control the refresh frequency of the pixel circuit.

[0113] Exemplarily, the driving module 10 generates a driving current according to the voltage of its control terminal G to drive the light-emitting device OLED to emit light. The control terminal G of the driving module 10 is connected to two branches. Among them, the first branch is connected between the control terminal G and the second terminal D of the driving module 10. When the first branch is turned on, the control terminal G and the second terminal D of the driving module 10 are connected to form a diode connection form, which can make the voltage related to the voltage connected to the first terminal S of the driving module 10 transmitted to the control terminal of the driving module 10. For example, one end of the second branch is connected to the control terminal G of the driving module 10, and the other end is connected to the initialization signal VREF; when the second branch is turned on, the initialization signal can be transmitted to the control terminal G of the driving module 10 to achieve the reset of the control terminal G.

[0114] The scanning phase of each display frame of the pixel circuit may include a first initialization phase and a data writing phase that occur successively: in the first initialization phase, whether the initialization signal VREF is transmitted to the control terminal G of the driving module 10 can be controlled by controlling whether the second branch is turned on; in the data writing phase, whether the voltage related to the data signal Vdata is transmitted to the control terminal G of the driving module 10 can be controlled by controlling whether the first branch is turned on. Among them, in the display frame in which the pixel circuit performs data refresh, that is, the writing frame, the second branch needs to be controlled to be turned on in the first initialization phase to achieve the reset of the control terminal G of the driving module 10, and the first branch needs to be controlled to be turned on in the data writing phase to achieve the data writing to the control terminal G of the driving module 10, thereby completing the data refresh. In the display frame in which the pixel circuit performs data retention, that is, the retention frame, the second branch needs to be controlled to be disconnected in the first initialization phase, and the first branch needs to be controlled to be disconnected in the data writing phase, so that the voltage of the control terminal G of the driving module 10 is not changed in the display frame to achieve data retention.

[0115] Exemplarily, the refresh frequency control principle of the pixel circuit is:

[0116] In the display frame (writing frame) in which the pixel circuit performs data refresh, in the first initialization stage, the frequency control signal CCL controls the structure of the frequency control module 40 connected to the second branch to be turned on, so that the on-off state of the second branch is controlled by the on-off state of the first initialization module 30. At this time, the second scanning signal S2 controls the first initialization module 30 to be turned on, so that the second branch can be turned on, thereby resetting the control terminal G of the driving module 10; in the data writing stage, the frequency control signal CCL cooperates with the first scanning signal S1 to control the structure of the frequency control module 40 connected to the first branch to be turned on, so that the on-off state of the first branch is controlled by the on-off state of the threshold compensation module 20. At this time, the first scanning signal S1 controls the threshold compensation module 20 to be turned on, so that the first branch can be turned on, thereby writing data to the control terminal G of the driving module 10.

[0117] In the display frame (holding frame) in which the pixel circuit holds data, in the first initialization stage, the frequency control signal CCL controls the structure of the frequency control module 40 connected to the second branch to be disconnected, so that the second branch is directly disconnected. At this time, regardless of whether the first initialization module 30 is turned on or not, the second branch remains disconnected, and the initialization signal VREF cannot be transmitted to the control terminal G of the driving module 10. Therefore, in this stage, the second scanning signal S2 can control the first initialization module 30 to be turned on; in the data writing stage, the frequency control signal CCL cooperates with the first scanning signal S1 to control the structure of the frequency control module 40 connected to the first branch to be disconnected, so that the first branch is directly disconnected. At this time, regardless of whether the threshold compensation module 20 is turned on or not, the first branch remains disconnected, and data cannot be written to the control terminal G of the driving module 10. Therefore, in this stage, the first scanning signal S1 can control the threshold compensation module 20 to be turned on.

[0118] Exemplarily, the frequency control signal CCL can directly control the on-off of the structure connected to the frequency control module 40 in the second branch. The first scanning signal S1 can control whether the frequency control signal CCL is transmitted to the internal node of the frequency control module 40, thereby controlling the on-off of the structure connected to the frequency control module 40 in the first branch; when the first scanning signal S1 controls the frequency control signal CCL to be transmitted to the internal node of the frequency control module 40, the voltage of the internal node is equal to the voltage of the frequency control signal CCL; when the first scanning signal S1 controls the frequency control signal CCL to be unable to be transmitted to the internal node of the frequency control module 40, the internal node maintains the voltage and does not change with the voltage of the frequency control signal CCL. In this way, by setting the internal node of the frequency control module 40 to have a stage where the voltage does not change with the frequency control signal CCL, the refresh frequency control of the pixel circuit can be made more flexible. For example, in the data writing stage of the holding frame, the internal nodes of the frequency control module 40 can be controlled by the first scanning signal S1 to maintain the voltage, then the frequency control signal CCL can perform voltage jumps in the data writing stage without affecting the on-off state of the structure connected to the first branch by the frequency control module 40, so that the first branch can remain disconnected; and in the data writing stage, since the second scanning signal S2 has controlled the first initialization module 30 to turn off, the second branch is disconnected, even if the frequency control signal CCL jumps to change the on-off state of the structure connected to the second branch by the frequency control module 40, it will not affect the on-off state of the second branch, and the second branch remains disconnected. In this way, compared with directly controlling the on-off state of the structure connected to the first branch and the second branch by the frequency control signal CCL, the voltage jump of the frequency control signal CCL can be made more flexible, and the frequency control signal CCL can perform voltage jumps in the data writing stage. Especially for the case where a column of pixel circuits is connected to the same frequency control signal CCL, if the pixel circuits belonging to the current row need to maintain data and the pixel circuits belonging to the next row need to refresh data, the frequency control signal CCL can be controlled to perform a voltage jump during the data writing phase of the current row, without having to wait for the data writing phase of the current row to be completed before performing a voltage jump. This allows the scanning phases of the pixel circuits in adjacent rows to overlap in time, and the pixel circuits belonging to the next row can also achieve data refresh normally, which is beneficial to shortening the frame time.

[0119] From the above analysis, it can be known that by controlling the on-off state of the frequency control module 40 in each branch according to the frequency control signal CCL and the first scanning signal S1, it is possible to control whether the pixel circuit performs data refresh in each display frame; by controlling the frequency of data refresh of the pixel circuit, or in other words, by controlling the number of frames maintained by the pixel circuit between two adjacent write frames, the refresh frequency of the pixel circuit can be adjusted.

[0120] In the pixel circuit provided by the embodiment of the present invention, a frequency control module 40 is provided to control the on and off of the first branch and the second branch. In the holding frame, the frequency control module 40 controls the first branch and the second branch to be disconnected, so that the threshold compensation module 20 and the first initialization module 30 can be turned on. Then, the first scanning signal S1 and the second scanning signal S2 can maintain the same waveform in the holding frame as in the display frame. Therefore, the embodiment of the present invention does not need to redesign the gate drive circuit for providing the scanning signal. In addition, by providing the frequency control module 40, the refresh frequency adjustment at the pixel level can be realized, so that the partition position of the display partition with different refresh frequencies in the display panel can be adjusted arbitrarily according to the demand, so that the display panel supports flexible partition and frequency display function.

[0121] Figure 2 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 2 On the basis of the above embodiments, optionally, the frequency control module 40 includes: a first switch unit 410 , a second switch unit 420 and a voltage control unit 430 .

[0122] Among them, the first switch unit 410 is connected in series with the threshold compensation module 20 in the first branch; the first switch unit 410 is used to turn on or off according to the voltage of its control end. The control end K of the first switch unit 410 is the internal node of the frequency control module 40. The second switch unit 420 is connected in series with the first initialization module 30 in the second branch, and the control end of the second switch unit 420 is connected to the frequency control signal CCL; the second switch unit 420 is used to turn on or off according to the frequency control signal CCL. The voltage control unit 430 is connected to the control end K of the first switch unit 410, and is connected to the frequency control signal CCL and the first scanning signal S1; the voltage control unit 430 is used to control whether the frequency control signal CCL is transmitted to the control end K of the first switch unit 410 according to the first scanning signal S1.

[0123] Specifically, when the first switch unit 410 is turned off, the first branch is disconnected; when the first switch unit 410 is turned on, the on-off state of the first branch is controlled by the threshold compensation module 20. When the second switch unit 420 is turned off, the second branch is disconnected; when the second switch unit 420 is turned on, the on-off state of the second branch is controlled by the first initialization module 30. When the voltage control unit 430 is turned on, the voltage of the frequency control signal CCL is written to the control terminal K of the first switch unit 410; when the voltage control unit 430 is turned off, the voltage of the control terminal K of the first switch unit 410 maintains the voltage written to the control terminal K before the voltage control unit 430 is turned off.

[0124] Exemplarily, the on-voltage of the first switch unit 410 is the same as the on-voltage of the second switch unit 420, for example, both are low voltages or both are high voltages. When the first scan signal S1 is the cut-off voltage of the threshold compensation module 20, the control voltage control unit 430 is turned on to transmit the frequency control signal CCL to the control terminal K of the first switch unit 410; when the first scan signal S1 is the on-voltage of the threshold compensation module 20, the control voltage control unit 430 is turned off to maintain the voltage at the control terminal K of the first switch unit 410.

[0125] In the following, the conduction voltages of the first switch unit 410, the second switch unit 420, the first initialization module 30 and the threshold compensation module 29 are all high voltages, and the conduction voltage of the voltage control unit 430 is low voltage. Figure 3-Figure 6 , the driving process of the pixel circuit is explained.

[0126] See also Figure 2-Figure 6 In any display frame, the scanning phase of the pixel circuit includes a first initialization phase T11 and a data writing phase T12 that occur successively. In the first initialization phase T11, the second scanning signal S2 is the on-voltage of the first initialization module 30, which controls the first initialization module 30 to be turned on, so that the on-off of the second branch is controlled by the second switch unit 420; in the data writing phase T12, the first scanning signal S1 is the on-voltage of the threshold compensation module 20, which controls the threshold compensation module 20 to be turned on, so that the on-off of the first branch is controlled by the first switch unit 410.

[0127] In the display frame (holding frame) in which the pixel circuit holds data, the period in which the frequency control signal CCL holds the cut-off voltage of the second switch unit 420 at least covers the start time of the first initialization phase T11 and the data writing phase T12. In this way, it can be ensured that in the frame, in the first initialization stage T11, the frequency control signal CCL controls the second switch unit 420 to be turned off, so that the second branch is disconnected, and the initialization signal VREF does not reset the control terminal G of the driving module 10; and before the start of the data writing stage T12, the first scanning signal S1 controls the voltage control unit 430 to be turned on, and the frequency control signal CCL with the cut-off voltage of the second switch unit 420 can be transmitted to the control terminal K of the first switch unit 410 to control the first switch unit 410 to be turned off. After the start of the data writing stage T12, the first scanning signal S1 controls the voltage control unit 430 to be turned off, and the control terminal K of the first switch unit 410 can maintain the cut-off voltage of the second switch unit 420 (which is also the cut-off voltage of the first switch unit 410), so that the first branch maintains a cut-off state in the data writing stage T12, and no data is written to the control terminal G of the driving module 10.

[0128] Specifically, in the period between the first initialization stage T11 and the data writing stage T12, the voltage of the frequency control signal CCL can be set arbitrarily. For example, the frequency control signal CCL can be set to maintain the cut-off voltage of the second switch unit 420 at least in the period from the beginning of the first initialization stage T11 to the beginning of the data writing stage T12, so as to reduce the voltage jump of the frequency control signal CCL. For example, see Figure 3 , the frequency control signal CCL can be set to maintain the cut-off voltage of the second switch unit 420 before the first initialization phase T11 starts and until the data writing phase T12 ends, so the voltage VK of the control terminal K of the first switch unit 410 is the same as the waveform of the frequency control signal CCL. Or, see Figure 4 , the frequency control signal CCL can be set to maintain the cut-off voltage of the second switch unit 420 during the period from the beginning of the first initialization stage T11 to the beginning of the data writing stage T12, and jump to the turn-on voltage of the second switch unit 420 during the data writing stage T12. Then, the voltage VK of the control terminal K of the first switch unit 410 follows the voltage change of the frequency control signal CCL before the data writing stage T12, maintains the cut-off voltage of the second switch unit 420 in the data writing stage T12, and follows the frequency control signal CCL to change the voltage again at the end of the data writing stage T12.

[0129] In a display frame (writing frame) in which the pixel circuit performs data refresh, the period in which the frequency control signal CCL maintains the on-voltage of the second switch unit 420 at least covers the start time of the first initialization phase T11 and the data writing phase T12. In this way, it can be ensured that in the write frame, in the first initialization stage T11, the frequency control signal CCL controls the second switch unit 420 to be turned on, so that the second branch is turned on, and the initialization signal VREF resets the control terminal G of the driving module 10; and before the start of the data writing stage T12, the first scanning signal S1 controls the voltage control unit 430 to be turned on, and the frequency control signal CCL with the turn-on voltage of the second switch unit 420 can be transmitted to the control terminal K of the first switch unit 410 to control the turn-on of the first switch unit 410. After the start of the data writing stage T12, the first scanning signal S1 controls the voltage control unit 430 to be turned off, and the control terminal K of the first switch unit 410 can maintain the turn-on voltage of the second switch unit 420 (which is also the turn-on voltage of the first switch unit 410), so that the first branch maintains the on state in the data writing stage T12, and data is written to the control terminal G of the driving module 10.

[0130] Specifically, in the period between the first initialization stage T11 and the data writing stage T12, the voltage of the frequency control signal CCL can be set arbitrarily. For example, the frequency control signal CCL can be set to maintain the on-voltage of the second switch unit 420 at least in the period from the beginning of the first initialization stage T11 to the beginning of the data writing stage T12, so as to reduce the voltage jump of the frequency control signal CCL. For example, see Figure 5 , the frequency control signal CCL can be set to maintain the on-voltage of the second switch unit 420 before the first initialization phase T11 starts and until the data writing phase T12 ends, so the voltage VK at the control terminal K of the first switch unit 410 is the same as the waveform of the frequency control signal CCL. Or, see Figure 6 , the frequency control signal CCL can be set to maintain the on-voltage of the second switch unit 420 during the period from the beginning of the first initialization stage T11 to the beginning of the data writing stage T12, and jump to the cut-off voltage of the second switch unit 420 during the data writing stage T12. Then, the voltage VK of the control terminal K of the first switch unit 410 follows the voltage change of the frequency control signal CCL before the data writing stage T12, maintains the on-voltage of the second switch unit 420 in the data writing stage T12, and follows the frequency control signal CCL for voltage change again at the end of the data writing stage T12.

[0131] In the above-mentioned embodiments, the refresh frequency control process of the pixel circuit is explained. The specific structure that the pixel circuit may have is exemplarily described below, but it is not intended to limit the present invention.

[0132] Figure 7 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 7 In one implementation, optionally, the first switch unit 410 includes: a first transistor M1, the first transistor M1 and the threshold compensation module 20 are connected in series in the first branch, and the gate of the first transistor M1 is connected to the control terminal K of the first switch unit 410. In this embodiment, the first switch unit 410 is configured to be composed of one transistor, so that its structure is simple and easy to implement.

[0133] In one embodiment, optionally, the second switch unit 420 includes: a second transistor M2, the second transistor M2 is connected in series with the first initialization module 30 in the second branch, and the gate of the second transistor M2 is connected to the frequency control signal CCL. In this embodiment, the second switch unit 420 is configured to be composed of one transistor, so that its structure is simple and easy to implement.

[0134] In one implementation, optionally, the voltage control unit 430 includes: a third transistor M3, a gate of the third transistor M3 is connected to the first scan signal S1, a first electrode of the third transistor M3 is connected to the frequency control signal CCL, and a second electrode of the third transistor M3 is connected to the control terminal K of the first switch unit 410. In this embodiment, the voltage control unit 430 is configured to be composed of one transistor, so that its structure is simple and easy to implement.

[0135] Furthermore, the voltage control unit 430 also includes: a first capacitor C1, a first end of the first capacitor C1 is connected to the control end K of the first switch unit 410, and a second end of the first capacitor C1 is connected to the fixed voltage signal VDC. By setting the first capacitor C1, when the third transistor M3 is disconnected, the voltage of the control end K of the first switch unit 410 can be maintained to improve the working stability of the circuit.

[0136] Figure 8 is a schematic diagram of the structure of another pixel circuit provided by an embodiment of the present invention. Figure 8 On the basis of the above embodiments, optionally, the threshold compensation module 20 includes: a fourth transistor M4, the fourth transistor M4 is connected in series with the first switch unit 410 in the first branch, and the gate of the fourth transistor M4 is connected to the first scanning signal S1. The first initialization module 30 includes: a fifth transistor M5, the fifth transistor M5 is connected in series with the second switch unit 420 in the second branch, and the gate of the fifth transistor M5 is connected to the second scanning signal S2.

[0137] On the basis of the above embodiments, optionally, the channel types of the first transistor M1 and the second transistor M2 may be set to be the same, so that the on-voltage of the first switch unit 410 is the same as the on-voltage of the second switch unit 420. The channel types of the third transistor M3 and the fourth transistor M4 may be set to be different, so that the on-voltage source of the threshold compensation module 20 and the cut-off voltage of the voltage control unit 430 are the same, so that the gate of the third transistor M3 and the gate of the fourth transistor M4 can both be connected to the first scan signal S1, and the on-off states are different.

[0138] Further, the channel types of the first transistor M1, the second transistor M2, the fourth transistor M4 and the fifth transistor M5 can be set to be the same, so that the turn-on voltages of the first switch unit 410, the second switch unit 420, the threshold compensation module 20 and the first initialization module 30 are the same.

[0139] On the basis of the above embodiments, optionally, the first transistor M1, the second transistor M2, the fourth transistor M4 and the fifth transistor M5 can be set to be N-type transistors, such as IGZO-type transistors, to reduce leakage on the first branch and the second branch; correspondingly, the third transistor M3 can be set to be a P-type transistor, such as an LTPS transistor.

[0140] Continue to see Figure 8 On the basis of the above embodiments, optionally, the driving module 10 includes: a driving transistor DTFT, a gate of the driving transistor DTFT connected to a control terminal G of the driving module 10, a first electrode of the driving transistor DTFT connected to a first terminal S of the driving module 10, and a second electrode of the driving transistor DTFT connected to a second terminal D of the driving module 10.

[0141] And, the pixel circuit may also include: a data writing module 50, a light emitting control module 60, a second initialization module 70 and a storage module 80. The data writing module 50 includes a sixth transistor M6; the gate of the sixth transistor M6 is connected to the third scanning signal S3, the first electrode of the sixth transistor M6 is connected to the data signal Vdata, and the second electrode of the sixth transistor M6 is connected to the first end S of the driving module 10. The light emitting control module 60 includes a seventh transistor M7 and an eighth transistor M8; the gate of the seventh transistor M7 and the gate of the eighth transistor M8 are both connected to the light emitting control signal EM, the first electrode of the seventh transistor M7 is connected to the first power supply signal VDD, the second electrode of the seventh transistor M7 is connected to the first end S of the driving module 10, the first electrode of the eighth transistor M8 is connected to the second end D of the driving module 10, the second electrode of the eighth transistor M8 is connected to the anode of the light emitting device OLED, and the cathode of the light emitting device OLED is connected to the second power supply signal VSS. The second initialization module 70 includes a ninth transistor M9; the gate of the ninth transistor M9 is connected to the fourth scanning signal S4, the first electrode of the ninth transistor M9 is connected to the initialization signal VREF, and the second electrode of the ninth transistor M9 is connected to the anode of the light emitting device OLED. The storage module 80 includes a storage capacitor Cst; a first end of the storage capacitor Cst is connected to the first power signal VDD, and a second end of the storage capacitor Cst is connected to the control terminal G of the driving module 10. The voltages of the first power signal VDD and the second power signal VSS are different, for example, the first power signal VDD is a high voltage, and the second power signal VSS is a low voltage.

[0142] Exemplarily, the first transistor M1, the second transistor M2, the fourth transistor M4 and the fifth transistor M5 are all N-type transistors, such as IGZO transistors; the other transistors in the pixel circuit are all P-type transistors, such as LTPS transistors. In this way, an LTPO pixel circuit can be formed, which can take into account the advantages of low leakage current of N-type transistors and good stability of P-type transistors, which is conducive to improving display effects.

[0143] Based on the above embodiments, optionally, any one of the initialization signal VREF, the first power signal VDD and the second power signal VSS can be multiplexed as a fixed voltage signal connected to the second end of the first capacitor C1 to avoid introducing additional DC voltage signals and simplify the display panel wiring.

[0144] Figure 8 The driving timing of the pixel circuit shown in the writing frame can be seen in Fig. 9 , while maintaining the frame drive timing, see Fig.10 . Fig. 9 and Fig.10 In the figure, L1 represents the first branch, L2 represents the second branch, the shaded filling represents the branch is disconnected, and the blank filling represents the branch is on. Figure 8-Figure 10 , the driving process of the pixel circuit in each display frame includes: a scanning stage T1 and a light-emitting stage T2. The scanning stage T1, for example, includes a stage in which the light-emitting control signal EM maintains the cut-off potential of the light-emitting control module 60. In the scanning stage T1, in addition to the first initialization stage T11 and the data writing stage T12, a second initialization stage T13 may also be included. In the second initialization stage T13, the fourth scanning signal S4 controls the second initialization module 70 to be turned on so that the initialization signal VREF resets the anode of the light-emitting device OLED. The second initialization stage T13 can be set at any position in the scanning stage T1, for example Fig. 9 and Fig.10 As shown, it is set between the first initialization stage T11 and the data writing stage T12, or it can also overlap at least partially with any stage of the first initialization stage T11 and the data writing stage T12 in time. It can be understood that in the data writing stage T12, the third scanning signal S3 controls the data writing module 50 to be turned on, so that the data signal Vdata is transmitted to the first terminal S of the driving module 10; in the light-emitting stage T2, the light-emitting control signal EM controls the light-emitting control module 60 to be turned on, so that the driving module 10 generates a driving current according to the voltage of its control terminal G, and drives the light-emitting device OLED to emit light.

[0145] See also Fig. 9 and Fig.10 It can be seen that in the driving process of the pixel circuit, no matter writing a frame or holding a frame, the waveforms of the scanning signals and the light-emitting control signal EM are consistent, and are all high-frequency signals. By controlling the voltage of the frequency control signal CCL, the on-off of the first branch and the second branch can be controlled, thereby controlling whether the pixel circuit performs data refresh in the display frame. For details, see Fig. 9In the writing frame, the frequency control signal CCL can be set to maintain the on-voltage (herein, a high voltage) of the second switch unit 420 at least in the first initialization phase T11 and around the start time of the data writing phase, so as to ensure that the second branch L2 is turned on in the first initialization phase T11 and the first branch L1 is turned on in the data writing phase T12. Fig.10 In the hold frame, the frequency control signal CCL can be set to maintain the cut-off voltage (here exemplarily a low voltage) of the second switch unit 420 at least in the first initialization phase T11 and around the start time of the data writing phase to ensure that the second branch L2 remains turned off in the display frame and the first branch L1 also remains turned off in the display frame.

[0146] In summary, the embodiments of the present invention provide a novel pixel circuit that helps to realize multi-frequency partitioning of any area of ​​a display panel, and can flexibly control the refresh frequency of the pixel circuit based on the frequency control signal CCL and the first scanning signal S1.

[0147] An embodiment of the present invention further provides a display panel, including the pixel circuit provided by any embodiment of the present invention, and having corresponding beneficial effects.

[0148] Fig.11 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Fig.11 , the display panel 1000 may include a plurality of pixel circuits 100, and the plurality of pixel circuits 100 may be arranged in an array in the display area AA of the display panel 1000. The display panel 1000 may also include a non-display area NAA surrounding the display area AA. In addition, a gate driving circuit 200 and a gate line extending along a row direction may also be provided in the display panel 1000; the gate driving circuit 200 is provided in the non-display area NAA, and the gate driving circuit 200 is connected to the gate line to provide a corresponding gate driving signal to the pixel circuit 100 connected to the gate line; the gate driving signal includes, for example, various scanning signals and light emitting control signals. Fig.11 The first gate line LS1 for transmitting the first scanning signal S1 and the second gate line LS2 for transmitting the second scanning signal S2 are exemplarily shown in FIG. 1 , but this is not intended to limit the present invention. In practical applications, the pixel circuit 100 has Figure 8 Taking the structure shown in the figure as an example, the display panel may also be provided with a third gate line for transmitting a third scanning signal S3, a fourth gate line for transmitting a fourth scanning signal S4, and a fifth gate line for transmitting a light emitting control signal EM. The gate driving circuit 200 may specifically include a scanning circuit for providing a scanning signal and a light emitting control circuit for providing a light emitting control signal. Specifically, the pixel circuit 100 is still provided with Figure 8Taking the structure shown as an example, the gate drive circuit 200 may include: a first scanning circuit for providing a first scanning signal S1 and a second scanning signal S2; a second scanning circuit for providing a third scanning signal S3 and a fourth scanning signal S4; and a light-emitting control circuit for providing a light-emitting control signal EM. The first scanning circuit uses a set of power supply voltages, and the second scanning circuit and the light-emitting control circuit can use another set of power supply voltages. The specific structure of the gate drive circuit 200 is not limited here, and it can provide the required gate drive signals to the pixel circuit according to the driving requirements of the pixel circuit 100.

[0149] On the basis of the above embodiments, optionally, the display panel 1000 further includes: at least one frequency control signal line LC. Each frequency control signal line LC is connected to each pixel circuit 100 to transmit a frequency control signal CCL to the pixel circuit 100. At least one column of pixel circuits 100 is connected to the same frequency control signal line LC, and the frequency control signal line LC is used to provide the frequency control signal CCL to the connected pixel circuit 100.

[0150] Furthermore, the display panel 1000 further includes: a plurality of data lines LD, each of which is connected to each column of pixel circuits 100 in a one-to-one correspondence; the data lines LD are used to transmit data signals Vdata. Exemplarily, the data lines LD and the frequency control signal lines LC extend in the same direction, for example, in the column direction, and the row direction is perpendicular to the column direction.

[0151] In the display panel, each row of pixel circuits 100 is scanned row by row, and the frequency control signal is supplied by column. Then, in the scanning stage of each row of pixel circuits 100, the frequency control signal CCL received by the pixel circuits 100 belonging to each column in a row can be set according to the display requirements to control whether each pixel circuit 100 in a row performs data refresh. Then, through the refresh frequency control at the pixel level, the partition of any position of the display panel 1000 can be realized, and each display partition can be displayed at different refresh frequencies. It can be understood that, with the highest pulse frequency of the gate drive signal that the gate drive circuit 200 can provide as the basic frequency, the refresh frequency of each display partition does not exceed the basic frequency; and the pixel circuit of the embodiment of the present invention realizes frequency adjustment by controlling the number of holding frames inserted between adjacent write frames, and the refresh frequency of each display partition is a frequency that can divide the basic frequency. The refresh frequency of the pixel circuits in each display partition can be controlled separately, and each pixel circuit 100 in the same display partition refreshes data at the refresh frequency of the display partition, and there is no size relationship between the refresh frequencies of the display partitions.

[0152] The following takes the example that each column of pixel circuits 100 is connected to a frequency control signal line LC and each frequency control signal line LC is insulated from each other to explain the process of displaying at different frequencies in different regions of the display panel 1000. Fig.12 , taking the three-partition display panel as an example, the display area AA of the display panel includes the first display partition A1, the second display partition A2 and the third display partition A3. Assume that the refresh frequencies of the first display partition A1, the second display partition A2 and the third display partition A3 decrease in sequence. For example, taking 120Hz as the base frequency, the refresh frequency of the first display partition A1 is 120Hz, the refresh frequency of the second display partition A2 is 60Hz, and the refresh frequency of the third display partition A3 is 40Hz. Then, for the pixel circuit in the first display partition A1, each display frame is a refresh frame; for the pixel circuit in the second display partition A2, one hold frame can be inserted between every two adjacent refresh frames; for the pixel circuit in the third display partition A3, two hold frames can be inserted between every two adjacent refresh frames. Specifically, see Fig.13 , six display frames (F1-F6) can be used as one display cycle, and the control process of one display cycle can be used as one cycle to repeatedly control each frequency control signal CCL. It can be understood that Fig.13 In the display, the partition division method is the same as Fig.12 Similarly, each number arranged in the array represents a pixel circuit, 0 indicates that the pixel circuit is maintaining data in the display frame, and 1 indicates that the pixel circuit is refreshing data in the display frame. For any pixel circuit, in its scanning phase, if the pixel circuit needs to maintain data, the frequency control signal CCL needs to cooperate with the first scanning signal S1, so that the frequency control module controls the second branch to be disconnected at least in the first initialization phase, and controls the first branch to be disconnected at least in the data writing phase; if the pixel circuit needs to refresh data, the frequency control signal CCL needs to cooperate with the first scanning signal S1, so that the frequency control module controls the second branch to be turned on in the first initialization phase, and controls the first branch to be turned on in the data writing phase.

[0153] Combine the following Fig.14 and Fig.15 , the control process of the boundary positions of different display partitions along the column direction is described. Exemplarily, along the column direction, the last row of pixel circuits of the previous display partition belongs to the nth row of pixel circuits, and the first row of pixel circuits of the next display partition belongs to the n+1th row of pixel circuits, where n is a positive integer. Fig.14 and Fig.15The first scanning signal S1n of the nth row, the second scanning signal S2n of the nth row, the first scanning signal S1n+1 of the n+1th row, the second scanning signal S2n+1 of the n+1th row, a column of frequency control signals CCL, the voltage VKn of the control end of the first switch unit in the pixel circuit belonging to the nth row in the same column, and the voltage VKn+1 of the control end of the first switch unit in the pixel circuit belonging to the n+1th row in the same column. The voltage of the frequency control signal CCL can represent the on-off of the second branch, and the voltage of the control end of the first switch unit can represent the on-off of the first branch.

[0154] Then, see Fig.14 , when the pixel circuit in the previous display partition needs to maintain data and the pixel circuit in the next display partition needs to refresh data: it is necessary to control the frequency control signal CCL to jump from the cut-off voltage of the second switch unit to the on-voltage of the second switch unit at the beginning or after the data writing phase T12n of the pixel circuit in the nth row, so that when entering the data writing phase T12n of the pixel circuit in the nth row, the voltage VKn at the control end of the first switch unit in the pixel circuit in the nth row that receives the frequency control signal CCL is the cut-off voltage of the second switch unit (equal to the cut-off voltage of the first switch unit), and maintain the cut-off voltage in the data writing phase T12n of the pixel circuit in the nth row. Preferably, it can be set to control the frequency control signal CCL to perform voltage jump after the data writing phase T12n of the pixel circuit in the nth row starts, so as to avoid abnormal driving of the pixel circuit belonging to the nth row in a column due to voltage jump delay and other reasons when the first scanning signal S1n of the nth row and the frequency control signal CCL jump at the same time.

[0155] Furthermore, it is necessary to control the frequency control signal CCL to jump from the cut-off voltage of the second switch unit to the on-voltage of the second switch unit at the beginning or before the beginning of the first initialization stage T11n+1 of the pixel circuit in the n+1th row, so that in the first initialization stage T11n+1 of the pixel circuit in the n+1th row, the second switch unit in the pixel circuit receiving the frequency control signal CCL in the n+1th row is turned on, and then the second branch is turned on, so as to achieve the reset of the control end of the driving module. For the first branch in the pixel circuit receiving the frequency control signal CCL in the n+1th row, even if the voltage Vkn+1 of the control end of the first switch unit jumps to the on-voltage of the second switch unit (equal to the on-voltage of the first switch unit) in the first initialization stage T11n+1 of the pixel circuit in the n+1th row, the first switch unit is controlled to be turned on, because the threshold compensation module is not turned on in this stage, the first branch will not be turned on, and the reset process of the control end of the driving module will not be affected.

[0156] See also Fig.15, when the pixel circuit in the previous display partition needs to refresh data and the pixel circuit in the next display partition needs to retain data: it is necessary to control the frequency control signal CCL to jump from the on-voltage of the second switch unit to the off-voltage of the second switch unit at the beginning or after the data writing phase T12n of the nth row pixel circuit and at the beginning or before the first initialization phase T11n+1 of the n+1th row pixel circuit, so that in a column of pixel circuits receiving the frequency control signal CCL, the pixel circuits belonging to the nth row refresh data normally, and the pixel circuits belonging to the n+1th row retain data normally.

[0157] In summary, in the case where the scanning phases of two adjacent rows of pixel circuits overlap, the pixel circuit and display panel structure provided by any of the above embodiments can be used to normally implement any setting of the number, position and size of partitions.

[0158] In the case where the pulse width of the conduction pulse used by the first scanning signal to control the threshold compensation module to conduct covers multiple line times, the pixel circuit and display panel structure provided by any of the above embodiments can also normally realize any partition number, partition position and partition size setting. Specifically, Fig.16 and Fig.17 exemplarily shows the first scanning signal S1n of the nth row to the scanning signal S1n+4 of the n+4th row, it can be seen that the pulse width of the conduction pulse (pulse with high voltage) in each first scanning signal is relatively wide, and there is overlap between the data writing stages of adjacent rows; Fig.16 and Fig.17 A column of frequency control signals CCL and the on / off states of the first branches (L1n to L1n+4) in each pixel circuit belonging to the nth row to the n+4th row in a column of pixel circuits connected to the frequency control signal CCL are also given. Exemplarily, along the column direction, the last row of pixel circuits in the previous display partition belongs to the n+3th row of pixel circuits, and the first row of pixel circuits in the next display partition belongs to the n+4th row of pixel circuits, where n is a positive integer. Fig.16, when the pixel circuit in the previous display partition needs to maintain data and the pixel circuit in the next display partition needs to refresh data: it is necessary to set the moment t01 when the frequency control signal CCL jumps from the cut-off voltage of the second switch unit to the on-voltage of the second switch unit, at or after the start of the data writing phase T12n+3 of the pixel circuit in the n+3th row, and before the start of the data writing phase T12n+4 of the pixel circuit in the n+4th row, so that the control terminal voltage of the first switch unit in the pixel circuit belonging to the n+3th row maintains the cut-off voltage of the first switch unit in the data writing phase T12n+3 of the pixel circuit in the n+3th row, and the control terminal voltage of the first switch unit in the pixel circuit belonging to the n+4th row maintains the on-voltage of the first switch unit in the data writing phase T12n+4 of the pixel circuit in the n+4th row. Similarly, refer to Fig.17 , when the pixel circuit in the previous display partition needs to refresh data and the pixel circuit in the next display partition needs to maintain data: it is necessary to set the moment t02 when the frequency control signal CCL jumps from the on-voltage of the second switch unit to the off-voltage of the second switch unit, at the beginning or after the data writing phase T12n+3 of the pixel circuit in the n+3th row, and before the beginning of the data writing phase T12n+4 of the pixel circuit in the n+4th row.

[0159] In the above-mentioned embodiments, the frequency control signal line LC is exemplarily connected to each column of the pixel circuit 100 in a one-to-one correspondence, but it is not intended to limit the present invention. In other embodiments, at least two pixel circuits 100 in the same row may be optionally connected to the same frequency control signal line LC to reduce the number of frequency control signal lines LC, which is conducive to simplifying the display panel wiring. It can be understood that the refresh frequencies of the pixel circuits connected to the same frequency control signal line LC in the same row change synchronously. In practical applications, the number and position of the pixel circuits connected to the same frequency control signal line LC in the same row can be set by comprehensively considering the wiring difficulty and the partition control accuracy.

[0160] On the basis of the above-mentioned embodiments, optionally, a pixel circuit 100 connected to the same frequency control signal line LC in the same row can be selected according to the pixel arrangement in the display panel 1000. Specifically, the display panel 1000 includes a plurality of pixel units, each pixel unit includes at least two pixel circuits 100; in the same row, each pixel circuit 100 belonging to the same pixel unit can be connected to the same frequency control signal line LC, and different pixel circuits 100 belonging to different pixel units can be connected to different frequency control signal lines LC. This arrangement allows the refresh frequency of the same pixel unit to change synchronously, which is equivalent to realizing frequency setting and partition setting at the pixel unit level. Since each pixel circuit 100 in the same pixel unit itself needs to display at the same refresh frequency, this arrangement of the present embodiment is equivalent to simplifying the wiring of the display panel without affecting the partition control accuracy. For example, see Fig.18 In the case of Real RGB pixel arrangement, three pixel circuits 100 in a row may share a frequency control signal line LC; or, see Fig.19 In the case of SPR pixel arrangement, two pixel circuits 100 in a row may share a frequency control signal line LC. It is understandable that Fig.18 and Fig.19 In the figure, R represents a pixel circuit driving a red sub-pixel, G represents a pixel circuit driving a green sub-pixel, and B represents a pixel circuit driving a blue sub-pixel.

[0161] On the basis of the above embodiments, optionally, in the pixel circuit 100, the frequency control module includes a first switch unit, a second switch unit and a voltage control unit. At least two pixel circuits 100 in the same row may share the same voltage control unit to further simplify the panel structure. Exemplarily, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits 100; in the same row, the pixel circuits 100 belonging to the same pixel unit share the same voltage control unit. Specifically, see Fig. 20 Taking two pixel circuits sharing the same voltage control unit 430 as an example, the control ends of the first switch units in the pixel circuits sharing the same voltage control unit 430 are connected together and connected to the third transistor M3; and the control ends of the second switch units in the pixel circuits sharing the same voltage control unit 430 are connected to the same frequency control signal line LC.

[0162] The embodiment of the present invention further provides a display device, which can realize flexible zone-by-zone and frequency-by-frequency display. Fig.21 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. Fig.21The display device includes: a display panel 1000 and a driving component 2000. The display panel 1000 includes a plurality of pixel circuits 100 and at least one frequency control signal line LC. Fig. 22 , the pixel circuit 100 includes: a driving module 10, a threshold compensation module 20, a first initialization module 30 and a frequency control module 40; the threshold compensation module 20 is arranged in the first branch connected between the control terminal G and the second terminal D of the driving module 10; the first initialization module 30 is arranged in the second branch connected to the control terminal G of the driving module 10; the frequency control module 40 is connected to the frequency control signal line LC corresponding to the pixel circuit 100, and the frequency control module 40 is used to control the on and off of the first branch and the second branch according to the frequency control signal CCL transmitted by the connected frequency control signal line LC, so as to control the refresh frequency of the pixel circuit 100. The driving component 2000 is connected to each frequency control signal line LC, and the driving component 2000 is used to control the voltage of the frequency control signal CCL transmitted by each frequency control signal line LC according to the partition frequency information SF.

[0163] Exemplarily, when the frequency control signal CCL is the cut-off voltage of the frequency control module 40, the frequency control module 40 controls both the first branch and the second branch to be disconnected; when the frequency control signal CCL is the on-voltage of the frequency control module 40, the frequency control module 40 controls the on-off of the first branch to be controlled by the threshold compensation module 20, and the on-off of the second branch to be controlled by the first initialization module 30.

[0164] In the display device provided by the embodiment of the present invention, a frequency control module 40 is provided to control the on / off of the first branch and the second branch in each pixel circuit 100 based on the frequency control signal CCL, thereby controlling the refresh frequency of each pixel circuit 100, and realizing pixel-level refresh frequency adjustment, so that the partition positions of display partitions with different refresh frequencies in the display panel can be adjusted arbitrarily according to requirements. And without redesigning the gate drive circuit 200, the display panel 1000 can support a flexible partition frequency display function.

[0165] Fig.23 is a schematic diagram of the structure of another display device provided by an embodiment of the present invention, see Fig.23On the basis of the above embodiments, optionally, the driving component 2000 includes: a timing controller 201, a driving chip 202, and level conversion circuits 203 having the same number as the frequency control signal lines LC. The timing controller 201 receives the partition frequency information SF, and the timing controller 201 is used to parse the partition frequency information SF and generate a display control signal DP. The driving chip 202 is connected to the timing controller 201, and the driving chip 202 receives and parses the display control signal DP. Each level conversion circuit 203 is connected to each frequency control signal line LC in a one-to-one correspondence; each level conversion circuit 203 is connected to the first level signal VGH and the second level signal VGL, and is connected to the driving chip 202. The driving chip 202 is used to control each level conversion circuit 203 to output the first level signal VGH or the second level signal VGL according to the display control signal DP. The second voltages of the first level signal VGH and the second level signal VGL are different, for example, the first level signal VGH has a high voltage, and the second level signal VGL has a low voltage.

[0166] Specifically, the display panel 1000 includes a plurality of pixel circuits 100 arranged in an array; the display panel 1000 also includes: a gate drive circuit 200, which is connected to a timing controller 201 and connected to each row of pixel circuits 100 through each gate line LS. The timing controller 201 is also used to control the output of the gate drive circuit 200 so that each row of pixel circuits 100 enters the scanning phase row by row. The timing controller 201 can, for example, output a gate control signal GP according to a basic frequency to control the working process of the gate drive circuit 200. The gate control signal GP may include a start signal and a clock signal required for the gate drive circuit 200 to work. The driver chip 202 is used to control the voltage of the frequency control signal CCL received by each pixel circuit 100 in a row according to the display control signal DP during the scanning phase of each row of pixel circuits 100, so that the frequency control signal CCL changes in real time with the position of the scanning row.

[0167] The display panel 1000 may include a plurality of frequency control signal lines LC, one frequency control signal line LC is connected to at least one column of pixel circuits 100, and accordingly, the driving component 2000 includes a plurality of level conversion circuits 203. The display control signal DP may include refresh control signals of each row of pixel circuits 100, and the timing controller 201 serially outputs the refresh control signals of each row of pixel circuits 100 to the driving chip 202; in the scanning phase of any row of pixel circuits 100, the driving chip 202 controls each level conversion circuit 203 to transmit the frequency control signal CCL to each frequency control signal line LC in parallel according to the refresh control signal of the pixel circuit 100 of the row.

[0168] This embodiment is configured such that, according to the serial data transmitted by the timing controller 201, after the serial-to-parallel conversion of the driver chip 202 and the level conversion of the level conversion circuit 203, the frequency control signal CCL signal of all sub-pixel columns can be generated, and each frequency control signal CCL changes in real time with the position of the scanning line. In this way, the refresh rate setting of any display partition can be converted into a specific pixel circuit control, and the high-frequency refresh area and the low-frequency refresh area are divided on the display screen. Moreover, the above-mentioned signal control method realizes the online setting function of any row, any column, and any number of areas, which is conducive to the real-time adjustment of the display partition position and frequency without power failure during the display process.

[0169] On the basis of the above embodiments, optionally, the display panel 1000 further includes: a plurality of data lines LD, connected to each column of pixel circuits 100 in a one-to-one correspondence; the driving chip 202 is also connected to each data line LD; the timing controller 201 is also used to control the driving chip 202 to transmit a corresponding data signal Vdata to each data line LD, so as to control the display panel 1000 to display a picture. The data lines LD and the frequency control signal lines LC extend in the same direction, for example, in the column direction.

[0170] On the basis of the above embodiments, optionally, a plurality of pixel circuits 100 are arranged in an array in the display panel 1000, and at least two pixel circuits 100 in the same row are connected to the same frequency control signal line LC to reduce wiring in the display panel. Exemplarily, the display panel 1000 includes a plurality of pixel units, each of which includes at least two pixel circuits 100; in the same row, each pixel circuit 100 belonging to the same pixel unit is connected to the same frequency control signal line LC, and different pixel circuits 100 belonging to different pixel units are connected to different frequency control signal lines LC.

[0171] Fig.24 is a schematic diagram of the structure of another display device provided by an embodiment of the present invention. Fig.24 , exemplarily, the display device includes a host 3000 and a display module 4000, and the display module 4000 includes, for example, a display panel 1000 and a driving component 2000. The host 3000 is connected to the driving component 2000, and the host 3000 is used to provide partition frequency information SF. Specifically, the partition frequency information SF may include: the number, position, and refresh frequency of each display partition in the display area AA of the display panel 1000. The position of the display partition can be reflected by the coordinates of each vertex, for example Fig.12The three partitions shown, the position of the first display partition A1 can be reflected by the coordinates of the pixel circuits of its four vertices in the display area AA, the position of the second display partition A2 can be reflected by the coordinates of the pixel circuits of its four vertices in the display area AA, and the positions in the display area AA except the first display partition A1 and the second display partition A2 all belong to the third display partition A3. Specifically, when the electronic product is in use, the host (or client / AP) 3000 can obtain the current small window status, know whether the small window displays a video, a picture, or text, and generate partition frequency information SF accordingly. The partition frequency information SF may specifically include the number of partitions, the coordinates of each partition, and the refresh frequency value of each partition. After receiving the partition frequency information SF, the timing controller 201 parses it to generate coordinate parsing data, where each binary digit represents a pixel, and the number of rows and columns of the parsed data is equal to the resolution of the display screen. The parsing result can be seen in Fig.13 The timing controller 201 temporarily stores the analysis results and outputs them serially and row by row to the driver chip 202 .

[0172] Based on the above embodiments, the display panel 1000 may optionally include a lower frame area and a display area AA which are sequentially away from the driving chip 202, and the level conversion circuit 203 may be arranged in the lower frame area (eg Fig.23 As shown in FIG. 2 ), the wiring between the driving chip 202 and the level conversion circuit 203, and between the level conversion circuit 203 and each frequency control signal line LC is facilitated. Alternatively, the level conversion circuit 203 may be disposed in a circuit board (such as an FPC or a PCB) for carrying the timing controller 201. Alternatively, see Fig.25 , the level conversion circuit can be integrated into the driving chip 202 to avoid the level conversion circuit occupying the volume of the display module 4000.

[0173] In summary, the embodiment of the present invention can realize the partition multi-frequency display technology at any position, and the partition position can be changed in real time according to the partition frequency information SF. The partition at any position includes two technical branches: partition by row and partition by column, both of which can be realized by a set of solutions. To facilitate understanding of the control process of the driver chip 202 on each level conversion circuit 203, Figure 26-Figure 28 The control signal CP provided by the driving chip 202 to each level conversion circuit 203 in different time periods within a frame in various different partitioning modes is provided in the figure, which will be described below respectively. Figure 26-Figure 28 In the figure, each bit in the control signal CP represents a control signal provided by the driving chip 202 to a level conversion circuit 203, wherein 0 represents the cut-off voltage of the frequency control module output by the control level conversion circuit 203, and 1 represents the on-voltage of the frequency control module output by the control level conversion circuit 203; the thick horizontal line represents the position of the pixel circuit row currently being scanned. Fig.26In the example, the display area AA is divided into two partitions, the display area AA is divided into a first display partition A11 and a second display partition A12, and in the current frame, the pixel circuit in the first display partition A11 performs data refresh, and the pixel circuit in the second display partition A12 performs data retention. Fig. 27 Exemplarily, the display area AA is divided into three partitions, and the display area AA is divided into a first display partition A21, a second display partition A22 and a third display partition A23, and the first display partition A21 and the second display partition A22 are arranged along the row direction; in the current frame, the pixel circuits in the first display partition A21 and the second display partition A22 refresh data, and the pixel circuits in the third display partition A23 retain data. Fig.28 For example, the display area AA is divided into three partitions, the display area AA is divided into a first display partition A31, a second display partition A32 and a third display partition A33, the first display partition A31 and the second display partition A32 are arranged along the column direction; in the current frame, the pixel circuits in the first display partition A31 and the second display partition A32 perform data refresh, and the pixel circuits in the third display partition A33 perform data retention. Figure 26-28 It can be seen that no matter how the display area AA is divided into display partitions, the driver chip 201 controls the level conversion circuit 203 connected to each pixel circuit that needs to be refreshed to output the on-voltage of the frequency control module, and controls the level conversion circuit 203 connected to each pixel circuit that needs to be maintained to output the off-voltage of the frequency control module. After each row of pixel circuits is scanned, the control signal CP is updated once according to the display control signal DP provided by the upstream.

[0174] For the voltage variation of the frequency control signal in each display frame, see Fig.28 and Fig.29 , here we select Fig.28 The first frequency control signal line LC1 on the right side of the middle provides a first frequency control signal CCL1, and Fig.28 The second frequency control signal CCL2 provided by the second frequency control signal line LC2 on the left side of the middle is shown, wherein the first frequency control signal line LC1 passes through the third display partition A33 and the second display partition A32, and the second frequency control signal line LC2 passes through the third display partition A33, the first display partition A31 and the second display partition A32. Fig.29In the first frame F11, the whole screen is refreshed, and the first frequency control signal CCL1 and the second frequency control signal CCL2 both maintain the on-voltage of the frequency control module (here, exemplarily, a high voltage); in the second frame F12, the first display partition A31 and the second display partition A32 are refreshed, and the third display partition A33 is data maintained. Then, in the second frame F12, the first frequency control signal CCL1 is the on-voltage of the frequency control module during the scanning phase of each row of pixel circuits in the first display partition A31 and each row of pixel circuits in the second display partition A32, and the other time periods are the cut-off voltage of the frequency control module. In the second frame F12, the second frequency control signal CCL2 is the on-voltage of the frequency control module during the scanning phase of each row of pixel circuits in the second display partition A32, and the other time periods are the cut-off voltage of the frequency control module.

[0175] In summary, in the display device provided by the embodiment of the present invention, the partition position and partition size can be completely controlled by signals and can be changed at any time during product use. If the partition position is to be changed, there is no need to change the hardware structure, and the product does not need to be powered off. The partition information can be directly updated in the client host or timing controller to achieve the update of the partition and realize real-time adjustable partition multi-frequency technology. Moreover, any partition position setting and any partition size can be achieved. Exemplarily, the display device can be a vehicle-mounted display screen, an industrial control display screen, a computer display screen, a TV, a PAD, etc.

[0176] In one embodiment, optionally, the pixel circuit may have the structure given in any of the above embodiments, and the frequency control module 40 may include a first switch unit, a second switch unit and a voltage control unit. Then, the on-voltage of the frequency control module 40 is equal to the off-voltage of the second switch unit.

[0177] In another embodiment, optionally, see Fig.30 The frequency control module 40 includes: a third switch unit 440 and a fourth switch unit 450. The third switch unit 440 is connected in series with the threshold compensation module 20 in the first branch, and the control end of the third switch unit 440 is connected to the frequency control signal CCL. The fourth switch unit 450 is connected in series with the first initialization module 30 in the second branch, and the control end of the second switch unit 450 is connected to the frequency control signal CCL.

[0178] Specifically, the on-voltage of the third switch unit 440 is the same as the on-voltage of the fourth switch unit 450. Accordingly, the on-voltage of the frequency control module 40 is equal to the on-voltage of the third switch unit 440. In any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase that occur successively; in the first initialization phase, the first initialization module 30 is turned on; in the data writing phase, the threshold compensation module 20 is turned on. In the display frame in which the pixel circuit performs data refresh, the frequency control signal CCL maintains the on-voltage of the third switch unit 440 at least in the first initialization phase and the data writing phase; in the display frame in which the pixel circuit performs data retention, the frequency control signal maintains the off-voltage of the third switch unit 440 at least in the first initialization phase and the data writing phase. Further, in the display frame in which the pixel circuit performs data refresh, the frequency control signal CCL maintains the on-voltage of the third switch unit 440 in the scanning phase; in the display frame in which the pixel circuit performs data retention, the frequency control signal CCL maintains the off-voltage of the third switch unit 440 in the scanning phase.

[0179] Specifically, the third switch unit 440 includes: a tenth transistor M10, the tenth transistor M10 is connected in series with the threshold compensation module 20 in the first branch, and the gate of the tenth transistor M10 is connected to the frequency control signal CCL. The fourth switch unit 450 includes: an eleventh transistor M11, the eleventh transistor M11 is connected in series with the first initialization module 30 in the second branch, and the gate of the eleventh transistor M11 is connected to the frequency control signal CCL. Exemplarily, the tenth transistor M10 and the eleventh transistor M11 have the same channel type. For example, the tenth transistor M10 and the eleventh transistor M11 are both N-type transistors, such as IGZO transistors, to reduce leakage on the first branch and the second branch; or, the tenth transistor M10 and the eleventh transistor M11 are both P-type transistors, such as LTPS transistors, to reduce the occupied area of ​​the tenth transistor M10 and the eleventh transistor M11, which is conducive to achieving high pixel density. The structures of other modules in the pixel circuit can be referred to. Figure 8 The explanation will not be repeated here.

[0180] In this embodiment, two transistors are added to each pixel circuit as control switches, a frequency control signal line is added to each sub-pixel column, and a level conversion circuit is set outside the display area AA. The refresh state control of the pixel level can be achieved under the control of the frequency control signal CCL. Even the pixel circuits in the same row can be in the two pixel states of data refresh and data write respectively.

[0181] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0182] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that: include: Driver module; A threshold compensation module is provided in a first branch connected between the control end and the second end of the driving module, and the threshold compensation module is used to be turned on or off according to a first scanning signal; A first initialization module, disposed in a second branch connected to the control end of the driving module, the first initialization module being used to be turned on or off according to a second scanning signal; A frequency control module is connected to the first branch and the second branch respectively, and is connected to a frequency control signal and the first scanning signal; the frequency control module is used to control the on-off of the first branch according to the frequency control signal and the first scanning signal, and to control the on-off of the second branch according to the frequency control signal, so as to control the refresh frequency of the pixel circuit.

2. The pixel circuit according to claim 1, characterized in that: The frequency control module comprises: A first switch unit is connected in series with the threshold compensation module in the first branch; the first switch unit is used to be turned on or off according to the voltage of its control terminal; A second switch unit is connected in series with the first initialization module in the second branch, and a control end of the second switch unit is connected to the frequency control signal; the second switch unit is used to be turned on or off according to the frequency control signal; a voltage control unit connected to the control end of the first switch unit and connected to the frequency control signal and the first scanning signal; the voltage control unit is used to control whether the frequency control signal is transmitted to the control end of the first switch unit according to the first scanning signal; Preferably, one end of the second branch is connected to the control end of the driving module, and the other end of the second branch is connected to the initialization signal; Preferably, the on-voltage of the first switch unit is the same as the on-voltage of the second switch unit; when the first scanning signal is the cut-off voltage of the threshold compensation module, the voltage control unit is controlled to transmit the frequency control signal to the control end of the first switch unit.

3. The pixel circuit according to claim 2, characterized in that: In any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase which occur successively; in the first initialization phase, the second scanning signal is a turn-on voltage of the first initialization module; in the data writing phase, the first scanning signal is a turn-on voltage of the threshold compensation module; In a display frame in which the pixel circuit performs data refresh, a period during which the frequency control signal maintains the on-voltage of the second switch unit at least covers the start time of the first initialization phase and the data writing phase; In a display frame in which the pixel circuit performs data retention, a period in which the frequency control signal maintains the cut-off voltage of the second switch unit at least covers the start time of the first initialization phase and the data writing phase; Preferably, in a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains the on-voltage of the second switch unit at least during a period from the start of the first initialization phase to the start of the data writing phase; In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the second switch unit at least during a period from when the first initialization phase starts to after the data writing phase starts.

4. The pixel circuit according to claim 2, characterized in that: The first switch unit comprises: a first transistor connected in series with the threshold compensation module in the first branch, and a gate of the first transistor is connected to a control terminal of the first switch unit; The second switch unit comprises: a second transistor connected in series with the first initialization module in the second branch, and a gate of the second transistor is connected to the frequency control signal; The voltage control unit comprises: a third transistor, a gate of the third transistor is connected to the first scanning signal, a first electrode of the third transistor is connected to the frequency control signal, and a second electrode of the third transistor is connected to the control end of the first switch unit; Preferably, the voltage control unit further includes: a first capacitor, a first end of the first capacitor is connected to the control end of the first switch unit, and a second end of the first capacitor is connected to a fixed voltage signal; Preferably, the threshold compensation module comprises: a fourth transistor connected in series with the first switch unit in the first branch, and a gate of the fourth transistor is connected to the first scanning signal; The first initialization module includes: a fifth transistor connected in series with the second switch unit in the second branch, and a gate of the fifth transistor is connected to the second scanning signal; Preferably, the first transistor and the second transistor have the same channel type, and the third transistor and the fourth transistor have different channel types; Preferably, the channel types of the first transistor, the second transistor, the fourth transistor and the fifth transistor are all the same; Preferably, the first transistor, the second transistor, the fourth transistor and the fifth transistor are all N-type transistors, and the third transistor is a P-type transistor.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that: The driving module comprises: a driving transistor, a gate of the driving transistor is connected to a control terminal of the driving module, a first electrode of the driving transistor is connected to a first terminal of the driving module, and a second electrode of the driving transistor is connected to a second terminal of the driving module; Preferably, the pixel circuit further includes: The data writing module comprises a sixth transistor; the gate of the sixth transistor is connected to the third scanning signal, the first electrode of the sixth transistor is connected to the data signal, and the second electrode of the sixth transistor is connected to the first end of the driving module; A light-emitting control module, comprising a seventh transistor and an eighth transistor; the gate of the seventh transistor and the gate of the eighth transistor are both connected to a light-emitting control signal, the first electrode of the seventh transistor is connected to a first power supply signal, the second electrode of the seventh transistor is connected to a first end of the driving module, the first electrode of the eighth transistor is connected to a second end of the driving module, the second electrode of the eighth transistor is connected to an anode of a light-emitting device, and the cathode of the light-emitting device is connected to a second power supply signal; A second initialization module includes a ninth transistor; a gate of the ninth transistor is connected to a fourth scanning signal, a first electrode of the ninth transistor is connected to an initialization signal, and a second electrode of the ninth transistor is connected to an anode of the light-emitting device; A storage module, comprising a storage capacitor; a first end of the storage capacitor is connected to the first power signal, and a second end of the storage capacitor is connected to a control end of the driving module; Preferably, the frequency control module includes a first capacitor, and a second end of the first capacitor is connected to a fixed voltage signal; wherein the initialization signal, the first power signal or the second power signal is multiplexed into the fixed voltage signal.

6. A display panel, characterized in that: include: The pixel circuit according to any one of claims 1 to 5; Preferably, the frequency control module comprises a first switch unit, a second switch unit and a voltage control unit; the display panel comprises a plurality of pixel circuits arranged in an array; at least two pixel circuits in the same row share the same voltage control unit; Preferably, the display panel comprises a plurality of pixel units, and each of the pixel units comprises at least two of the pixel circuits; In the same row, the pixel circuits belonging to the same pixel unit share the same voltage control unit; Preferably, the display panel further comprises: at least one frequency control signal line, at least one column of the pixel circuits is connected to the same frequency control signal line, and the frequency control signal line is used to provide the frequency control signal to the connected pixel circuits; Preferably, at least two pixel circuits in the same row are connected to the same frequency control signal line; Preferably, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines; Preferably, the display panel further comprises: a plurality of data lines connected to the pixel circuits of each column in a one-to-one correspondence; the data lines and the frequency control signal lines extend in the same direction.

7. A display device, characterized in that: include: A display panel, comprising a plurality of pixel circuits and at least one frequency control signal line; the pixel circuit comprises: a driving module, a threshold compensation module, a first initialization module and a frequency control module; the threshold compensation module is arranged in a first branch connected between a control end and a second end of the driving module; the first initialization module is arranged in a second branch connected to the control end of the driving module; the frequency control module is connected to the frequency control signal line corresponding to the pixel circuit, and the frequency control module is used to control the on and off of the first branch and the second branch according to the frequency control signal transmitted by the connected frequency control signal line, so as to control the refresh frequency of the pixel circuit; A driving component is connected to each of the frequency control signal lines and is used to control the voltage of the frequency control signal transmitted by each of the frequency control signal lines according to the partition frequency information.

8. The display device according to claim 7, characterized in that: The drive assembly comprises: A timing controller, used for analyzing the partition frequency information and generating a display control signal; A driving chip connected to the timing controller; level conversion circuits having the same number as the frequency control signal lines, each of the level conversion circuits being connected to each of the frequency control signal lines in a one-to-one correspondence; each of the level conversion circuits being connected to a first level signal and a second level signal, and being connected to the driving chip; the driving chip being used to control each of the level conversion circuits to output the first level signal or the second level signal according to the display control signal; Preferably, the display panel includes a plurality of pixel circuits arranged in an array; the display panel also includes: a gate driving circuit connected to the timing controller and each pixel circuit respectively; the timing controller is further used to control the output of the gate driving circuit so that each row of the pixel circuits enters the scanning stage row by row; The driving chip is used to control the voltage of the frequency control signal received by each pixel circuit in a row according to the display control signal during the scanning phase of each row of pixel circuits; Preferably, the display panel includes a plurality of frequency control signal lines, one of which is connected to at least one column of pixel circuits; the display control signal includes refresh control signals of the pixel circuits in each row, and the timing controller serially outputs the refresh control signals of the pixel circuits in each row to the driver chip; in a scanning phase of any row of pixel circuits, the driver chip controls the level conversion circuits to transmit frequency control signals to the frequency control signal lines in parallel according to the refresh control signals of the pixel circuits in that row; Preferably, the display panel further comprises: a plurality of data lines, connected to each column of pixel circuits one by one; the driving chip is also connected to each of the data lines; the timing controller is also used to control the driving chip to transmit a corresponding data signal to each of the data lines; Preferably, the data line and the frequency control signal line extend in the same direction; Preferably, at least two pixel circuits in the same row are connected to the same frequency control signal line; Preferably, the display panel includes a plurality of pixel units, each of which includes at least two pixel circuits; in the same row, the pixel circuits belonging to the same pixel unit are connected to the same frequency control signal line, and different pixel circuits belonging to different pixel units are connected to different frequency control signal lines; Preferably, the display device further comprises: a host connected to the driving component and configured to provide the partition frequency information; Preferably, the partition frequency information includes: the number, position and refresh frequency of each display partition in the display area of ​​the display panel; Preferably, the display panel comprises a lower frame area and a display area which are sequentially away from the driving chip, the level conversion circuit is arranged in the lower frame area, and the pixel circuit is arranged in the display area; Alternatively, the level conversion circuit is integrated into the driver chip; Alternatively, the level conversion circuit is arranged in a circuit board for carrying the timing controller.

9. The display device according to claim 7, characterized in that: The pixel circuit is the pixel circuit according to any one of claims 1 to 5.

10. The display device according to claim 7, characterized in that: The frequency control module comprises: A third switch unit is connected in series with the threshold compensation module in the first branch, and a control end of the third switch unit is connected to the frequency control signal; a fourth switch unit, connected in series with the first initialization module in the second branch, and a control end of the second switch unit is connected to the frequency control signal; Preferably, the on-voltage of the third switch unit is the same as the on-voltage of the fourth switch unit; Preferably, in any display frame, the scanning phase of the pixel circuit includes a first initialization phase and a data writing phase which occur successively; in the first initialization phase, the first initialization module is turned on; in the data writing phase, the threshold compensation module is turned on; In a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains a turn-on voltage of the third switch unit at least in the first initialization phase and the data writing phase; In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switch unit at least in the first initialization phase and the data writing phase; Preferably, in a display frame in which the pixel circuit performs data refresh, the frequency control signal maintains a turn-on voltage of the third switch unit in the scanning phase; In a display frame in which the pixel circuit performs data retention, the frequency control signal maintains a cut-off voltage of the third switch unit in the scanning phase; Preferably, the third switch unit comprises: a tenth transistor, connected in series with the threshold compensation module in the first branch, and a gate of the tenth transistor is connected to the frequency control signal; The fourth switch unit comprises: an eleventh transistor, connected in series with the first initialization module in the second branch, and a gate of the eleventh transistor is connected to the frequency control signal; Preferably, the tenth transistor and the eleventh transistor have the same channel type.

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